CN117255560A - Semiconductor memory and preparation method thereof - Google Patents

Abstract

The invention provides a semiconductor device and a preparation method thereof, wherein a gap with the bottom exposed out of a first word line material layer is arranged in a second word line material layer of an embedded word line structure, so that a word line conductive plug extends into the gap and is further in direct contact with the first word line material layer positioned below the second word line material layer, and the purpose of better contact between the enhanced word line conductive plug and the embedded word line structure is realized. In addition, the top surface of the second word line material layer is in an uneven shape, so that in the preparation process of the embedded word line structure, the gap in the second word line material layer can be formed by only utilizing a one-step etching process without carrying out chemical mechanical polishing before etching, one polishing manufacturing procedure is saved, the production efficiency is improved, and the production cost of a semiconductor device is reduced.

Description

Semiconductor memory and preparation method thereof

Technical Field

The invention relates to the technical field of memories, in particular to a semiconductor memory and a preparation method thereof.

Background

A memory, such as a dynamic random access memory, typically includes a storage capacitor for storing charge representing stored information and a storage transistor electrically connected to the storage capacitor, which may be electrically connected to the storage capacitor through a node contact structure. With the trend toward miniaturization of various electronic products, the density of memory cells of dynamic random access memories (hereinafter referred to as DRAMs) is continuously increasing, for example, the size of the repetition pitch of interconnections of DRAM word lines and bit lines is decreasing, and the distances between word lines and between bit lines are decreasing, resulting in an increase in the difficulty and complexity of the related manufacturing process and design, and thus in an increase in the production cost. Accordingly, there remains a need to reduce manufacturing costs by improving production efficiency through structural design and/or improvements in manufacturing processes.

Disclosure of Invention

One of the objectives of the present invention is to provide a semiconductor device and a method for manufacturing the same, which can enhance the contact between a word line conductive plug and a buried word line structure, save manufacturing processes, improve production efficiency and reduce device manufacturing cost.

In order to achieve the above object, in one embodiment of the present invention, a method for manufacturing a semiconductor device is provided, which includes at least the following steps:

a substrate;

shallow trench isolation arranged in the substrate and surrounding the plurality of active areas;

a plurality of buried word line structures spanning the plurality of active regions, and the buried word line structures comprising:

a first word line material layer

A second word line material layer located over the first word line material layer;

at least one word line conductive plug, the length of the word line conductive plug in direct contact with the first word line material layer in the horizontal direction is smaller than the length of the first word line material layer in the horizontal direction.

In one alternative example, the step of forming the buried word line structure includes:

forming a plurality of word line trenches extending in the horizontal direction and arranged at intervals in the active region and the shallow trench isolation;

sequentially forming a first word line material layer and a second word line material layer in each word line trench, wherein the second word line material layer fills the word line trenches and extends to cover a substrate between two adjacent word line trenches, and the top surface of the second word line material layer covered on the substrate is in an uneven shape;

and etching the second word line material layer back to form the embedded word line structure in the word line trench, wherein the etched second word line material layer has a gap therein and exposes the first word line material layer.

In one alternative example, the voids in the plurality of buried word line structures have an inverted "ladder" shape in cross-section along the horizontal direction.

In one alternative example, the length of the inverted "ladder" shaped bottom is smaller than the length of the first word line material layer in the buried word line structure in the horizontal direction.

In one alternative example, the voids in the plurality of buried word line structures have a "V" shape in cross section along the horizontal direction.

In one optional example, after forming the plurality of word line trenches in the active region and the shallow trench isolation, and before forming the first word line material layer, the preparation method further includes:

a first insulating layer is formed on the sidewalls and bottom of each of the word line trenches.

In order to achieve the above object and based on the same inventive concept, in a second aspect, there is provided a semiconductor memory device, including:

a substrate;

shallow trench isolation arranged in the substrate and surrounding the plurality of active areas;

a plurality of buried word line structures spanning the plurality of active regions, and the buried word line structures comprising:

a first word line material layer

A second word line material layer located over the first word line material layer;

at least one word line conductive plug, the length of the word line conductive plug in direct contact with the first word line material layer in the horizontal direction is smaller than the length of the first word line material layer in the horizontal direction.

In one alternative example, the second word line material layer has a void therein.

In one alternative example, the voids in the plurality of buried word line structures have an inverted "ladder" shape in cross-section along the horizontal direction.

In one alternative example, the length of the inverted "ladder" -shaped bottom is less than the length of the first word line material layer in the horizontal direction.

In one alternative example, the voids in the plurality of buried word line structures have a "V" shape in cross section along the horizontal direction.

In order to achieve the above object and based on the same inventive concept, another embodiment of the present invention also provides a semiconductor memory, including:

a substrate;

shallow trench isolation arranged in the substrate and surrounding the plurality of active areas;

a plurality of buried word line structures spanning the plurality of active regions, and the buried word line structures comprising:

a first word line material layer, comprising:

a metal layer; and

a barrier layer surrounding the metal layer;

a second word line material layer located over the first word line material layer;

at least one word line conductive plug in direct contact with the first word line material layer;

the distance between the second word line material layer surface in the vertical direction and the barrier layer is a first distance, the distance between the second word line material layer surface in the vertical direction and the metal layer is a second distance, and the first distance is different from the second distance.

In one optional example, the second word line material layer includes:

a first polysilicon layer; and

a second polysilicon layer;

wherein the word line conductive plug is filled between the first polysilicon layer and the second polysilicon layer.

In one optional example, the second word line material layer includes:

a first polysilicon layer; and

a second polysilicon layer;

the first polysilicon layer is not in direct contact with the second polysilicon layer.

In order to achieve the above object and based on the same inventive concept, another embodiment of the present invention further provides a semiconductor memory, including:

a substrate;

shallow trench isolation arranged in the substrate and surrounding the plurality of active areas;

a plurality of buried word line structures spanning the plurality of active regions, and the buried word line structures comprising:

a first word line material layer

A second word line material layer located over the first word line material layer;

at least one word line conductive plug in direct contact with the first word line material layer;

wherein a height between the word line conductive plug top surface and the first word line material layer in a vertical direction is greater than a height between the word line conductive plug top surface and the second word line material layer.

Compared with the prior art, the technical scheme provided by the invention has at least one of the following beneficial effects:

a gap with the bottom exposing the first word line material layer is arranged in the second word line material layer of the embedded word line structure, so that the word line conductive plug extends into the gap and is further in direct contact with the first word line material layer below the second word line material layer, and the purpose of better contact between the enhanced word line conductive plug and the embedded word line structure is achieved.

In addition, the top surface of the second word line material layer is in an uneven shape, so that in the preparation process of the embedded word line structure, the gap in the second word line material layer can be formed by only utilizing a one-step etching process without carrying out chemical mechanical polishing before etching, one polishing manufacturing procedure is saved, the production efficiency is improved, and the production cost of a semiconductor device is reduced.

Drawings

Fig. 1 is a schematic top view of a semiconductor memory according to some embodiments of the invention.

FIG. 2 is a schematic cross-sectional view of a buried word line structure 130 along line B-B of FIG. 1, as provided in some embodiments of the present invention.

Fig. 3 is a schematic cross-sectional view of a buried word line structure 130 of fig. 1 along line B-B with a word line conductive plug 140 formed therein, in accordance with some embodiments of the present invention.

Fig. 4 is a cross-sectional view of a buried word line structure 130 of fig. 1 along a line B-B where no word line conductive plugs 140 are formed.

Fig. 5-7 are schematic partial cross-sectional views of methods of manufacturing semiconductor devices along the line B-B in fig. 1 during manufacturing according to some embodiments of the present invention.

Fig. 8 is a schematic partial cross-sectional view of the semiconductor memory device of fig. 1 along a line C-C in accordance with some embodiments of the present invention.

Fig. 9 is a schematic partial cross-sectional view of a semiconductor memory along the line D-D in fig. 1 provided in some embodiments of the invention.

Wherein, the reference numerals are as follows:

100-substrate; 101-word line trenches;

110-a first insulating layer; 120-a barrier layer;

130-buried word line structure; 140-word line conductive plugs;

131-a first word line material layer; 132-a second word line material layer;

150-a second insulating layer; 160-a third insulating layer;

170-a fourth insulating layer; 180-a fifth insulating layer;

102-void.

Detailed Description

In order to make the technical scheme and advantages of the embodiments of the present invention more clear, the technical scheme of the present invention will be further described in detail below with reference to the accompanying drawings and the embodiments. While exemplary embodiments of the invention are shown in the drawings, it should be understood that the invention may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

The invention is more particularly described by way of example in the following paragraphs with reference to the drawings. Advantages and features of the invention will become more apparent from the following description and from the claims. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention. It is to be understood that the meanings of "on … …", "over … …" and "over … …" in the present invention are to be interpreted in the broadest sense so that "on … …" means not only that it is "on" something with no intervening features or layers therebetween (i.e., directly on something), but also that it is "on" something with intervening features or layers therebetween.

Further, spatially relative terms such as "on … …," "above … …," "above … …," "upper" and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated for ease of description. In addition to the orientations depicted in the drawings, the spatially relative terms are intended to encompass different orientations of the device in use or operation. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

In embodiments of the present invention, the terms "first," "second," and the like are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. The technical schemes described in the embodiments of the present invention may be arbitrarily combined without any collision.

For convenience of understanding, a horizontal direction and a vertical direction are defined hereinafter, wherein the horizontal direction is a direction parallel to the surface of the substrate 100; the vertical direction is a direction perpendicular to the surface of the substrate 100; in fig. 1 to 9, an X direction, a Y direction, and a Z direction are defined, wherein the X direction is in the same plane as the Y direction and corresponds to the horizontal direction, the Z direction is perpendicular to the plane in which the X direction and the Y direction are located and corresponds to the vertical direction, and the X direction is perpendicular to the Y direction, the horizontal direction, and the vertical direction, and the Z direction is perpendicular to the X direction and the Y direction.

Referring to fig. 1, fig. 1 is a schematic top view of a semiconductor memory according to an embodiment of the invention. As shown in fig. 1, the semiconductor memory includes a substrate 100, a plurality of active areas AA, shallow trench isolation STI, a plurality of buried word line structures 130 and at least one word line conductive plug 140 disposed on the substrate 100.

In some embodiments, the base 100 is any suitable substrate material known in the art, such as, but not limited to, a silicon substrate, a silicon-containing substrate (e.g., siC, siGe), or a silicon-on-insulator substrate (silicon-on-insulator substrate), or other suitable substrate materials. The plurality of active areas AA and the shallow trench isolation STI are disposed in the substrate 100, wherein the plurality of active areas AA extend along the X-direction and the Y-direction and are arranged in parallel, the plurality of shallow trench isolation STI surrounds the plurality of active areas AA to isolate adjacent active areas AA, the plurality of buried word line structures 130 are arranged at intervals along the X-direction, any one of the buried word line structures 130 is arranged on the plurality of active areas AA arranged along the Y-direction in a penetrating manner along the Y-direction, and the word line conductive plugs 140 are disposed on the buried word line structures 130 along the Z-direction.

As shown in fig. 1, only a portion of the embedded word line structure 130 has the word line conductive plug 140 formed thereon, and the rest of the embedded word line structure 130 has no word line conductive plug 140 formed thereon.

Referring to fig. 2-3, fig. 2 is a schematic cross-sectional view of a buried word line structure 130 along a line B-B of fig. 1 before forming a word line conductive plug 140; fig. 3 is a cross-sectional view of a buried word line structure 130 along line B-B of fig. 1 after forming word line conductive plugs 140.

As shown in fig. 2, and in combination with fig. 1, a buried word line structure 130 is formed in a word line trench 101 in the substrate 100, and the word line trenches 101 extend in the Y direction to form a plurality of buried word line structures 130 crossing the active areas AA and shallow trench isolation STI in the Y direction on the substrate 100;

specifically, a buried word line structure 130 includes: a first word line material layer 131 and a second word line material layer 132; wherein the first word line material layer 131 is located at a lower region of the word line trench 101, the second word line material layer 132 is located above the first word line material layer 131, and the second word line material layer 132 further has a void 102 therein exposing a portion of the surface of the first word line material layer 131.

In some embodiments, the cross-sectional shape of the void 102 in the buried word line structure 130 in the horizontal direction (X-direction) is in particular inverted "ladder" shape, and the length P1 of the bottom of the inverted "ladder" shape is smaller than the length P2 of the first word line material layer 131 in the horizontal direction (X-direction). Illustratively, the material of the first word line material layer 131 is a metal, such as tungsten, and the material of the second word line material layer 132 is polysilicon.

As shown in fig. 3, in this arrangement, the word line conductive plugs 140 formed on at least one of the embedded word line structures 130 are in direct contact with the first word line material layer 131 in the embedded word line structure 130, and the length of the word line conductive plugs 140 in direct contact with the first word line material layer 131 in the horizontal direction is smaller than the length of the first word line material layer 131 in the horizontal direction, in other words, the length P1 of the bottom in the horizontal direction of the void 102 in the shape of an inverted "ladder" in the embedded word line structure 130 is smaller than the length P2 in the horizontal direction of the first word line material layer 131.

With continued reference to fig. 2 and 3, a first insulating layer 110 and a barrier layer 120 are further formed in the word line trench 101 with the buried word line structure 130 formed therein, wherein the first insulating layer 110 at least covers the sidewalls and bottom of the word line trench 101, and the barrier layer 120 is located between the first insulating layer 110 and the first word line material layer 131.

Since the buried word line structure 130 has a void 102 therein, the void 102 divides the second word line material layer 132 made of polysilicon into a first polysilicon layer 132a and a second polysilicon layer 132b which are not in direct contact, and an extension 140a of a word line conductive plug 140 electrically connected to the buried word line structure 130, which is formed later, is filled between the first polysilicon layer 132a and the second polysilicon layer 132b and is in direct contact with the first word line material layer 131.

In some embodiments, a distance between a surface of the second word line material layer 132 (or the first polysilicon layer 132a or the second polysilicon layer 132 b) and the barrier layer 120 in a vertical direction (Z direction) is a first distance S1, a distance between a surface of the second word line material layer 132 (or the first polysilicon layer 132a or the second polysilicon layer 122 b) and the first word line material layer 131 in a vertical direction is a second distance S2, and then the first distance S1 is different from the second distance S2, i.e., the first distance S1 is greater than the second distance S2.

In other embodiments, the height between the top surface of the word line conductive plug 140 and the first word line material layer 131 in the vertical direction is a first height H1, and the height between the top surface of the word line conductive plug 140 and the second word line material layer 132 is a second height H2, then the first height H1 is greater than the second height H2.

Obviously, since the semiconductor device in the embodiment of the invention is provided with the gap with the bottom exposing the first word line material layer in the second word line material layer of the embedded word line structure, the word line conductive plug for electrically connecting the embedded word line structure extends into the gap and is further in direct contact with the first word line material layer positioned below the second word line material layer, thereby achieving the purpose of better contact between the enhanced word line conductive plug and the embedded word line structure.

Referring to fig. 4, fig. 4 is a schematic partial cross-sectional view of a buried word line structure 130 of fig. 1 along a line B-B where no word line conductive plugs 140 are formed.

As shown in fig. 4, the buried word line structure 130 includes: a first word line material layer 131 and a second word line material layer 132; wherein, the first word line material layer 131 and the second word line material layer 132 are formed in the word line trench 101 extending along the Y direction in the active area AA and the shallow trench isolation STI, the second word line material layer 132 is located above the first word line material layer 131, and the second word line material layer 132 has a void 102 therein exposing a part of the surface of the first word line material layer 131.

In some embodiments, the voids 102 in the buried word line structure 130 have a cross-sectional shape in the horizontal direction that is "V" shaped. Illustratively, the material of the first word line material layer 131 is a metal, such as tungsten, and the material of the second word line material layer 132 is polysilicon.

With continued reference to fig. 4, a first insulating layer 110 and a barrier layer 120 are further formed in the word line trench 101 with the buried word line structure 130 formed therein, wherein the first insulating layer 110 at least covers the sidewalls and bottom of the word line trench 101, and the barrier layer 120 is located between the first insulating layer 110 and the first word line material layer 131.

It should be noted that, in the embodiment of the present invention, the purpose of disposing the second word line material layer of the embedded word line structure in the semiconductor device with a bottom portion exposing the gap of the first word line material layer is: in order to enhance better contact between the word line conductive plugs and the buried word line structure 130 shown in fig. 4, the second word line material layer 132 in the buried word line structure 130 shown in fig. 4 may be provided with the voids 102 having a V-shaped cross-section in the horizontal direction, or the voids 102 may not be provided, that is, the beneficial effects of the embodiments of the present invention may be achieved as long as the second word line material layer in at least one buried word line structure 130 shown in fig. 1 is provided with a void 102 with a bottom portion exposing the first word line material layer 131 as shown in fig. 2.

In order to enable a person skilled in the art to easily understand the semiconductor device according to the embodiments of the present invention, a method for manufacturing the semiconductor device according to the present invention will be further described below.

Referring to fig. 5 to 7, fig. 5 to 7 are schematic partial cross-sectional views of a semiconductor device along a line B-B in fig. 1 according to some embodiments of the present invention during a manufacturing process.

As shown in fig. 5, a substrate 100 is provided, and a plurality of shallow trench isolation STI is formed in the substrate 100, and a plurality of active areas AA are defined by the plurality of shallow trench isolation STI.

In some embodiments, the shallow trench isolation STI is fabricated, for example, by forming a plurality of trenches (not shown) in the substrate 100 respectively by an etching process, filling each of the trenches with an insulating material such as oxide (silicon dioxide) or nitride (silicon nitride), and forming a plurality of shallow trench isolation STI after the planarization process, i.e. defining a plurality of active areas AA at the same time, but not limited thereto. Then, a plurality of word line trenches 101 extending in the horizontal direction (X direction) and arranged at intervals are formed in the active region AA and the shallow trench isolation STI, then, an insulating material such as silicon nitride is deposited in at least each of the word line trenches 101 by a deposition process such as a physical vapor deposition process or a chemical vapor deposition process, then, the insulating material is etched such as a dry etching process to at least preserve the insulating material on the bottom and both side walls of the word line trenches 101, thereby forming a first insulating layer 110, then, a barrier layer 120 and a first word line material layer 131 are sequentially formed in each of the word line trenches 101 by the same preparation process (deposition-before-etching), and finally, a second word line material layer 132 filling the remaining space of the word line trenches 101 and extending over the substrate 100 between the adjacent word line trenches 101 is formed by the deposition process.

Specifically, the first insulating layer 110 covers the sidewalls and bottoms of the word line trenches 101 and extends over the substrate 100 between two adjacent word line trenches 101, the barrier layer 120 is located between the first insulating layer 110 and the first word line material layer 131, the first word line material layer 131 fills in the lower region of the word line trenches 101, the second word line material layer 132 fills the word line trenches 101 and extends over the first insulating layer 110 between two adjacent word line trenches 101, wherein the top surface of the second word line material layer 132 covering the first insulating layer 110 is rugged.

In some embodiments, the asperities may be of a sine-like wave shape with high sides, low middle, and gradually decreasing from high to low from side to middle; illustratively, as shown in fig. 5, the top surface of the second word line material layer 132 covered on the first insulating layer 110 on the substrate 100 between two adjacent word line trenches 101 is higher, while the top surface of the second word line material 132 formed in and over the word line trenches 101 is lower.

Obviously, since the top surface of the second word line material layer 132 is high on both sides and has a low middle roughness, in the subsequent etching process of the second word line material layer 132 by using the etching process, the time required for etching the polysilicon of the second word line material layer 132 with a lower middle top surface is short and the etching rate is faster, while the time required for etching the polysilicon of the second word line material layer 132 with a higher top surface on both sides is longer and the etching rate is slower, i.e. the void 102 is formed in the middle region of the second word line material layer 132.

As shown in fig. 6, the second word line material layer 132 is etched back by an etching process to form a buried word line structure 130 of a first word line material layer 131 and a second word line material layer 132 in the word line trench 101, wherein the material of the first word line material layer 131 is metal, such as metal tungsten, and the material of the second word line material layer 132 is polysilicon.

In some embodiments, the etched-back second word line material layer 132 has a void 102 therein, and the void 102 exposes the first word line material layer 131. Illustratively, the cross-sectional shape of the void 102 in the horizontal direction is specifically inverted "ladder" -shaped, and the length P1 of the bottom of the inverted "ladder" -shaped is smaller than the length P2 of the first word line material layer 131 in the horizontal direction.

As shown in fig. 7, a second insulating layer 150 filling the remaining space of the word line trench 101, and a third insulating layer (not shown), a fourth insulating layer (not shown), and a fifth insulating layer (not shown) on the substrate 100 for subsequently forming the word line conductive plug 140 are then formed on the second word line material layer 132 having the void 102.

Then, an etching process is used to form a through hole in the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer 150 above the buried word line structure 130 with the word line conductive plug 140 formed thereon, and a deposition process is used to fill the through hole with a conductive material, thereby forming the word line conductive plug 140.

In order to enable one of ordinary skill in the art to easily understand the specific structure of the buried word line structure in the embodiments of the present invention, the semiconductor device shown in fig. 2 or 3 formed by the method for manufacturing a semiconductor device according to the present invention will be further described from other tangential directions.

Referring to fig. 8-9, fig. 8 is a schematic partial cross-sectional view of the semiconductor memory device of fig. 1 along a tangent line C-C; fig. 9 is a schematic partial cross-sectional view of the semiconductor memory along the line D-D in fig. 1.

As can be seen from fig. 8 and 9, with respect to the semiconductor device shown in fig. 3, since the second word line material layer 132 in the partially embedded word line structure 130 formed in the embodiment of the present invention has an inverted "ladder" -shaped void 102 therein, when the tangential lines C-C and D-D, which are vertically taken in the Z direction, are respectively observed, it can be seen that the different word line material layers in the embedded word line structure 130 are in direct contact with the word line conductive plugs 140.

Obviously, for the polysilicon material of the second word line material layer with the rugged top surface in the embedded word line structure, the preparation method adopted in the embodiment of the invention directly etches the polysilicon material to form the second word line material layer 132 with the gap 102 shown in fig. 5, instead of performing chemical mechanical polishing to planarize the surface, and then etching to form the second word line material layer 132 with the gap 102.

In other embodiments, the etched-back second word line material layer 132 has a void 102, 102 with a cross-sectional shape along the horizontal direction that is "V" shaped (not shown).

In the embodiment of the present invention, only a part of the embedded word line structures 130 are correspondingly formed with the word line conductive plugs 140, and the shapes of the voids in the second word line material layers 132 in the embedded word line structures 130 correspondingly formed with the word line conductive plugs 140 need to be arranged in an inverted "ladder" shape (a cross-sectional shape along the horizontal direction), and the voids in the second word line material layers 132 in the other embedded word line structures 130 may or may not be arranged.

In summary, in the semiconductor device and the method for manufacturing the same according to the embodiments of the present invention, a gap is provided in the second word line material layer of the buried word line structure, in which the bottom portion of the gap exposes the first word line material layer, so that the word line conductive plug extends into the gap and directly contacts the first word line material layer under the second word line material layer, thereby achieving the purpose of enhancing the contact between the word line conductive plug and the buried word line structure.

In addition, the top surface of the second word line material layer is uneven, so that in the preparation process of the embedded word line structure, only an etching process is needed to form a gap in the second word line material layer, namely, one grinding and manufacturing process is saved, and further, the production efficiency is improved and the production cost of the semiconductor device is reduced.

It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

In this specification, each embodiment is described in a related manner, and identical and similar parts of each embodiment are all referred to each other, and each embodiment mainly describes differences from other embodiments. In particular, for apparatus, electronic devices, and computer-readable storage medium embodiments, the description is relatively simple, as it is substantially similar to method embodiments, with reference to portions of the description of method embodiments being relevant.

The foregoing description is only of the preferred embodiments of the present invention and is not intended to limit the scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention are included in the protection scope of the present invention.

Claims (15)

1. A method of manufacturing a semiconductor memory device, comprising:

a substrate;

shallow trench isolation arranged in the substrate and surrounding the plurality of active areas;

a plurality of buried word line structures spanning the plurality of active regions, and the buried word line structures comprising:

a first word line material layer

A second word line material layer located over the first word line material layer;

at least one word line conductive plug, the length of the word line conductive plug in direct contact with the first word line material layer in the horizontal direction is smaller than the length of the first word line material layer in the horizontal direction.

2. The method of manufacturing a semiconductor memory device according to claim 1, wherein the step of forming the buried word line structure comprises:

forming a plurality of word line trenches extending in the horizontal direction and arranged at intervals in the active region and the shallow trench isolation;

sequentially forming a first word line material layer and a second word line material layer in each word line trench, wherein the second word line material layer fills the word line trenches and extends to cover a substrate between two adjacent word line trenches, and the top surface of the second word line material layer covered on the substrate is in an uneven shape;

and etching the second word line material layer back to form the embedded word line structure in the word line trench, wherein the etched second word line material layer has a gap therein and exposes the first word line material layer.

3. The method of manufacturing a semiconductor memory device according to claim 2, wherein the voids in the plurality of buried word line structures have an inverted "ladder" shape in cross-section along the horizontal direction.

4. The method for manufacturing a semiconductor memory according to claim 3, wherein a length of a bottom of the inverted "ladder" shape is smaller than a length of the first word line material layer in the buried word line structure in the horizontal direction.

5. The method for manufacturing a semiconductor memory according to claim 2, wherein the voids in the plurality of buried word line structures have a "V" shape in cross section in the horizontal direction.

6. The method of manufacturing a semiconductor memory device according to claim 2, wherein after forming the plurality of word line trenches in the active region and the shallow trench isolation, and before forming the first word line material layer, the method further comprises:

a first insulating layer is formed on the sidewalls and bottom of each of the word line trenches.

7. A semiconductor memory device, comprising:

a substrate;

shallow trench isolation arranged in the substrate and surrounding the plurality of active areas;

a plurality of buried word line structures spanning the plurality of active regions, and the buried word line structures comprising:

a first word line material layer

A second word line material layer located over the first word line material layer;

at least one word line conductive plug, the length of the word line conductive plug in direct contact with the first word line material layer in the horizontal direction is smaller than the length of the first word line material layer in the horizontal direction.

8. The semiconductor memory according to claim 7, wherein the second word line material layer has a void therein.

9. The semiconductor memory according to claim 8, wherein the voids in the plurality of buried word line structures have an inverted "ladder" shape in cross-section along the horizontal direction.

10. The semiconductor memory according to claim 9, wherein a length of a bottom of the inverted "ladder" shape is smaller than a length of the first word line material layer in the horizontal direction.

11. The semiconductor memory according to claim 8, wherein a cross-sectional shape of the void in the plurality of buried word line structures in the horizontal direction is "V" shaped.

12. A semiconductor memory device, comprising:

a substrate;

shallow trench isolation arranged in the substrate and surrounding the plurality of active areas;

a plurality of buried word line structures spanning the plurality of active regions, and the buried word line structures comprising:

a first word line material layer, comprising:

a metal layer; and

a barrier layer surrounding the metal layer;

a second word line material layer located over the first word line material layer;

at least one word line conductive plug in direct contact with the first word line material layer;

the distance between the second word line material layer surface in the vertical direction and the barrier layer is a first distance, the distance between the second word line material layer surface in the vertical direction and the metal layer is a second distance, and the first distance is different from the second distance.

13. The semiconductor memory according to claim 12, wherein the second word line material layer includes:

a first polysilicon layer; and

a second polysilicon layer;

wherein the word line conductive plug is filled between the first polysilicon layer and the second polysilicon layer.

14. The semiconductor memory according to claim 12, wherein the second word line material layer includes:

a first polysilicon layer; and

a second polysilicon layer;

the first polysilicon layer is not in direct contact with the second polysilicon layer.

15. A semiconductor memory device, comprising:

a substrate;

shallow trench isolation arranged in the substrate and surrounding the plurality of active areas;

a plurality of buried word line structures spanning the plurality of active regions, and the buried word line structures comprising:

a first word line material layer

A second word line material layer located over the first word line material layer;

at least one word line conductive plug in direct contact with the first word line material layer;

wherein a height between the word line conductive plug top surface and the first word line material layer in a vertical direction is greater than a height between the word line conductive plug top surface and the second word line material layer.