CN117729770A - Semiconductor memory and preparation method thereof - Google Patents
Semiconductor memory and preparation method thereof Download PDFInfo
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- CN117729770A CN117729770A CN202311744698.3A CN202311744698A CN117729770A CN 117729770 A CN117729770 A CN 117729770A CN 202311744698 A CN202311744698 A CN 202311744698A CN 117729770 A CN117729770 A CN 117729770A
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- Semiconductor Memories (AREA)
Abstract
The invention provides a semiconductor memory and a preparation method thereof, which are applied to the technical field of semiconductors. Specifically, the upper surface of the first part of the first work function material layer in the embedded word line structure is lower than the upper surface of the second part of the first work function material layer, and the second work function material layer is not arranged on the upper surface of the first part of the first work function material layer, so that the word line conductive plug can be in direct contact with the first work function material layer, the fact that the second work function material layer is not remained at the bottom corner and other positions of the word line conductive plug is ensured, the contact between the word line conductive plug and the embedded word line structure is enhanced, the production efficiency is improved, and the production cost of a device is reduced.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a semiconductor memory and a preparation method thereof.
Background
Dynamic Random Access Memory (DRAM) is a type of volatile memory. DRAM devices typically include a memory region comprised of an array of memory cells, and a peripheral region comprised of control circuitry. The control circuit in the peripheral region may address each memory cell in the memory region by crossing a plurality of column word lines (word lines) and a plurality of row bit lines (bit lines) of the memory region and electrically connect with each memory cell to perform reading, writing or erasing of data.
In advanced semiconductor manufacturing, the chip size of a DRAM device can be greatly reduced by adopting the architecture of an embedded word line or an embedded bit line, but the performance of the DRAM device is easily affected due to materials and/or processes used in forming the embedded word line.
Disclosure of Invention
The invention aims to provide a semiconductor memory and a preparation method thereof, which are used for ensuring that a second work function material layer cannot be remained at the bottom corner and the like of a word line conductive plug, enhancing the contact between the word line conductive plug and a buried word line structure, improving the production efficiency and reducing the production cost of devices.
In order to solve the above technical problem, the present invention provides a semiconductor memory, which at least includes:
a substrate;
an insulating structure disposed in the substrate and disposed adjacent to the plurality of fin structures, the insulating structure including a first insulating structure having a first width in a horizontal direction and a second insulating structure having a second width in the horizontal direction, the first width being greater than the second width;
a buried word line structure extending across the fin structures, the insulating structure and in a horizontal direction in the substrate, and comprising:
a first work function material layer comprising:
a first portion located on the first insulating structure; and
a second portion on the second insulating structure, and an upper surface of the first portion is lower than an upper surface of the second portion in a vertical direction;
and a word line conductive plug in direct contact with the first portion of the first work function material layer.
In some of these alternative examples, the fin structure includes:
a first fin structure disposed between adjacent first and second insulating structures;
and the second fin-shaped structures are arranged between the adjacent second insulating structures, and the width of the first fin-shaped structures in the horizontal direction is larger than that of the second fin-shaped structures in the horizontal direction.
In some alternative examples, the bottom profile of the first insulating structure is semi-arc shaped protruding towards the direction approaching the upper surface of the substrate.
In some of these alternative examples, the distance between the top surface and the bottom surface of the first portion of the first work function material layer is less than the distance between the top surface and the bottom surface of the second portion of the first work function material layer.
In some of these alternative examples, the upper surface profile of the first portion of the first work function material layer is arc-shaped recessed toward a direction proximate to the bottom surface of the first insulating structure.
In some of these optional examples, an interface of the first portion and the second portion of the first work function material layer is located on the first fin structure, and an upper surface of the first work function material layer at the interface is in a gradually decreasing slope shape in a horizontal direction from the first fin structure to the first insulating structure.
In some of these alternative examples, the buried word line structure further includes:
and a second work function material layer over a second portion of the first work function material layer, and having a work function less than a work function of the first work function material layer.
In some of these alternative examples, the sidewall of the second work function material layer is located above the first fin structure, and the sidewall thereof is tapered in a horizontal direction from the second fin structure to the first fin structure.
In some of these alternative examples, the first work function material layer has a thickness within the first insulating structure and in a vertical direction that is not less than a thickness above the second fin structure and in a vertical direction.
In a second aspect, to achieve the above object, and based on the same inventive concept, the present invention also provides a method for manufacturing a semiconductor memory, comprising:
a substrate;
an insulating structure disposed in the substrate and disposed adjacent to the plurality of fin structures, the insulating structure including a first insulating structure having a first width in a horizontal direction and a second insulating structure having a second width in the horizontal direction, the first width being greater than the second width;
a buried word line structure extending across the fin structures, the insulating structure and in a horizontal direction in the substrate, and comprising:
a first work function material layer comprising:
a first portion located on the first insulating structure; and
a second portion on the second insulating structure, and an upper surface of the first portion is lower than an upper surface of the second portion in a vertical direction;
and a word line conductive plug in direct contact with the first portion of the first work function material layer.
In some of these alternative examples, the buried word line structure further includes:
and a second work function material layer over a second portion of the first work function material layer, and having a work function less than a work function of the first work function material layer.
In some of these alternative examples, the step of forming the buried word line structure includes:
forming a groove extending in the horizontal direction in the substrate;
sequentially forming a first work function material layer and a second work function material layer in the groove;
removing a portion of the height of the second work function material layer over a first portion of the first work function material layer; and
the second work function material layer remaining on the first portion of the first work function material layer and a portion of the first work function material layer of a height are further removed.
In some of these alternative examples, the process of removing the first work function material layer and the second work function material layer includes an etching process.
In some of these alternative examples, the distance between the top surface and the bottom surface of the first portion of the first work function material layer is less than the distance between the top surface and the bottom surface of the second portion of the first work function material layer.
In some of these alternative examples, after removing the remaining second work function material layer and a portion of the height of the first work function material layer on the first portion of the first work function material layer, an upper surface profile of the first portion of the remaining first work function material layer is in an arc shape recessed toward a direction approaching the bottom surface of the first insulating structure.
In some of these alternative examples, after removing the remaining second work function material layer and a portion of the height of the first work function material layer on the first portion of the first work function material layer, sidewalls of the remaining second work function material layer are tapered in a horizontal direction from the second insulating structure to the first insulating structure.
Compared with the prior art, the technical scheme provided by the invention has at least one of the following beneficial effects:
the upper surface of the first part of the first work function material layer in the embedded word line structure is lower than the upper surface of the second part of the first work function material layer, and the second work function material layer is not arranged on the upper surface of the first part of the first work function material layer, so that the word line conductive plug can be in direct contact with the first work function material layer, the fact that the second work function material layer is not remained at the corners at the bottom of the word line conductive plug is ensured, the contact between the word line conductive plug and the embedded word line structure is enhanced, the production efficiency is improved, and the production cost of a device is reduced.
In addition, in the preparation process of the embedded word line structure, the first part of the first work function material layer is ensured to have no residue of the second work function material layer, and further, the bottom corner of the word line conductive plug formed later is ensured to have no residue of the second work function material layer, so that the method has the advantages of simple process, high production efficiency and low device manufacturing cost.
Drawings
Fig. 1 is a cross-sectional view of a semiconductor memory provided in an embodiment of the present invention;
fig. 2 is another cross-sectional view of a semiconductor memory provided in an embodiment of the present invention;
fig. 3 is another cross-sectional view of a semiconductor memory provided in an embodiment of the present invention;
fig. 4 to fig. 7 are schematic structural diagrams of a method for manufacturing a semiconductor memory according to an embodiment of the invention in a manufacturing process.
Wherein, the reference numerals are as follows:
100-substrate;
the bottom surface of BS-substrate 100;
STI-insulating structure;
STI 1-a first insulating structure;
STI 2-second insulating structure;
STI 3-third insulating structure;
an AR-fin structure;
AR 1-a first fin structure;
AR 2-a second fin structure;
AR 3-third fin structure;
110-buried word line structure;
111-a first work function material layer;
112-a second work function material layer;
111.1-a first portion of the first work function material layer 111;
111.2-a second portion of the first work function material layer 111;
s1-an upper surface of the first portion 111.1 of the first work function material layer 111;
s2-an upper surface of the second portion 111.2 of the first work function material layer 111;
BS1—the bottom surface of the first portion 111.1 of the first work function material layer 111;
BS 2-bottom surface of the second portion 111.2 of the first work function material layer 111;
BS 3-bottom surface of the first insulating structure STI 1;
the interface of the first portion 111.1 of the INT1/INT 2-first work function material layer 111 with its second portion 111.2;
h1—distance between the upper surface S1 and the bottom surface BS1 of the first portion 111.1 of the first work function material layer 111;
h2—distance between the upper surface S2 and the bottom surface BS2 of the second portion 111.2 of the first work function material layer 111;
h3—the thickness of the first work function material layer 111 above the second fin structure AR2 and in the vertical direction D2;
CT-word line conductive plugs;
d1-horizontal direction;
d2-vertical direction;
d1—a first width of the first insulating structure STI1 in the horizontal direction D1;
d2—a second width of the second insulating structure STI2 in the horizontal direction D1;
d3—the width of the first fin structure AR1 in the horizontal direction D1;
d4—width of the second fin structure AR2 in the horizontal direction D1;
d5—the width of the third fin structure AR3 in the horizontal direction D1;
120-patterned photoresist layer.
Detailed Description
In order to make the technical scheme and advantages of the embodiments of the present invention more clear, the technical scheme of the present invention will be further described in detail below with reference to the accompanying drawings and the embodiments. While exemplary embodiments of the invention are shown in the drawings, it should be understood that the invention may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.
The invention is more particularly described by way of example in the following paragraphs with reference to the drawings. Advantages and features of the invention will become more apparent from the following description and from the claims. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention. It is to be understood that the meanings of "on … …", "over … …" and "over … …" in the present invention are to be interpreted in the broadest sense so that "on … …" means not only that it is "on" something with no intervening features or layers therebetween (i.e., directly on something), but also that it is "on" something with intervening features or layers therebetween.
Further, spatially relative terms such as "on … …," "above … …," "above … …," "upper" and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated for ease of description. In addition to the orientations depicted in the drawings, the spatially relative terms are intended to encompass different orientations of the device in use or operation. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
In embodiments of the present invention, the terms "first," "second," and the like are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. The technical schemes described in the embodiments of the present invention may be arbitrarily combined without any collision.
For convenience of understanding, a horizontal direction D1 and a vertical direction D2 are defined hereinafter, wherein the horizontal direction D1 is a direction parallel to the surface of the substrate 100; the vertical direction D2 is a direction perpendicular to the surface of the substrate 100.
Referring to fig. 1 to 3, fig. 1 is a schematic structural diagram of a semiconductor memory according to an embodiment of the present invention, fig. 2 is another cross-sectional view of the semiconductor memory according to an embodiment of the present invention, and fig. 3 is a cross-sectional view of the semiconductor memory after the junction between the first portion 111.1 and the second portion 111.2 of the first work function material layer 111 in fig. 2 and fig. 1 is disposed at other positions on the first fin structure AR 1.
As shown in fig. 1 to 3, the semiconductor memory includes a substrate 100, a plurality of insulating structures STI, a plurality of fin structures AR, a buried word line structure 110, and a word line conductive plug CT for electrically connecting the buried word line structure 110 disposed on the substrate 100.
In some embodiments, a plurality of insulating structures STI for isolating adjacent fin structures AR are disposed on the substrate 100 in an adjacent arrangement with the fin structures AR, and the plurality of insulating structures STI may be specifically divided into a first insulating structure STI1, a second insulating structure STI2, and a third insulating structure STI3 according to a width difference thereof in the horizontal direction D1, wherein the width of the first insulating structure STI1 is a first width D1, the width of the second insulating structure STI2 is a second width D2, and D1> D2. Similarly, the fin structures AR may be divided into a first fin structure AR1, a second fin structure AR2, and a third fin structure AR3 according to a width difference thereof in the horizontal direction D1, wherein the width of the first fin structure AR1 in the horizontal direction D1 is D3, the width of the second fin structure AR2 in the horizontal direction D1 is D4, the width of the third fin structure AR3 in the horizontal direction D1 is D5, and D5> D3> D4.
Specifically, the first fin structure AR1 is specifically located between the first insulating structure STI1 and the second insulating structure STI2 that are adjacently disposed, the second fin structures AR2 are arranged in pairs in the horizontal direction D1, two second fin structures AR2 that are arranged in pairs are specifically located between the second insulating structures STI2 that are adjacently disposed, the third fin structure AR3 is specifically located below the two second fin structures AR2 that are arranged in pairs in the vertical direction D2 and is communicated with bottoms of the two second fin structures AR2, and is located between the adjacent second insulating structures AR2 together with the two second fin structures AR2 that are arranged in pairs in the horizontal direction D1.
It will be appreciated that, for simplicity of drawing, the bottom profile of the first insulation structure STI1 may be a planar structure as shown in fig. 1, but is not limited thereto, and for conforming to the actual semiconductor manufacturing result, the bottom profile of the first insulation structure STI1 should be a semicircular arc shape protruding toward the upper surface of the substrate 100 as shown in fig. 2, but is not limited thereto.
In some embodiments, the buried word line structure 110 spans the first fin structures AR1, the second fin structures AR2, the third fin structures AR3, the first insulating structures STI1, the second insulating structures STI2, and the third insulating structures STI3 in the horizontal direction D1 and is disposed in the trench in the substrate 100 to bury the fin structures and the insulating structures.
Wherein the buried word line structure 110 may specifically include a first work function material layer 111 and a second work function material layer 112 stacked along a bottom surface BS remote from the substrate 100; the first work function material layer 111 may be specifically divided into a first portion 111.1 and a second portion 111.2 along the horizontal direction D1, the first portion 111.1 of the first work function material layer 111 is located on at least a portion of the top surface of the first insulating structure STI1 and the first fin structure AR1 adjacent to the first insulating structure STI1, the second portion 111.2 of the first work function material layer 111 is located on the second insulating structure STI2, the third insulating structure STI3, and the second and third fin structures AR2 and AR3, and the upper surface S1 of the first portion 111.1 of the first work function material layer 111 is lower than the upper surface S2 of the second portion 111.2 of the first work function material layer 111 in the vertical direction D2, in other words, the distance H1 between the upper surface S1 of the first portion 111.1 of the first work function material layer 111 and the bottom surface BS1 is smaller than the distance H2 between the upper surface S2 of the second portion 111.2 of the first work function material layer 111 and the bottom surface BS 2.
Further, the upper surface profile of the first portion 111.1 of the first work function material layer 111 may be an arc shape recessed toward the direction close to the bottom surface BS3 of the first insulating structure STI1, and the junction between the first portion 111.1 of the first work function material layer 111 and the second portion 111.2 thereof is located on the first fin structure AR1, and the upper surface of the first work function material layer 111 at the junction is in a gradually decreasing slope shape in the horizontal direction D1 from the first fin structure AR1 to the first insulating structure STI 1.
It is understood that, since the first fin structure AR1 has a width D3 in the horizontal direction D1 and D3>0, the boundary between the first portion 111.1 of the first work function material layer 111 and the second portion 111.2 thereof on the first fin structure AR1 may be specifically disposed on the top surface of the first fin structure AR1 near the second portion 111.2 of the first work function material layer 111, such as INT1 shown in fig. 1 or fig. 2, or may be disposed on the top surface of the first fin structure AR1 near the first portion 111.1 of the first work function material layer 111, such as INT2 shown in fig. 3, or may be disposed anywhere else on the top surface of the first fin structure AR1, which is not specifically limited by the present invention.
Further, a thickness H1 of the first work function material layer 111 in the vertical direction D2 located within the first insulating structure STI1 is not smaller than a thickness H3 in the vertical direction D2 located above the second fin structure AR 2.
Further, the second work function material layer 112 is specifically located above the second portion 111.2 of the first work function material layer 111, and the work function of the second work function material layer 112 is smaller than the work function of the first work function material layer 111; the sidewall of the second work function material layer 112 is located above the first fin structure AR1, and the sidewall thereof is in a gradually decreasing slope shape in the horizontal direction D1 from the second fin structure AR2 to the first fin structure AR1, that is, the shape of the boundary INT1 (or the boundary INT 2) between the first portion 111.1 and the second portion 111.2 of the first work function material layer 111 and the sidewall of the second work function material layer 112 stacked above the second portion 111.2 of the first work function material layer 111 in the horizontal direction D1 is similar.
Obviously, since the word line conductive plug CT in the embodiment of the present invention is specifically formed in the upper area of the first portion 111.1 of the first work function material layer 111, and the upper surface S1 of the first portion 111.1 of the first work function material layer 111 in the vertical direction D2 is lower than the upper surface S2 of the second portion 111.2 of the first work function material layer 111, and the second work function material layer 112 covers only the first portion 111.1 of the first work function material layer 111, the purpose that the word line conductive plug CT can be in direct contact with the exposed first portion 111.1 of the first work function material layer 111, that is, the contact between the word line conductive plug and the buried word line structure is enhanced is ensured.
In some embodiments, the base 100 is any suitable substrate material known in the art, such as, but not limited to, a silicon substrate, a silicon-containing substrate (e.g., siC, siGe), or a silicon-on-insulator substrate (silicon-on-insulator substrate), or a substrate made of other suitable materials; the materials of the first, second and third insulating structures STI1, STI2 and STI3 may include single or multiple layers of insulating materials such as oxide insulating materials, nitride insulating materials or other suitable insulating materials, but are not limited thereto; the material of the first work function material layer 111 in the buried word line structure 110 may include a single layer or multiple layers of conductive materials, such as, but not limited to, titanium nitride, titanium carbide, tantalum nitride, tantalum carbide, tungsten nitride, tungsten carbide, titanium aluminide, aluminum nitride, titanium, tungsten, aluminum, copper, titanium, tantalum, or other suitable metallic or non-metallic conductive materials; the material of the second work function material layer 112 may include doped polysilicon, undoped polysilicon, or other materials different from the conductive layer, but is not limited thereto.
In order to enable a person skilled in the art to easily understand the semiconductor device according to the embodiments of the present invention, a method for manufacturing the semiconductor device according to the present invention will be further described below.
Referring to fig. 4 to 7, fig. 4 to 7 are schematic structural diagrams of a method for manufacturing a semiconductor memory according to an embodiment of the invention in a manufacturing process.
As shown in fig. 4, the method for manufacturing the semiconductor memory according to the embodiment of the invention may include the following steps: providing a substrate 100, forming a plurality of trenches sequentially arranged at intervals along a horizontal direction D1 in the substrate 100 by a dry etching process or a wet etching process, defining a plurality of fin structures AR sequentially arranged at intervals along the horizontal direction D1 and having different widths by the plurality of trenches, and then etching down along a vertical direction D2 to remove part of the heights of the fin structures AR, thereby forming a plurality of first fin structures AR1, a plurality of second fin structures AR2, and a plurality of third fin structures AR3, wherein a width D3 of the first fin structures AR1 in the horizontal direction D1 is greater than a width D4 of the second fin structures AR2 in the horizontal direction D1, and a width D5 of the third fin structures AR3 in the horizontal direction D1 is greater than a width D3 of the first fin structures AR1 in the horizontal direction D1, i.e., D5> D3> D4.
Further, insulating materials, such as silicon dioxide or silicon nitride, are filled between two adjacent first fin structures AR1, two adjacent second fin structures AR2, and two adjacent second fin structures AR2 with partially connected bottoms, which are included in a third fin structure AR3, by using deposition processes, such as physical vapor deposition, chemical vapor deposition, atomic layer deposition, etc., so as to form a plurality of insulating structures STI between the first fin structures AR1, the second fin structures AR2, and the third fin structures AR3, wherein the upper surfaces of the insulating structures STI are lower than the upper surfaces of the first fin structures AR1, the second fin structures AR2, and the third fin structures AR 3.
Specifically, the plurality of insulation structures STI may be specifically divided into a first insulation structure STI1 having a first width D1 in the horizontal direction D1 and a second insulation structure STI2 having a second width D2 in the horizontal direction D1, and a third insulation structure STI3, where the first width D1 is greater than the second width D2, the first fin structure AR1 is specifically located between the first insulation structure STI1 and the second insulation structure STI2 that are adjacently disposed, the second fin structure AR2 is arranged in pairs in the horizontal direction D1, two second fin structures AR2 that are arranged in pairs are specifically located between the adjacent second insulation structures STI2, and the third fin structure AR3 is specifically located below the two second fin structures AR2 that are arranged in pairs in the vertical direction D2, is in communication with the bottoms of the two second fin structures AR2, and is located between the two adjacent second fin structures AR2 that are arranged in pairs in the horizontal direction D1.
Further, the deposition process is further utilized to continue depositing the stacked first work function material layer 111, second work function material layer 112 and patterned photoresist layer 120 in the trenches where the first fin structure AR1, the second fin structure AR2, the third fin structure AR3, the first insulating structure STI1, the second insulating structure STI2 and the third insulating structure STI3 are formed, wherein the patterned photoresist layer 120 exposes the top surface of the second work function material layer 112 above the first fin structure AR1 and the first insulating structure STI1 adjacent thereto, the material of the second work function material layer 112 may be polysilicon, and the material of the first work function material layer 111 may be tungsten metal.
As shown in fig. 5 and 6, the second work function material layer 112 is removed by an etching process, such as a dry etching process, along a vertical direction D2, and then the etched second work function material layer 112 near the sidewall of the patterned photoresist layer 120, that is, the surface of the second work function material layer 112 is gradually reduced in a slope shape in a horizontal direction D1 from the first fin structure AR1 to the first insulating structure STI1, and then the patterned photoresist layer 120 may be etched or cleaned.
As shown in fig. 6 and 7, the etching process, such as a dry etching process, is continuously utilized, and the second work function material layer 112 on the slope shape gradually decreasing from the first fin structure AR1 to the horizontal direction D1 of the first insulating structure STI1 is completely removed along the vertical direction D2 while the first work function material layer 111 with a part of the thickness being located on the plurality of second fin structures AR2, the plurality of third fin structures AR3, the plurality of second insulating structures STI2 and the plurality of second work function material layers 112 on the plurality of third insulating structures STI3 are removed along the vertical direction D2, so that the first work function material layer 111 with a part of the thickness being located on the lower side of the first work function material layer 111 is obtained, that is, the first work function material layer 111 with a part of the height being different on the upper surface in different positions of the different areas on the horizontal direction D1 is specifically divided into the first part 111.1 and the second part 111.2 along the horizontal direction D1, and the upper surface of the first work function material layer 111.1 of the first part 111.1 is lower than the first work function material layer 111.1 of the second work function material layer 111.2 located on the upper part of the second work function material layer 111.2.
Thereafter, an interlayer dielectric layer (not shown) may be further formed on the substrate 100 by a deposition process, and the interlayer dielectric layer may be etched, thereby forming a word line contact plug CT directly contacting the first portion 111.1 of the first work function material layer 111.
It should be noted that fig. 1 to 7 in the embodiments of the present invention only illustrate the points related to the semiconductor device and the method for manufacturing the same, but may also include other components, such as a stress layer and a bit line, but are not limited thereto.
In summary, by making the upper surface of the first portion of the first work function material layer lower than the upper surface of the second portion of the first work function material layer in the embedded word line structure, and not disposing the second work function material layer on the upper surface of the first portion of the first work function material layer, the word line conductive plug can be directly contacted with the first work function material layer, so that no second work function material layer remains at the bottom corner of the word line conductive plug, and the like, contact between the word line conductive plug and the embedded word line structure is enhanced, production efficiency is improved, and device production cost is reduced.
In addition, in the preparation process of the embedded word line structure, the first part of the first work function material layer is ensured to have no residue of the second work function material layer, and further, the bottom corner of the word line conductive plug formed later is ensured to have no residue of the second work function material layer, so that the method has the advantages of simple process, high production efficiency and low device manufacturing cost.
It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
In this specification, each embodiment is described in a related manner, and identical and similar parts of each embodiment are all referred to each other, and each embodiment mainly describes differences from other embodiments. In particular, for apparatus, electronic devices, and computer-readable storage medium embodiments, the description is relatively simple, as it is substantially similar to method embodiments, with reference to portions of the description of method embodiments being relevant.
The foregoing description is only of the preferred embodiments of the present invention and is not intended to limit the scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention are included in the protection scope of the present invention.
Claims (16)
1. A semiconductor memory device, comprising:
a substrate;
an insulating structure disposed in the substrate and disposed adjacent to the plurality of fin structures, the insulating structure including a first insulating structure having a first width in a horizontal direction and a second insulating structure having a second width in the horizontal direction, the first width being greater than the second width;
a buried word line structure extending across the fin structures, the insulating structure and in a horizontal direction in the substrate, and comprising:
a first work function material layer comprising:
a first portion located on the first insulating structure; and
a second portion on the second insulating structure, and an upper surface of the first portion is lower than an upper surface of the second portion in a vertical direction;
and a word line conductive plug in direct contact with the first portion of the first work function material layer.
2. The semiconductor memory of claim 1, wherein the fin structure comprises:
a first fin structure disposed between adjacent first and second insulating structures;
and the second fin-shaped structures are arranged between the adjacent second insulating structures, and the width of the first fin-shaped structures in the horizontal direction is larger than that of the second fin-shaped structures in the horizontal direction.
3. The semiconductor memory according to claim 1, wherein a bottom profile of the first insulating structure is in a semicircular arc shape protruding toward a direction approaching an upper surface of the substrate.
4. The semiconductor memory according to claim 2, wherein a distance between an upper surface and a bottom surface of the first portion of the first work function material layer is smaller than a distance between an upper surface and a bottom surface of the second portion of the first work function material layer.
5. The semiconductor memory according to claim 4, wherein an upper surface profile of the first portion of the first work function material layer is arc-shaped recessed toward a direction approaching a bottom surface of the first insulating structure.
6. The semiconductor memory according to claim 5, wherein an intersection of the first portion and the second portion of the first work function material layer is located on the first fin structure, and an upper surface of the first work function material layer at the intersection is tapered in a horizontal direction from the first fin structure to the first insulating structure.
7. The semiconductor memory according to claim 2, wherein the buried word line structure further comprises:
and a second work function material layer over a second portion of the first work function material layer, and having a work function less than a work function of the first work function material layer.
8. The semiconductor memory according to claim 7, wherein a sidewall of the second work function material layer is located above the first fin structure, and the sidewall thereof is tapered in a horizontal direction from the second fin structure to the first fin structure.
9. The semiconductor memory of claim 2, wherein a thickness of the first work function material layer in a vertical direction within the first insulating structure is not less than a thickness in a vertical direction above the second fin structure.
10. A method of manufacturing a semiconductor memory device, comprising:
a substrate;
an insulating structure disposed in the substrate and disposed adjacent to the plurality of fin structures, the insulating structure including a first insulating structure having a first width in a horizontal direction and a second insulating structure having a second width in the horizontal direction, the first width being greater than the second width;
a buried word line structure extending across the fin structures, the insulating structure and in a horizontal direction in the substrate, and comprising:
a first work function material layer comprising:
a first portion located on the first insulating structure; and
a second portion on the second insulating structure, and an upper surface of the first portion is lower than an upper surface of the second portion in a vertical direction;
and a word line conductive plug in direct contact with the first portion of the first work function material layer.
11. The method of manufacturing a semiconductor memory device according to claim 10, wherein the buried word line structure further comprises:
and a second work function material layer over a second portion of the first work function material layer, and having a work function less than a work function of the first work function material layer.
12. The method of manufacturing a semiconductor memory device according to claim 11, wherein the step of forming the buried word line structure comprises:
forming a groove extending in the horizontal direction in the substrate;
sequentially forming a first work function material layer and a second work function material layer in the groove;
removing a portion of the height of the second work function material layer over a first portion of the first work function material layer; and
the second work function material layer remaining on the first portion of the first work function material layer and a portion of the first work function material layer of a height are further removed.
13. The method of manufacturing a semiconductor memory according to claim 12, wherein the process of removing the first work function material layer and the second work function material layer includes an etching process.
14. The method of manufacturing a semiconductor memory according to claim 10, wherein a distance between an upper surface and a bottom surface of the first portion of the first work function material layer is smaller than a distance between an upper surface and a bottom surface of the second portion of the first work function material layer.
15. The method of manufacturing a semiconductor memory device according to claim 13, wherein after removing the remaining second work function material layer and a part of the first work function material layer in height on the first portion of the first work function material layer, an upper surface profile of the remaining first portion of the first work function material layer is in an arc shape recessed toward a direction approaching a bottom surface of the first insulating structure.
16. The method of manufacturing a semiconductor memory device according to claim 14, wherein after removing the remaining second work function material layer and a part of the height of the first work function material layer on the first portion of the first work function material layer, sidewalls of the remaining second work function material layer are tapered gradually decreasing in a horizontal direction from the second insulating structure to the first insulating structure.
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