CN117253795A - Manufacturing method of LDMOS device structure - Google Patents

Manufacturing method of LDMOS device structure Download PDF

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Publication number
CN117253795A
CN117253795A CN202311255494.3A CN202311255494A CN117253795A CN 117253795 A CN117253795 A CN 117253795A CN 202311255494 A CN202311255494 A CN 202311255494A CN 117253795 A CN117253795 A CN 117253795A
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layer
region
forming
substrate
device structure
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许昭昭
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Hua Hong Semiconductor Wuxi Co Ltd
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Hua Hong Semiconductor Wuxi Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/7823—Lateral DMOS transistors, i.e. LDMOS transistors with an edge termination structure

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
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  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Composite Materials (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The invention provides a manufacturing method of an LDMOS device structure, which comprises the steps of providing a substrate of a first conductivity type, forming a local field oxide layer on the substrate to define an active region, forming a drift region of a second conductivity type in the active region by utilizing ion implantation, wherein the active region between the drift regions of the second conductivity type is a channel region, the channel region is a region for forming the source region, and one end of the drift region far away from the channel region is a region for forming a drain region; forming a first photoresist layer on the substrate, and photoetching to open the first photoresist layer above the drift region to form a comb-shaped structure, so that the opening area from the channel region to the drain region is gradually reduced; forming a resurf layer of the first conductivity type under the drift region by ion implantation, wherein the ion implantation concentration of the resurf layer gradually decreases from the channel region to the drain region, and then removing the first photoresist layer; forming a gate dielectric layer and a gate polysilicon layer on the gate dielectric layer on the substrate; a second photoresist layer is formed over the gate polysilicon layer. The device of the invention can improve the overall performance of the device.

Description

Manufacturing method of LDMOS device structure
Technical Field
The invention relates to the technical field of semiconductors, in particular to a manufacturing method of an LDMOS device structure.
Background
DMOS (Double-diffused MOS) is widely used in power management circuits at present due to its characteristics of high voltage resistance, large current driving capability, extremely low power consumption, and the like. In the LDMOS (Lateral DMOS) device, the breakdown voltage, on-resistance of the device is optimized by introducing a laterally uniformly distributed drift region implant 106 and resurf implant 105, but the design has not yet reached an optimization of the device characteristics.
In the conventional LDMOS structure (as shown in fig. 1), taking an N-LDMOS as an example, the reference numerals in fig. 1 are respectively as follows: 101-P-type substrate/P-type epitaxial layer, 102-Field plate dielectric layer/shallow trench isolation (Shallow Trench Isolation, STI), 103-gate dielectric layer, 104-gate polysilicon, 105-P-type resurf (reduced surface electric Field Reduced Surface E-Field) layer implant uniformly distributed laterally, 106-N-drift region implant with gradual linear thickening from channel end to drain end, 107-P-body region implant, 108-sidewall dielectric layer, 109-N-type heavily doped implant, 110-P-type heavily doped implant, 111-metal silicide, 112-ILD etch stop layer (bottom silicon oxide layer, top silicon nitride layer), 113-interlayer dielectric layer (Interlayer Dielectric, ILD), 114-contact via.
For device reliability (especially HCI reliability, hot carrier injection, hot Carriers Injection), hot carrier injection is primarily dependent on the performance of the P-type body region-N-type drift region junction (107-106 junction), so hot carrier injection optimization often involves optimization of the 107-106 junction of the device.
In order to solve the above problems, a new method for manufacturing the LDMOS device structure needs to be proposed.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a method for manufacturing an LDMOS device structure, which is used to solve the problem that in the prior art, in LDMOS (Lateral DMOS) devices, the breakdown voltage and on-resistance of the device are optimized by introducing drift region implantation and resurf implantation which are uniformly distributed laterally, but the design has not yet reached the optimization of the device characteristics.
To achieve the above and other related objects, the present invention provides a method for manufacturing an LDMOS device structure, comprising:
providing a substrate of a first conductivity type, forming a local field oxide layer on the substrate to define an active region, forming a drift region of a second conductivity type in the active region by utilizing ion implantation, wherein the active region between the drift regions of the second conductivity type is a channel region, the channel region is a region for forming the source region, and one end of the drift region far away from the channel region is a region for forming a drain region;
step two, forming a first photoresist layer on the substrate, and photoetching the first photoresist layer above the drift region to form a comb-shaped structure, so that an opening area from the channel region to the drain region is gradually reduced;
forming a resurf layer of a first conductivity type below the drift region by ion implantation, wherein the ion implantation concentration of the resurf layer gradually decreases from the channel region to the drain region, and then removing the first photoresist layer;
forming a gate dielectric layer and a gate polysilicon layer on the gate dielectric layer on the substrate;
forming a second photoresist layer on the gate polysilicon layer, photoetching and opening the second photoresist layer to define the boundary of the gate polysilicon layer in the channel region, and then etching and removing part of the gate polysilicon layer and the gate dielectric layer on the channel region to enable one end of the gate dielectric layer to extend to the channel region and the rest of the channel region to be exposed;
step six, forming a body region of a first conductivity type on the exposed channel region by utilizing ion implantation, and then removing the second photoresist layer;
forming a third photoresist layer covering the gate polysilicon layer on the substrate, photoetching and opening the third photoresist layer to define the boundary of the gate polysilicon layer in the drift region, etching and removing part of the gate polysilicon layer and the gate dielectric layer on the gate region, and then removing the third photoresist layer;
forming a side wall on the side wall of the grid polycrystalline silicon layer;
step nine, forming a first heavy doping region in the source region and the drain region respectively;
step ten, forming metal silicide on the source region, the drain region and the grid dielectric layer;
and eleventh, forming an etching barrier layer on the substrate, forming an interlayer dielectric layer on the etching barrier layer, and forming a contact hole structure for leading out the source region, the drain region and the gate dielectric layer on the interlayer dielectric layer.
Preferably, the substrate in step one comprises a bulk semiconductor substrate or a silicon-on-insulator (SOI) substrate.
Preferably, in the first step, an NLDMOS is formed on the substrate, the first conductivity type is P-type, and the second conductivity type is N-type.
Preferably, in the first step, PLDMOS is formed on the liner, the first conductivity type is N-type, and the second conductivity type is P-type.
Preferably, the ion implantation concentration of the resurf layer in the third step gradually decreases from 1e 17-1 e18cm-3 to 5e 16-5 e17cm-3 from the channel region to the drain region.
Preferably, the etching method in the fifth step is dry etching.
Preferably, the lithography in the fifth step further includes defining gate structures of other devices.
Preferably, the etching method in the seventh step is dry etching.
Preferably, in the eighth step, the material of the side wall is silicon nitride.
Preferably, the method for forming the side wall in the eighth step includes: forming a side wall material layer covering the grid polycrystalline silicon layer on the substrate; and etching the side wall material layer back to form the side wall.
Preferably, the method of etching back in the step eight is dry etching.
Preferably, the method for forming the metal silicide in the step ten comprises the following steps: forming a metal silicide blocking layer on the substrate, and then patterning the metal silicide blocking layer to define the position of the metal silicide; forming a metal layer covering the gate polysilicon layer on the substrate; forming a protective layer on the metal layer; forming the metal silicide on the source region, the drain region and the gate polysilicon by annealing; and removing the remaining protective layer, the metal layer and the metal silicide blocking layer.
Preferably, the material of the metal layer in the step ten is cobalt, titanium, nickel or nickel-platinum alloy.
Preferably, the material of the metal silicide blocking layer in the step ten includes at least one of silicon-rich oxide, siO2, siON, and Si3N 4.
Preferably, in step eleven, the method for forming a contact hole structure for leading out the source, drain and gate dielectric layers on the interlayer dielectric layer includes: forming a photoresist layer on the interlayer dielectric layer; photoetching and opening the photoresist layer to define a contact hole; etching the interlayer dielectric layer to form a contact hole with the bottom end communicated with the source region, the drain region and the grid polysilicon; and forming conductive metal in the contact hole by deposition and grinding.
Preferably, the etching method in the step eleven is dry etching.
Preferably, the conductive metal in step eleven is tungsten.
As described above, the manufacturing method of the LDMOS device structure of the present invention has the following advantages:
the device of the present invention is exemplified by an N-LDMOS having a laterally uniformly distributed N-type drift region implant, with a P-type resurf layer implant (Reduced Surface E-Field) that tapers linearly from the channel end to the drain end. The junction which is more easily used by the resurf layer in an auxiliary way is realized by forming a more concentrated (1 e 17-1 e18cm < -3 >) P-type region below the N-type drift region near the channel end, so that the performance of the junction is improved; and a lighter (5 e 16-5 e17cm < -3 >) P-type region is formed below the N-type drift region near the drain end, so that higher breakdown voltage of the device is realized, and the overall performance of the device is improved.
Drawings
Fig. 1 is a schematic diagram showing a structure of an LDMOS device according to the prior art;
FIG. 2 is a schematic illustration of the process flow of the present invention;
FIG. 3 is a schematic diagram of forming a drift region according to the present invention;
FIG. 4 is a schematic diagram of a photolithography opening of a first photoresist layer according to the present invention;
FIG. 5 is a schematic diagram of a first patterned gate dielectric layer and a gate polysilicon layer according to the present invention;
FIG. 6 is a schematic diagram of a second patterned gate dielectric layer and a gate polysilicon layer according to the present invention;
fig. 7 is a schematic diagram showing the structure of an LDMOS device according to the present invention.
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
Referring to fig. 2, the present invention provides a method for manufacturing an LDMOS device structure, which includes:
providing a substrate 101 of a first conductivity type, forming a local field oxide layer 102 on the substrate 101 to define an active region, forming a drift region 106 of a second conductivity type in the active region by ion implantation, wherein the active region between the drift regions 106 of the second conductivity type is a channel region 107, the channel region 107 is a region for forming the source region, and one end of the drift region 106 away from the channel region 107 is a region for forming a drain region;
for example, referring to fig. 3, the forming method of the drift region 106 includes: after forming the local field oxide layer 102 on the substrate 101, forming a fourth photoresist layer 501 on the substrate 101, opening the fourth photoresist layer by photolithography to define a forming position of the drift region 106, forming the drift region 106 by ion implantation, and removing the fourth photoresist layer 501 by ashing and wet cleaning.
In an alternative embodiment, the substrate 101 in step one comprises a bulk semiconductor substrate or a silicon-on-insulator (SOI) substrate. The SOI substrate includes an insulator layer under a thin semiconductor layer that is an active layer of the SOI substrate. The semiconductor and bulk semiconductor of the active layer typically comprise crystalline semiconductor material silicon, but may also comprise one or more other semiconductor materials such as germanium, silicon germanium alloys, compound semiconductors (e.g., gaAs, alAs, inAs, gaN, alN, etc.) or alloys thereof (e.g., gaxAl1-xAs, gaxAl1-xN, inxGa1-xAs, etc.), oxide semiconductors (e.g., znO, snO2, tiO2, ga2O3, etc.), or combinations thereof. The semiconductor material may be doped or undoped. Other substrates that may be used include multilayer substrates, gradient substrates, or hybrid orientation substrates.
In an alternative embodiment, the substrate 101 in the first step is formed with an NLDMOS, the first conductivity type is P-type, and the second conductivity type is N-type.
In an alternative embodiment, the substrate in step one is formed with a PLDMOS, the first conductivity type being N-type and the second conductivity type being P-type.
Step two, referring to fig. 4, a first photoresist layer 502 is formed on the substrate 101, and the first photoresist layer 502 above the drift region 106 is opened by photolithography to form a comb-shaped structure, so that the opening area from the channel region 107 to the drain region is gradually reduced;
forming a resurf layer 105 of the first conductivity type under the drift region 106 by ion implantation, wherein the ion implantation concentration of the resurf layer 105 gradually decreases from the channel region 107 to the drain region, and then removing the first photoresist layer 502;
in an alternative embodiment, the ion implantation concentration of resurf layer 105 in step three is gradually reduced from 1e 17-1 e18cm-3 to 5e 16-5 e17cm-3 from channel region 107 to the drain region.
Step four, forming a gate dielectric layer 103 and a gate polysilicon layer 104 on the gate dielectric layer 103 on the substrate 101;
step five, forming a second photoresist layer 503 on the gate polysilicon layer 104, opening the second photoresist layer 503 by photolithography to define the boundary of the gate polysilicon layer 104 in the channel region 107, and then etching to remove part of the gate polysilicon layer 104 and the gate dielectric layer 103 on the channel region 107, so that one end of the gate dielectric layer 103 extends to the channel region 107, and the rest of the channel region 107 is exposed to form a structure as shown in fig. 5;
in an alternative embodiment, the method of etching in step five is dry etching.
In an alternative embodiment, the lithography in step five further includes defining gate structures of other devices.
Step six, forming a body region of the first conductivity type on the exposed channel region 107 by ion implantation, and then removing the second photoresist layer 503;
step seven, forming a third photoresist layer 504 covering the gate polysilicon layer 104 on the substrate 101, photoetching and opening the third photoresist layer 504 to define the boundary of the gate polysilicon layer 104 in the drift region 106, etching and removing part of the gate polysilicon layer 104 and the gate dielectric layer 103 on the gate region to form a structure shown in fig. 6, and removing the third photoresist layer 504;
in an alternative embodiment, the method of etching in step seven is dry etching.
Step eight, forming a side wall 108 on the side wall of the gate polysilicon layer 104;
in an alternative embodiment, the material of the sidewall 108 in the eighth step is silicon nitride.
In an alternative embodiment, the method for forming the sidewall 108 in the eighth step includes: forming a side wall 108 material layer covering the gate polysilicon layer 104 on the substrate 101; the sidewall 108 material layer is etched back to form the sidewall 108.
In an alternative embodiment, the method of etching back in step eight is dry etching.
Step nine, forming a first and a second heavily doped regions (110, 109) in the source region and the drain region respectively; for example, when forming an NLDMOS, the first heavily doped region 110 of the source region is a P-type heavily doped implant and the second heavily doped region 109 of the drain region is an N-type heavily doped implant.
Step ten, forming metal silicide 111 on the source and drain regions and the gate dielectric layer 103;
in an alternative embodiment, the method of forming the metal silicide 111 in step ten includes: forming a metal silicide 111 barrier layer on the substrate 101, and then patterning the metal silicide 111 barrier layer to define the position of the metal silicide 111; forming a metal layer covering the gate polysilicon layer 104 on the substrate 101; forming a protective layer on the metal layer; forming metal silicide 111 on the source region, the drain region and the gate polysilicon by annealing; the remaining protective layer, metal layer and metal silicide 111 barrier layer are removed.
In an alternative embodiment, the material of the metal layer in step ten is cobalt, titanium, nickel or nickel platinum alloy.
In an alternative embodiment, the material of the metal silicide 111 barrier layer in step ten comprises at least one of silicon-rich oxide, siO2, siON, and Si3N 4.
Step eleven, forming an etching barrier layer 112 on the substrate 101, then forming an interlayer dielectric layer 113 on the etching barrier layer 112, and then forming a contact hole structure 114 for leading out the source, drain and gate dielectric layers 103 on the interlayer dielectric layer 113, thereby forming the structure shown in fig. 7.
In an alternative embodiment, the method for forming the contact hole structure 114 for extracting the source, drain and gate dielectric layers 103 on the interlayer dielectric layer 113 in the eleventh step includes: forming a photoresist layer on the interlayer dielectric layer 113; photoetching and opening the photoresist layer to define a contact hole; etching the interlayer dielectric layer 113 to form a contact hole with the bottom end communicated with the source region, the drain region and the grid polysilicon; conductive metal is formed in the contact hole by deposition and grinding.
In an alternative embodiment, the method of etching in step eleven is dry etching.
In an alternative embodiment, the conductive metal in step eleven is tungsten.
It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
In summary, the device of the present invention is exemplified by an N-LDMOS device having an N-type drift region implant uniformly distributed laterally, and a P-type resurf implant (Reduced Surface E-Field) that gradually tapers linearly from the channel end to the drain end. The junction which is more easily used by the resurf layer in an auxiliary way is realized by forming a more concentrated (1 e 17-1 e18cm < -3 >) P-type region below the N-type drift region near the channel end, so that the performance of the junction is improved; and a lighter (5 e 16-5 e17cm < -3 >) P-type region is formed below the N-type drift region near the drain end, so that higher breakdown voltage of the device is realized, and the overall performance of the device is improved. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.

Claims (17)

1. The manufacturing method of the LDMOS device structure is characterized by at least comprising the following steps:
providing a substrate of a first conductivity type, forming a local field oxide layer on the substrate to define an active region, forming a drift region of a second conductivity type in the active region by utilizing ion implantation, wherein the active region between the drift regions of the second conductivity type is a channel region, the channel region is a region for forming the source region, and one end of the drift region far away from the channel region is a region for forming a drain region;
step two, forming a first photoresist layer on the substrate, and photoetching the first photoresist layer above the drift region to form a comb-shaped structure, so that an opening area from the channel region to the drain region is gradually reduced;
forming a resurf layer of a first conductivity type below the drift region by ion implantation, wherein the ion implantation concentration of the resurf layer gradually decreases from the channel region to the drain region, and then removing the first photoresist layer;
forming a gate dielectric layer and a gate polysilicon layer on the gate dielectric layer on the substrate;
forming a second photoresist layer on the gate polysilicon layer, photoetching and opening the second photoresist layer to define the boundary of the gate polysilicon layer in the channel region, and then etching and removing part of the gate polysilicon layer and the gate dielectric layer on the channel region to enable one end of the gate dielectric layer to extend to the channel region and the rest of the channel region to be exposed;
step six, forming a body region of a first conductivity type on the exposed channel region by utilizing ion implantation, and then removing the second photoresist layer;
forming a third photoresist layer covering the gate polysilicon layer on the substrate, photoetching and opening the third photoresist layer to define the boundary of the gate polysilicon layer in the drift region, etching and removing part of the gate polysilicon layer and the gate dielectric layer on the gate region, and then removing the third photoresist layer;
forming a side wall on the side wall of the grid polycrystalline silicon layer;
step nine, forming a first heavy doping region in the source region and the drain region respectively;
step ten, forming metal silicide on the source region, the drain region and the grid dielectric layer;
and eleventh, forming an etching barrier layer on the substrate, forming an interlayer dielectric layer on the etching barrier layer, and forming a contact hole structure for leading out the source region, the drain region and the gate dielectric layer on the interlayer dielectric layer.
2. The method of manufacturing an LDMOS device structure of claim 1, wherein: the substrate in step one comprises a bulk semiconductor substrate or a silicon-on-insulator (SOI) substrate.
3. The method of manufacturing an LDMOS device structure of claim 1, wherein: and in the first step, NLDMOS is formed on the substrate, wherein the first conduction type is P type, and the second conduction type is N type.
4. The method of manufacturing an LDMOS device structure of claim 1, wherein: and in the first step, PLDMOS is formed on the liner, wherein the first conductivity type is N type, and the second conductivity type is P type.
5. The method of manufacturing an LDMOS device structure of claim 1, wherein: and in the third step, the ion implantation concentration of the resurf layer is gradually reduced from 1e 17-1 e18cm & lt-3 & gt to 5e 16-5 e17cm & lt-3 & gt from the channel region to the drain region.
6. The method of manufacturing an LDMOS device structure of claim 1, wherein: and step five, the etching method is dry etching.
7. The method of manufacturing an LDMOS device structure of claim 1, wherein: the lithography in the fifth step further includes defining gate structures of other devices.
8. The method of manufacturing an LDMOS device structure of claim 1, wherein: and step seven, the etching method is dry etching.
9. The method of manufacturing an LDMOS device structure of claim 1, wherein: and in the eighth step, the material of the side wall is silicon nitride.
10. The method of manufacturing an LDMOS device structure of claim 1, wherein: the method for forming the side wall in the eighth step comprises the following steps: forming a side wall material layer covering the grid polycrystalline silicon layer on the substrate; and etching the side wall material layer back to form the side wall.
11. The method of manufacturing an LDMOS device structure of claim 10, wherein: and step eight, the etching back method is dry etching.
12. The method of manufacturing an LDMOS device structure of claim 1, wherein: the method for forming the metal silicide in the step ten comprises the following steps: forming a metal silicide blocking layer on the substrate, and then patterning the metal silicide blocking layer to define the position of the metal silicide; forming a metal layer covering the gate polysilicon layer on the substrate; forming a protective layer on the metal layer; forming the metal silicide on the source region, the drain region and the gate polysilicon by annealing; and removing the remaining protective layer, the metal layer and the metal silicide blocking layer.
13. The method of fabricating an LDMOS device structure of claim 12, wherein: the material of the metal layer in the step ten is cobalt, titanium, nickel or nickel-platinum alloy.
14. The method of fabricating an LDMOS device structure of claim 12, wherein: the material of the metal silicide blocking layer in step ten includes at least one of silicon-rich oxide, siO2, siON, and Si3N 4.
15. The method of manufacturing an LDMOS device structure of claim 1, wherein: in the eleventh step, the method for forming a contact hole structure for leading out the source region, the drain region and the gate dielectric layer on the interlayer dielectric layer includes: forming a photoresist layer on the interlayer dielectric layer; photoetching and opening the photoresist layer to define a contact hole; etching the interlayer dielectric layer to form a contact hole with the bottom end communicated with the source region, the drain region and the grid polysilicon; and forming conductive metal in the contact hole by deposition and grinding.
16. The method of fabricating the LDMOS device structure of claim 15, wherein: the etching method in the step eleven is dry etching.
17. The method of fabricating the LDMOS device structure of claim 15, wherein: the conductive metal in step eleven is tungsten.
CN202311255494.3A 2023-09-26 2023-09-26 Manufacturing method of LDMOS device structure Pending CN117253795A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117497420A (en) * 2023-12-26 2024-02-02 粤芯半导体技术股份有限公司 Semiconductor device and method for manufacturing the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117497420A (en) * 2023-12-26 2024-02-02 粤芯半导体技术股份有限公司 Semiconductor device and method for manufacturing the same
CN117497420B (en) * 2023-12-26 2024-04-16 粤芯半导体技术股份有限公司 Semiconductor device and method for manufacturing the same

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