CN117252861A

CN117252861A - Method, device and system for detecting wafer surface defects

Info

Publication number: CN117252861A
Application number: CN202311434546.3A
Authority: CN
Inventors: 曹阳
Original assignee: Xi'an Xinhui Testing Technology Co ltd
Current assignee: Xi'an Xinhui Testing Technology Co ltd
Priority date: 2023-10-31
Filing date: 2023-10-31
Publication date: 2023-12-19

Abstract

The invention discloses a method, a device and a system for detecting wafer surface defects, which belong to the technical field of semiconductor manufacturing and comprise the following steps: acquiring a plurality of wafer images to be tested; acquiring a plurality of first communication domains of surface defects in each wafer image to be detected aiming at each wafer image to be detected; obtaining a corresponding second communicating domain by morphological expansion of each first communicating domain; forming a defect region to be detected according to the first connected domain corresponding to the second connected domain; and identifying the defect type based on the defect area to be detected. Determining a final defect region to be detected according to the relation between the connected domains of the surface defects before and after expansion in the surface image of the wafer to be detected; based on the finally determined defect region to be detected, the defect type is identified, a plurality of connected domains belonging to one defect can be combined and identified, the calculation error of the characteristic value caused by expansion operation can be avoided, and the defect identification accuracy is improved.

Description

Method, device and system for detecting wafer surface defects

Technical Field

The disclosure relates to the technical field of semiconductor manufacturing, and in particular relates to a method, a device and a system for detecting wafer surface defects.

Background

In the field of semiconductors, a single crystal silicon rod is prepared by a crystal growth apparatus of the Czochralski method, and then a series of industrial processes including slicing and the like are performed on the single crystal silicon rod to prepare a single crystal silicon wafer, and then a Wen Tongchen wafer is prepared. Defects such as edge breakage, scratch, chemical dirt and the like caused by friction, scratch, bump or chemical liquid dip dyeing and the like in the wafer transportation or production process are the most main defects on the surface of the wafer. Wafers containing such defects, if not effectively detected and flowed into subsequent processes, can easily cause debris problems during the subsequent polishing process, thereby causing failure and downtime of polishing equipment, damaging the equipment, and causing serious economic loss.

Therefore, it is a very important link to evaluate various defects of the wafer, for example: edge chipping, scratches, particles, chemical dirt, defects, and the like. Detection is performed using a manual re-detection approach, which has significant limitations. Firstly, manually judging the cost of a great deal of human resources consumed; secondly, the manual discrimination is biased to subjective discrimination, and the recheck result is different due to the state of the recheck operator; finally, the accuracy of the eyes of the person cannot reach the accuracy of the camera, and still a certain degree of omission is caused. Therefore, an accurate, stable, and efficient inspection method is needed to improve quality inspection level and provide improved direction and suggestion for the preamble process, aiming at the defect inspection problem of the wafer surface appearance.

Disclosure of Invention

In view of the foregoing, it is desirable to provide a method, apparatus and system for detecting a wafer surface defect; the wafer surface defects can be accurately identified.

The technical scheme of the present disclosure is realized as follows:

in a first aspect, the present disclosure provides a method for detecting a wafer surface defect, including:

acquiring a plurality of wafer images to be tested;

acquiring a plurality of first communication domains of surface defects in each wafer image to be detected aiming at each wafer image to be detected;

obtaining a corresponding second communicating domain by morphological expansion of each first communicating domain;

forming a defect region to be detected according to the first connected domain corresponding to the second connected domain;

and identifying defect types based on the defect areas to be detected.

In some examples, the obtaining the corresponding second connected domain by morphologically expanding each of the first connected domains includes:

carrying out morphological expansion on each first communication domain to obtain a corresponding expanded first communication domain;

when any one of the expanded first communicating domains is not connected with other expanded first communicating domains or overlapping pixels exist, determining the first communicating domain after expansion as a second communicating domain corresponding to the first communicating domain before expansion;

When any one of the expanded first communicating domains is connected with other expanded first communicating domains or overlapped pixels exist, combining the any one of the expanded first communicating domains with the other expanded first communicating domains connected with any one of the expanded first communicating domains or overlapped pixels exist, and obtaining combined communicating domains; the combined communicating domain is a second communicating domain corresponding to the first communicating domain before any expansion.

In some examples, the forming the defect area to be detected according to the first connected domain corresponding to the second connected domain includes:

when the single second connected domain corresponds to the single first connected domain, the single first connected domain is used as a defect area to be detected;

when a single second connected domain corresponds to at least two first connected domains, the at least two first connected domains are used as a defect area to be detected.

In a second aspect, the present disclosure provides a wafer surface defect detecting apparatus including an image acquisition section, a first extraction section, a second extraction section, a determination section, and an identification section, wherein,

the image acquisition section configured to: acquiring a plurality of wafer images to be tested;

The first extraction portion is configured to: acquiring a plurality of first communication domains of surface defects in each wafer image to be detected aiming at each wafer image to be detected;

the second extraction portion is configured to: obtaining a corresponding second communicating domain by morphological expansion of each first communicating domain;

the determining section is configured to: forming a defect region to be detected according to the first connected domain corresponding to the second connected domain;

the identification portion is configured to: and identifying defect types based on the defect areas to be detected.

In a third aspect, the present disclosure provides a computer storage medium storing a program for detecting a wafer surface defect, where the program for detecting a wafer surface defect, when executed by at least one processor, implements the method and steps for detecting a wafer surface defect according to the first aspect.

In a fourth aspect, the present disclosure provides a system for detecting a wafer surface defect, the system comprising:

a first line camera configured to: the method comprises the steps that the wafer to be tested is located above the edge of the wafer to be tested, and a first wafer image to be tested is collected through one or more times of scanning of the wafer to be tested;

a first light source configured to: the first linear array camera irradiates the edge part of the upper surface of the wafer to be detected when acquiring the image of the first wafer to be detected;

A second line camera configured to: the wafer to be measured is positioned below the edge of the wafer to be measured, and a second wafer image to be measured is acquired through scanning the wafer to be measured for one or more times;

a second light source configured to: the second linear array camera irradiates the edge part of the lower surface of the wafer to be detected when acquiring the image of the second wafer to be detected;

a third linear camera configured to: the wafer to be measured is positioned obliquely above the edge of the wafer to be measured, and the side surface of the wafer to be measured is collected through one or more times of scanning of the wafer to be measured, so that a third wafer image to be measured is obtained;

a fourth linear camera configured to: the wafer to be tested is positioned obliquely below the edge of the wafer to be tested, and the lower side surface of the wafer to be tested is collected through one or more times of scanning of the wafer to be tested, so that a fourth wafer image to be tested is obtained;

a third light source configured to: the C-type light source irradiates the side surface part of the wafer to be detected when the third linear array camera collects the image of the wafer to be detected and/or the fourth linear array camera collects the image of the wafer to be detected;

a support member configured to: when the image of the wafer to be detected is acquired, supporting and driving the wafer to be detected to rotate;

a computing device configured to: the method and the steps for detecting the wafer surface defects in the first aspect are realized when the method and the steps are executed.

The present disclosure provides a method, apparatus and system for detecting surface defects; determining a final defect region to be detected according to the relation between the connected domains of the surface defects before and after expansion in the image surface of the wafer to be detected; based on the finally determined defect region to be detected, the defect type is identified, a plurality of connected domains belonging to one defect can be combined and identified, the calculation error of the characteristic value caused by expansion operation can be avoided, and the defect identification accuracy is improved.

Drawings

FIG. 1 is a schematic view of an environment for performing a method for detecting a wafer surface defect according to the present disclosure;

FIG. 2 is a schematic flow chart of a method for detecting a wafer surface defect according to the present disclosure;

FIG. 3 is a schematic side view of a wafer provided by the present disclosure;

FIG. 4 is a schematic diagram of a wafer edge defect detection system provided by the present disclosure;

FIG. 5 is a schematic view of an acquired wafer edge image provided by the present disclosure;

FIG. 6 is a schematic diagram of a first communication domain of a wafer to be tested according to the present disclosure;

fig. 7 is a schematic diagram of providing a second communication domain of a wafer to be tested according to the present disclosure;

FIG. 8 is a schematic diagram of a defect area to be tested of a wafer according to the present disclosure;

FIG. 9 is a schematic diagram of a process for identifying a defect class of a wafer to be tested according to the present disclosure;

FIG. 10 is a schematic diagram of a defect class determination process provided by the present disclosure;

FIG. 11 is a schematic diagram of a wafer surface defect inspection apparatus according to the present disclosure;

fig. 12 is a flow chart of a wafer quality evaluation method provided in the present disclosure.

Detailed Description

The terms "first," "second," and the like in this disclosure are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature.

The terms "upper", "lower", "left", "right", and the like in the embodiments of the invention indicate an azimuth or a positional relationship based on the azimuth or the positional relationship shown in the drawings, and are merely for convenience of description and simplification of description, and do not indicate or imply that the apparatus or element referred to must have a specific azimuth, be configured and operated in a specific azimuth, and thus should not be construed as limiting the present application.

In order to more clearly illustrate the present disclosure or the prior art solutions, the following description will clearly and completely describe the technical solutions in the present disclosure with reference to the drawings in the present disclosure, and it is apparent that the described embodiments are only some embodiments of the present disclosure, not all embodiments. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the disclosure, are within the scope of the disclosure.

Referring to fig. 1, an environmental schematic diagram of a method for detecting a wafer surface defect according to the present disclosure is shown. In fig. 1, a wafer W to be measured is laid flat on a supporting member 40, and a light source 20 emits a light beam toward the wafer W to be measured. The scanning camera 10 collects reflected light or scattered light passing through the surface of the wafer W to be measured, generates an image of the wafer W to be measured, and transmits the image to the computing device 30. The computing device 30 may perform the techniques of this disclosure based on the received wafer image to identify the type of surface defect of the wafer under test.

It should be noted that the implementation environment shown in fig. 1 is only illustrative and not limiting. It can be appreciated that, those skilled in the art may acquire the surface image of the wafer W to be measured by other methods or systems, which are not described in detail in this disclosure.

Referring to fig. 2, which illustrates a method of detecting wafer surface defects provided by the present disclosure, the method may be performed by the computing device 30 illustrated in fig. 1, and the method may include:

s201: acquiring a plurality of wafer images to be tested;

when the defect of the wafer surface is detected by adopting an optical method, the light source emits detection light, the wafer surface is irradiated at a specific angle outside the wafer, and the detection light scattered or reflected by the defect is detected at the specific angle through the scanning camera, so that the image of the wafer surface to be detected is acquired.

Alternatively, the scanning camera may be an area-array camera or a line-array camera.

Alternatively, the wafer image to be measured may be one or more scanning cameras that collect images of the entire wafer to be measured at the same time; or a plurality of scanning cameras can respectively acquire different areas of the wafer to be detected at the same time to obtain images of the different areas of the wafer to be detected; or respectively collecting different areas of the wafer to be tested by a plurality of scanning cameras, and splicing to form a complete image of the wafer to be tested; or a scanning camera scans the wafer to be tested for multiple times, and images of different areas of the wafer to be tested are collected to form a plurality of images of the wafer to be tested; or a single scanning camera can scan for multiple times to obtain partial area images of a plurality of wafers to be tested, and the images of the complete wafers to be tested are obtained through splicing.

Optionally, when the scanning camera scans the surface of the wafer to be measured, the scanning camera may be fixed and the wafer to be measured may be moved, or the scanning camera may be moved and the wafer to be measured may be fixed.

Optionally, the wafer image to be measured obtained by scanning the scanning camera may be a front image of the wafer or may be a back image of the wafer. The scanning camera for scanning the front surface of the wafer to be tested and the scanning camera for scanning the back surface of the wafer to be tested can be the same group of cameras, and can finish scanning by arranging a plurality of groups of cameras. When the front and back images of the wafer to be measured are collected by the same group of cameras, the front and back images can be obtained by adjusting the positions of the cameras and the light sources and fixing the positions of the wafer to be measured, or by fixing the positions of the scanning cameras and the light sources and adjusting the direction of the wafer to be measured, or by adjusting the scanning cameras, the light sources and the wafer to be measured at the same time.

Edge chipping and crack defects at the edge of a wafer can even cause fragments to appear in the subsequent production process and damage production equipment, meanwhile, the edge chipping and crack defects at the edge can also show a trend of diffusing into the wafer, and the process is seriously influenced, so that the edge defects of the wafer become necessary detection items.

Optionally, in the process that the linear array camera and the wafer to be tested relatively move along the edge direction of the wafer to be tested, multiple scanning is performed by one linear array camera or multiple linear array cameras scan different areas of the edge of the wafer to be tested simultaneously, so as to obtain multiple edge images of the wafer to be tested, and the edge images are used as multiple images of the wafer to be tested.

In some examples, a linear camera is mounted on one side of the wafer, and the camera acquires an elongated optical image of the edge of the wafer after one rotation of the wafer. Because the side surface of the wafer is a curved surface, imaging cannot be integrally focused, so that part of imaging areas are blurred, and defects cannot be accurately detected and classified. In some examples, when the present disclosure collects an edge image of a wafer to be measured, the edge structure of the wafer to be measured is split into four portions close to planes, and the four planes are respectively focused and scanned to obtain a clear image. In the schematic side view of the wafer to be tested shown in fig. 3, the surface of the wafer W to be tested is divided into four parts, i.e., an upper surface, a lower surface, an upper side surface and a lower side surface. The surface contacting the support member 40 is a lower surface of the wafer W to be measured, and the other surface opposite to the lower surface is an upper surface. In fig. 3, the width of the edge regions of the upper and lower surfaces of the wafer W to be measured can be adjusted according to actual requirements. The side surface of the wafer is a curved surface, and in order to facilitate focusing of the scanning camera, the side curved surface of the wafer to be tested is divided into an upper side surface and a lower side surface which are close to plane parts, and the upper side surface and the lower side surface are scanned respectively to obtain a wafer side surface image.

Optionally, scanning multiple times by a linear array camera or scanning different areas of the edge of the wafer to be tested simultaneously by multiple linear array cameras to obtain multiple edge images of the wafer to be tested, including scanning the edge of the upper surface of the wafer to be tested to obtain a first edge image of the wafer to be tested, scanning the edge of the lower surface of the wafer to be tested to obtain a second edge image of the wafer to be tested, scanning the upper side of the wafer to be tested to obtain a third edge image of the wafer to be tested, and scanning the lower side of the wafer to be tested to obtain a fourth edge image of the wafer to be tested.

Specifically, in some examples, as shown in a schematic diagram of a wafer edge defect detection system in fig. 4, the supporting component 40 drives the wafer W to be tested to rotate one circle, and a complete image of the edge area of the wafer W to be tested is acquired by four line cameras. The first linear array camera 101 acquires the edge of the upper surface of the wafer W to be measured to obtain a first wafer image to be measured, the second linear array camera 102 acquires the edge of the lower surface of the wafer to be measured to obtain a second wafer image to be measured, the third linear array camera 103 acquires the side surface part of the wafer to be measured to obtain a third wafer image to be measured, and the fourth linear array camera 104 acquires the lower side surface part of the wafer to be measured to obtain a fourth wafer image to be measured.

By dividing the surface of the edge part of the wafer W to be tested into four parts close to the plane, the image of the edge part of the wafer W to be tested is acquired, the problem of imaging blurring caused by the fact that the side surface is a curved surface is solved, the imaging quality of the surface of the wafer to be tested is improved, and the identification accuracy of the surface defects of the wafer to be tested is further improved.

S202: acquiring a plurality of first communication domains of surface defects in each wafer image to be detected aiming at each wafer image to be detected;

the wafer image to be measured, which is acquired, comprises a wafer area image of the wafer to be measured as a shooting target and a background area image formed by surrounding environment. In a schematic diagram of an acquired wafer edge image shown in fig. 5, an acquired image of a wafer W to be measured includes a wafer area image and a background area image. It should be noted that the notch (notch) is a small notch cut at the edge of the wafer, so that the apparatus can accurately position the wafer or mark the wafer. The boundaries of the wafer area image and the background area image are not always approximately straight lines as shown in fig. 5. It will be appreciated that in the wafer image to be tested containing the wafer grooves, the boundary between the wafer area image and the background area image is a regular curved line recessed toward the wafer area.

Optionally, for each wafer image to be tested, acquiring a plurality of first communication domains of the surface defect in each wafer image to be tested includes:

intercepting an interested area image aiming at each wafer image to be detected;

removing a background part in the region-of-interest image to obtain a first wafer region image;

identifying and removing a wafer groove part in the wafer area image to obtain a final wafer area image;

a plurality of first communication domains of surface defects are acquired based on the final wafer area image.

In some cases, the wafer region image obtained in the defect detection scene is only for the wafer edge region, and other wafer regions not requiring defect detection except for the image of the wafer edge region requiring defect detection are partially imaged in the acquired wafer image to be detected. By intercepting the image of the region of interest, the image processing region can be reduced, the wafer region and most of the background region which do not need to be processed are removed, and the data volume which needs to be processed is reduced. For each wafer image to be tested, the intercepted region of interest image can comprise the wafer region of interest and the residual partial background region which is not completely removed. By intercepting the region of interest, the data volume of subsequent processing is reduced, and the detection efficiency is improved. The background area image and the wafer groove area image are further removed from the interested area, so that the processed data size can be further reduced, interference to defect identification in subsequent defect detection is avoided, and the accuracy rate of defect identification and the processing efficiency are improved.

For each wafer edge image to be tested, the capturing the region of interest image for each wafer image to be tested includes:

establishing a coordinate system by taking the direction of the relative movement as a vertical axis aiming at each wafer edge image to be detected;

constructing a vertical gray value projection function for each wafer edge image to be detected;

and selecting an interested region image from each wafer edge image to be detected based on the first derivative of the vertical gray value projection function.

In detail, the image of the wafer to be measured obtained by the linear camera performing relative motion along the edge of the wafer to be measured is shown in fig. 5. In the horizontal axis direction, the edge of the wafer to be tested has an obvious boundary with the background area. It will be appreciated that the vertical gray function varies significantly at the boundary along the horizontal axis. For example, a rectangular planar coordinate system is established with the pixel in the lower left corner of the image pixels shown in fig. 5 as the origin of the coordinate system. The horizontal axis direction is the X axis, and the vertical axis is the Y axis. And constructing a vertical gray projection function taking the X-axis pixel serial number as a variable by calculating the average value of the gray scales of pixels in the vertical direction in the image matrix of the wafer to be detected. The vertical gray value projection function constructed for the wafer image to be measured is shown as follows:

Wherein c represents the column coordinate of the wafer image to be measured, r represents the row coordinate of the wafer image to be measured, c _r Represents the c-th column and the r-th row, n represents the total number of rows of pixels of the wafer image to be tested, and gray (c _r ) The pixel gray value of the r-th row and the c-th column is represented.

And determining the X-axis pixel position corresponding to the boundary of the wafer area and the background area by calculating the first derivative extremum of the vertical gray value projection function. However, in the actually acquired edge image of the wafer to be measured, the boundary between the wafer area and the background area is not strictly a straight line or perpendicular to the X-axis. The method comprises the steps of expanding according to a certain rule or requirement according to the position determined by the first derivative of the vertical gray value projection function to obtain a region of interest.

Optionally, selecting an image of a region of interest from the edge images of each wafer to be measured based on the first derivative of the vertical gray value projection function includes:

taking a column corresponding to an extremum of a first derivative of the vertical gray value projection function as a central axis;

the central shaft extends a column reaching a first width along the forward direction of the horizontal shaft to form a first column;

the central axis extends along the negative direction of the horizontal axis to form a second column with a second width;

And the region between the first column and the second column in each wafer edge image to be detected is an interested region image.

In detail, the second width of the left expansion should consider the width of the wafer groove with the column corresponding to the extremum of the first derivative of the vertical gray value projection function as the central axis. The first width extending to the right should be considered to be able to contain all wafer areas. Alternatively, on the other hand, the values of the first width and the second width are set according to actual requirements with reference to the first derivative of the vertical gray value projection function. For example, if it is desired to detect all surface defects of the wafer under test, the second width may be set to include the width of all wafer areas. In the wafer edge image to be measured shown in fig. 5, the left side is the wafer area, and the second width may not be set, i.e., the central axis is the area of interest from the central axis to the leftmost column in the wafer edge image to be measured. If it is desired to detect defects only in the edge region, the second width may be set to a width that at least covers the wafer recess. The first width and the second width may also be set to equal widths. By selecting the region of interest, the range of image processing is reduced, the data processing amount is reduced, and the data processing efficiency is improved.

It should be noted that, in the captured region of interest image, a partial background region image still exists. In general, an image processing method of dividing a wafer area image and a background area image by threshold division is adopted.

Optionally, removing a background portion in the region of interest image to obtain a first wafer region image, including:

performing binarization processing on the region-of-interest image to obtain a binary image of the region-of-interest image;

carrying out morphological open operation and morphological close operation on a wafer part in a binary image of the region-of-interest image to obtain a first wafer region;

the image of the first wafer area part in each wafer edge image to be detected is a first wafer area image.

The first wafer region obtained by performing binarization processing and morphological opening and closing operation on the region of interest image can filter out some fine spots and fill in negligible holes and wafer groove regions. And intercepting an obtained image in the originally obtained wafer image to be detected according to the range of the first wafer area as the first wafer area image. In the process of obtaining the first wafer area image, the wafer groove area or part of the wafer groove area is filled through morphological opening and closing operation.

Further, identifying and removing the wafer groove portion in the first wafer area image to obtain a final wafer area image, including:

the method comprises the steps of performing binarization processing on a first wafer area image, and identifying and obtaining a wafer groove area;

subtracting the wafer groove area from the first wafer area to obtain a final wafer area;

and the part of each wafer image to be detected, which is positioned in the final wafer area, is a final wafer area image.

The grooves of the wafer have the shape characteristics of regular shape, specific position, specific size, etc. And analyzing morphological characteristics of connected areas in the image of the binarized first wafer area based on the specific appearance characteristics of the grooves, and identifying the wafer groove areas. Subtracting the wafer groove area from the first wafer area to obtain a final wafer area; and the part of each wafer image to be detected, which is positioned in the final wafer area, is a final wafer area image. And the wafer grooves are removed from the final wafer area image, so that misjudgment of the wafer grooves as wafer surface defects is avoided when defects are identified based on the final wafer area, and the accuracy of the wafer surface defects is further improved.

Optionally, acquiring a plurality of first communication domains of the surface defect based on the final wafer area image includes:

and acquiring a plurality of first communication domains of the surface defects by combining the gray threshold and the edge detection for the final wafer area image.

Optionally, for the final wafer area image, acquiring a plurality of first connection domains of the surface defect by combining a gray threshold and edge detection includes:

performing binarization processing on the final wafer area image based on a gray threshold value to obtain a first defective pixel;

obtaining a gradient image based on an edge detection operator for the final wafer area image, and screening and obtaining a second defect pixel according to a gradient threshold value;

a plurality of first connection domains are obtained based on the first defective pixel and the second defective pixel.

It should be noted that, in the present disclosure, the final wafer area image is combined with the gray threshold and the edge detection to screen the defective pixel, and the defective pixel is subjected to connected domain analysis to obtain a plurality of first connected domains, and defect identification is performed based on the plurality of first connected domains. And setting a reasonable gray threshold value based on the difference between the pixel gray value of the defective part and the pixel gray value of the normal part on the surface of the wafer to be detected, and performing binarization processing on the final wafer area image to obtain a first defective pixel. The first defective pixel obtaining process may be obtained by setting a gray threshold value, or may be obtained by setting a plurality of gray threshold values and performing multiple times of screening on the final wafer area image. For example, for a defect having a gray value greater than that of a normal region pixel, a first gray threshold is set, and a pixel greater than the first gray threshold is a first defective pixel acquired for the first time. For defects with gray values smaller than the gray values of pixels in the normal region, a second gray threshold is set, and pixels smaller than the second gray threshold are the first defective pixels acquired for the second time. And merging the twice acquired first defective pixels to serve as first defective pixels. The gray threshold may also be set to an interval gray threshold by two gray values to screen for defective pixels.

The defective pixels are screened by setting a gray threshold based on the gray value, and some defective pixels of detail parts are omitted. In the method, the final wafer area image is processed through the edge detection operator, defective pixels are further screened, and screening accuracy of the defective pixels is improved. And obtaining a gradient image of the wafer area image according to the edge detection operator, and screening out a second defect pixel by setting a gradient threshold value. The first defective pixel and the second defective pixel are merged into a defective pixel.

Specifically, the final wafer area image may be processed by a sobel edge detector. Wherein the horizontal direction convolution template in the sobel edge detection operator isThe convolution template in the vertical direction is

It should be noted that, the defective pixels obtained by screening the final wafer area image may obtain one or more first connected areas through connected area analysis. Optionally, the connected domain analysis includes connected domain labeling of defective pixels using a 4-neighborhood or 8-neighborhood. Illustratively, in the first communication domain diagram of the wafer under test shown in fig. 6, the area within the boundary 60 is the final wafer area. The final wafer region segmentation within boundary 60 yields 3 first connected regions, namely a region within boundary 601, a region within boundary 602, and a region within boundary 603. For convenience of description, the region within the boundary 601 is referred to as a first connected domain 601, the region within the boundary 602 is referred to as a first connected domain 602, and the region within the boundary 603 is referred to as a first connected domain 603.

S203: carrying out morphological expansion on each of the first communicating domains to obtain a corresponding second communicating domain;

morphological dilation is based on the expansion of white or black areas in a binary image by structural elements, typically used to fill holes, connect broken patterns, or smooth edges of patterns. The wafer image to be detected is acquired, and one defect is divided into a plurality of connected domains due to an image acquisition imaging error or an error in a subsequent image processing process. The present disclosure identifies a plurality of connected domains belonging to one defect through an expansion operation, improving accuracy of defect identification. The effect of the expansion operation depends on the shape and size of the structural elements used.

Optionally, the present disclosure uses a circle with a radius R as a structural element to perform a morphological dilation operation on each first connected domain.

Optionally, the obtaining the corresponding second communicating domain by morphological expansion of each first communicating domain includes:

For example, in the first connected domain schematic diagram of the wafer to be tested shown in fig. 6, the first connected domain 601 is closer to the first connected domain 602, and the two first connected domains may be images of two portions of the same defect. The defect identification is performed by combining the first communication domain 601 with the first communication domain 602, so that the accuracy is higher. There are no other connected domains around the first connected domain 603, and defect recognition is performed individually for the first connected domain 603.

In the second communicating region schematic diagram of the wafer to be tested shown in fig. 7, the first communicating region 601 expands to form an expanded first communicating region 601, the first communicating region 602 expands to form an expanded first communicating region 602, and the first communicating region 603 expands to form an expanded first communicating region 603.

For the expanded first communicating domain 601, the other expanded first communicating domain includes an expanded first communicating domain 602 and an expanded first communicating domain 603. There is a partial pixel overlap of the expanded first connected domain 601 and the expanded first connected domain 602. The expanded first communicating region 601 and the expanded first communicating region 602 are merged to form the second communicating region 701 in fig. 7. The second communicating region corresponding to the first communicating region 601 is a second communicating region 701. It is understood that, similarly, the second communicating region corresponding to the first communicating region 602 is the second communicating region 701. For the expanded first communicating domain 603, the other expanded first communicating domain includes an expanded first communicating domain 601 and an expanded first communicating domain 602. The expanded first connected domain 603 and the other expanded first connected domains are not connected, and there is no overlapping pixel. The region of the expanded first communicating region 603 forms a second communicating region 702 in fig. 7. The second communicating region corresponding to the first communicating region 603 is a second communicating region 702.

S204: and forming a defect area to be detected according to the first connected domain corresponding to the second connected domain.

Forming a defect region to be detected according to the first connected domain corresponding to the second connected domain, including:

For example, in the schematic diagram of the defect area to be measured of the wafer to be measured shown in fig. 8, the connected domain a-1 corresponds to the first connected domain 601 in fig. 6, and the connected domain a-2 corresponds to the first connected domain 602 in fig. 6. Since the second communicating region 701 in fig. 7 is formed after the expansion of the first communicating region 601 and the first communicating region 602, the second communicating region 701 corresponds to the two communicating regions of the first communicating region 601 and the first communicating region 602 in fig. 6. According to the relationship between the connected domains after expansion, the connected domain A-1 and the connected domain A-2 belong to two parts of one defect area A to be detected. A-1 and A-2 in the defect area A to be detected are not adjacent and do not overlap the pixel area. The connected domain B corresponds to the first connected domain 603 in fig. 6. Since the second communicating region 702 in fig. 7 is formed after the expansion of the first communicating region 603, the second communicating region 702 corresponds to one of the first communicating regions 603. A defective region B to be measured is formed according to the first communicating region 603 in fig. 6. The range of the defective area B to be measured is the same as that of the first communication area 603.

It should be noted that the descriptions "60", "601", "602", "603", "701", "702", "a", "B", "a-1", "a-2" in the examples of fig. 6, 7 and 8 are not intended to limit the present disclosure. The shape of the connected region or the defective region may be any shape. Many possible variations and modifications may be made to the disclosed technology, or equivalents may be modified, without departing from the scope of the disclosed technology.

Optionally, in some examples, the forming the defect area to be detected according to the first connected domain corresponding to the second connected domain includes:

setting corresponding first marks in the plurality of first communication domains;

setting a corresponding second mark for the second communication domain;

when the single second connected domain corresponds to the single first connected domain, taking the single first connected domain as a defect area to be detected, including:

when a single second connected domain corresponds to a single first connected domain, updating a first mark in the single first connected domain to a second mark of the corresponding single second connected domain, and determining the single first connected domain after updating the mark to be a corresponding defect region to be detected;

When a single second connected domain corresponds to at least two first connected domains, taking the at least two first connected domains as a defect area to be detected, wherein the defect area to be detected comprises:

when a single second connected domain corresponds to at least two first connected domains, updating the first marks of the at least two first connected domains to the second marks of the corresponding single second connected domain, and determining the at least two first connected domains after updating the marks to be corresponding defect areas to be detected.

It should be noted that, in the above embodiment, the forming of the defect area to be detected according to the first connected domain corresponding to the second connected domain is achieved by setting the mark. For example, the first connected domains shown in fig. 6 are denoted by 601, 602, 603, respectively. After the expansion operation, as shown in fig. 7, the first communication domain 601, the first communication domain 602, and the communication domain composed of pixels corresponding to the expansion region are labeled 701. The first connected domain 603 and the connected domain composed of the corresponding expanded regions are marked 702. The tag of the first connected domain is updated to the connected domain tag of the second connected domain, i.e., the tag of the first connected domain 601 is changed to the tag 701, and the tag of the first connected domain 602 is changed to the tag 701. The first communication domain 603 is marked with an update 702. And after the connected domain mark of the first connected domain is updated to the mark of the second connected domain, forming a defect region to be detected. In the defective area to be measured, the range including the connected domains a-1 and a-2 shown in fig. 8 in the defective area to be measured denoted by 701 is the same as the range of the first connected domain 601, and the range of a-2 is the same as the range of the first connected domain 602. The defective area to be measured, which is marked 702, is the same as the extent of the communication domain 603 in the first communication domain.

S205: and identifying defect types based on the defect areas to be detected.

For the types of defects common in wafers, such as edge chipping, scratching, and cracking, they all have specific topographical features on the wafer surface that can be characterized by characteristic values in the image. The characteristic value of each defective region may include an area, an aspect ratio, a roundness, a gray average, a length, a width, a direction angle, a minimum bounding rectangle filling rate, a minimum bounding circle filling rate, and the like of the defective region.

If the feature value calculation is performed based on the second connected domain, there is a problem in that the feature value calculation is inaccurate. For example, in the second connected domain shown in fig. 7, the second connected domain 701 includes the first connected domain 601 in the solid border and the expansion portion between the solid border and the solid border in the figure, and the gray value of the expansion portion is determined according to a certain rule. When the gray average value characteristic value is calculated for the second connected domain 701, a certain error is introduced into the gray average value calculation due to the introduction of the gray value of the expansion part. It will be appreciated that there are also errors in the calculation of other eigenvalues.

Determining a final defect region to be detected according to the relation between connected domains of surface defects before and after expansion in the image surface of a wafer to be detected; based on the finally determined defect region to be detected, the defect type is identified, a plurality of connected domains belonging to one defect can be combined and identified, the calculation error of the characteristic value caused by expansion operation can be avoided, and the defect identification accuracy is improved.

Each defect area to be tested can contain a plurality of connected domains, and the defect category is identified for each defect area to be tested. When a defect area to be detected comprises a plurality of connected domains, feature calculation is performed by combining the connected domains, and defect types are identified. For example, in the schematic diagram of the defect area to be detected shown in fig. 8, the average gray value of the defect area to be detected marked as a is the average gray value of the pixels within the two connected areas a-1 and a-2, the length of the defect area is the total length of a-1 and a-2, and so on.

When determining a defect class based on the characteristics of the defect region, the present disclosure defines a series of characteristics and characteristic value ranges capable of determining the defect class as defect class identification rules for the defect class. For example, the morphological features of the edge-chipping defect have feature value ranges such as corresponding area range, gray average value range, defect length-width ratio range and roundness range in the image, and the specific features and feature value ranges form an edge-chipping defect identification rule. It will be appreciated that the topographical features of the scratch and crack defects also present in the image corresponding ranges of values for the area, gray-scale average, aspect ratio, and roundness, respectively, to form the scratch and crack defect identification rules.

When defect classification identification is performed on a defect area to be detected, in the above example, if the area, the gray average value, the aspect ratio of the defect, and the roundness of the defect area to be detected are in the area range, the gray average value range, the aspect ratio range of the defect, and the roundness range corresponding to the edge breakage defect, respectively, the defect in the defect area to be detected is confirmed to be the edge breakage defect. And if at least one characteristic value of the area, the gray average value, the defect length-width ratio and the roundness of the defect area to be detected is not in the area range, the gray average value range, the defect length-width ratio range and the roundness range corresponding to the corresponding edge breakage defect, confirming that the defect in the defect area to be detected is not the edge breakage defect.

In the defect type determination flow chart shown in fig. 10, the determination of the edge defect is taken as an example. The area range of the edge-chipping defect is defined by an upper limit of the area of the edge-chipping defect and a lower limit of the area of the edge-chipping defect. Similarly, the range of the gray level average of the edge-collapse defect is defined by the upper limit of the gray level average of the edge-collapse defect and the lower limit of the gray level average of the edge-collapse defect, the range of the aspect ratio of the edge-collapse defect is defined by the upper limit of the aspect ratio of the edge-collapse defect and the lower limit of the aspect ratio of the edge-collapse defect, and the range of the roundness of the edge-collapse defect is defined by the upper limit of the roundness of the edge-collapse defect and the lower limit of the roundness of the edge-collapse defect. And sequentially judging the area, the gray average value, the length-width ratio and the roundness of the defect area to be detected. Any feature is not in the range of the characteristic value of the edge-collapse defect, namely the judgment of the type of the edge-collapse defect is finished.

It will be appreciated that the above-mentioned characteristic values of the defect area to be detected may also be compared with the characteristic value ranges corresponding to the scratch defect recognition rule and the crack defect recognition rule, respectively. And if the characteristic value of the defect area to be detected is in the characteristic value range corresponding to the scratch defect identification rule or the crack defect identification rule, confirming that the defect in the defect area to be detected is a scratch defect or a crack defect. Otherwise, it is confirmed that the scratch or crack is not generated.

Optionally, identifying a defect class based on the defect area to be detected includes:

the following judgment is carried out for each defect area to be detected:

when the area, the length-width ratio, the roundness and the gray average value of each defect area to be detected are in the area range, the length-width ratio range, the roundness range and the gray average value range corresponding to the edge breakage defect, determining the defect type of each defect area to be detected as the edge breakage defect;

when the area, the length-width ratio, the roundness and the gray average value of each defect area to be detected are in the area range, the length-width ratio range, the roundness range and the gray average value range corresponding to the crack defect, determining the defect type of each defect area to be detected as the crack defect;

And when the area, the length-width ratio, the roundness and the gray average value of each defect area to be detected are in the area range, the length-width ratio range, the roundness range and the gray average value range corresponding to the scratch defect, determining the defect type of each defect area to be detected as the scratch defect.

Optionally, when defect type identification is performed for each defect area in the defect areas to be detected, the defect type identification may be performed sequentially according to the influence degree of the defect type. For example, in the defect type identification flow chart shown in fig. 9, the order of discriminating the defect types is a broken edge defect, a crack defect, and a scratch defect in this order. In detail, whether the current defect area to be detected is the edge breakage defect is judged according to the edge breakage defect identification rule, and if the current defect area to be detected is determined to be the edge breakage defect, the defect type judging process of the current defect area to be detected is ended. If the defect can not be confirmed as the edge breakage defect, the crack defect and the scratch defect are continuously judged according to the corresponding defect identification rule.

Based on the same inventive concept as the foregoing technical solution, referring to fig. 11, there is shown a wafer surface defect detection apparatus 110 provided by the present disclosure, where the apparatus 110 includes: an image acquisition section 1101, a first extraction section 1102, a second extraction section 1103, a determination section 1104, an identification section 1105; wherein,

The image acquisition section 1101 is configured to: acquiring a plurality of wafer images to be tested;

the first extraction portion 1102 is configured to: acquiring a plurality of first communication domains of surface defects in each wafer image to be detected aiming at each wafer image to be detected;

the second extraction portion 1103 is configured to: obtaining a corresponding second communicating domain by morphological expansion of each first communicating domain;

the determining section 1104 is configured to: forming a defect region to be detected according to the first connected domain corresponding to the second connected domain;

the identifying portion 1105 is configured to: and identifying defect types based on the defect areas to be detected.

For the specific implementation of the functions configured by the "parts" in the above-mentioned device, reference may be made to the implementation manner of the corresponding steps in the method for detecting the wafer surface defect shown in fig. 2 and examples thereof, which are not described herein again.

Based on the same concept as the foregoing technical solutions, the present disclosure further provides a wafer quality evaluation method, which further includes, after the foregoing method for detecting a wafer surface defect: and evaluating the quality of the wafer to be tested based on the defect type.

Optionally, evaluating the quality of the wafer to be tested based on the defect class includes:

The number of the defects of the wafer to be detected is larger than 0, and the defect types of the defect areas to be detected comprise edge breakage and/or crack defects, so that the quality of the wafer to be detected is marked as not passing;

otherwise, the quality of the wafer to be tested is marked as passing.

In detail, in the flow chart of the wafer quality evaluation method shown in fig. 12, after defect identification is performed on the wafer to be tested by the wafer surface defect detection method, the number of identified defects is counted, and if the number of defects is equal to 0, the quality of the wafer to be tested is marked as passing. If the number of the defects is greater than 0, judging whether the identified defect type has broken edges and/or crack defects. If the edge breakage and/or crack defect exists, the quality of the wafer to be detected is marked as not passing. And if the edge breakage defect does not exist and the crack defect does not exist, marking the quality of the wafer to be tested as passing.

Based on the same concept as the above technical solution, the present disclosure further provides a system for detecting a wafer surface defect, as shown in fig. 4, where the system includes:

a first line camera 101 configured to: the method comprises the steps that the wafer to be tested is located above the edge of the wafer to be tested, and a first wafer image to be tested is collected through one or more times of scanning of the wafer to be tested;

A first light source 201 configured to: the first linear array camera irradiates the edge part of the upper surface of the wafer to be detected when acquiring the image of the first wafer to be detected;

a second line camera 102 configured to: the wafer to be measured is positioned below the edge of the wafer to be measured, and a second wafer image to be measured is acquired through scanning the wafer to be measured for one or more times;

a second light source 202 configured to: the second linear array camera irradiates the edge part of the lower surface of the wafer to be detected when acquiring the image of the second wafer to be detected;

a third line camera 103 configured to: the wafer to be measured is positioned obliquely above the edge of the wafer to be measured, and the side surface of the wafer to be measured is collected through one or more times of scanning of the wafer to be measured, so that a third wafer image to be measured is obtained;

a fourth linear camera 104 configured to: the wafer to be tested is positioned obliquely below the edge of the wafer to be tested, and the lower side surface of the wafer to be tested is collected through one or more times of scanning of the wafer to be tested, so that a fourth wafer image to be tested is obtained;

a third light source 203 configured to: the C-type light source irradiates the side surface part of the wafer to be detected when the third linear array camera collects the image of the wafer to be detected and/or the fourth linear array camera collects the image of the wafer to be detected;

A support member 40 configured to: when the image of the wafer to be detected is acquired, supporting and driving the wafer to be detected to rotate;

a computing device 30 configured to: the method and the steps for detecting the surface defects of the wafer shown in fig. 2 are realized when the method and the steps are executed.

In some examples, the computing device 30 is configured to perform the method and steps for detecting the wafer surface defect in the method for detecting the wafer surface defect described above, which are not described herein.

In some examples, computing device 30 may be at least one of a smart phone, a smart watch, a desktop computer, a laptop computer, a virtual reality terminal, an augmented reality terminal, a wireless terminal, and a laptop portable computer. The computing device 30 has communication capabilities and may access a wired network or a wireless network. Computing device 30 may refer broadly to one of a plurality of terminals, and those skilled in the art will recognize that the number of terminals may be greater or lesser. In some examples, computing device 30 may receive the wafer image transmitted by scanning camera 20 based on an accessed wired network or wireless network. It will be appreciated that the computing device 30 performs the computing and processing operations after acquiring the wafer image in the technical solution of the present disclosure, which is not limited in this disclosure.

A computing device in this application may include one or more of the following components: a processor and a memory.

In the alternative, the processor uses various interfaces and lines to connect various portions of the overall computing device, execute various functions of the computing device, and process data by executing or executing instructions, programs, code sets, or instruction sets stored in memory, and invoking data stored in memory. Alternatively, the processor may be implemented in at least one hardware form of digital signal processing (Digital Signal Processing, DSP), field-Programmable gate array (FPGA), programmable logic array (Programmable Logic Array, PLA). The processor may integrate one or a combination of several of a central processing unit (Central Processing Unit, CPU), an image processor (Graphics Processing Unit, GPU), a Neural network processor (Neural-network Processing Unit, NPU), and baseband chips, etc. The CPU mainly processes an operating system, a user interface, an application program and the like; the GPU is used for rendering and drawing the content required to be displayed by the touch display screen; the NPU is used to implement artificial intelligence (Artificial Intelligence, AI) functionality; the baseband chip is used for processing wireless communication. It will be appreciated that the baseband chip may not be integrated into the processor and may be implemented by a single chip.

The Memory may include random access Memory (Random Access Memory, RAM) or Read-Only Memory (ROM). Optionally, the memory includes a non-transitory computer readable medium (non-transitory computer-readable storage medium). The memory may be used to store instructions, programs, code sets, or instruction sets. The memory may include a stored program area and a stored data area, wherein the stored program area may store instructions for implementing an operating system, instructions for at least one function (such as a touch function, a sound playing function, an image playing function, etc.), instructions for implementing the various method embodiments described below, etc.; the storage data area may store data created from the use of the computing device, and the like.

In addition, those skilled in the art will appreciate that the structures of the computing devices described above are not limiting of the computing devices, and that a computing device may include more or fewer components than shown, or may combine certain components, or a different arrangement of components. For example, the computing device further includes a display screen, a camera component, a microphone, a speaker, a radio frequency circuit, an input unit, a sensor (such as an acceleration sensor, an angular velocity sensor, a light sensor, etc.), an audio circuit, a WiFi module, a power supply, a bluetooth module, etc., which are not described herein.

The present disclosure provides a computer storage medium storing a method program for detecting a wafer surface defect, where the method program for detecting a wafer surface defect implements the steps of the method for detecting a wafer surface defect in the above technical solution when executed by at least one processor.

The present disclosure also provides a computer program product comprising computer instructions stored in a computer-readable storage medium; the processor of the computing device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions, so that the computing device executes to implement the wafer surface defect detection method described in the above embodiments.

Those of skill in the art will appreciate that in one or more of the examples described above, the functions described in this disclosure may be implemented in hardware, software, firmware, or any combination thereof. When implemented in software, these functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A storage media may be any available media that can be accessed by a general purpose or special purpose computer.

It should be noted that: the embodiments described in the present disclosure may be arbitrarily combined without any collision.

The foregoing is merely specific embodiments of the disclosure, but the protection scope of the disclosure is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the disclosure, and it is intended to cover the scope of the disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims

1. A method for detecting a wafer surface defect, the method comprising:

acquiring a plurality of wafer images to be tested;

and identifying defect types based on the defect areas to be detected.

2. The method according to claim 1, wherein the obtaining of the corresponding second connected domain by morphological expansion of each first connected domain comprises:

3. The method according to claim 2, wherein the forming the defect area to be detected according to the first connected domain corresponding to the second connected domain includes:

4. The method of claim 1, wherein the acquiring a plurality of wafer images to be measured comprises:

in the process of relatively moving the linear array camera and the wafer to be tested along the edge direction of the wafer to be tested, a plurality of edge images of the wafer to be tested are obtained through scanning the linear array camera for a plurality of times or scanning different areas of the edge of the wafer to be tested through a plurality of linear array cameras at the same time, and the edge images are used as the images of the wafer to be tested.

5. The method of claim 4, wherein the acquiring, for each wafer image to be tested, a plurality of first communication fields of the surface defect in each wafer image to be tested comprises:

identifying and removing a wafer groove part in the first wafer area image to obtain a final wafer area image;

6. The method of claim 5, wherein, for each wafer edge image to be inspected, the intercepting the region of interest image for each wafer image to be inspected comprises:

7. The method of claim 5, wherein the acquiring a plurality of first communication fields of surface defects based on the final wafer area image comprises:

performing binarization processing on the final wafer area image based on a defect threshold value to obtain a first defective pixel;

8. The method of claim 1, wherein the identifying defect categories based on the defect areas under test comprises:

the following judgment is carried out for each defect area to be detected:

9. A wafer surface defect detecting apparatus includes an image acquiring section, a first extracting section, a second extracting section, a determining section, an identifying section, wherein,

10. A system for detecting defects on a wafer surface, the system comprising:

a computing device configured to: the method and steps of detecting defects on a wafer surface as claimed in any one of claims 1 to 8 are carried out.