CN117251313A - L0BTB fault tolerance design system and method based on full connection structure - Google Patents

Abstract

The invention relates to the field of fault-tolerant design of branch target buffers, and provides an L0BTB fault-tolerant design system and method based on a full connection structure, wherein the system comprises the following steps: the current instruction address is subjected to exclusive OR logic to obtain an exclusive OR check code of the current instruction address; splicing the current instruction address and the exclusive or check code and simultaneously writing two L0 BTB; the current instruction address accesses two L0BTB at the same time, and whether the L0BTB is hit or not is determined by comparing the current instruction address with the target instruction address; if one L0BTB is hit, the enabling signal value is 1, the table item content is obtained, the table item is subjected to exclusive OR check, and if the exclusive OR check value of the table item is the same as the check value stored in the table item, the table item is used as a candidate table item; and making a decision according to the obtained candidate list item, and if the check result shows that the candidate list item does not appear, considering that the current instruction address does not hit the L0 BTB.

Description

L0BTB fault tolerance design system and method based on full connection structure

Technical Field

The invention relates to the field of fault-tolerant design of branch target buffers, in particular to an L0BTB fault-tolerant design system and method based on a full connection structure.

Background

Two potential errors may occur in the running process of the processor, the first is that the hardware circuit of the chip has a problem; the second is that the processor is disturbed by the external environment, so that the impact of high-energy particles causes transient faults, specifically, the L0BTB (L0 Branch Target Buffer) in the branch prediction module in the design of the processor is affected by the irradiation of the external environment, such as Single Event Upset (SEU) (Single Event Upset). For the first type of error, it is a permanent fault generated by the circuit unit, and is not recoverable. The second error can eliminate the effect of transient faults by adding redundancy technology.

The branch prediction module is one of key modules in the design process of the processor, predicts the current instruction address, and sends the predicted result to the PC register as a target instruction address for instruction fetching. L0BTB is used as a key ring in the branch prediction module, and if an entry has a flip error, the entry with the flip error may be output to the cache module. Even if the fault-tolerant design success rate of the cache reaches 100%, an erroneous target instruction is brought. Therefore, the fault-tolerant design of the L0BTB is beneficial to improving the accuracy of the cache instruction fetching, and the maintenance processor can normally and stably run.

Fault tolerant design approaches with respect to caches and register files are well established and are successfully deployed for use in a variety of different processors. However, there is no special research work about the fault-tolerant design of the L0BTB, and the problem of hit rate reduction is caused by directly using the fault-tolerant design work of the cache and the register file for the L0 BTB. It is therefore desirable to design a fault tolerant design scheme specific to the L0BTB of the fully connected architecture.

Disclosure of Invention

The invention aims to provide an L0BTB fault-tolerant design system and method based on a full connection structure, aiming at reducing the influence of external environment radiation, such as single event upset, received by an L0BTB through coding logic verification, ensuring the normal operation of a branch prediction module and the normal and stable execution of a Cache instruction fetching function.

The invention solves the technical problems and adopts the following technical scheme:

on one hand, the invention provides an L0BTB fault-tolerant design system based on a full connection structure, which comprises:

the master-slave redundancy module comprises two L0BTB structures, the two structures are identical and each contain a plurality of table entries, and when an L0BTB prediction target instruction is carried out, a prediction result is output through the two L0BTB structures;

the checking decision module comprises two checking modules and a decision module, wherein the two checking modules respectively correspond to the master module and the slave module and are used for checking the prediction results of the two L0BTB structures, the structures of the two checking modules are completely consistent, an enabling signal and a checking result are output, if the enabling signal and the checking result are both 1, the table item is a candidate table item, and if one of the enabling signal and the checking result is 0, the table item is considered to be a non-selectable target table item.

As a further optimization, the two L0BTB structures are L0BTB 1 and L0BTB2, respectively, and each of the L0BTB 1 and L0BTB2 contains 40 entries.

As a further optimization, the contents contained in each entry are: the current instruction address, the target instruction address, the enable signal, and the exclusive or check value.

As further optimization, when writing the table entry, the current address is firstly subjected to exclusive-or logic to obtain an exclusive-or check code of the current address, and the current address and the exclusive-or check code are spliced and then are respectively input into two L0BTB structures as input.

As a further optimization, when reading an entry, the current instruction address accesses two L0BTB structures at the same time, and by comparing the current instruction address with the target instruction address, determining whether to hit the L0BTB, if one of the L0 BTBs is hit, the enabling signal value is 1, obtaining the content of the entry and performing exclusive-or checking on the entry, if the exclusive-or checking value of the entry is the same as the checking value stored in the entry, taking the entry as a candidate entry, deciding according to the obtained candidate entry, and if the checking result indicates that the candidate entry does not appear, considering that the current instruction address does not hit the L0 BTB.

On the other hand, the invention provides an L0BTB fault-tolerant design method based on a full connection structure, which is applied to the L0BTB fault-tolerant design system based on the full connection structure, and comprises the following steps:

the current instruction address is subjected to exclusive OR logic to obtain an exclusive OR check code of the current instruction address;

splicing the current instruction address and the exclusive or check code to be used as the input of the L0BTB module;

writing the spliced current instruction into the L0BTB 1 and the L0BTB2 at the same time;

the current instruction address simultaneously accesses the L0BTB 1 and the L0BTB2, and whether the L0BTB is hit or not is determined by comparing the current instruction address with the target instruction address;

if one L0BTB is hit, the enabling signal value is 1, the table item content is obtained, the table item is subjected to exclusive OR check, and if the exclusive OR check value of the table item is the same as the check value stored in the table item, the table item is used as a candidate table item;

and making a decision according to the obtained candidate list item, and if the check result shows that the candidate list item does not appear, considering that the current instruction address does not hit the L0 BTB.

As further optimization, when the spliced current instruction is written into the L0BTB 1 and the L0BTB2 at the same time, a counter is set to determine the placement position of the table entry, and the replacement strategy is a first-in first-out strategy.

The beneficial effects of the invention are as follows: through the L0BTB fault-tolerant design system and the L0BTB fault-tolerant design method based on the full connection structure, the current instruction address can be matched with correct table entries in two identical L0BTB structures through the master-slave redundancy module, and the prediction results of the two L0BTB structures can be checked through the checking decision module to output the correct table entries. The method can greatly reduce the influence of the L0BTB on external environment radiation such as single event upset, and ensure the normal operation of the branch prediction module and the normal and stable execution of the Cache instruction fetching function. The present invention is not only useful for fully associative L0 BTBs, but also can be used for Return Address Stack (RAS) (Return address stack) modules in branch prediction, demonstrating that the proposed solution of the present invention is versatile for many different structures.

Drawings

FIG. 1 is a schematic diagram of the overall structure of an L0BTB fault tolerant design system based on a fully connected structure in embodiment 1 of the present invention;

FIG. 2 is a schematic diagram of the verification logic in embodiment 1 of the present invention;

FIG. 3 is a register file and BTB structure access comparison diagram of embodiment 1 of the present invention;

fig. 4 is a flowchart of an L0BTB fault tolerant design method based on a fully connected structure in embodiment 2 of the present invention.

Detailed Description

The technical scheme of the invention is described in detail below with reference to the accompanying drawings and the embodiments.

Example 1

The embodiment provides an L0BTB fault-tolerant design system based on a fully connected structure, the overall structure of which is shown in fig. 1, wherein the system comprises:

the master-slave redundancy module comprises two L0BTB structures, the two structures are identical and each contain a plurality of table entries, and when an L0BTB prediction target instruction is carried out, a prediction result is output through the two L0BTB structures; in this embodiment, the two L0BTB structures are L0BTB 1 and L0BTB2, respectively, and each of L0BTB 1 and L0BTB2 includes 40 entries, and each entry includes: the current instruction address, the target instruction address, the enable signal, and the exclusive or check value.

The checking decision module, see fig. 2, includes two checking modules and a decision module, where the two checking modules respectively correspond to the master module and the slave module and are used to check the prediction results of the two L0BTB structures, the structures of the two checking modules are completely consistent, both output an enabling signal and a checking result, if the enabling signal and the checking result are both 1, it is indicated that the table entry is a candidate table entry, and if one of them is 0, the table entry is considered as not being an optional target table entry.

When the table entry is written, the current address is firstly subjected to exclusive OR logic to obtain an exclusive OR check code of the current address, and the current address and the exclusive OR check code are spliced and then are respectively input into two L0BTB structures as input.

When reading an item, the current instruction address accesses two L0BTB structures at the same time, the current instruction address is compared with the target instruction address to determine whether the L0BTB is hit, if one of the L0BTB is hit, the enabling signal value is 1, the content of the item is obtained, the item is subjected to exclusive-or check, if the exclusive-or check value of the item is the same as the check value stored in the item, the item is taken as a candidate item, a decision is made according to the obtained candidate item, if the check result shows that the candidate item does not appear, and the current instruction address is considered to not hit the L0 BTB.

It is noted that the L0BTB module mainly comprises two parts, the first part being a master-slave redundancy and the second part comprising check decision logic. The redundancy scheme of the master-slave is to ensure that each table item has the corresponding correct table item, for example, if an error occurs in a, the data in B can be matched with the corresponding correct table item.

For the above system of the present embodiment, there are two paths:

path 1: when reading L0BTB table entries, two L0BTB table entries are accessed at the same time to see whether hit occurs, if hit occurs in both tables, namely, the vld signals are 0, the result is directly output, and the fact that hit does not occur in the L0BTB structure is indicated.

Path 2: accessing the L0BTB structure, if there is more than one hit, then it is considered that a hit may occur. At this time, parity check is performed on the hit entry to verify whether the entry is correct.

During writing, parity check is performed first, the parity check is added to the table entry content, and the table entries are written into two L0BTB tables at the same time.

For a master-slave redundancy module:

in this implementation, the master-slave redundancy provides a backup for the L0BTB structure and the decision module selects the correct entry content output. The embodiment has the advantages that the hit success rate of branch prediction is guaranteed to be compared with a protection mechanism of an ECC code, so that the success rate of branch prediction is not reduced due to the increase of fault tolerance design, and the area and power consumption problems are effectively reduced on the premise of guaranteeing error correction capability compared with a fault tolerance scheme using multimode redundancy.

To achieve a low entry miss rate for L0BTB, the present embodiment selects a master-slave redundancy scheme. Firstly, the difference between the L0BTB structure and the general register in the working principle is analyzed, the possible problems caused by adopting an ECC coding scheme and a multimode redundancy method are analyzed, and finally, the structure is described.

Wherein, for ECC encoding, an L0BTB structure entry miss condition is caused:

in fault-tolerant protection of register files, most of the previous methods use ECC encoding, and can achieve good results. However, the structure and working principle of the L0BTB are different from those of the register file, and the fault-tolerant protection is performed by directly using the check code, which may cause a table entry miss and bring performance loss.

For a register file, each entry has a specific number, and only a specific one of the entries needs to be accessed according to the register number. FIG. 3 (a) is a register file containing 32 registers, where the Z-tag represents the bit flipped. The signal Rs_i gives the index of the table entry to be accessed, determines the only table entry to be accessed through the decoding of the register file, outputs the content of the table entry, and performs fault tolerance verification. Since rs_i determines the unique entry to be accessed, the unique entry can be accessed by decoding only through the decoder according to the index number. When the read L0BTB table item has errors (2a7f_XXXX), the error correction is performed by using a check code mode (2a6f_XXXX) so as to ensure the correct execution of branch prediction.

For the L0BTB structure, the largest difference from the general register file is the absence of the index number Rs_i and decoding logic. The L0BTB structure requires access to each entry and then uses the current instruction address as a TAG to compare with each entry of the L0 BTB. If the table entry is successfully matched, the table entry content is output, and when all the table entries are not successfully matched, the output vld value is 0.

This presents a serious problem when the TAG bit in the L0BTB structure is flipped by mistake, resulting in a match failure. For example, in fig. 3 (b), 2a6f in the L0BTB structure is changed to 2a7f due to the occurrence of the false rollover, and when matching, the entry is not matched due to (2 a6f |=2a7f), resulting in the entry being lost.

The use of check codes is a good fault tolerance scheme for the register file because the unique entry can be obtained and error corrected by the rs_i signal, regardless of whether or not an entry has been flipped. However, for the L0BTB structure, if an error occurs in the matched address portion, that is, if there is bit flip in the TAG, the entry is lost, and if the error is corrected by using only check code in the design scheme, performance loss is caused.

There are two ways to solve this problem, one is to design the L0BTB structure as a register file, and the other is to add a backup. The former is not viable because the general register file corresponds to 32 registers, which are associated with the instruction. A particular register may be accessed by the demand of an instruction. However, for the L0BTB structure, there is no unique index TAG to find an entry, and the entry contents are stored in a matching manner. Thus, to ensure that each piece of data can be retrieved, a backup mode is added.

The embodiment aims at bit flip of the L0BTB table entry, and the hit condition of the table entry is not affected, namely the hit success rate of the L0BTB is not reduced. The most straightforward solution to this problem is to add redundancy, a triple modular redundancy scheme is commonly used to consolidate the flip-flops, etc. critical components. The TMR structure adopts a three-out-of-two strategy to realize system fault tolerance, and the three-out-of-two strategy follows a few rules obeying majority, namely in the three structures, as long as two results are correct, the correct results can be output. The core idea of triple modular redundancy is that the same entry does not flip together in different structures.

The triple modular redundancy scheme can solve the problem of table entry loss caused by fault tolerance by using check codes. When one of the entries is in error, the match cannot be completed, but its backup can hit. The correct results can still be obtained by vote.

In general, multimode backup brings higher accuracy. However, multimode backup causes an increase in area and power consumption. For the structure of register files and SRAM, multimode redundancy itself presents large area and power consumption issues. This problem is more serious for the L0BTB structure.

If the L0BTB only accesses one entry, the triple modular redundancy also only accesses 3 entries simultaneously. But for the L0BTB structure, all entries are accessed simultaneously for matching. For an L0BTB structure containing 40 entries, 120 entries are accessed simultaneously. For larger L0BTB structures, the cost of access may double. This can present a significant additional power consumption problem.

In this embodiment, a master-slave redundancy scheme is selected to solve the problem of entry misses. The premise is that the same table item of the L0BTB structure and the backup L0BTB structure cannot be in error at the same time, and the idea and triple-modular redundancy are consistent. For example, entry a (2a6f_3a5c) and the corresponding a' (2a6f_3a5c) in the backup are stored in L0 BTB. If the TAG bit in the table item A is turned to be A (2a7f_3a5c), and the TAG (2 a6 f) is used for comparison, the backup is necessarily matched with the successful A', and the correct table item is selected to be output through the check logic. If the target address in the table item A is overturned and becomes A (2a6f_3a5b), the two table items can be matched through TAG (2 a6 f) at the moment, and then correct output is selected through check logic. When the inversion occurs in the backup in accordance with the above logic, the benefit of using master-slave redundancy is that a correct entry can always be found and output.

For the check decision module:

in order to output the correct entry, the output results of L0BTB 1 and L0BTB2 need to be decided. For a general register file, the output results are two entries. And the check decision module is used for judging whether the correct table entry exists or not and outputting the correct table entry. For the L0BTB structure, there are a total of 8 potential outputs (case 1-case 8). As shown in table 1, three cases including no L0BTB structure hit, 1L 0BTB structure hit, and 2L 0BTB structures hit are included. A selection circuit is designed to make decisions about this potential situation.

The present embodiment first uses a structure to decide whether an output entry hits. When an entry hits, the vld signal is 1. And performing exclusive OR check on the stored address, and comparing the exclusive OR check with the stored check value. If the comparison value is 1, the table entry is indicated to be not flipped and can be used as a candidate table entry. Otherwise, the table entry is indicated to have a overturn error.

The above procedure can be represented using a logical expression, cx, to indicate whether an entry is valid and whether an error occurred. Firstly, the exclusive or value of the target address is acquired and compared with the stored check value, and the value is ANDed with an enabling signal. For the output control signal Cx divided into three cases, L0BTB 1 and L0BTB2 hit and are valid, there is one hit and valid in L0BTB 1 and L0BTB2 and L0BTB 1 and L0BTB2 are invalid (case 1). When hit and valid entries occur in L0BTB 1 and L0BTB2, i.e., hit case, when Cx value is 0, it indicates no hit occurs, corresponding to case 1. But for cases 2-8 it is necessary to further distinguish between entries. It is complex and wasteful if one circuit is designed for each case.

Through research, a certain correlation is found between the cases 2 and 8. The core idea is to do without considering which of L0BTB 1 and L0BTB2 hits in each case when designing the circuit. For only one L0BTB active, the candidate for which the entry is selected. For both BTB entries to be correct, either one may be selected as a candidate.

The L0BTB 1 is set to the primary BTB structure, and when the L0BTB 1 entry is valid, L0BTB 1 is directly selected as the target. When L0BTB 1 is inactive but L0BTB2 is active, L0BTB2 is selected as the target entry.

Referring to Table 1, the present invention includes several cases in which the flipped bits are framed:

TABLE 1

Case 6: vld 1=1, cx1=1, vld2=1, cx2=1, indicating that a jump has occurred, target instruction address=ta 1.

The Cx1 value is 1 and the Cx2 value is also 1, indicating that the master-slave module contains two potential target entries, one of which is selected as the target entry. To simplify the decision circuit, when a target entry exists in the L0BTB, L0BTB 1 is selected as the target of the output.

Case 7: vld 1=1, cx1=0, vld2=1, cx2=1, indicating that a jump has occurred, target instruction address=ta2.

Vld1 has a value of 1, but Cx1 has a value of 0. Two potential predictors exist, TAG is the occurrence of a flip and the occurrence of a target instruction address. It can be seen from the table that the hit error entry is caused by the TAG flipping. And through exclusive or check, finding that an error occurs in the L0BTB 1, and selecting the L0BTB2 as a target table entry.

Case 8: vld 1=1, cx1=1, vld2=1, cx2=0, indicating that a jump has occurred, target instruction address=ta 1.Vld2 has a value of 1, but Cx2 has a value of 0. Two potential predictors exist, TAG is the occurrence of a flip and the occurrence of a target instruction address. It can be seen from the table that the hit error entry is caused by the TAG flipping. And through exclusive or check, finding that an error occurs in the L0BTB2, and selecting the L0BTB 1 as a target table entry.

Example 2

On the basis of embodiment 1, the embodiment provides an L0BTB fault-tolerant design method based on a full connection structure, and a flowchart of the method is shown in fig. 4, wherein the method comprises the following steps:

s1, carrying out exclusive OR logic on a current instruction address to obtain an exclusive OR check code of the current instruction address;

s2, splicing the current instruction address and the exclusive or check code to serve as input of an L0BTB module;

s3, writing the spliced current instruction into the L0BTB 1 and the L0BTB2 at the same time;

s4, the current instruction address simultaneously accesses the L0BTB 1 and the L0BTB2, and whether the L0BTB is hit or not is determined by comparing the current instruction address with the target instruction address;

s5, if one L0BTB is hit, enabling a signal value to be 1, acquiring the content of the table entry, performing exclusive-OR check on the table entry, and if the exclusive-OR check value of the table entry is the same as a check value stored in the table entry, taking the table entry as a candidate table entry;

s6, deciding according to the obtained candidate list items, and if the check result shows that the candidate list items do not appear, considering that the current instruction address does not hit the L0 BTB.

In this embodiment, when the current instruction of the concatenation is written into the L0BTB 1 and the L0BTB2 at the same time, a counter may be set to determine the placement position of the table entry, and the replacement policy is a first-in first-out policy.

The fault-tolerant design method in this embodiment is the same as the working principle of the fault-tolerant design system in embodiment 1, and therefore, will not be described again.

Example 3

Based on the embodiment 1 and the embodiment 2, the technical effects of the present invention are further described in connection with simulation experiments:

1. simulation conditions and content:

hardware platform used in this experiment: processor Intel Core i7-7700 CPU (3.6 GHZ), memory 16GB. Simulation experiment software platform python3.6, vivado2019.1.

Simulation one: the number of L0BTB table entry misses is verified. The L0BTB is used for predicting target instruction addresses, and the number of hit addresses and the number of miss addresses are used for reflecting the performance of the L0 BTB. When SEU overturn errors occur, the hit of the table entry which can be hit originally is caused to be missed, and the table entry is caused to be missed. Meanwhile, if the flip error occurs at the target address, the PC register can acquire the wrong instruction address and influence the instruction fetching result of the cache, so that the number of L0BTB deletions is as low as possible, and the method is important for the performance of the branch prediction structure.

Simulation II: verification increases the fault tolerance after fault tolerant design. Soft errors caused by SEU and the like are reduced by adding fault tolerant designs. The fault tolerance of the L0BTB is verified, meanwhile, the fault tolerance of a RAS (Return Address Stack) module in branch prediction is verified by using the proposed method, and the proved scheme has universality for various different structures.

2. Simulation result analysis:

TABLE 2

In order to explore the influence of external environment radiation on normal operation of a processor, taking single event upset as an example, the influence of single event upset errors in L0BTB on branch prediction hit conditions and branch missing conditions is simulated. It can be seen from table 1 that experiments were performed on different trace of 10, each of which 10 contains 100 tens of thousands of branch instructions.

First, hit and miss of trace through L0BTB in these 10 were counted under normal conditions. Then, the injection error design is performed on 1% of the number of missing entries, and as seen in table 1, for trace of 100 ten thousand branch instructions, 572 errors are injected on average, which is equivalent to one error injected every 1 ten thousand branch instructions.

The flip error includes two aspects, CA (Current Address present Address) and TA (Target Address Target Address). When a flip error occurs in the CA bit, the matching between the current address and the CA bit fails, resulting in hit loss. As can be seen from the experimental results, the number of hits after the injection of errors was 7 times, and the number of hits was reduced to 37 times for 10 different trace. The number of actual hit decreases is the sum of the two, on average 44 times. Because the number of table entry deletions caused by the overturn is increased to 32 times, the single event overturn is proved to produce serious test on the normal operation of the branch prediction L0BTB module, and the prediction performance of the L0BTB is affected, so that a fault-tolerant design method is required to be added to solve the influence of external severe environments such as SEU and the like.

TABLE 3 Table 3

The above table shows the hit and miss conditions of the entries by adding the proposed fault tolerance method. As can be seen from the table, the average number of injection error entries is 572 times and the number of times the injection error entries are hit 2597 times, using the same injection error pattern and injection error ratio. Including the number of miss hits due to rollover errors. The L0BTB fault-tolerant design method solves the hit problem caused by overturning, and realizes 100% fault-tolerant capability.

TABLE 4 Table 4

In addition to achieving 100% fault tolerance at the L0BTB module, the proposed method is also used for the return address stack module (RAS) (Return address stack). The distinction between the L0BTB and RAS modules is shown in FIG. 3, where L0BTB is a fully connected structure that, by matching all entries, decides the hit entry. And the RAS module pushes the target table item to stack each time, and takes out the stack top element as the target table item. The fault-tolerant design method of the L0BTB can be deployed with an RAS module, and experimental results show that the fault-tolerant capacity of 100% is realized for the RAS module, the method can be deployed in various different register structures, and the method has certain universality.

The above description is only one specific example of the invention and does not constitute any limitation of the invention, and it will be apparent to those skilled in the art that various modifications and changes in form and details may be made without departing from the principles, construction of the invention, but these modifications and changes based on the idea of the invention are still within the scope of the claims of the invention.

Claims (7)

1. L0BTB fault tolerant design system based on full connection structure, its characterized in that includes:

the master-slave redundancy module comprises two L0BTB structures, the two structures are identical and each contain a plurality of table entries, and when an L0BTB prediction target instruction is carried out, a prediction result is output through the two L0BTB structures;

the checking decision module comprises two checking modules and a decision module, wherein the two checking modules respectively correspond to the master module and the slave module and are used for checking the prediction results of the two L0BTB structures, the structures of the two checking modules are completely consistent, an enabling signal and a checking result are output, if the enabling signal and the checking result are both 1, the table item is a candidate table item, and if one of the enabling signal and the checking result is 0, the table item is considered to be a non-selectable target table item.

2. The fully connected structure-based L0BTB fault tolerant design system of claim 1, wherein the two L0BTB structures are L0BTB 1 and L0BTB2, respectively, and wherein each of the L0BTB 1 and L0BTB2 comprises 40 entries.

3. The L0BTB fault tolerant design system based on fully connected architecture of claim 1, wherein each entry contains the following contents: the current instruction address, the target instruction address, the enable signal, and the exclusive or check value.

4. The L0BTB fault tolerant design system based on a fully connected structure according to any one of claims 1-3, wherein when writing an entry, the current address is first subjected to an exclusive-or logic to obtain an exclusive-or check code of the current address, and the current address and the exclusive-or check code are spliced and then are respectively input into two L0BTB structures as inputs.

5. The L0BTB fault tolerant design system based on fully connected structure according to claim 4, wherein when reading an entry, the current instruction address accesses two L0BTB structures simultaneously, and by comparing the current instruction address with the target instruction address, it is determined whether to hit an L0BTB, if one of the L0BTB is hit, the enable signal value is 1, the entry content is obtained and the entry is subjected to exclusive OR check, if the exclusive OR check value of the entry is the same as the check value stored in the entry, the entry is used as a candidate entry, a decision is made according to the obtained candidate entry, and if the check result indicates that no candidate entry exists, the current instruction address is considered to not hit the L0 BTB.

6. The L0BTB fault-tolerant design method based on the full connection structure is applied to the L0BTB fault-tolerant design system based on the full connection structure as claimed in any one of claims 1 to 5, and is characterized by comprising the following steps:

the current instruction address is subjected to exclusive OR logic to obtain an exclusive OR check code of the current instruction address;

splicing the current instruction address and the exclusive or check code to be used as the input of the L0BTB module;

writing the spliced current instruction into the L0BTB 1 and the L0BTB2 at the same time;

the current instruction address simultaneously accesses the L0BTB 1 and the L0BTB2, and whether the L0BTB is hit or not is determined by comparing the current instruction address with the target instruction address;

if one L0BTB is hit, the enabling signal value is 1, the table item content is obtained, the table item is subjected to exclusive OR check, and if the exclusive OR check value of the table item is the same as the check value stored in the table item, the table item is used as a candidate table item;

and making a decision according to the obtained candidate list item, and if the check result shows that the candidate list item does not appear, considering that the current instruction address does not hit the L0 BTB.

7. The L0BTB fault tolerant design method based on fully connected architecture of claim 6, wherein when writing the current instruction of the concatenation into both L0BTB 1 and L0BTB2, a counter is set to determine the placement position of the entry, and the replacement policy is a fifo policy.