CN117251133A - Design method of subtractor-free rapid three-dividing circuit - Google Patents
Design method of subtractor-free rapid three-dividing circuit Download PDFInfo
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- CN117251133A CN117251133A CN202211527691.1A CN202211527691A CN117251133A CN 117251133 A CN117251133 A CN 117251133A CN 202211527691 A CN202211527691 A CN 202211527691A CN 117251133 A CN117251133 A CN 117251133A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/491—Computations with decimal numbers radix 12 or 20.
- G06F7/498—Computations with decimal numbers radix 12 or 20. using counter-type accumulators
- G06F7/4983—Multiplying; Dividing
- G06F7/4988—Multiplying; Dividing by table look-up
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/57—Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations
- G06F7/575—Basic arithmetic logic units, i.e. devices selectable to perform either addition, subtraction or one of several logical operations, using, at least partially, the same circuitry
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Abstract
The invention relates to the field of design of a rapid three-removing circuit without a subtracter, and provides a design method of the rapid three-removing circuit without the subtracter, which comprises the following steps: constructing a basic divide-by-three operation unit, wherein the bit width of an input dividend is 4 bits, and the input dividend is a quotient with 2 bits and a remainder with 2 bits; cascading the basic divide-by-three operation units to construct an 8-bit number divide-by-three operation unit, wherein the bit width of the input dividend is 10 bits, and the remainder of the quotient of 8 bits and the remainder of 2 bits is output; constructing a multi-bit number division three operation unit by using a basic division three operation unit and an 8-bit number division three operation unit, solving the lowest 2 bits of the dividend by using the basic division three operation unit from the lowest bit, then solving by using the 8-bit number division three operation unit every 8 bits, supplementing 0 to the high bit if the number of bits is less than 8 bits, and then solving by using the 8-bit number division three operation unit; the dividend is input to a multibit division three operation unit to obtain a quotient and a remainder.
Description
Technical Field
The invention relates to the field of design of a rapid three-removing circuit without a subtracter, in particular to a design method of a rapid three-removing circuit without a subtracter.
Background
Product Codes (Product Codes), also known as AN Codes, are used to protect arithmetic operations from circuit faults. The fault tolerance principle by using the product code is to represent a number N as a product AN, wherein A is a check modulus constant, and whether AN error occurs in the operation process can be determined by carrying out integer divisibility checking on the operation result about A. The product code is an inseparable code (Nonseparate Codes), the original data is mixed with redundant information for checking, and the final operation result is obtained by dividing the check modulus constant A.
AN code with AN odd check modulus constant a can detect all single bit errors occurring during the operation and, to ensure easy implementation of the AN code encoding process, the check modulus constant a is usually selected as a low cost product code (Low Cost Product Codes) in the form of a=2 a -1, so that the encoding process of AN code can be obtained by shifting and subtracting the logarithm N, the value of the usual check modulus constant a is 3, i.e. a=2 2 -1。
At present, the integer divisibility check of the A on the operation result of the AN code is carried out by using a divider, a quotient and a remainder are obtained through operation, the quotient is a final operation result, and the remainder is used for judging whether errors occur in the process of the arithmetic operation.
The current divider is mainly realized based on a subtracter, a quotient is obtained through iterative subtraction operation, and the quotient with a limit number can be determined through each iterative operation, so that for multi-bit division operation, multiple iterations are needed to complete, and the time cost of an arithmetic operation unit using a product code for fault tolerance is high when the result is checked.
Disclosure of Invention
The invention aims to provide a design method of a rapid three-dividing circuit without a subtracter, which is characterized in that a basic three-dividing operation unit is constructed, the basic three-dividing operation unit is subjected to cascade connection to realize three-dividing operation of multiple bit numbers, quotient and remainder can be obtained rapidly, no subtracter is needed in the operation process, and the problem of high time expenditure when an arithmetic operation unit using a product code for fault tolerance is used for executing result inspection is solved.
The invention solves the technical problems and adopts the following technical scheme:
the invention provides a design method of a rapid three-removing circuit without a subtracter, which comprises the following steps:
constructing a basic divide-by-three operation unit, wherein the bit width of an input dividend is 4 bits, the effective data formats are 00xx, 01xx and 10xx, the effective data formats are binary, x represents 0 or 1, and the quotient with 2 bits of width and the remainder with 2 bits of width are output;
the basic divide-by-three operation unit is cascaded to construct an 8-bit divide-by-three operation unit, the bit width of the input dividend is 10 bits, the effective data formats are 00_xxxx_xxxx, 01_xxxx_xxxx and 10_xxxx_xxxx, the effective data formats are binary, x represents 0 or 1, and the remainder of the quotient of 8 bits and 2 bits is output;
constructing a multi-bit number division three operation unit by using a basic division three operation unit and an 8-bit number division three operation unit, wherein the 2 least bits of the divisor are solved by using the basic division three operation unit from the lowest bit, then each 8 bits are solved by using the 8-bit number division three operation unit, and if the number of bits is less than 8, 0 is complemented to the high bit firstly, and then the solution is performed by using the 8-bit number division three operation unit;
the dividend is input to a multibit division three operation unit to obtain a quotient and a remainder.
As a further optimization, the basic divide-by-three arithmetic unit is constructed using a look-up table.
As a further optimization, the basic divide-by-three operation unit includes a quotient lookup table and a remainder lookup table, and the input dividend is used as an address selection for the quotient lookup table and the remainder lookup table.
As a further optimization, the 8-bit number divide-by-three arithmetic units are constructed in cascade in a serial fashion by means of 4 basic divide-by-three arithmetic units.
As a further optimization, the dividend input by the basic divide-by-three operation unit and the valid input of the highest 2 bits of the dividend input by the 8-bit divide-by-three operation unit are each 00, 01 or 10 and are each binary.
As a further optimization, the remainder output by the basic divide-by-three operation unit and the remainder output by the 8-bit number divide-by-three operation unit are 00, 01 or 10 in value and are binary.
As further optimization, the multi-bit number dividing three operation units are constructed in a cascade manner in a serial manner or in a parallel manner.
The beneficial effects of the invention are as follows: by the design method of the rapid three-dividing circuit without the subtracter, three-dividing operation of multiple bit numbers can be realized, compared with a conventional three-dividing operation circuit, the method does not use the subtracter in the operation process, has small arithmetic operation delay, and solves the problem of high time expenditure when an arithmetic operation unit using a product code for fault tolerance performs operation result inspection.
Drawings
FIG. 1 is a flow chart of a design method of a fast divide-by-three circuit without a subtracter according to an embodiment of the present invention;
FIG. 2 is a block diagram of the overall structure of a subtracter-free fast divide-by-three circuit provided in an embodiment of the present invention;
FIG. 3 is a block diagram of a basic divide-by-three arithmetic unit provided in an embodiment of the present invention;
FIG. 4 is a block diagram of an 8-bit divide-by-three arithmetic unit according to an embodiment of the present invention;
FIG. 5 is a block diagram of a cascade structure of multiple-bit divide-by-three operation units in a serial manner according to an embodiment of the present invention;
fig. 6 is a block diagram of a parallel cascade structure of multiple-bit divide-by-three operation units according to an embodiment of the present invention.
Wherein div3_w2 represents constructing a basic divide-by-three operation unit, div3_w8 represents constructing an 8-bit number divide-by-three operation unit, div3 represents a multi-bit number divide-by-three operation unit, qt represents a quotient, rt represents a remainder, qt_rom represents a lookup table of quotient values, and rt_rom represents a lookup table of remainder.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. The components of the embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.
Examples
The embodiment provides a design method of a rapid three-way removal circuit without a subtracter, a flow chart of which is shown in fig. 1, and an overall structure block diagram of the rapid three-way removal circuit without the subtracter is shown in fig. 2, wherein the method comprises the following steps:
s1, constructing a basic divide-by-three operation unit div3_w2, wherein the structural block diagram is shown in FIG. 3, the bit width of an input dividend is 4 bits, the effective data formats are 00xx, 01xx and 10xx, the effective data formats are binary, x represents 0 or 1, and the quotient qt with the 2-bit width and the remainder rt with the 2-bit width are output;
s2, carrying out cascade connection on the basic divide-by-three operation unit to construct an 8-bit number divide-by-three operation unit div3_w8, wherein the block diagram is shown in FIG. 4, the bit width of the input dividend is 10 bits, the effective data formats are 00_xxxx_xxxx, 01_xxxx_xxxx and 10_xxxx_xxxx, the effective data formats are binary, x represents 0 or 1, and the quotient qt with 8 bits of bit width and the remainder rt with 2 bits of bit width are output;
s3, constructing a multi-bit number division three operation unit div3 by using a basic division three operation unit div3_w2 and an 8-bit number division three operation unit div3_w8, wherein the multi-bit number division three operation unit div3 is shown in fig. 5 and 6, starting from the lowest bit, the lowest 2 bits of the divisor are solved by using the basic division three operation unit div3_w2, then each 8 bits are solved by using the 8-bit number division three operation unit div3_w8, and if the number of bits is less than 8, the higher bit is supplemented with 0, and then the solution is performed by using the 8-bit number division three operation unit div3_w8;
s4, inputting the divisor into a multi-bit number division three operation unit div3 to obtain a quotient qt and a remainder rt.
Compared with a conventional divide-by-three operation circuit, the method of the embodiment does not use a subtracter in the operation process, has small arithmetic operation delay, can solve the problem that an arithmetic operation unit which uses a product code for fault tolerance has large time expenditure when executing operation result inspection, and does not need any subtracter in the whole operation process.
It should be noted that the basic divide-by-three arithmetic unit div3_w2 in step S1 is internally composed of qt_rom, rt_rom, the input dividend is used as address selection of the quotient lookup table qt_rom and the remainder lookup table rt_rom, and the corresponding quotient and remainder can be obtained from qt_rom and rt_rom by the table lookup method.
In addition, in steps S1 and S2, the remainder output by the basic divide-by-three operation unit div3_w2 and the 8-bit divide-by-three operation unit div3_w8 has a value of 00, 01 or 10, and is binary, the most significant 2-bit input of the input dividend is 00, 01 or 10, and is binary, and div3_w2 and div3_w8 can construct the multi-bit divide-by-three operation unit in a cascade manner. In steps S2, S3, the specific operation of the cascade is to connect units (or modules) of the same (or similar) structure together.
In the specific application process, in step S3, the multi-bit number dividing three operation units div3 can be constructed in a cascade connection or parallel connection mode, the area consumption of the multi-bit number dividing three operation units div3 constructed in the cascade connection mode is small, the time delay is large, the area consumption of the multi-bit number dividing three operation units div3 in the parallel connection mode is large, the time delay is small, and both the two can meet the requirements of dividing three operation in different application scenes.
The above description is only a specific example of the invention and does not constitute any limitation of the invention, and it will be apparent to those skilled in the art that various modifications and changes in form and details may be made without departing from the principles, construction of the invention, but these modifications and changes based on the idea of the invention are still within the scope of the claims of the invention.
Claims (7)
1. The design method of the fast three-removing circuit without the subtracter is characterized by comprising the following steps of:
constructing a basic divide-by-three operation unit, wherein the bit width of an input dividend is 4 bits, the effective data formats are 00xx, 01xx and 10xx, the effective data formats are binary, x represents 0 or 1, and the quotient with 2 bits of width and the remainder with 2 bits of width are output;
the basic divide-by-three operation unit is cascaded to construct an 8-bit divide-by-three operation unit, the bit width of the input dividend is 10 bits, the effective data formats are 00_xxxx_xxxx, 01_xxxx_xxxx and 10_xxxx_xxxx, the effective data formats are binary, x represents 0 or 1, and the remainder of the quotient of 8 bits and 2 bits is output;
constructing a multi-bit number division three operation unit by using a basic division three operation unit and an 8-bit number division three operation unit, wherein the 2 least bits of the divisor are solved by using the basic division three operation unit from the lowest bit, then each 8 bits are solved by using the 8-bit number division three operation unit, and if the number of bits is less than 8, 0 is complemented to the high bit firstly, and then the solution is performed by using the 8-bit number division three operation unit;
the dividend is input to a multibit division three operation unit to obtain a quotient and a remainder.
2. The method for designing a fast divide-by-three circuit without a subtracter according to claim 1, wherein the basic divide-by-three operation unit is constructed using a table look-up method.
3. The method of designing a subtractor-less fast divide-by-three circuit according to claim 1, wherein the basic divide-by-three operation unit includes a quotient lookup table and a remainder lookup table, and the input dividend is used as address selections for the quotient lookup table and the remainder lookup table.
4. A method of designing a subtractor-less fast divide-by-three circuit according to any one of claims 1 to 3, characterized in that said 8-bit number divide-by-three operation units are constructed in cascade in a series manner by means of 4 basic divide-by-three operation units.
5. The method of claim 4, wherein the divisor input by the basic divide-by-three operation unit and the valid input of the highest 2 bits of the divisor input by the 8-bit divide-by-three operation unit are each 00, 01 or 10 and are each binary.
6. The method for designing a fast divide-by-three circuit without a subtracter according to claim 5, wherein the remainder output by the basic divide-by-three operation unit and the remainder output by the 8-bit number divide-by-three operation unit are each 00, 01 or 10 and are binary.
7. The method for designing a subtractor-free fast divide-by-three circuit according to claim 1, wherein the multi-bit number divide-by-three arithmetic units are constructed in cascade in a serial manner or in parallel manner.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202211527691.1A CN117251133A (en) | 2022-11-29 | 2022-11-29 | Design method of subtractor-free rapid three-dividing circuit |
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| CN202211527691.1A CN117251133A (en) | 2022-11-29 | 2022-11-29 | Design method of subtractor-free rapid three-dividing circuit |
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| CN202211527691.1A Pending CN117251133A (en) | 2022-11-29 | 2022-11-29 | Design method of subtractor-free rapid three-dividing circuit |
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