CN109683085B - Electronic cell self-checking method - Google Patents
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Abstract
The invention provides an electronic cell self-checking method, which is applied to the technical field of circuit detection and comprises the following steps: determining a first code of the electronic cell address generating module based on the residue code; determining a second code of the electronic cell input and output module based on the Berger code and the residual code; and inputting the first code and the second code to the first TRC cascade circuit to obtain fault indication information of the electronic cell. The electronic cell self-checking method provided by the invention can detect single faults and unidirectional multi-bit faults and realize the coding self-checking of the embryo electronic cells.
Description
Technical Field
The invention belongs to the technical field of circuit detection, and particularly relates to an electronic cell self-checking method.
Background
With the progress of process technology, the reliability of electronic systems is receiving more and more attention. The embryo circuit is a digital integrated circuit simulating the growth and development mechanism of multicellular organisms, the circuit is formed by mutually connecting circuit module units (namely embryo electronic cells) with the same structure to form an embryo array, and when one or more cells have faults, the circuit detects the embryo electronic cells, so that redundant cells are controlled to replace the faulty cells to complete corresponding functions, and fault self-repair is realized. Due to the excellent performances of self-organization, self-diagnosis and self-repair of the embryo circuit, the embryo circuit has good application prospect in the fields of unmanned aerial vehicles, aerospace equipment, deep diving equipment, military robots and the like.
Cell self-detection is the basis for self-repair. At present, the detection method of the embryonic electronic cells mainly comprises two detection methods, namely intercellular detection and intracellular detection. The intercellular detection is mainly based on a dual-mode redundancy detection method, which has high fault coverage rate, but has high hardware resource consumption, complex layout and wiring and certain requirements on the embryo circuit array structure. The intracellular detection mainly comprises dual-mode redundancy detection aiming at a cell function module, fault detection aiming at a cell storage module, redundancy detection aiming at intercellular connecting lines and intercellular dual-mode redundancy detection. These detection methods only detect locally for cells, the detection capability is affected by the cell structure, the fault coverage is limited, and the detection unit cannot perform effective self-detection.
Disclosure of Invention
The invention aims to provide an electronic cell self-checking method to solve the technical problem that a detection unit in the prior art cannot effectively perform self-checking.
In view of the above technical problems, an embodiment of the present invention provides an electronic cell self-checking method, including:
determining a first code of the electronic cell address generating module based on the residue code;
determining a second code of the electronic cell input and output module based on the Berger code and the residual code;
and inputting the first code and the second code to the first TRC cascade circuit to obtain fault indication information of the electronic cell.
Optionally, the determining a first code of the electronic cell address generating module based on the residue code comprises:
generating first verification information of the electronic cell address generation module based on the residual code;
inputting the address output information of the address generation module to a residual code checker to obtain a first check bit;
and inputting the first check information and the first check bit to a second TRC cascade circuit to obtain a first code.
Optionally, the inputting the address output information of the address generation module to the residue code checker to obtain a first check bit includes:
inputting the address output information of the address generation module to a residual code checker;
and the residual code checker calculates the residual code of the address output information to obtain a first check bit.
Optionally, the determining a second code of the electronic cell input-output module based on the Berger code and the residue code includes:
generating second check information of the electronic cell input and output module based on the Berger code and the residual code;
inputting the input information of the input and output end to an encoding circuit to obtain a second check bit;
and inputting the second check information and the second check bit to a third TRC cascade circuit to obtain a second code.
Optionally, the input information of the input/output terminal includes transit input information and functional input information, and the inputting the input information of the input/output terminal to the encoding circuit to obtain the second parity bit includes:
inputting the switching input information to a first coding circuit to obtain a first output code;
inputting the function input information to a second coding circuit to obtain a second output code;
a second parity bit is determined from the first output encoding and the second output encoding.
Optionally, the first encoding circuit comprises a first equivalent circuit and a transit input encoding circuit; the inputting the switching input information to the first encoding circuit to obtain a first output code comprises:
inputting the switching input information to the first equivalent circuit;
the first equivalent circuit calculates and outputs a Berger code of the switching input information;
and the transit input coding circuit receives the Berger code of the transit output information and calculates the residual code of the Berger code of the transit output information to obtain a first output code.
Optionally, the second encoding circuit includes a functional input encoding circuit and a second equivalent circuit, and the inputting the functional input information to the second encoding circuit to obtain a second output code includes:
inputting the function input information to the function input encoding circuit;
the function input encoding circuit receives the function input information and outputs parity bits of the function input information;
and the second equivalent circuit receives the parity check bit and calculates to obtain a second output code according to the parity check bit.
Optionally, the receiving, by the second equivalence circuit, the parity bits and calculating a second output code according to the parity bits includes:
determining a functional signal according to the parity check bit and the functional check bit;
and calculating a Berger code of the functional signal according to the functional signal and the connection sequence to obtain a second output code.
Optionally, the method for determining the function check bit includes:
if the parity bit is equal to a preset function configuration gene, the function check gene is equal to 0;
and if the parity bit is not equal to the preset function configuration gene, the function check gene is equal to 1.
Optionally, the calculating a Berger code of the functional signal according to the functional signal and the connection sequence to obtain a second output code includes:
calculating the residue code of the connecting sequence to obtain a functional remainder check gene;
and obtaining a second output code according to the functional remainder check gene and the functional signal.
The self-checking method of the electronic cell provided by the invention has the beneficial effects that: the electronic cell self-checking method provided by the invention establishes a mathematical model between input and output signals of the embryo electronic cell based on the relation between the residue code and the Berger code between the operand and the result number in the basic logic and arithmetic operation. And detecting single fault through the residual code, detecting multi-bit one-way fault through the Berger code, and processing input of the embryonic electronic cells to obtain verification information. By arranging the detection circuit, the output of the embryonic electronic cell is processed to obtain a check bit, and the check bit are compared to obtain a detection code, so that the code self-checking of the embryonic electronic cell is completed according to the detection code.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed for the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.
Fig. 1 is a schematic structural diagram of an electronic cell self-test circuit according to an embodiment of the present invention;
fig. 2 is a schematic flow chart illustrating an electronic cell self-inspection method according to an embodiment of the invention;
fig. 3 is a schematic structural diagram of an electronic cell self-test circuit according to another embodiment of the present invention;
fig. 4 is a schematic flow chart of an electronic cell self-test method according to another embodiment of the present invention;
fig. 5 is a schematic flow chart illustrating an electronic cell self-inspection method according to still another embodiment of the invention;
fig. 6 is a schematic structural diagram of an electronic cell self-test circuit according to yet another embodiment of the present invention;
fig. 7 is a schematic flow chart illustrating an electronic cell self-test method according to another embodiment of the present invention;
fig. 8 is a schematic flow chart illustrating an electronic cell self-test method according to another embodiment of the present invention;
fig. 9 is a schematic flow chart illustrating an electronic cell self-test method according to another embodiment of the present invention;
fig. 10 is a schematic flow chart illustrating an electronic cell self-test method according to another embodiment of the present invention;
fig. 11 is a schematic flow chart illustrating an electronic cell self-test method according to another embodiment of the present invention;
fig. 12 is a schematic flow chart illustrating an electronic cell self-test method according to another embodiment of the present invention;
fig. 13 is a schematic structural diagram of a functional input encoding circuit according to an embodiment of the present invention.
Detailed Description
In order to make the technical problems, technical solutions and advantageous effects to be solved by the present invention more clearly apparent, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
Referring to fig. 1, fig. 1 is a schematic structural diagram of an electronic cell self-test circuit according to an embodiment of the invention. The circuit mainly comprises an address generation module code detection circuit 10, an input/output module code detection circuit 20 and a TRC cascade circuit 30.
The address generation module code detection circuit 10 mainly receives two types of input information: the first checking information stored by the gene storage module of the electronic cell and the information output by the output end of the address generation module of the electronic cell. Wherein, the output end of the address generation module code detection circuit 10 is connected to the input end of the TRC cascade circuit.
The input/output module code detection circuit 20 mainly receives two types of input information: the second check information input by the superior module and the information output by the input/output module output end of the electronic cell. Wherein, the output end of the input/output module code detection circuit 20 is connected to the input end of the TRC cascade circuit.
Referring to fig. 1 and fig. 2 together, fig. 2 is a schematic flow chart of an electronic cell self-inspection method according to an embodiment of the invention. The method comprises the following steps:
s101: a first code of the electronic cell address generation module is determined based on the residue code.
In this embodiment, the address generation module code detection circuit 10 may obtain the first check bit of the address generation module according to the output information of the electronic cell address generation module, and then determine the first code according to the first check bit and the first check information stored in the gene storage module.
S102: and determining a second code of the electronic cell input and output module based on the Berger code and the residual code.
In this embodiment, the i/o module code detection circuit 20 may generate the second parity bits according to the output information of the i/o module, and then determine the second code according to the second parity bits and the second parity information input by the upper module.
S103: and inputting the first code and the second code to the first TRC cascade circuit to obtain the fault indication information of the electronic cell.
In this embodiment, the TRC cascade circuit 30 is a first TRC cascade circuit, and is mainly used for comparing detection codes, that is, comparing a first code with a second code, the TRC cascade circuit has a full self-checking function, there is no logic shield, it can self-check only by its own input, when the output fault indication information is "00" or "11", it indicates that there is a fault in the system, and when the fault indication information is "01" or "10", the system normally operates.
From the above description, it can be known that the electronic cell self-inspection method provided by the embodiment of the present invention establishes a mathematical model between input and output signals of an embryonic electronic cell based on the residue code and the Berger code relationship between the operand and the result number in the basic logic and arithmetic operations. And detecting single fault through the residual code, detecting multi-bit one-way fault through the Berger code, and processing input of the embryonic electronic cells to obtain verification information. By arranging the detection circuit, the output of the embryonic electronic cell is processed to obtain a check bit, and the check bit are compared to obtain a detection code, so that the code self-checking of the embryonic electronic cell is completed according to the detection code.
Referring to fig. 3 and fig. 4 together, as an embodiment of the method for detecting electronic cells provided by the present invention, on the basis of the above embodiment, step S101 can be detailed as follows:
s201: and generating first verification information of the electronic cell address generation module based on the residue code.
In this embodiment, given that the residue code obtains the check bits by performing a modulo operation on the information bits, the first check information is obtained by performing a modulo operation on the input information of the electronic cell address generating module, and is stored in the gene storage module.
S202: and inputting the address output information of the address generation module to the residual code checker to obtain a first check bit.
In this embodiment, the output information of the e-cell address generating module may be input to the residue code checker 101, and the residue code checker 101 calculates the output information to obtain the first check bit.
S203: and inputting the first check information and the first check bit to a second TRC cascade circuit to obtain a first code.
In this embodiment, the gene storage module inputs the first check information to the TRC cascade circuit 102, the residue code checker also inputs the calculated first check bit to the TRC cascade circuit 102, and the TRC cascade circuit 102 compares the first check information with the first check bit to output the first code. The TRC cascade circuit 102 is a second TRC cascade circuit.
Referring to fig. 5, fig. 5 is a schematic flow chart of an electronic cell detection method according to still another embodiment of the present invention, and step S202 may be detailed as follows based on the above-mentioned embodiment:
s301: inputting the address output information of the address generation module to the residual code checker.
S302: the residual code checker calculates the residual code of the address output information to obtain a first check bit.
In this embodiment, the address generation module includes two parts, namely a row address and a column address, and actually comprises two 1-in adders. When single fault occurs in the embryo electronic cell, the output end of the address generation module does not have a plurality of faults, namely only one-bit address information output error occurs, so that residual code coding detection can be directly carried out on the output of the address generation module.
As is known, the residue code addition rule is: the modulus of the sum of several codes is equal to the modulus of the sum of the moduli of each code, i.e.
A in formula (1)iIs a codeword, m is the modulus.
The multiplication rule of the residue code is as follows: the modulus of the product of several codes is equal to the modulus of the product of the moduli of each code, i.e.
A in formula (2)iIs a codeword, m is the modulus.
When the modulus of the self-checking method of the residual code is odd, single error detection in the code can be realized. To facilitate the design of the detection circuit, the lowest cost residue code detection method can be adopted, i.e. the modulus m is 2dAnd 1, after the first check information is generated, storing the first check information in a gene storage module in an inverted code mode, and comparing the first check information with the first check bit in a self-checking mode through a TRC circuit.
The present embodiment takes (0,14) cells in a 16 × 16 array as an example to describe the residue code detection output by the address generation module. Assuming that the cell output coordinate is (1,15) and the modulus is 3, d is 2, the binary form of the output coordinate is 00011111, the binary form of the output coordinate is divided into a group of bits d from low to high to be added, the insufficient bits are added by 0 to be filled, and then the modulus is taken. When a carry is present, the carry is cancelled and 1 is added to the lowest bit, i.e., 00+01+11+ 11-01. That is, the first check bit is 01, and at this time 01 is compared with the check information stored in the gene storage module, and if the check information stored in the gene storage module is 10, it indicates that the address generation module has not failed. When the actual circuit design is carried out, the residual code checker can be obtained by cascading a plurality of full adders.
Referring to fig. 6 and 7 together, as a specific implementation of the method for detecting electronic cells according to the embodiment of the present invention, step S102 may be detailed as follows based on the above-mentioned embodiment:
s401: and generating second check information of the electronic cell input and output module based on the Berger code and the residual code.
In this embodiment, the Berger code obtains the check bits by counting the number of "0" or "1" in the code word, and if the number of the check bits is large, the final check bits can be obtained by modulo the check bits obtained by the Berger by means of residue code modulo operation. The second check information is obtained by performing Berger code and residue code joint coding on the input information of the input/output module, and is provided to the TRC cascade circuit 205 by output block coding.
S402: inputting the input information of the input/output end to the coding circuit to obtain a second check bit.
In this embodiment, the output end of the input/output module is connected to three inputs in other directions and function outputs, and if the outputs connected to the same input are grouped into one group, the outputs can be grouped into w groups, each group has four outputs, where w is defined as the width of the input/output module. When the output end of the input/output module is connected with the function output, the output end of the input/output module plays a role of function output. When the output end of the input and output module is connected with the output in other directions, the output end of the input and output module plays a role of switching output. Due to the different connection relationship between the switching output and the function output, the equivalent operation of the switching output and the function output is different.
Therefore, the present embodiment can separately set the equivalent operation circuit to obtain the second check bit. Referring to fig. 6, the transit input information is input to the first equivalence calculation circuit 201, and is processed by the first equivalence calculation circuit 201 and the transit input packet encoding circuit 202 to obtain the first output code. The function signal input information is input to the function input encoding circuit 203, and is processed by the function input encoding circuit 203 and the second equivalent operation circuit 204 to obtain a second output code. The second parity bits may be derived from the first output encoding and the second output encoding.
S403: and inputting the second check information and the second check bit to a third TRC cascade circuit to obtain a second code.
In this embodiment, the second check information and the second check bit are input to the TRC cascade circuit 205 for comparison to obtain a second code, where the second code is the output of the TRC cascade circuit 205. The TRC cascade circuit 205 is a third TRC cascade circuit.
Referring to fig. 6 and 8, fig. 8 is a schematic flow chart of an electronic cell detection method according to another embodiment of the present invention, and step S402 can be detailed as follows based on the above-mentioned embodiment:
s501: the switching input information is input to the first coding circuit to obtain a first output code.
S502: and inputting the function input information to a second coding circuit to obtain a second output code.
In this embodiment, the first encoding circuit, i.e., the circuit composed of the first equivalence calculating circuit 201 and the transit input packet encoding circuit 202, inputs transit input information into the first encoding circuit to obtain the first output code. The second encoding circuit, i.e. the circuit composed of the function input encoding circuit 203 and the second equivalent operation circuit 204, inputs the function input information into the second encoding circuit to obtain a second output code. The first output code is output through the switched input block coding circuit 202, and the second output code is output through the second equivalent operation circuit 204.
S503: the second parity bit is determined from the first output encoding and the second output encoding.
In this embodiment, on the basis of the above embodiments, the second parity bit can be obtained by inputting the first output code and the second output code to the TRC circuit.
Referring to fig. 6 and 9, fig. 9 is a schematic flow chart of an electronic cell detection method according to another embodiment of the present invention, and step S501 may be detailed as follows based on the above-mentioned embodiment:
s601: the switching input information is input to the first equivalent circuit.
S602: the first equivalence circuit calculates and outputs a Berger code for switching the input information.
In the present embodiment, B in Berger code is used1The Berger code detection of the transfer input circuit will be described by taking the code calculation method as an example. Wherein, B1The code counts the number of '1's in the codeword.
For n-bit binary operands in basic logical and arithmetic operations: x ═ Xn,xn-1,…,x1) And Y ═ Yn,yn-1,…,y1) The operation result is (S)n,sn-1,…,s1) The Berger code check information b(s) and the Berger code check information b (x) and b (y) of the operand satisfy a specific relationship, which is explained by taking logic and operation as an example. Assuming that the operand X is 0 and the operand Y is 1, the result of bitwise and operation between them S is 0. The Berger code check code of the operand X is 0, the Berger code check code of the operand Y is 1, the Berger code check code of the result number S is 0, in addition, the Berger code check code of the result obtained by the OR operation of the operand X and the operand Y is 1, and the Berger codes of the operand X, the operand Y and the result number S meet the following relational expression
B(S)＝B(X)+B(Y)-B(X|Y)
Due to the nature of basic logic and arithmetic operations, the number of '0' or '1' in the code word has a passing rule during operation, so that a fixed Berger code relationship always exists between the operand and the result number. The output of the embryo electronic cell is equivalent to the result number, the input is equivalent to one operand, and the Berger code self-checking of the circuit can be realized by constructing an equivalent circuit with the input and output relation by using the configuration gene to construct the other operand.
In this embodiment, the first equivalence circuit, namely the first equivalence calculating circuit 202 in fig. 6, performs the equivalence calculation of:
the switched output is first analyzed. For an input, it may have 0 to 3 outputs connected by switching. Therefore, a group of switching outputs can be subjected to equivalence operation conversion, and the switching outputs are regarded as results of multiplying 4 inputs by a 4-bit connection sequence respectively and then summing, and the specific conversion flow is as follows:
the Berger code relation for known multiplications is:
B(S)＝B(X)×B(Y)-B(C) (3)
for one input i, X ═ 000i, the concatenation sequence Y ═ Y4y3y2y1(ynWhen b (x) is equal to i and b (c) is equal to 0,1, the following results are obtained
B(Si)＝i×B(Y) (4)
S in the formula (4)iThe number of results corresponding to the input i and the connection sequence Y, and the sum of the number of results corresponding to each group of 4 inputs is the output corresponding to the group.
For example, a set of inputs W1in, N1in, E1in and S1in is 0101, W1in is connected to outputs N1out and E1out, N1in is connected to output S1out, E1in is connected to output W1out, S1in is not connected to the output, then outputs W1out, N1out, E1out and S1out are 0001. The conversion is equivalent to an arithmetic operation, namely W1in is multiplied by a connecting sequence 0110, N1in is multiplied by a connecting sequence 0001, E1in is multiplied by a connecting sequence 1000, S1in is multiplied by a connecting sequence 0000, and then the number of the added results is 0001. The result number 0001 is the output of this set.
That is, the equivalence conversion process of the first equivalence calculating circuit 202 is a process of calculating the above result number 0001. Here, the connection sequence (referred to as a first connection sequence herein) can be obtained according to a first configuration gene shown in fig. 6, that is, a configuration gene input to the first equivalence calculation circuit 202, which includes configuration information input to the first equivalence calculation circuit 202. For example, for W1in, which is connected to outputs N1out and E1out, but not to outputs S1out and W1out, the connection sequence of W1in is 0110 for a circuit whose input order is WNES, and similarly, the connection sequence of E1in is 1000 for a circuit whose input order is E1out and E1in are connected to outputs W1 out.
S603: the switching input coding circuit receives the Berger code of the switching output information and calculates the residual code of the Berger code of the switching output information to obtain a first output code.
In this embodiment, based on the above embodiment, the switched input coding circuit performs a residue code modulo operation on the output result number 0001 to obtain a first output code.
Referring to fig. 6 and 10, fig. 10 is a schematic flow chart of an electronic cell detection method according to another embodiment of the present invention, and step S502 may be detailed as follows based on the above-mentioned embodiment:
s701: function input information is input to the function input encoding circuit.
S702: the functional input encoding circuit receives functional input information and outputs parity bits of the functional input information.
In this embodiment, the functional input encoding circuit is used for calculating parity bits of functional input information, and mainly comprises an and gate array and an xor gate array. For example, referring to fig. 13, it is assumed that the input/output block width is 2, W1out and E1out are connected to function signals, LUT input ports are S1in, S2in, E1in and W2in, 8 input signals S1in, S2in, E1in, E2in, N1in, N2in, W1in and W2in are input to a function signal input encoding circuit, and the function signal input encoding circuit is composed of an and gate array and an xor gate, where the number of and gates is the same as the number of input terminals of the xor gate and is equal to the number of input/output block inputs.
Where MNC (7) to MNC (0) are functional signal input screening genes, and T is an encoded value, i.e., a parity of functional input information. The AND gate array is responsible for screening input signals from W2in to S1in, when the input port corresponding to the functional signal input screening gene is the LUT input port, the functional signal input screening gene is 1, otherwise, the functional signal input screening gene is 0, and the MNC is 10010011 because the LUT input ports are S1in, S2in, E1in and W2 in. And (4) processing the screened signals by an exclusive-OR gate to obtain a parity check bit T.
S703: the second equivalence circuit receives the parity bits and computes a second output code based on the parity bits.
In this embodiment, the second equivalent circuit performs mainly two equivalent conversions. Firstly, converting the parity check bit of the function input information into a function signal through a function check gene, and secondly, calculating a Berger code of the function signal.
In this embodiment, each group of LUT inputs corresponds to one functional check gene, and the result of the xor operation between the functional check gene and the parity bit is the same as the functional signal. Thus, the functional signal X can be obtained by xoring the parity bits of the functional input information with the functional check gene.
Berger code calculation for functional signal X, with B in Berger code1The code calculation method is described as an example, and Berger code detection by the function input circuit is described as follows:
the function signals are connected with 0 to 4n outputs of the input-output module, so that the detection circuit part of the second equivalent circuit is designed to be multiplied with a 4n connection sequence by referring to the Berger code detection method of the switching input circuit, and the Berger code check information of each group is obtained. Taking the outputs W1out, N1out, E1out and S1out as an example, when the input of the transition between N1out and S1out is 0 and W1out and E1out are connected to the functional signal, if the value of the functional signal X is 1 at this time, the outputs W1out, N1out, E1out and S1out are 1010, and the Berger code check information is 10. When the connection sequence of the function signal is 1010 and the equivalent operation is performed using the function signal, it is found that b (x) is 1, b (y) is 10, and b (c) is 0, the second output code b(s) is: b(s) ═ b (x) × b (y) -b (c).
Wherein the linker sequence of the functional signal (herein referred to as the second linker sequence) is obtained according to the second configuration gene shown in FIG. 6. For example, the second configuration gene is the configuration gene input to the second equivalent arithmetic circuit 204, and includes the configuration information input to the second equivalent arithmetic circuit 204. For example, for a functional signal X, which is connected to W1out and E1out, the connection sequence corresponding to the functional signal X is 1010 for a circuit with WNES as the input sequence.
The second equivalent circuit in this embodiment is the second equivalent operation circuit 204 of fig. 6.
Referring to fig. 11, fig. 11 is a schematic flow chart of an electronic cell detection method according to another embodiment of the present invention, and step S703 may be detailed as follows based on the above embodiment:
s801: a functional signal is determined based on the parity check bits and the functional check bits.
In this embodiment, the functional signal is obtained by determining the parity check bit and the functional check bit, i.e. performing xor on the parity check bit and the functional check bit.
S802: and calculating the Berger code of the functional signal according to the functional signal and the connection sequence to obtain a second output code.
In this embodiment, the second output code is obtained from the Berger code of the function signal and the concatenation sequence, that is, the second output code b(s) is obtained from formula b(s) ═ b (x) × b (y) -b (c). Wherein X is a functional signal, Y is a linker sequence, and b (c) ═ 0.
Optionally, as a specific implementation manner of the electronic detection method provided in the embodiment of the present invention, the method for determining the function check bit includes:
if the parity bit is equal to the predetermined functional configuration gene, the functional configuration gene is equal to 0.
If the parity bit is not equal to the predetermined functional configuration gene, the functional configuration gene is equal to 1.
In the present embodiment, for example, if the function input information is 0000, the parity is 0. If the default configuration base is 0, the function check base is 0, and if the default configuration base is 1, the function check base is 0. The function input information is 1110, the parity bit is 1. If the default configuration base is 0, the function checking base is 1, and if the default configuration base is 1, the function checking base is 1.
Optionally, referring to fig. 12, fig. 12 is a schematic flow chart of an electronic cell detection method according to another embodiment of the present invention, and on the basis of the above embodiment, step S802 may be detailed as follows:
s901: and calculating the residue code of the connecting sequence to obtain a functional remainder check gene.
S902: and checking the gene and the functional signal according to the functional remainder to obtain a second output code.
In this embodiment, the connecting sequence is a connecting sequence of the functional signal, and the residue number check gene can be obtained by performing residue code modulo operation on the connecting sequence, so as to shorten the number of connecting sequence bits. And obtaining a second output code according to the shortened connecting sequence and the function signal. In other words, in b(s) ═ b (X) × b (y) -b (c), X may be a shortened concatenation sequence, that is, the functional remainder check gene is X, and the Berger code is calculated.
Those of ordinary skill in the art will appreciate that the elements and steps of the various examples described in connection with the embodiments disclosed herein may be embodied in electronic hardware, computer software, or combinations of both, and that the components and steps of the various examples have been described in a functional general in the foregoing description for the purpose of illustrating clearly the interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
It can be clearly understood by those skilled in the art that, for convenience and brevity of description, the specific working processes of the modules and units described above may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.
In the several embodiments provided in the present application, it should be understood that the disclosed modules and methods may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, a division of a unit is merely a logical division, and an actual implementation may have another division, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may also be an electric, mechanical or other form of connection.
Units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment of the present invention.
In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.
While the invention has been described with reference to specific embodiments, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (9)
1. An electronic cell self-checking method, comprising:
determining a first code of the electronic cell address generating module based on the residue code;
determining a second code of the electronic cell input and output module based on the Berger code and the residual code;
inputting the first code and the second code to a first TRC cascade circuit to obtain fault indication information of the electronic cell;
wherein the determining a first code of the electronic cell address generation module based on the residue code comprises:
generating first verification information of the electronic cell address generation module based on the residual code;
inputting the address output information of the address generation module to a residual code checker to obtain a first check bit;
and inputting the first check information and the first check bit to a second TRC cascade circuit to obtain a first code.
2. The method as claimed in claim 1, wherein the inputting the address output information of the address generation module to the residue code checker to obtain the first check bit comprises:
inputting the address output information of the address generation module to a residual code checker;
and the residual code checker calculates the residual code of the address output information to obtain a first check bit.
3. The electronic cell self-test method according to claim 1, wherein the determining the second code of the electronic cell input-output module based on the Berger code and the residue code comprises:
generating second check information of the electronic cell input and output module based on the Berger code and the residual code;
inputting the output information of the input/output module to an encoding circuit to obtain a second check bit;
and inputting the second check information and the second check bit to a third TRC cascade circuit to obtain a second code.
4. The method for electronic cell self-test according to claim 3, wherein the output information of the input/output module includes switching input information and functional input information, and the inputting the output information of the input/output module to the encoding circuit to obtain the second check bit includes:
inputting the switching input information to a first coding circuit to obtain a first output code;
inputting the function input information to a second coding circuit to obtain a second output code;
a second parity bit is determined from the first output encoding and the second output encoding.
5. The method for electronic cellular self-test according to claim 4, wherein the first encoding circuit comprises a first equivalent circuit and a switched input encoding circuit; the inputting the switching input information to the first encoding circuit to obtain a first output code comprises:
inputting the switching input information to the first equivalent circuit;
the first equivalent circuit calculates and outputs a Berger code of the switching input information;
and the transit input coding circuit receives the Berger code of the transit input information and calculates the residual code of the Berger code of the transit input information to obtain a first output code.
6. The electronic cell self-test method according to claim 4, wherein the second encoding circuit includes a functional input encoding circuit and a second equivalent circuit, and the inputting the functional input information to the second encoding circuit to obtain a second output code includes:
inputting the function input information to the function input encoding circuit;
the function input encoding circuit receives the function input information and outputs parity bits of the function input information;
and the second equivalent circuit receives the parity check bit and calculates to obtain a second output code according to the parity check bit.
7. The electronic cellular self-test method of claim 6, wherein the second equivalent circuit receiving the parity bits and calculating a second output code from the parity bits comprises:
determining a functional signal according to the parity check bit and the functional check bit;
and calculating a Berger code of the functional signal according to the functional signal and the connection sequence to obtain a second output code.
8. The electronic cell self-test method according to claim 7, wherein the method for determining the function check bits comprises:
if the parity bit is equal to a preset function configuration gene, the function check gene is equal to 0;
and if the parity bit is not equal to the preset function configuration gene, the function check gene is equal to 1.
9. The method for electronic cellular self-test according to claim 7, wherein the calculating the Berger code of the functional signal according to the functional signal and the connection sequence to obtain the second output code comprises:
calculating the residue code of the connecting sequence to obtain a functional remainder check gene;
and obtaining a second output code according to the functional remainder check gene and the functional signal.
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