CN117240243A - Signal phase control method of compact-size high-precision numerical control phase shifter based on GaAs technology - Google Patents
Signal phase control method of compact-size high-precision numerical control phase shifter based on GaAs technology Download PDFInfo
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Abstract
The invention belongs to the field of semiconductor integrated circuit design, and particularly relates to a signal phase control method of a compact-size high-precision numerical control phase shifter based on a GaAs process, which comprises the following steps: a first power distribution network, a second power distribution network, a quadrature network, a first dual-phase attenuator, and a second dual-phase attenuator; the input signal is converted into two paths of signals through a first power distribution network; inputting the two paths of signals into a quadrature network for phase adjustment to obtain two paths of quadrature signals; respectively inputting two paths of orthogonal signals into a first biphase attenuator and a second biphase attenuator for amplitude adjustment; inputting the adjusted signal output by the first biphase attenuator and the adjusted signal output by the first biphase attenuator into a second power distribution network for vector addition to obtain a phase-shifted signal; the power distribution network adopts a lumped Wilkinson power divider structure, so that the chip size is effectively reduced while the phase shifting precision is ensured.
Description
Technical Field
The invention belongs to the field of semiconductor integrated circuit design, and particularly relates to a signal phase control method of a compact-size high-precision numerical control phase shifter based on a GaAs process.
Background
The Digital phase shifter (Digital-Controlled Phase Shifter) is a key component in the analog phased array receiving/transmitting (T/R) component, and has the functions of step control on the phase of a radio frequency signal, and the insertion loss, linearity, phase resolution, amplitude-phase error and other performance parameters of the Digital phase shifter have great influence on the performance of the system. The GaAs process is widely used for manufacturing the numerical control phase shifter by virtue of the advantages of high cut-off frequency, high linearity, low loss and the like. With the rapid development of miniaturized application systems such as airborne phased array radar, spaceborne phased array radar, microwave guide heads and the like, urgent demands are made on compact-size high-precision numerical control phase shifters. The traditional GaAs numerical control phase shifter mostly adopts a switch filter structure and a reflection type structure, a plurality of filter networks formed by inductance-capacitance devices and 3dB quadrature couplers are contained in the switch filter structure and the reflection type structure, a large amount of chip area can be occupied, and the chip size of the switch filter structure can be rapidly increased along with the improvement of the phase resolution and the phase precision of the phase shifter. Taking X wave band as an example, the chip area of the existing 6-bit digital phase shifter based on GaAs technology is generally larger than 1.5mm 2 Is unfavorable for the miniaturization of the whole system.
Disclosure of Invention
In order to solve the problems in the prior art, the invention provides a signal phase control method of a compact size high-precision numerical control phase shifter based on a GaAs process, which comprises the following steps: a first power distribution network, a second power distribution network, a quadrature network, a first dual-phase attenuator, and a second dual-phase attenuator; the input signal is converted into two paths of signals through a first power distribution network; inputting the two paths of signals into a quadrature network for phase adjustment to obtain two paths of quadrature signals with the same amplitude and 90-degree phase difference; respectively inputting two paths of orthogonal signals into a first biphase attenuator and a second biphase attenuator for amplitude adjustment; and inputting the adjusted signal output by the first biphase attenuator and the adjusted signal output by the second biphase attenuator into a second power distribution network for vector addition to obtain a phase-shifted signal.
Preferably, the first power distribution network comprises: coupling inductance Lc1, coupling inductance Lc2, capacitance Ca1, capacitance Ca2, and resistance Ra1; the coupling inductor Lc1 is composed of an inductor L1 and an inductor L2; the coupling inductor Lc2 is composed of an inductor L3 and an inductor L4; one end of the capacitor Ca1 is grounded, the other end of the capacitor Ca1 is connected with the inductor L1 and the inductor L2 respectively, and the other end of the inductor L1 is connected with one end of the inductor L3; the other end of the inductor L2 is connected with a resistor Ra1, and the other end of the resistor Ra1 is connected with one end of the inductor L4; the other end of the inductor L3 and the other end of the inductor L4 are connected with a capacitor Ca2; the other end of the capacitor Ca2 is grounded.
Preferably, the quadrature network comprises a T-type high-pass filter and a T-type low-pass filter, wherein the T-type high-pass filter is composed of a capacitor Cf1, a capacitor Cf2 and an inductor Lf 1; the T-shaped low-pass filter consists of an inductor Lf2, an inductor Lf3 and a capacitor Cf 3.
Preferably, the dual-phase attenuator adopts a cross-connected multi-way switch array structure, namely the dual-phase attenuator comprises two balun and four switch arrays; the first output end of the first balun is connected with the input ends of the first switch array and the second switch array, and the second output end of the first balun is connected with the input ends of the third switch array and the fourth switch array; the output end of the first switch array is respectively connected with the first input end of the second balun and the output end of the third switch array; the output end of the second switch array is respectively connected with the output end of the fourth switch array and the second input end of the second balun.
Further, the switch array is formed by connecting n switch transistors in parallel, wherein the gates of the switch transistors M1, M2, M3, …, mn are respectively connected to the digital logic signals a1, a2, a3, …, an.
The invention has the beneficial effects that:
the invention is based on the GaAs process, adopts a passive vector synthesis architecture, and is beneficial to realizing high linearity; the power distribution network adopts a lumped Wilkinson power divider structure, the dual-phase attenuator adopts a cross-bridge multi-way switch array structure, and the chip size is effectively reduced while the phase shifting precision is ensured.
Drawings
FIG. 1 is a schematic diagram of a compact size high precision numerical control phase shifter based on a GaAs process of the present invention;
FIG. 2 is a diagram of a power distribution network according to the present invention;
FIG. 3 is a diagram of an orthogonal network architecture of the present invention;
FIG. 4 is a block diagram of a dual phase attenuator of the present invention;
FIG. 5 is a block diagram of a switch array of the present invention;
fig. 6 is a diagram of the coupled electrical and balun structure of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
A signal phase control method of a compact size high precision numerical control phase shifter based on GaAs technology comprises the following steps: a first power distribution network, a second power distribution network, a quadrature network, a first dual-phase attenuator, and a second dual-phase attenuator; the input signal is converted into two paths of signals through a first power distribution network; inputting the two paths of signals into a quadrature network for phase adjustment to obtain two paths of quadrature signals with the same amplitude and 90-degree phase difference; respectively inputting two paths of orthogonal signals into a first biphase attenuator and a second biphase attenuator for amplitude adjustment; and inputting the adjusted signal output by the first biphase attenuator and the adjusted signal output by the second biphase attenuator into a second power distribution network for vector addition to obtain a phase-shifted signal.
A compact size high precision digital controlled phase shifter based on GaAs process, as shown in fig. 1, the structure comprising: the power distribution network 1, the power distribution network 2, the orthogonal network, the dual-phase attenuator 1 and the dual-phase attenuator 2 are five modules, wherein the power distribution network 1 and the power distribution network 2 have the same structure, and the dual-phase attenuator 1 and the dual-phase attenuator 2 have the same structure.
The whole circuit of the compact size high-precision digital controlled phase shifter based on the GaAs process comprises an input end, an output end and four groups of n-bit digital logic control ends, which are respectively [ Va1, va2, va3 … Van ], [ Vb1, vb2, vb3 … Vbn ], [ Vc1, vc2, vc3 … Vcn ] and [ Vd1, vd2, vd3 … Vdn ], wherein [ Vb1, vb2, vb3 … Vbn ] is an inverted signal of [ Va1, va2, va3 … Van ] (namely, vb1=Va1 is non-Vb2=Va2 is non- …), and [ Vd1, vd2, vd3 … Vdn ] is an inverted signal of [ Vc1, vc2, vc3 … Vcn ]. The power distribution network comprises A1 end, A2 end and A3 end, the orthogonal network comprises A1 end, A2 end, A3 end and a 4 end, and the dual-phase attenuator 1 comprises A1 end, A2 end, an A3 end, a … end, an end, a B1 end, a B2 end, a B3 end, a … end and a Bn end. The input end is connected with the 1 end of the power distribution network 1, the 2 end of the power distribution network 1 is connected with the 1 end of the orthogonal network, and the 3 end of the power distribution network 1 is connected with the 3 end of the orthogonal network; the end 2 of the orthogonal network is connected with the end 1 of the dual-phase attenuator 1, and the end 4 of the orthogonal network is connected with the end 1 of the dual-phase attenuator 2; the 2 end of the dual-phase attenuator 1 is connected with the 2 end of the power distribution network 2, the 2 end of the dual-phase attenuator 2 is connected with the 3 end of the power distribution network 2, and the 1 end of the power distribution network 2 is connected with the output end; the [ A1, A2, A3 … An ] ends of the dual-phase attenuator 1 are respectively connected with the control ends [ Va1, va2, va3 … Van ], the [ B1, B2, B3 … Bn ] ends of the dual-phase attenuator 1 are respectively connected with the control ends [ Vb1, vb2, vb3 … Vbn ], the [ A1, A2, A3 … An ] ends of the dual-phase attenuator 2 are respectively connected with the control ends [ Vc1, vc2, vc3 … Vcn ], and the [ B1, B2, B3 … Bn ] ends of the dual-phase attenuator 2 are respectively connected with the control ends [ Vd1, vd2, vd3 … Vdn ].
In this embodiment, the circuit operates according to the following principle: the power distribution network 1 converts an input signal into two signals, both of which have the same amplitude and phase. The two paths of signals are subjected to phase adjustment through a quadrature network, and two paths of quadrature signals with the same amplitude and 90-degree phase difference are output from the 2 end and the 4 end of the quadrature network. The two orthogonal signals are then subjected to amplitude adjustment in the two-phase attenuator 1 and the two-phase attenuator 2 respectively, and the two signals subjected to amplitude adjustment are finally subjected to vector addition in the power distribution network 2 to output signals with required phases. The output signal of the dual-phase attenuator after the amplitude adjustment of the signal can be in phase with the input signal or in phase opposition (180 degrees out of phase). The vector addition in the power distribution network 2 can thus cover four quadrants and the output signal phase can cover 0-360 °. The attenuation amounts of the dual-phase attenuator 1 and the dual-phase attenuator 2 are independently controlled by four sets of n-bit digital logic control signals [ Va1, va2, va3 … Van ], [ Vb1, vb2, vb3 … Vbn ], [ Vc1, vc2, vc3 … Vcn ], and [ Vd1, vd2, vd3 … Vdn ], wherein [ Vb1, vb2, vb3 … Vbn ] is an inverted signal of [ Va1, va2, va3 … Van ] (i.e., v1=v1 is non-taken, v2=v2 is non- …), and [ Vd1, vd2, vd3 … Vdn ] is an inverted signal of [ Vc1, vc2, vc3 … Vcn ]. The larger the value of n is, the higher the amplitude adjustment resolution and the accuracy of the dual-phase attenuator are, so that the higher the phase shift resolution and the accuracy of the whole phase shifter are. In particular, when the two-phase attenuator 1 is in-phase minimum attenuation and the two-phase attenuator 2 is full attenuation, the phase shifter is in a reference state; when the dual-phase attenuator 1 is completely attenuated and the dual-phase attenuator 2 is in-phase minimum attenuated, the phase shifter is in a 90-degree phase shifting state; when the two-phase attenuator 1 is the minimum attenuation of the opposite phase and the two-phase attenuator 2 is the complete attenuation, the phase shifter is in a 180-degree phase shifting state; when the two-phase attenuator 1 is full attenuation and the two-phase attenuator 2 is anti-phase minimum attenuation, the phase shifter is in a 270 DEG phase shifting state.
In this embodiment, as shown in fig. 2, the power distribution network adopts a compact size lumped wilkinson power divider structure, and the function of the power distribution network is to convert one signal into two signals with the same amplitude and phase (the power distribution network 2 is to use the two signals in reverse, that is, the two signals are combined into one signal, and the combining mode is vector addition). The power distribution network has the advantages of small loss, good port matching characteristic, small amplitude-phase error and the like. And the circuit only comprises five lumped devices of coupling inductors Lc1 and Lc2, capacitors Ca1 and Ca2 and a resistor Ra1, and the occupied chip size is far smaller than that of a traditional distributed Wilkinson power divider.
Specifically, the power distribution network includes: coupling inductance Lc1, coupling inductance Lc2, capacitance Ca1, capacitance Ca2, and resistance Ra1; the coupling inductor Lc1 is composed of an inductor L1 and an inductor L2; the coupling inductor Lc2 is composed of an inductor L3 and an inductor L4; one end of the capacitor Ca1 is grounded, the other end of the capacitor Ca1 is connected with the inductor L1 and the inductor L2 respectively, and the other end of the inductor L1 is connected with one end of the inductor L3; the other end of the inductor L2 is connected with a resistor Ra1, and the other end of the resistor Ra1 is connected with one end of the inductor L4; the other end of the inductor L3 and the other end of the inductor L4 are connected with a capacitor Ca2; the other end of the capacitor Ca2 is grounded.
As shown in fig. 3, which is a structure diagram of a quadrature network, the capacitors Cf1, cf2 and the inductor Lf1 form a T-type high-pass filter, and the inductors Lf2, lf3 and the capacitor Cf3 form a T-type low-pass filter. The signal input from the 1 terminal passes through the high-pass filter to generate phase lead, and the signal input from the 2 terminal passes through the low-pass filter to generate phase lag. By reasonably selecting the capacitance and inductance values, two paths of signals output from the 2 end and the 4 end have the same amplitude and 90-degree phase difference.
Specifically, the circuit structure of the quadrature network includes 1 terminal, 2 terminal, 3 terminal, 4 terminal, capacitors Cf1, cf2, cf3, and inductors Lf1, lf2, lf3. The end 1 of the orthogonal network is connected with one end of a capacitor Cf1, the other end of the Cf1 is connected with one end of an inductor Lf1 and one end of a capacitor Cf2, the other end of the Lf1 is grounded, and the other end of the Cf2 is connected with the end 2 of the orthogonal network; the 3 ends of the orthogonal network are connected with one end of an inductor Lf2, the other end of the Lf2 is connected with one end of a capacitor Cf3 and one end of the inductor Lf3, the other end of the Cf3 is grounded, and the other end of the Lf3 is connected with the 4 ends of the orthogonal network.
In this embodiment, the dual-phase attenuator includes six modules including balun 1, balun 2, switch array 1, switch array 2, switch array 3, and switch array 4, where the balun 1 and the balun 2 have the same structure, and the switch arrays 1 to 4 have the same structure; the dual-phase attenuator comprises A1 end, A2 end and two groups of n-bit digital logic control ends, namely [ A1, A2, A3 … An ] and [ B1, B2, B3 … Bn ]; balun includes 1 end, 2 end and 3 end; the switch array comprises a1 terminal, a2 terminal and n-bit digital logic control terminals a1, a2, a3, … and an. The 1 end of the dual-phase attenuator is connected with the 1 end of the balun 1; the end 2 of the balun 1, the end 1 of the switch array 1 and the end 1 of the switch array 2 are connected; the 3 end of the balun 1, the 1 end of the switch array 3 and the 1 end of the switch array 4 are connected; the 2 end of the switch array 1, the 2 end of the switch array 3 and the 2 end of the balun 2 are connected; the 2 end of the switch array 2, the 2 end of the switch array 4 and the 3 end of the balun 2 are connected; the 1 end of the balun 2 is connected with the 2 end of the dual-phase attenuator; the [ A1, A2, A3 … An ] ends of the switch array 1 are respectively connected with the control ends [ A1, A2, A3 … An ] of the dual-phase attenuator, and the [ A1, A2, A3 … An ] ends of the switch array 4 are also respectively connected with the control ends [ A1, A2, A3 … An ] of the dual-phase attenuator; the [ a1, a2, a3 … an ] ends of the switch array 2 are respectively connected with the control ends [ B1, B2, B3 … Bn ] of the dual-phase attenuator, and the [ a1, a2, a3 … an ] ends of the switch array 3 are also respectively connected with the control ends [ B1, B2, B3 … Bn ] of the dual-phase attenuator.
Fig. 4 shows a block diagram of a dual-phase attenuator, which adopts a cross-over multi-channel switch array structure and is composed of two balun and four switch arrays. The working principle is as follows: the balun 1 converts a single-ended signal input by the end of the dual-phase attenuator 1 into a differential signal (the amplitude is the same and the phase difference is 180 degrees), wherein the end 2 of the balun 1 outputs an in-phase signal, and the end 3 of the balun 1 outputs an anti-phase signal. The differential signal is subjected to amplitude adjustment through four switch arrays, and the differential signal subjected to amplitude adjustment is converted into a single-ended signal by the balun 2 and is output by the end of the dual-phase attenuator 2. The 1 end and the 2 end of the switch array 2 are respectively connected with the in-phase end and the anti-phase end of the differential signal in a bridging way, and the 1 end and the 2 end of the switch array 3 are respectively connected with the anti-phase end and the in-phase end of the differential signal in a bridging way. Thus, the output signals of switch array 1 and switch array 3 cancel each other, and the output signals of switch array 2 and switch array 4 cancel each other. The attenuation of the switch array is determined by the control terminals a1, a2, a3, …, an logic. Because the logic signals of the control ends of the switch array 1 and the switch array 4 are the same and are A1, A2, A3, … and An, the attenuation of the switch array 1 and the attenuation of the switch array 4 are the same and are marked as att1; similarly, the logic signals at the control ends of switch array 2 and switch array 3 are the same, and B1, B2, B3, …, bn, so the attenuation of switch array 2 and switch array 3 is the same, denoted att2. When att1 is less than att2, the output signals of the switch array 2 and the switch array 3 are smaller than the output signals of the switch array 1 and the switch array 4, and the biphase attenuator outputs an in-phase signal with amplitude adjusted; when att1 > att2, the output signals of switch array 2 and switch array 3 are greater than the output signals of switch array 1 and switch array 4, and the dual-phase attenuator outputs an amplitude-adjusted inverted signal. Since the control logic [ A1, A2, A3, …, an ] and [ B1, B2, B3, …, bn ] are inverted, att2 is minimal when att1 is maximal, and vice versa. In particular, when att1 is minimum, att2 is maximum, and the dual-phase attenuator is in-phase output minimum attenuation state; when att1 is maximum, att2 is minimum, and the dual-phase attenuator is in an inverse output minimum attenuation state; when att1=att2, the in-phase and anti-phase signals inside the dual-phase attenuator cancel completely, and the dual-phase attenuator attenuates completely.
As shown in fig. 5, the switch array includes n switch transistors M1, M2, M3, …, mn, 1-terminal, 2-terminal, and n-bit digital logic control terminals a1, a2, a3, …, an. The drains of the n switch transistors M1, M2, M3, … and Mn are all connected together and connected with the 1 end of the switch array; the sources of the n switch transistors M1, M2, M3, … and Mn are all connected together and connected with the 2 end of the switch array; the gates of the switching transistors M1, M2, M3, …, mn are connected to a1, a2, a3, …, an of the switching array, respectively.
Alternatively, the switching transistors M1, M2, M3, …, mn are of one of GaAs MESFET, gaAs HEMT and GaAs pHEMT.
The operating principle of the switch array comprises: when the digital logic signal is at a high level, the switching transistor is turned on, and the switching transistor is equivalent to an on-resistance; when the digital logic signal is at a low level, the switching transistor is turned off, and the on-resistance is infinite. The switching transistors M1, M2, M3, …, mn are sequentially increased in size in a two-fold incremental relationship, thereby achieving a step-down controlled by the digital logic signal. In particular, when a1, a2, a3, …, an are all high, the switching transistors M1, M2, M3, …, mn are all on, and the switching array is at minimum attenuation; when a1, a2, a3, …, an are all low, the switching transistors M1, M2, M3, …, mn are all off, and the switching array is fully attenuated.
An example of a layout implementation of a coupled inductor in a power distribution network is shown in fig. 6 (a), which uses a planar spiral structure. An example of a layout implementation of balun in a dual-phase attenuator is shown in fig. 6 (b), which uses a coplanar 5-port transformer structure. The structure has good symmetry and smaller size, the coupling coefficient is determined by the metal thickness, the metal line width and the metal line spacing, and the inductance value is determined by the coil number and the inner diameter.
In a typical embodiment, the X-band digital control phase shifter realized by adopting the circuit structure can realize 6-phase resolution, insertion loss is less than 15dB, root mean square phase precision is better than 2 degrees, amplitude error is less than +/-1 dB, input 1dB compression point is greater than 22dBm, and chip size is only 1.2mm multiplied by 0.6mm.
While the foregoing is directed to embodiments, aspects and advantages of the present invention, other and further details of the invention may be had by the foregoing description, it will be understood that the foregoing embodiments are merely exemplary of the invention, and that any changes, substitutions, alterations, etc. which may be made herein without departing from the spirit and principles of the invention.
Claims (6)
1. The signal phase control method of the compact size high-precision numerical control phase shifter based on the GaAs process is characterized by comprising the following steps of: a first power distribution network, a second power distribution network, a quadrature network, a first dual-phase attenuator, and a second dual-phase attenuator; the input signal is converted into two paths of signals through a first power distribution network; inputting the two paths of signals into a quadrature network for phase adjustment to obtain two paths of quadrature signals with the same amplitude and 90-degree phase difference; respectively inputting two paths of orthogonal signals into a first biphase attenuator and a second biphase attenuator for amplitude adjustment; and inputting the adjusted signal output by the first biphase attenuator and the adjusted signal output by the second biphase attenuator into a second power distribution network for vector addition to obtain a phase-shifted signal.
2. The method for controlling signal phase of a compact size high precision digitally controlled phase shifter based on GaAs process according to claim 1, wherein the first power distribution network comprises: coupling inductance Lc1, coupling inductance Lc2, capacitance Ca1, capacitance Ca2, and resistance Ra1; the coupling inductor Lc1 is composed of an inductor L1 and an inductor L2; the coupling inductor Lc2 is composed of an inductor L3 and an inductor L4; one end of the capacitor Ca1 is grounded, the other end of the capacitor Ca1 is connected with the inductor L1 and the inductor L2 respectively, and the other end of the inductor L1 is connected with one end of the inductor L3; the other end of the inductor L2 is connected with a resistor Ra1, and the other end of the resistor Ra1 is connected with one end of the inductor L4; the other end of the inductor L3 and the other end of the inductor L4 are connected with a capacitor Ca2; the other end of the capacitor Ca2 is grounded.
3. The method for controlling the signal phase of a compact size high precision digitally controlled phase shifter based on GaAs technology according to claim 1, wherein the circuit structure of the second power distribution network is identical to the circuit structure of the first power distribution network.
4. The signal phase control method of the compact size high precision digital controlled phase shifter based on the GaAs process according to claim 1, wherein the quadrature network comprises a T-shaped high-pass filter and a T-shaped low-pass filter, wherein the T-shaped high-pass filter is composed of a capacitor Cf1, a capacitor Cf2 and an inductor Lf 1; the T-shaped low-pass filter consists of an inductor Lf2, an inductor Lf3 and a capacitor Cf 3.
5. The method for controlling the signal phase of the compact size high-precision numerical control phase shifter based on the GaAs process according to claim 1, wherein the dual-phase attenuator adopts a cross-bridge multi-path switch array structure, namely the dual-phase attenuator comprises two balun and four switch arrays; the first output end of the first balun is connected with the input ends of the first switch array and the second switch array, and the second output end of the first balun is connected with the input ends of the third switch array and the fourth switch array; the output end of the first switch array is respectively connected with the first input end of the second balun and the output end of the third switch array; the output end of the second switch array is respectively connected with the output end of the fourth switch array and the second input end of the second balun.
6. The method for controlling signal phase of compact size high precision digital controlled phase shifter based on GaAs process according to claim 5, wherein the switch array is composed of n switch transistors connected in parallel, wherein the gates of the switch transistors M1, M2, M3, …, mn are connected to the digital logic signals a1, a2, a3, …, an, respectively.
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