CN117240056A - Switching circuit, corresponding equipment and method - Google Patents

Abstract

Embodiments of the present disclosure relate to switching circuits, corresponding devices, and methods. The switching circuit comprises a first half-bridge and a second half-bridge for powering an electrical load via a filter network. During the alternating switching sequence, the first transistor pair (high side in one half-bridge and low side in the other half-bridge) is switched to a non-conductive state and the second transistor pair (high side in the other half-bridge and low side in the one half-bridge) is switched to a conductive state. The current flow line is provided by an inductance between the outputs of the half-bridge, the first switch and the second switch. In the medium-high power mode, the first switch and the second switch are in a conductive state between switching the first pair of transistors to a non-conductive state and switching the second pair of transistors to a conductive state. In the low power or static power mode, switching of the first switch and the second switch to the conducting state is inhibited due to the longer delay applied.

Description

Switching circuit, corresponding equipment and method

Priority claim

The present application claims the benefit of priority from italian patent application No. 102022000012683 filed 15 at 2022, month 06, the contents of which are incorporated herein by reference in their entirety to the maximum extent allowed by law.

Technical Field

The present description relates to switching circuits.

One or more embodiments may be applied to bridge switching power stages in, for example, class D bridge power amplifiers.

Background

Power dissipation is an important parameter for switching power stages.

It is desirable to minimize power dissipation not only at medium and high output power levels, but also at low power levels and under static conditions: in an audio power device, the nature of the signal is such that a non-negligible part of the total operating time lies in the region from pout=0 (zero output power, i.e. static state) to an output power Pout of less than 1/100 of the maximum output power.

For this reason, in addition to the power dissipated during high signal operation, the power dissipated during low signal operation and in the static state also works: in the latter case the dissipated power will affect the styling of the associated heat sink and in the case of a battery powered device the duration of the battery used to power the device.

The automotive market is a field where dissipated power targets under various conditions, including operation at low output power, are becoming increasingly stringent.

For example, reducing the power dissipation of medium-low to high output power has been considered in U.S. patent publication No. 2019/0238094 (corresponding to EP3522373B 1), the contents of which are incorporated herein by reference.

In this document, a switching circuit stage configured to supply a load via a filter network is disclosed, the switching circuit stage comprising control circuit means configured to control an alternating switching sequence of transistors in a half bridge of the switching circuit stage. A current flow line is provided between the output nodes of the half bridge, the current flow line comprising an inductance between the two switches. The first capacitor and the second capacitor are coupled to an output node of the half bridge. At intervals of the alternating switching sequence of the transistors in the half bridge between switching the first pair of transistors to a non-conductive state and switching the second pair of transistors to a conductive state, the control circuit means switches the first switch and the second switch to a conductive state.

There is a need in the art to contribute to providing improved solutions that reduce power dissipation while paying attention to low power operation and/or static state conditions.

Disclosure of Invention

One or more embodiments may relate to a circuit.

One or more embodiments may relate to a corresponding device (e.g., a class D audio power amplifier).

One or more embodiments may relate to a corresponding method.

In one embodiment, a circuit includes a switching circuit stage and a control circuit arrangement. The switching circuit stage includes first and second half-bridges including first and second high-side transistors, the first and second half-bridges including respective output nodes therebetween, the output nodes configured to: the load is powered via a respective filter network between the output node and the electrical load. The control circuitry is configured to: an alternating switching sequence of high-side and low-side transistors in a first half-bridge and a second half-bridge is controlled, wherein the first pair of transistors is switched to a non-conductive state, the first pair of transistors comprises a high-side transistor in one of the half-bridges and a low-side transistor in the other of the half-bridges, and the second pair of transistors is switched to a conductive state, the second pair of transistors comprises a high-side transistor in the other of the half-bridges and a low-side transistor in the one of the half-bridges.

The circuit further includes: a current flow line between the output nodes in the first half-bridge and the second half-bridge, the current flow line comprising an inductance having opposing terminals coupled to first and second switches, the first and second switches being selectively switchable between a non-conductive state and at least one conductive state; and a first capacitor and a second capacitor coupled to the output nodes of the first half-bridge and the second half-bridge.

The control circuitry is configured to alternately: operating in a first mode of operation in which the control circuitry is responsive to switching the first pair of transistors to a non-conductive state and the second pair of transistors to a conductive state to switch the first switch and the second switch to at least one conductive state at intervals of the alternating switching sequence; or in a second mode of operation in which the control circuitry is responsive to switching the first pair of transistors to a non-conductive state and the second pair of transistors to a conductive state to avoid switching the first switch and the second switch to at least one conductive state at intervals in the alternating switching sequence.

In one embodiment, an apparatus comprises: a PWM modulator for receiving an input signal and generating therefrom a PWM modulated drive signal; a circuit as described above coupled to the PWM modulator, wherein the first half-bridge and the second half-bridge are configured to be driven by the PWM modulated drive signal; and a respective low pass filter network coupled to the output nodes of the first half-bridge and the second half-bridge.

In one embodiment, a method of amplifying an input signal includes: applying an input signal to a PWM modulator in an apparatus as described above; and obtaining an amplified copy of the input signal at the respective low-pass filter networks coupled to the output nodes of the first half-bridge and the second half-bridge.

Drawings

One or more embodiments will now be described, by way of example only, with reference to the accompanying drawings, in which:

FIG. 1 is an exemplary block diagram of a switching amplifier with reduced switching loss;

FIG. 2 is an exemplary circuit diagram of power stages in an amplifier as illustrated in FIG. 1;

FIG. 2A is an exemplary circuit diagram of a possible implementation of certain elements in the power stage illustrated in FIG. 2;

FIG. 3 includes various diagrams sharing a common time scale, illustrating possible time behavior of certain signals that may occur in an amplifier as illustrated in FIG. 1;

FIG. 4 is an exemplary diagram of a control circuit arrangement that may be coupled to the power stages as illustrated in FIG. 2 to produce the operations as illustrated in FIG. 3;

FIG. 5 is an exemplary flow chart of possible modes of operation of the amplifier as illustrated in the previous figures;

FIG. 6 includes various diagrams sharing a common time scale, illustrating possible time behavior of certain signals that may occur in an amplifier as illustrated in FIG. 1;

FIG. 7 is a block diagram illustrating a possible modification of a switching amplifier in an embodiment according to the present description;

fig. 8 is an exemplary diagram of a control circuit arrangement in a switching amplifier in accordance with an embodiment of the present description;

FIG. 9 includes various diagrams sharing a common time scale illustrating possible time behavior of certain signals that may occur in a switching amplifier in accordance with an embodiment of the present description;

FIGS. 10 and 11 are exemplary flowcharts of possible modes of operation of the switching amplifier in accordance with embodiments of the present description;

FIG. 12 is a general block diagram of a switching amplifier in an embodiment in accordance with the present description;

FIG. 13 is a functional block diagram illustrating possible implementation details of an embodiment;

FIG. 14 is an example flow chart of a possible operation of the elements detailed in FIG. 13;

fig. 15 and 16 are further exemplary timing diagrams of possible operation of the elements detailed in fig. 12-14;

FIG. 17 is a functional block diagram illustrating possible implementation details of an embodiment; and

fig. 18 is a diagram illustrating possible operations of a Finite State Machine (FSM) that may be included in embodiments of the present description.

Detailed Description

Corresponding reference numerals in the different figures generally refer to corresponding parts unless otherwise indicated.

The drawings are drawn to clearly illustrate the relevant aspects of the embodiments and are not necessarily drawn to scale.

The edges of features depicted in the drawings do not necessarily indicate the termination of the feature's range.

Moreover, for simplicity and ease of explanation, the same names may be applied throughout this description to refer to circuit nodes or lines and signals appearing at the nodes or lines.

In the following description, one or more specific details are set forth in order to provide a thorough understanding of examples of the described embodiments. Embodiments may be obtained without one or more of the specific details, or with other methods, components, materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of the embodiments.

References to "an embodiment" or "one embodiment" in the framework of this description are intended to indicate that a particular configuration, structure, or feature described in connection with the embodiment is included in at least one embodiment. Thus, phrases such as "in an embodiment" or "in one embodiment" that may occur in one or more points of the present description do not necessarily refer to the same embodiment. Furthermore, the particular structures, or characteristics may be combined in any suitable manner in one or more embodiments.

The reference numerals used herein are provided for convenience only and thus do not limit the scope of the protection or the embodiments.

Fig. 1 is an exemplary block diagram of a switching circuit, such as a class D audio amplifier a (for use in, for example, a car audio system), that includes a switching bridge architecture and elements for increasing efficiency, including an inductance Laux.

As is conventional IN the art of such switching amplifiers, a (voltage or current) input signal IN is applied to the input circuit arrangement 10 to be processed (IN a manner known per se to a person skilled IN the art) to generate a two-stage PWM (pulse width modulation) modulated signal IN-PWM, which is clocked by a clock signal CLK. The average value of the signal In _ pwm is proportional to the input signal In, with a (fixed frequency) carrier defined by the clock signal CLK.

The PWM modulated signal In PWM is forwarded via a Zero Switching Loss (ZSL) circuit arrangement 12 to a power stage 14, the power stage 14 comprising for example four power transistors plus two switches according to the circuit topology illustrated In fig. 2.

The circuit topology illustrated in fig. 2 corresponds substantially to the solution disclosed in us patent publication No. 2019/0238094 (corresponding to EP3522373B 1) comprising two half-bridge circuits HB1, HB 2.

The two half-bridge circuits HB1, HB2 (each comprising a high-side switch H1, H2 and a low-side switch L1, L2, e.g. a power MOSFET transistor) are driven by two signals in_pwm1, in_pwm2 corresponding to the signal in_pwm provided by the input circuit 10, and PWM modulated power signals are generated across an LC output filter network comprising, e.g., respective inductances Lo1, lo2 and capacitances C1, C2 In a mirror-symmetrical configuration.

In the class D bridge circuit considered herein, the two signals in_pwm1, in_pwm2 corresponding to signal in_pwm and thus the outputs from half-bridges HB1, HB2 will have opposite phases (i.e. 180 ° phase shift): that is, either of the signals in_pwm1 and in_pwm2 is an "inverted" or "reverse" copy of the other.

Thus, an amplified version of the input signal IN will become available at the load L (assuming a resistive value Rload), which is coupled across a first node between the inductance Lo1 and the capacitance C1 and a second node between the inductance Lo2 and the capacitance C2.

The load L (and possibly the LC filter network associated therewith) may be a different element than the amplifier a. Further, the two nodes Vout1, vout2 will hereinafter be referred to as "output" nodes (of the half-bridges HB1, HB 2), although strictly speaking they do not represent the output nodes of the amplifier a (see, for example, fig. 1), between which the load L is coupled.

In the following discussion, the following names of signals/nodes/components will apply:

pout=output power=vout (rms)/(2/rload=iout (rms)/(2×rload)

Pin=input power=power delivered by the power supply=vdd×ivdd

Pdis=power dissipation=pin-Pout

Efficiency = Pout/Pin

Iload=current (absolute value) flowing through load L

Iripple = current flowing through the output filter inductor in the power switching stage. Under static conditions, it is a triangular wave whose value depends on the frequency, vsupply and inductance values

Iripple (peak) =peak (absolute value) of Iripple

Minimum (resistance) value of Rload (min) =load L

Vthr=iripple (peak) ×rload. Output voltage threshold Vds (L1), vds (L2) =l1, L2 for iload=iripple, voltage between drain and source, positive when >0

Vds (H1), vds (H2) =voltage between drain and source of H1, H2, positive when >0

The arrangement as illustrated in fig. 2 comprises a current flow line between the output nodes Vout1, vout2 in the first half-bridge HB1 and the second half-bridge HB 2.

The current flow line between the output nodes Vout1, vout2 comprises an inductance Laux having opposite terminals coupled to the first switch S1 and the second switch S2. The switches S1, S2 may be comprised in the same (monolithic) integrated circuit of the amplifier a (see fig. 1).

The first switch S1 and the second switch S2 are selectively switchable (via signals Cs1a, cs1b and Cs2a, cs2 b) between a non-conductive state and at least one conductive state.

In a possible implementation illustrated in fig. 2A, the switches S1 and S2 comprise first and second (e.g., MOSFET) transistors M1, M2, the first and second transistors M1, M2 having their control electrodes (e.g., gates in the exemplary case of field effect transistors) coupled at a first common node a and having current paths (e.g., source-drain in the exemplary case of field effect transistors) therethrough coupled at a second common node B in an anti-series arrangement. The first circuit is connected between the first common node a and a current path through the first transistor M1 (at a terminal, e.g. at a drain) opposite the second transistor M2. The first circuit comprises a first switch SC1 switchable between a conducting state and a non-conducting state. The second circuit is connected between the first common node a and a current path through a second transistor (at a terminal, e.g., drain) opposite the first transistor. The second electrical path comprises a second switch SC2 switchable between a conducting state and a non-conducting state. The third circuit is connected between the first common node a and the second common node B. The third circuit comprises a third switch SC3 switchable between a conducting state and a non-conducting state; and includes a logic network (e.g., nand gate G12) coupling the third switch SC3 with the first switch SC1 and the second switch SC2.

The logic network is configured to switch the third switch SC3 to: a) Is in a conductive state, wherein both the first switch SC1 and the second switch SC2 are switched to a non-conductive state; and b) a non-conductive state in which either one of the first switch SC1 and the second switch SC2 is switched to the conductive state.

The circuit of fig. 2A may be selectively entered: an "off" operating condition in which the first switch SC1 and the second switch SC2 are non-conductive, thereby preventing the flow of current in the current line between the first electrical line node Va and the second electrical line node Vb, the third switch being conductive; and either of two "on" operating conditions a) or b). Wherein: in case the third switch SC3 is not conductive in condition a), the first switch SC1 is conductive and the second switch SC2 is not conductive, thereby facilitating the flow of current from Va to Vb in the current line; or in case b), when the third switch SC3 is not conductive, the first switch SC1 is not conductive and the second switch SC2 is conductive, thereby facilitating the flow of current from Vb to Va in the current line.

Thus, the switching of such a switching circuit as illustrated in fig. 2A involves two control signals, csXa, csXb, where x=1 or 2 (i.e. for switch S1 these signals can be distinguished as Cs1a and Cs1b and for switch S2 these signals can be distinguished as Cs2A and Cs2 b), such that with these two signals at a first level (e.g. 0) the switches (e.g. S1, S2, see the basic exemplary diagram of fig. 2) are in an open, non-conducting state.

CsXa and CsXb are selectively controlled (either of the switches SC1, SC2 is brought into a conducting state (while the switch SC3 is not conducting in both cases) such that the switch is conducting (i.e. "closed") in one or the other direction through Laux (see again the basic exemplary diagram of fig. 2).

Fig. 2 illustrates a first capacitance and a second capacitance coupled with output nodes Vout1, vout2 of a first half-bridge HB1 and a second half-bridge HB2, wherein an associated control circuitry 12 (illustrated in fig. 4) is configured to: the respective intervals (ta, tb;

t1, t2, see fig. 3, discussed below), the first switch S1 and the second switch S2 are switched to a conductive state.

The inductance Laux may include an independent inductance component of the circuit (as illustrated in fig. 2) and/or a conductive line (e.g., a trace on a PCB printed circuit board) coupling the first switch S1 and the second switch S2, the conductive line having a line inductance.

Likewise, the first and second capacitances may include independent capacitive components of the circuit coupled between the output nodes Vout1, vout2 of the first and second half-bridges HB1, HB2 and ground, and/or parasitic capacitances CparH1, cparL1, cparH2, cparL2 of the high-side and low-side transistors in the first and second half-bridges HB1, HB2 (as illustrated in fig. 2).

The solution disclosed in the already cited U.S. patent publication No. 2019/238094 (EP 3522373B 1) is based on the following recognition: in the circuits considered herein, a significant contribution to power dissipation is due to the switching of the transistor in the process of activation to release the charge stored in its body diode. If the transition is fast, this current may be significantly higher than Iout.

This results in a correspondingly high power dissipation, since the drain-source voltage Vds is approximately equal to Vdd (the supply voltage of the two half-bridges HB1, HB 2).

If it is considered that the two half-bridges HB1, HB2 can be switched simultaneously, this critical switching may occur simultaneously with a corresponding high current.

The solution disclosed in the already cited us patent publication No. 2019/238094 (EP 3522373B 1) helps to provide a circuit suitable for e.g. a monolithic class D audio amplifier with a high switching frequency, which has the following capabilities: the amount of power dissipated by switching is reduced (e.g., due to critical switching as previously discussed) while improving linearity.

The diagram In fig. 3 is an example of possible time behavior of the various signals as discussed In U.S. patent publication No. 2019/238094 (EP 3522373B 1), provided (as should be the case) that in_pwm1 and in_pwm2 (generally labeled vin_pwm In the top diagram of fig. 3) have complementary PWM modulation behavior.

The second graph in fig. 3 shows the behavior of the signal Vout 1: the signal Vout2 will behave the same way in a complementary way, i.e. Vout2 is "low" when Vout1 is "high", and Vout2 is "high" when Vout1 is "low".

The third and fourth diagrams in fig. 3 depict the on and off conditions of the high-side and low-side transistors (H2 and L2, respectively) in half-bridge HB 2. For simplicity, only the behavior of half-bridge HB2 (including high-side transistor H2 and low-side transistor L2) is illustrated: as mentioned, due to the complementary temporal behaviour of in_pwm1 and in_pwm2, the same behaviour is In fact mirrored In the half-bridge HB1 In a complementary way (180 ° phase offset).

The fifth and sixth diagrams in fig. 3 depict possible control signals vcs1a=vcs2b and vcs1b=vcs2a applied to switches S1 and S2 (assuming that an "on" or "high" value corresponds to making the associated switch conductive and an "off" or "low" value corresponds to making the associated switch non-conductive).

In view of the possibility to implement the switches S1, S2 illustrated in fig. 2A (fig. 11 of us patent publication No. 2019/238094 (EP 3522373B 1) discussed above (of course, this is not mandatory), two different control signals VCsXa and VCsXb are shown herein, where x=1 or 2, i.e. VCs1a, VCs1B (for switch S1) and VCs2A, VCs2B (for switch S2).

Finally, the lowest graph in fig. 3 shows a possible time behavior of the current ILaux through the auxiliary inductance Laux.

This type of operation, including the alternating switching sequence of the high-side transistors H1, H2 and the low-side transistors L1, L2 in the half-bridges HB1, HB2, is conventional in the art and therefore need not be provided herein in more detail.

The representation of fig. 3 shows (reference to the case of a peak of Iload large Yu Wenbo current) that the switches S1, S2 can be implemented (e.g., by means of two MOS transistors arranged in anti-series or back-to-back as discussed in fig. 2A) such that the switches S1 and S2 can be selectively turned on in either one of the flow directions of current through it (i.e., in one flow direction that facilitates discharge of the body diodes of L1 (and L2) in this case).

This makes it possible to eliminate the "reverse" current ILaux through the inductance Laux, for example during the intervals ta, tb.

The diagram of fig. 4 is an example of control circuitry 12, control circuitry 12 may be coupled to power stages as illustrated in fig. 2 to produce operations as illustrated in fig. 3.

The circuit arrangement 12 illustrated in fig. 4 comprises four comparators 21, 22, 23, 24 which compare the signals Vout1, vout2 at the nodes between the high-side and low-side transistors (H1, H2 and L1, L2, respectively) with threshold values vth_h, vth_1, which are adjustable as setting parameters of the circuit.

For example, in the embodiment illustrated in fig. 4, possible connections of comparators 21 to 24 may include: a comparator 21 (Vout 2-non-inverting input, vth_h-inverting input); comparator 22 (Vout 1-inverting input, vth_1-non-inverting input); a comparator 23 (Vout 1-non-inverting input, vth_h-inverting input); and a comparator 24 (Vout 2-inverting input, vth_1-non-inverting input).

The outputs from the comparators 21, 22 and the outputs from the comparators 23 and 24 are input to or gates 25, 26, the or gates 25, 26 providing corresponding signals to respective inputs of a control circuit block 27, the control circuit block 27 turning the switches S1, S2 on (conductive state) and off (non-conductive state).

For example, the signals from the or gates 25, 26 may provide two input signals vth_a and vth_b to the circuit block 27, which, as previously described, helps to turn off the switches S1, S2, while the conduction of these switches may be controlled by the rising/falling edges of either of the signals in_pwm1 or in_pwm2. Thus, the general indication in_pwm without the suffix 1 or 2 is reproduced In fig. 4.

In the diagram of fig. 4, four output lines from the control circuit 27 are illustrated, wherein: VH1 = VL2 is a control signal applied to control terminals (e.g., gates) of the power transistors H1 and L2; vcs1a=vcs2b and vcs1b=vcs2a are control signals of the switches S1 and S2 (see fig. 2 and 2A); and VL1 = VH2 is a control signal applied to control terminals (e.g., gates) of the power transistors L1 and H2.

Throughout this description, for purposes of explanation and by way of example, a switch such as a transistor will be considered "on" (active/on) when the control signal is "high" and "off" (inactive/non-on) when the control signal is "low". Other embodiments of the same operating principles and functions can of course be devised by those skilled in the art.

The flow chart in fig. 5 is an example of a possible cyclic operation of the arrangement discussed previously, starting from an initial condition in which: VL1 = VH2 = 1 (i.e., L1 and H2 are on); VH1 = VL2 = 0 (i.e., H1 and L2 are non-conductive); and vcs1a=vcs2b=0 and vcs1b=vcs2a=0 (i.e., S1 and S2 are non-conductive).

The blocks in the diagram of fig. 5 identify the following steps or actions:

100: it is checked whether a transition (e.g. 0→1) occurs In the input signal In _ pwm (for the reasons given before, here again the suffixes 1 and 2 are not reproduced).

102: given a positive result in block 100, the currently active power transistor is turned off (e.g., vl1=vh 2 1 →0).

104': switches CS1-CS2 are activated even though they are on (e.g., vcs1=vcs 2 0 →1).

106: it is checked whether an "off" threshold (e.g., vth_a0→1) has been reached.

108': given a positive result in block 106, switches S1, S2 are off even though they are not conducting (e.g., vcs1=vcs 2 1 →0).

110: the currently inactive power transistor is turned on (e.g., VH1 = VL 20 →1).

112: it is checked whether a new transition occurs In the input signal In _ pwm.

114: given a positive result in block 112, the currently active power transistor is turned off (e.g., VH1 = VL2 1 → 0).

116': switches CS1-CS2 are activated even though they are on (e.g., vcs1=vcs 20 →1).

118: it is checked whether an "off" threshold (e.g., vth_b0→1) has been reached.

120': given a positive result in block 116, switches S1, S2 are turned off even if they are not conductive (e.g., vcs1=vcs 2 1 →0).

122: the currently inactive power transistor is turned on (e.g., vl1=vh 20 →1).

The process then continues (e.g., returns to 100).

The structure and operation of the power stages in the switching amplifier a discussed so far substantially corresponds to the disclosure of us patent publication No. 2019/238094 (EP 3522373B 1), which has been repeatedly referenced: these documents may be referenced for further details and information.

The preceding discussion has mainly involved the case where the current Iload through the load L is greater than the peak value Iripple (peak) of the ripple current through the output filter impedance.

In this case, as shown for example in fig. 3, the output PWM waveform (before the LC output filter) corresponds to a stable current flowing into the output node. This is the usual case of switching between a medium output power level and a high output power level of the amplifier.

Under low power and static conditions, the current Iload through the load L predicts a peak value Iripple (peak) of small Yu Wenbo current.

This may result in the behavior depicted in fig. 6.

Here again, the complementary PWM modulation behavior of in_pwm1 and in_pwm2 is generally labeled vin_pwm In the top diagram of fig. 6.

The second graph in fig. 6 shows the behavior of the signal Vout 1: the signal Vout2 will behave the same way in a complementary way, i.e. Vout2 is "low" when Vout1 is "high", and Vout2 is "high" when Vout1 is "low".

The third and fourth diagrams in fig. 6 depict the on and off conditions of the high-side and low-side transistors (H2 and L2, respectively) in half-bridge HB 2. Here, too, only the behavior of the half-bridge HB2 (including the high-side transistor H2 and the low-side transistor L2) is illustrated: due to the complementary time behaviour of in_pwm1 and in_pwm2, the same behaviour is actually mirrored In the half bridge HB1 In a complementary way (180 ° phase offset).

The fifth and sixth diagrams in fig. 6 depict possible control signals vcs1a=vcs2b and vcs1b=vcs2a applied to switches S1 and S2 (assuming that an "on" or "high" value corresponds to making the associated switch conductive and an "off" or "low" value corresponds to making the associated switch non-conductive).

Here, too, in view of the possibility of implementing the switches S1, S2 illustrated in fig. 2A as discussed above, two different control signals VCsXa and VCsXb are shown herein, wherein x=1 or 2, i.e. VCs1a, VCs1b (for switch S1) and VCs2A, VCs2b (for switch S2).

Finally, the lowest graph in fig. 6 shows a possible time behavior (zero or near zero, i.e. static or near static) of the current ILaux through the auxiliary inductance Laux.

In the case of Iload < Iripple (peak), the waveform of the voltage Vout1 (and, complementarily, of the voltage Vout 2) is a rectangular waveform in which the current changes sign (flow direction) at each half cycle of the output square wave.

For example, as shown in fig. 6, in a region where the voltage Vout1 approaches the value Vdd, the current is initially an inflow current, which then becomes an outflow current before 1→0 switching.

As a result, the voltage Vout1 is first higher than the value Vdd, and then becomes lower than Vdd.

When the input switches from 1 to 0, in response to transistor H1 being turned off, voltage Vout1 may reach zero without the intervention of other active elements, provided that the energy stored in the filter inductance is sufficient for this purpose.

Under these conditions, ZSL control circuitry 12 (as illustrated in fig. 4, and configured to activate auxiliary switches S1 and S2 with a (negligible) delay in response to transistor H1 being turned off) does not need to zero the output.

Thus, activation of the ZSL control network 12 unnecessarily increases the dissipated power, and this increase is not negligible if it is noted that this situation occurs where the output signal is zero or near zero.

By providing a sufficient delay (e.g., on the order of tens of nanoseconds) between the switching off and on of the switches S1, S2 so that the switches do not interfere with these conditions, the efficiency under such operating conditions can be improved, resulting in a so-called "ZSL low power mode" (where ZSL = zero switching loss).

When in this ZSL low power mode configuration, the system will also operate adequately with slightly higher distortion at high Yu Wenbo currents in the output current.

This shows that in an audio system where low distortion is desired, the ZSL low power mode just discussed should be activated only in the region of Iload < Iripple (peak), once Iload > Iripple (peak), operation returns to normal ZSL operation (e.g., as disclosed in us patent publication No. 2019/0238094 (EP 3522373B 1)).

Fig. 7 is an example of a possible way of activating the ZSL low power mode within the framework of the arrangement presented in fig. 1 (only directly involved elements are shown in fig. 7).

As illustrated in fig. 7, a logic command signal ZSL delay control may be added.

When the ZSL delay control command is at a first logic level (e.g., "0"), the delay between turning off the power transistor and turning on the switches S1, S2 has a first "long" value Tlong (e.g., 30 ns), and the system operates in the ZSL low power mode.

As illustrated in fig. 8 (by direct comparison with fig. 4), ZSL delay control commands (various ways of generating the commands will be discussed below) may be injected into the control circuit block 27, the control circuit block 27 controlling the on and off of the switches S1 and S2.

Advantageously, the long value Tlong is an order of magnitude longer than the short value Tshort (e.g., 30ns versus 3 ns).

In the event that the ZSL delay control command is at a second logic level (e.g., "1"), the delay between turning the power transistor off and turning the switches S1, S2 on has a second "short" value Tshort (e.g., 3 ns), i.e., the ratio Tlong is shorter, and the system operation returns to the normal ZSL configuration.

Of course, the quantitative values (3 ns and 30 ns) are merely exemplary.

More generally: the first delay Tshort is advantageously chosen to be shorter than the time between switching the first pair of transistors to the non-conductive state and switching the second pair of transistors to the conductive state: in this manner, the operation (with medium-high output power levels) is substantially as illustrated in fig. 3; and the second delay Tlong is advantageously chosen to be longer than the time between switching the first pair of transistors to the non-conductive state and switching the second pair of transistors to the conductive state: in this way, the switches S1, S2 are rendered non-conductive (they do not reach the conductive state "fast enough" by the command before the second pair of transistors is switched to the conductive state), and the operation (with low output power level or in a static or near static condition) is substantially as illustrated in fig. 9.

By direct comparison with fig. 6, fig. 9 shows a possible time behavior of the following signals: a complementary PWM modulated signal, generally labeled vin_pwm; signal Vout1 (signal Vout2 will exhibit the same behavior in a complementary manner, i.e., vout2 is "low" when Vout1 is "high", and Vout2 is "high" when Vout1 is "low"); the on and off conditions of the high-side and low-side transistors (H2 and L2, respectively) in half-bridge HB2 (here, again, only the behavior of half-bridge HB2 is illustrated, the same behavior being mirrored in half-bridge HB1 in a complementary manner (180 ° phase offset); control signals vcs1a=vcs2b and vcs1b=vcs2a intended to be possibly applied to the switches S1 and S2; and a (zero or near zero, i.e. static or near static) current ILaux through the auxiliary inductance Laux.

The delay d1, d2 (i.e. Tlong) between the power down of the power transistor concerned and the (nominal) on-time of the associated auxiliary switch S1 or S2 (applied in response to the command signal ZSL delay control) is illustrated at the top of fig. 9.

A comparison of fig. 9 with fig. 6 shows that in response to the commanded ZSL low power mode (as shown in fig. 9), the control signals vcs1a=vcs2b and vcs1b=vcs2a eventually (steadily) are zero, since the applied "long" delay Tlong (as shown by d1, d2 at the top of fig. 9) results in the switches S1 and S2 not being activated, thereby avoiding any increase in dissipated power.

As mentioned, in the case where the output signal is zero or near zero, this increase (unnecessary for the reasons explained above) will be non-negligible: for example, the ZSL low power mode discussed herein (i.e., in response to switching the first pair of transistors to a non-conductive state and the second pair of transistors to a conductive state), the ZSL control circuitry 12 avoiding switching the first switch S1 and the second switch S2 to the conductive state) may involve reducing the quiescent current in the bridge circuit by approximately 40% (e.g., from 30mA to 17 mA). Of course, these values are merely exemplary and not limiting.

By direct comparison with the flowchart of fig. 5, the flowchart of fig. 10 shows a possible implementation of the operations discussed herein, starting from the same initial conditions, namely: VL1 = VH2 = 1 (i.e., L1 and H2 are on); VH1 = VL2 = 0 (i.e., H1 and L2 are non-conductive); and vcs1a=vcs2b=0 and vcs1b=vcs2a=0 (i.e., S1 and S2 are non-conductive).

The boxes labeled with the same reference numerals in fig. 5 and 10 have the same meaning, namely:

100: it is checked whether a transition (e.g. 0→1) has occurred In the input signal In _ pwm (for the reasons given before, here again the suffixes 1 and 2 are not reproduced).

102: given a positive result in block 100, the currently active power transistor is turned off (e.g., vl1=vh 2 1 →0).

104': the switches CS1-CS2 are activated, i.e., made conductive (e.g., vcs1=vcs20→1).

106: it is checked whether an "off" threshold (e.g., vth_a0→1) has been reached.

108': given a positive result in block 106, switches S1, S2 are turned off, i.e., rendered non-conductive (e.g., vcs1=vcs 2 1 →0).

110: the currently inactive power transistor is turned on (e.g., VH1 = VL 20 →1).

112: it is checked whether a new transition occurs In the input signal In _ pwm.

114: given a positive result in block 112, the currently active power transistor is turned off (e.g., VH1 = VL 21 → 0).

116': the switches CS1-CS2 are activated, i.e., made conductive (e.g., vcs1=vcs20→1).

118: it is checked whether an "off" threshold (e.g., vth_b0→1) has been reached.

120': given a positive result in block 116, switches S1, S2 are turned off, i.e., rendered non-conductive (e.g., vcs1=vcs 21 →0).

122: the currently inactive power transistor is turned on (e.g., vl1=vh 20 →1).

In contrast to the flowchart of fig. 5, in the flowchart of fig. 10, the transition from block 102 (VL 1 = VH21 → 0) to block 104 '(e.g., vcs1b = vcs2a0→ 1) and from block 114 (VH 1 = VL 21 → 0) to block 116' (e.g., vcs1a = vcs2b0→ 1) is conditioned on the results of the test (illustrated by blocks T1 and T2 for simplicity), where the possible occurrence of a low power/static condition is checked, e.g., by checking (e.g., based on sensing of load L) whether Iload < Iripple (peak) is satisfied.

In response to a negative result (N) of test T1 and test T2, the system immediately transitions from block 102 to block 104 'and from block 114 to block 116' (e.g., with a "short" delay Tshort of, for example, 3 ns), thus operating in a "normal" ZSL mode.

Conversely, in response to a positive result (Y) of test T1 and test T2, the system transitions from block 102 to block 104 'and from block 114 to block 116' with a "long" delay Tlong of, for example, 30ns, as represented by blocks d1 and d2 (see also the top diagram in fig. 9), wherein the system operates in ZSL low power mode.

Although shown separately for clarity, in the above exemplary case, tests T1 and T2 may be the same test, e.g., based on whether Iload < Iripple (peak) is satisfied by sensing on load L.

If (in absolute value) Iload < Iripple (peak), a sufficient delay (Tlong) is introduced before turning on auxiliary switches S1 and S2 as indicated by d1, d 2. The delay (e.g., 30 ns) is selected such that the output voltage completes the conversion due to the energy stored in the output inductance and exceeds the threshold vth_1 or vth_h (see fig. 9, depending on whether it is a falling or rising edge).

Thus, in the low power ZSL mode, the switches S1, S3 are not activated because the power corresponding to the phase reached is directly turned on.

In contrast, if (in absolute value) Iload > Iripple (peak), the delay is avoided and the auxiliary switches S1, S2 are immediately turned on (or the delay is negligible), the threshold vth_a or vth_b is still at 0. This case is thus returned to the case of fig. 6.

A substantially similar mode of operation (still based on the flowchart as illustrated in fig. 10) may involve performing tests T1 and T2 as respective tests to identify low power operation or static conditions that are performed by: instead of being based on current sensing (Iload < Iripple (peak)) on the load L, a voltage threshold test is utilized, i.e. by checking if Vds (L1) and Vds (H2) are above a threshold Vthr (test T1) and if Vds (L2) and Vds (H1) are above a threshold Vthr (test T2).

Vds represents the drain-source voltages of the transistors involved (i.e., transistors L1, H2 and transistors L2, H1).

In this case, at the moment of switching off, the comparison of the current Iload in the load with the ripple (peak) current Iripple (peak) in the filter inductance is performed only by comparing the drain-source voltages Vds of the low-side drivers L1, L2 and the high-side drivers H1, H2 with a predefined threshold.

The current in these transistors H1, H2, L1, L2 is given by the sum of Iripple and Iout, if Iripple (Peak) < Iload, the voltage Vds across the transistors L1, L2 will be slightly above zero and will be slightly below the voltage Vdd across the transistors H1, H2. Thus, the current threshold becomes a voltage threshold; these are easier to manage because for the high-side transistors H1, H2 the voltage threshold is referenced to Vdd and for the low-side transistors L1, L2 the voltage threshold is referenced to ground GND.

The flow chart of fig. 11 illustrates a further possible implementation of the operations discussed herein, starting from the same initial conditions, namely: VL1 = VH2 = 1 (i.e., L1 and H2 are on); VH1 = VL2 = 0 (i.e., H1 and L2 are non-conductive); and vcs1a=vcs2b=0 and vcs1b=vcs2a=0 (i.e., S1 and S2 are non-conductive).

The boxes labeled with the same reference numerals in fig. 5, 10, 11 have the same meaning, namely:

100: it is checked whether a transition (e.g. 0→1) occurs In the input signal In _ pwm (for the reasons given before, here again the suffixes 1 and 2 are not reproduced).

102: given a positive result in block 100, the currently active power transistor is turned off (e.g., vl1=vh 2 1 →0).

104': switches CS1-CS2 are activated even though they are on (e.g., vcs1=vcs 2 0 →1).

106: it is checked whether an "off" threshold (e.g., vth_a0→1) has been reached.

108': given a positive result in block 106, switches S1, S2 are off even though they are not conducting (e.g., vcs1=vcs 2 1 →0).

110: the currently inactive power transistor is turned on (e.g., VH1 = VL2 0 →1).

112: it is checked whether a new transition occurs In the input signal In _ pwm.

114: given a positive result in block 112, the currently active power transistor is turned off (e.g., VH1 = VL2 1 → 0).

116': switches CS1-CS2 are activated even though they are on (e.g., vcs1=vcs 20 →1).

118: it is checked whether an "off" threshold (e.g., vth_b0→1) has been reached.

120': given a positive result in block 116, switches S1, S2 are turned off even if they are not conductive (e.g., vcs1=vcs 21 →0).

122: the currently inactive power transistor is turned on (e.g., vl1=vh 20 →1).

Basically, in the flow chart of fig. 11, the possible application of delays d1 and d2 (ZSL low power mode) is conditioned on a finer test, wherein the tests T1 and T2 of fig. 10 are each replaced by a pair of tests T11, T12 and T21, T22.

In test T11, the (logical) value of the variable HighCurr is checked, which is set to a first logical value (e.g., "1") in response to the load current Iout being higher than the threshold value Ithr.

In response to a positive result (Y) of test T11, the system transitions from block 102 to block 104' "immediately" (e.g., with a short delay Tshort of, for example, 3 ns), thus operating in "normal" ZSL mode, after (re) setting, the variable HighCurr changes to a second logic value (e.g., "0") in block 1001.

In response to a negative result (N) of the test T11, the system transitions to a second test T12, in which a check is made as to whether Vds (L1) is above a threshold Vthr.

In response to a negative result (N) of test T12, the system transitions from block 102 to block 104' "immediately" (e.g., with a short delay Tshort of, for example, 3 ns), thus operating in "normal" ZSL mode, after which, in block 1002, the variable HighCurr becomes a first logical value (e.g., "1").

In response to a positive result (Y) of test T12, the system transitions from block 102 to block 104' with a "long" delay Tlong of, for example, 30ns (as represented by block d 1), and the system operates in ZSL low power mode.

In a corresponding manner, in test T21, the (logical) value of the variable HighCurr is checked, which is set to a first logical value (e.g. "1") in response to the load current Iout being higher than the threshold value Ithr.

In response to a positive result (Y) of test T21, the system transitions from block 114 to block 116' "immediately" (e.g., with a short delay Tshort of, for example, 3 ns), thus operating in "normal" ZSL mode, after (re) setting, the variable HighCurr changes to a second logic value (e.g., "0") in block 2001.

In response to a negative result (N) of the test T21, the system transitions to a second test T22, in which a check is made as to whether Vds (L2) is above a threshold Vthr.

In response to a negative result (N) of test T22, the system transitions from block 114 to block 116' "immediately" (e.g., with a short delay Tshort of, for example, 3 ns), thus operating in "normal" ZSL mode, after which, in block 2002, the variable HighCurr becomes a first logical value (e.g., "1").

In response to a positive result (Y) of test T22, the system transitions from block 114 to block 116' with a "long" delay Tlong of, for example, 30ns (as represented by block d 2), and the system operates in ZSL low power mode.

Basically, in the flow chart of fig. 11, sensing is performed only on the low-side drivers L1, L2 of the two branches.

As In the previous case (flow chart of fig. 10), the signal in_pwm is considered slightly ahead of the output transition (on the order of tens of nanoseconds), the output signal Vout1 is In phase with the input signal, and the output signal Vout2 is In the opposite phase (see fig. 2 for reference).

The flow chart of fig. 11 is based on the following (reasonable) assumption: the condition of the output current level does not change significantly between the two input edges. This assumption holds if the switching frequency is much higher than the modulation frequency (as is typically the case in switching (class D) amplifiers).

The solution of the flow chart of fig. 11 changes the delay when the drain-source voltage Vds of the transistor L1, L2 exceeds a certain threshold Vthr at the moment of time considered (from Tshort to Tlong, for example from 3ns to 30ns, these being purely exemplary values as such).

In the example considered, if the threshold Vthr is exceeded, the variable "HighCurr" becomes 1 and is reset on the next edge, with a Tshort delay, regardless of the current value.

In case operation with very low distortion is desired, a substantially similar mode of operation based on the flow chart as illustrated in fig. 11 may be employed.

The solutions discussed so far may lead to a certain level of distortion, which may be considered as a limiting factor for high-end applications.

For this reason, note the harmonic distortion, the solution illustrated in fig. 11 can be further improved.

The basic principle of such improvement is to counteract the transition (in either direction) between the "standard" ZSL mode and the ZSL "low power" mode, which may occur on each half-wave of the audio signal (e.g., lowest frequency fmin=20 Hz), where the benefits associated with reducing the quiescent current are negligible.

To this end, the timer TimerHighCurrent may be activated by crossing Vds L1> Vthr or Vds L2>0 Vthr.

The timer starts from the Tmax value and decreases with a fixed clock until a zero level is reached after a certain period of time.

If the threshold current is not (again) exceeded during this period, the delay returns to Tlong, otherwise if the threshold current is again exceeded during this period, the timer returns to Tmax.

In view of this low distortion option, the portion of the flow chart of FIG. 11 that includes tests T11, T12 and T21, T22 lends themselves to understanding as follows.

In test T11, it is checked whether the timer TimerHighCurr has a value higher than zero.

In response to a positive result (Y) of test T11, the system transitions from block 102 to block 104' "immediately" (e.g., with a short delay Tshort of, for example, 3 ns), thus operating in "normal" ZSL mode after the value of timer TimerHighCurr decrements by 1.

In response to a negative result (N) of the test T11, the system transitions to a second test T12, in which a check is made as to whether Vds (L1) is above a threshold Vthr.

In response to a negative result (N) of test T12, the system transitions from block 102 to block 104' "immediately" (e.g., with a short delay Tshort of, for example, 3 ns), thus operating in "normal" ZSL mode after setting timer TimerHighCurr to its maximum Tmax.

In response to a positive result (Y) of test T12, the system transitions from block 102 to block 104' with a "long" delay Tlong of, for example, 30ns (as represented by block d 1), and the system operates in ZSL low power mode.

In a corresponding manner, in test T21, it is checked whether the timer TimerHighCurr has a value higher than zero.

In response to a positive result (Y) of test T21, the system transitions from block 102 to block 104' "immediately" (e.g., with a short delay Tshort of, for example, 3 ns), thus operating in "normal" ZSL mode after the value of timer TimerHighCurr decrements by 1.

In response to a negative result (N) of the test T21, the system transitions to a second test T22, in which a check is made as to whether Vds (L2) is above a threshold Vthr.

In response to a negative result (N) of test T22, the system transitions from block 102 to block 104' "immediately" (e.g., with a short delay Tshort of, for example, 3 ns), thus operating in "normal" ZSL mode after setting timer TimerHighCurr to its maximum Tmax.

In response to a positive result (Y) of test T22, the system transitions from block 102 to block 104' with a "long" delay Tlong of, for example, 30ns (as represented by block d 2), and the system operates in ZSL low power mode.

In the audio amplifier Tmax is advantageously chosen such that its duration is half the period of the lowest reproducible frequency, for example 30ms for a fmin=20 Hz system.

In addition, note that the functional improvement can be applied to all cases of the current detection described previously.

The previously discussed solutions based on direct or indirect measurement of the output current Iout are expected to operate in noisy environments, such as switching systems.

Operation in this context may be facilitated/improved by processing the signal in its analog form prior to the modulation stage, or in the digital domain in the case of a power audio system with digital input.

To this end, the peak value (absolute value) of the input signal may be analyzed, verifying whether the input signal may result in an output current Iload greater than Iripple (peak).

This approach is illustrated in fig. 12 (which makes it unnecessary to measure the current or to rely on the time relationship with the transitions 1→0 and 0→1 of the PWM output signal), here again with reference to the same high-level box representation of fig. 1.

In fig. 12, the input signal processing block 30 is illustrated as being configured to receive as input a digital signal Din containing an audio signal, encoded using pulse code modulation or PCM or other formats (bit stream, DSD, etc.).

Also shown in fig. 12 is an Input Signal Analysis (ISA) and decision block 32.

As illustrated, block 32 receives digital signal Din and: digital signal D (Vdd), with information about the (voltage) value Vdd used to power the power stage 14; and one or more setting parameters Pvar, to be defined a priori (priori) in consideration of factors (i.e., substantially Lo, fsw, and Rload) that can change ripple current values in Lo1, lo2 and output currents of the same voltage output.

Accordingly, a ZSL delay control signal may be generated that indicates (e.g., to block 27 in ZSL control circuit arrangement 12) whether the system is in medium-high power operation or low power operation, so that "standard" ZSL operation (Tshort) or "low power" ZSL operation (Tlong) may be controlled as previously described.

Fig. 13 shows a possible implementation of block 32 in fig. 12.

Block 32 is configured to: it is determined whether the level of the digital input word (PCM or otherwise encoded) suggests that ZSL switches S1, S2 should act with a short delay (e.g., tshort, 3 ns) or a long delay (e.g., tlong, 30 ns), respectively, in "standard" ZSL mode or in "low power" ZSL mode.

The illustrated block 32 is built around a comparator 320, the comparator 320 receiving on one input (e.g. non-inverting) the absolute value |din| (expected to be proportional to the output voltage) of a signal obtained via a modulus (absolute value) circuit 322 of any known type, weighted in a multiplier module 324 by a factor taking into account the output stage gain (via a parameter Gvar included in the set of parameters Pvar).

The other (e.g., inverting) input of comparator 320 receives a digital reference level Dref that corresponds to the peak value of the output voltage such that the current in the load is equal to the peak value of the ripple current in the inductor.

Since the ripple current is a function of Vdd, dref may be derived from D (Vdd) by a scaling factor (included in the set of parameters Pvar) via scaling module 326. This parameter depends substantially on the absolute value of the impedance of the load L (for example Zload (min)), the switching frequency and the value of the output filter inductance.

These parameters are fixed, known, and not particularly critical for a given application.

Advantageously, the level Dref is set so that even in the worst case, for a current Iout equal to or higher than the ripple current Iripple, the output OutComp from the comparator 320 is equal to 1.

Block 328 in fig. 13 is an exemplary circuit arrangement configured (e.g., via SW) to implement the procedure illustrated by the flowchart of fig. 14. Advantageously, the program may be clocked by a frame clock of the input (e.g., PCM) signal.

The blocks in the flow chart of fig. 14 have the following meanings:

2000-starting from a timer reset and signal ZSL delay control is set to Tlong (e.g., logic 0-low power ZSL).

2002-check if the output Out Comp from the comparator 320 is equal to 1; if the result is negative (N), then the flow returns downstream of block 2002 (maintaining a low power ZSL).

2004-in response to a positive result (Y) of the check at 2002 (output Out Comp from comparator 320 equals 0), signal ZSL delay control is set to Tshort (e.g., logic 1-switch to standard ZSL).

2006-check if the output Out Comp from comparator 320 is equal to 1; if the result is affirmative (Y), the timer is reset in block 2008 and returns upstream of block 2006 (standard ZSL is maintained).

2008-in response to the check in block 2006 being negative (N), goes to block 2010.

2010-increment the timer by 1 and check if it is above the hold threshold; if the result is negative (N), then the flow returns upstream of block 2006 (maintains the standard ZSL).

2012-in response to the result of the check in block 2010 being affirmative (Y), the signal ZSL delay control is set to Tlong (e.g., logic 0-switching to low power ZSL).

2014-reset the timer, and return upstream of block 2002.

The basic concept of the procedure is similar to that discussed in connection with fig. 10 and 11: once the absolute value of the output current, lout, approaches the ripple peak value Iripple (peak), the ZSL delay control output transitions from 0 to 1. After the last transition of the output signal Out Comp from the comparator 320 from 1 to 0, the opposite transition occurs (only) after the Thold time (e.g. 30 ms) defined by the timer.

The timing diagrams of fig. 15 and 16 are possible examples of this type of operation.

Fig. 17 illustrates one possible alternative embodiment of block 32.

In this embodiment, the inverting input of comparator 320 receives the reference value Dref (digitized) value D (Vdd) of the supply voltage.

The non-inverting input of comparator 320 again receives the absolute level Din of the (digital) input signal weighted (horizontally shifted in horizontal shifter module 327) by a factor according to the output inductance value, the modulus of the minimum load impedance, the final gain, and the switching frequency.

As noted, these are all fixed parameters for a given application.

The embodiment of fig. 17 takes advantage of the low criticality of the system, which facilitates transfer from |din| to |dinw| for comparison with a corresponding weighting reference DrefW (i.e., a weighting value obtained from the above factors) at the output of horizontal shifter 327. If a power of 2 value is used, this horizontal shift can be achieved by simply shifting the values in the binary string.

The downstream processing of comparator 320 may be implemented using a simple two-state Finite State Machine (FSM) 40 as illustrated in fig. 18, such FSM: in response to finding Din less than Dref, switching from the first state 40A ("standard" ZSL mode) "to the second state 40B (" low power "ZSL mode), the counter is for example between 30ms and 100 ms; and in response to finding Din higher than DrefW, switching from the second state 40B ("low power" ZSL mode) to the first state 40A ("standard" ZSL mode).

Without prejudice to the underlying principles, the details and the embodiments may vary, even significantly, with respect to what has been described purely by way of example, without thereby departing from the scope of the protection.

The claims are an integral part of the technical teaching provided herein with respect to the embodiments.

The scope of protection is determined by the appended claims.

Claims (24)

1. A circuit, comprising:

a switching circuit stage comprising a first half-bridge and a second half-bridge, each half-bridge comprising a high-side transistor and a low-side transistor with an output node therebetween, the output nodes of the first half-bridge and the second half-bridge being configured to: powering the load via a respective filter network between the output node and an electrical load;

control circuitry configured to: controlling an alternating switching sequence of the high side transistors and the low side transistors in the first half-bridge and the second half-bridge, wherein a first pair of transistors is switched to a non-conductive state, the first pair of transistors comprising the high side transistor in one of the half-bridges and the low side transistor in the other of the half-bridges, and a second pair of transistors is switched to a conductive state, the second pair of transistors comprising the high side transistor in the other of the half-bridges and the low side transistor in the one of the half-bridges; and

A current flow line between the output nodes in the first and second half-bridges, the current flow line comprising an inductance having opposing terminals coupled to first and second switches, wherein the first and second switches are selectively switchable between a non-conductive state and at least one conductive state; and

wherein the control circuitry is configured to:

in a first mode of operation in which the switching circuit stage operates at a first power level, responsive to switching the first pair of transistors to the non-conductive state and the second pair of transistors to the conductive state, switching the first switch and the second switch to the at least one conductive state at intervals of the alternating switching sequence; and

in a second mode of operation in which the switching circuit stage operates at a second power level lower than the first power level, switching the first switch and the second switch to the at least one conductive state is avoided at intervals in the alternating switching sequence in response to switching the first pair of transistors to the non-conductive state and the second pair of transistors to the conductive state.

2. The circuit of claim 1, wherein:

in the first mode of operation, the control circuitry is configured to: transmitting a switching command to the first switch and the second switch to the at least one conductive state with a first delay relative to switching the first pair of transistors to the non-conductive state; and

in the second mode of operation, the control circuitry is configured to: transmitting a switching command to the first switch and the second switch to the at least one conductive state with a second delay relative to switching the first pair of transistors to the non-conductive state;

wherein the second delay is longer than the first delay.

3. The circuit of claim 2:

wherein the first delay is shorter than a time between switching the first pair of transistors to the non-conductive state and switching the second pair of transistors to the conductive state; and

wherein the second delay is longer than a time between switching the first pair of transistors to the non-conductive state and switching the second pair of transistors to the conductive state.

4. The circuit of claim 1, wherein the control circuitry is configured to generate a control signal having a first logic level that instructs the switching circuit stage to operate at the first power level to select the first mode of operation and a second logic level that instructs the switching circuit stage to operate at the second power level to select the second mode of operation.

5. The circuit of claim 4, wherein the control circuitry comprises input side circuitry configured to:

receiving an input signal driving the switching circuit stage and an input reference signal, the input reference signal preferably being a function of a supply voltage applied to the switching circuit stage;

performing a comparison of an absolute value of the input signal with the input reference signal; and

generating the control signal:

responsive to the comparison indicating that the absolute value of the input signal is higher than the input reference signal, the control signal has the first logic level; and

the control signal has the second logic level in response to the comparison indicating that the absolute value of the input signal is lower than the input reference signal.

6. The circuit of claim 5, wherein the input side circuit means comprises scaling circuit means configured to: scaling of the input signal and/or the input reference signal is performed prior to the comparing.

7. The circuit of claim 5, wherein the input side circuit arrangement comprises a delay feature configured to: delaying the issuance of the control signal having the second logic level in response to the comparison indicating that the absolute value of the input signal is lower than the input reference signal.

8. The circuit of claim 1, wherein the control circuitry is configured to:

sensing a magnitude of a load current provided to the electrical load;

comparing the intensity of the load current to a current intensity threshold;

operating in the first mode of operation in response to the sensed intensity of the load current being above the current intensity threshold; and

operating in the second mode of operation in response to the sensed intensity of the load current being below the current intensity threshold.

9. The circuit of claim 1, wherein the control circuitry is configured to:

sensing a voltage drop across the high-side transistor and the low-side transistor of the first pair of transistors when switched to the non-conductive state, the first pair of transistors including the high-side transistor of one of the half-bridges and the low-side transistor of the other of the half-bridges;

performing a comparison of the sensed voltage drop with a voltage threshold;

operating in the first mode of operation in response to the sensed voltage drop being above the voltage threshold; and

operating in the second mode of operation in response to the sensed voltage decreasing below the voltage threshold.

10. The circuit of claim 1, wherein the control circuitry is configured to:

sensing a low-side voltage drop across the low-side transistor in the one or the other of the half-bridges when switched to a non-conductive state;

performing a comparison of the sensed low side voltage drop with a low side voltage threshold;

operating in the first mode of operation in response to the sensed voltage drop being above the low-side voltage threshold; and

operating in the second mode of operation in response to the sensed voltage decreasing below the low-side voltage threshold.

11. The circuit of claim 10, wherein the control circuitry is configured to:

in response to the sensed voltage drop being above the low-side voltage threshold, setting a counter to a high value, the counter decrementing to zero in a zeroing interval;

checking whether the sensed low-side voltage drop further exceeds the low-side voltage threshold by checking whether the sensed low-side voltage drop is again above the low-side voltage threshold during the zeroing interval of the counter;

continuing to operate in the first mode of operation in response to the sensed low-side voltage drop being again above the low-side voltage threshold during the zeroing interval of the counter further exceeding the low-side voltage threshold, and resetting the counter to the high value; and

In response to the sensed voltage drop being below the low-side voltage threshold during the zeroing interval of the counter without exceeding the low-side voltage threshold, transitioning to operate in the second mode of operation.

12. The circuit of claim 1, wherein the first and second modes of operation are alternating modes of operation.

13. The circuit of claim 1, further comprising first and second capacitances coupled to the output nodes of the first and second half-bridges.

14. The circuit of claim 1, wherein in the second mode of operation, the control circuitry avoids switching the first switch and the second switch to the at least one conductive state for a delay period that is longer than a delay period provided in the first mode of operation for switching the first switch and the second switch to the at least one conductive state.

15. An apparatus, comprising:

a PWM modulator for receiving an input signal and generating therefrom a PWM modulated drive signal;

a circuit coupled with the PWM modulator, wherein the circuit comprises:

A switching circuit stage comprising a first half-bridge and a second half-bridge, each half-bridge comprising a high-side transistor and a low-side transistor, wherein there is an output node between the high-side transistor and the low-side transistor, the output nodes of the first half-bridge and the second half-bridge being configured to power an electrical load;

control circuitry configured to: controlling an alternating switching sequence of the high-side transistors and the low-side transistors in the first half-bridge and the second half-bridge in response to the PWM modulated drive signal, wherein a first pair of transistors is switched to a non-conductive state, the first pair of transistors including the high-side transistor in one of the half-bridges and the low-side transistor in the other of the half-bridges, and a second pair of transistors is switched to a conductive state, the second pair of transistors including the high-side transistor in the other of the half-bridges and the low-side transistor in the one of the half-bridges; and

a current flow line between the output nodes in the first and second half-bridges, the current flow line comprising an inductance having opposing terminals coupled to first and second switches, wherein the first and second switches are selectively switchable between a non-conductive state and at least one conductive state; and

Wherein the control circuitry is configured to:

in a first mode of operation in which the switching circuit stage operates at a first power level, responsive to switching the first pair of transistors to the non-conductive state and the second pair of transistors to the conductive state, switching the first switch and the second switch to the at least one conductive state at intervals of the alternating switching sequence; and

in a second mode of operation in which the switching circuit stage operates at a second power level lower than the first power level, in response to switching the first pair of transistors to the non-conductive state and the second pair of transistors to the conductive state, avoiding switching the first switch and the second switch to the at least one conductive state at intervals in the alternating switching sequence; and

respective low pass filter networks are coupled to the output nodes of the first half-bridge and the second half-bridge.

16. The apparatus of claim 15, comprising the electrical load coupled to the circuit and powered from the output nodes of the first half-bridge and the second half-bridge via the respective low-pass filter networks.

17. A method of operating a class D amplifier, the method comprising:

receiving an input signal;

generating a PWM signal based on the input signal;

alternately switching a first half-bridge and a second half-bridge of the class D amplifier in an alternating switching sequence based on the PWM signal, the half-bridges having respective output nodes coupled to a load via respective filter networks, wherein alternately switching the first half-bridge and the second half-bridge in the alternating switching sequence comprises:

turning on the first pair of transistors of the half bridge when the second pair of transistors of the half bridge is turned off, and

when the first pair of transistors is off, the second pair of transistors is on, wherein the first pair of transistors includes a high-side transistor in one of the half-bridges and a low-side transistor in the other of the half-bridges, and the second pair of transistors includes a high-side transistor in the other of the half-bridges and a low-side transistor in the one of the half-bridges;

in a first mode of operation when operating at a first power level, at an interval in the alternating switching sequence between turning off the first pair of transistors and turning on the second pair of transistors, turning on a first switch coupled to the output node of the first half bridge and a second switch coupled to the output node of the second half bridge; and

In a second mode of operation when operating at a second power level lower than the first power level, avoiding turning on the first switch and the second switch at an interval in the alternating switching sequence between turning off the first pair of transistors and turning on the second pair of transistors;

wherein an auxiliary inductance is coupled between the first switch and the second switch.

18. The method of claim 17, wherein the PWM signal is a fixed frequency signal.

19. The method of claim 18, wherein the fixed frequency signal has a frequency between 2MHz and 2.5 MHz.

20. The method of claim 17, wherein the first switch and the second switch are further coupled to a reference voltage node via respective resistors.

21. The method of claim 17, wherein the first switch and the second switch are further coupled to a reference voltage node via respective third and fourth switches, the method further comprising:

turning on the third switch when the first switch is turned off, and turning off the third switch when the first switch is turned on; and

the fourth switch is turned on when the second switch is turned off, and is turned off when the second switch is turned on.

22. The method of claim 17, wherein the first switch and the second switch are further coupled to a reference voltage node via respective low pass filters.

23. The method of claim 17, wherein a capacitor and a resistor are coupled in series between the first switch and the second switch.

24. The method of claim 17, further comprising obtaining an amplified copy of the input signal at the respective low pass filter networks coupled to the output nodes of the first half bridge and the second half bridge.