CN117239538A - Ceramic heat sink and combination thereof - Google Patents

Abstract

The invention discloses a ceramic heat sink and a combination thereof, comprising: ceramic substrate and wiring layer. The ceramic substrate has a first face and a second face disposed opposite each other in a thickness direction of the ceramic heat sink. The wiring layer includes an upper wiring layer disposed on the first side of the ceramic substrate to connect the semiconductor device. The upper circuit layer comprises a plurality of grooves which are arranged at intervals. Through set up the recess on last circuit layer, the surface area of last circuit layer can be increased to the recess, has reduced or avoided because of the production of skin effect leads to the equivalent resistance increase of last circuit layer when the electric current passes through, and then has reduced last circuit layer self heat loss, has promoted the current-carrying capacity of last circuit layer, has improved the power of semiconductor device, can also prolong the life of ceramic heat sink simultaneously, has improved the stability of ceramic heat sink operation.

Description

Ceramic heat sink and combination thereof

Technical Field

The invention relates to the technical field of laser devices, in particular to a ceramic heat sink and a combination thereof.

Background

The semiconductor laser is a laser which operates by using stimulated radiation generated by a semiconductor material, and has advantages of miniaturization, low power consumption, high efficiency, high-speed modulation, long lifetime, and the like. Semiconductor lasers are widely used in the fields of optical communication, laser printing and scanning, medical technology, material processing, optical information processing, and the like.

In the prior art, a circuit layer of a ceramic heat sink is connected with a semiconductor device, and the circuit layer is of an integral flat plate structure. However, when the ceramic heat sink is loaded with direct current, alternating current or pulse current, the current distribution of the circuit layer is uneven due to skin effect generated when the current passes through the circuit layer, and the current is concentrated on the skin part of the circuit layer. That is, when current flows through the circuit layer, the current is concentrated on the thin layer of the circuit layer adjacent to the surface, and when the current frequency is higher, the adjacent depth is smaller, the current is closer to the surface of the circuit layer, the current density is larger, and the current actually passing through the circuit layer is smaller, so that the actual effective sectional area of the current flowing through the circuit layer is reduced, the equivalent resistance of the circuit layer is increased, the loss power of the circuit layer is increased, and the current carrying capacity of the circuit layer cannot be met.

Accordingly, improvements are needed for existing ceramic heat sinks.

Disclosure of Invention

The invention aims to provide a ceramic heat sink and a combination thereof, which reduce or avoid the increase of equivalent resistance of an upper circuit layer caused by skin effect when current passes, thereby reducing self heat loss of the upper circuit layer, improving current carrying capacity of the upper circuit layer and improving power of a semiconductor device.

The invention adopts the following technical scheme:

a ceramic heat sink for soldering a semiconductor device, comprising:

a ceramic substrate having a first face and a second face disposed opposite to each other in a thickness direction of the ceramic heat sink;

the circuit layer comprises an upper circuit layer arranged on the first surface of the ceramic substrate to be connected with the semiconductor device;

the upper circuit layer comprises a plurality of grooves which are arranged at intervals.

Preferably, the upper circuit layer includes a dividing region, and the plurality of grooves disposed at intervals are disposed in the dividing region.

Preferably, the upper circuit layer further includes a reserved area corresponding to the semiconductor device, the reserved area is in an integral plate-shaped structure, and the dividing area is integrally connected with the corresponding reserved area.

Preferably, the grooves are long and divide the upper circuit layer into a plurality of comb-tooth-shaped sub-circuit layers, or the grooves are hole-shaped and divide the upper circuit layer into a grid shape.

Preferably, the grooves penetrate through the upper circuit layer to the first surface of the ceramic substrate.

Preferably, the groove does not penetrate through the upper circuit layer, the upper circuit layer comprises a bottom wall located below the groove and side walls located on two sides of the groove, and the groove is formed by surrounding the bottom wall and the side walls.

Preferably, the upper circuit layer comprises a first circuit-dividing layer positioned below the groove and a second circuit-dividing layer superposed on the first circuit-dividing layer, the bottom wall is formed on the first circuit-dividing layer, the side wall is formed on the second circuit-dividing layer, and the first circuit-dividing layer is in contact with the ceramic substrate and is of an integral plate-shaped structure.

Preferably, the ends of the sub-line layers are connected to each other, so that the sub-line layers form a current loop with parallel lines.

Preferably, the upper circuit layer comprises a first upper circuit layer and a second upper circuit layer which are simultaneously arranged on the first surface of the ceramic substrate at intervals, and the first upper circuit layer and the second upper circuit layer both comprise the dividing region.

Preferably, the first upper circuit layer is divided into a plurality of first sub-circuit layers, the second upper circuit layer is divided into a plurality of second sub-circuit layers, the first sub-circuit layers are provided with opposite first end portions and second end portions, the first end portions are integrally connected to the reserved area, the second end portions are completely separated, the second sub-circuit layers are provided with opposite third end portions and fourth end portions, and the third end portions and the fourth end portions are completely separated.

Preferably, the second ends of the plurality of first sub-wiring layers are arranged in the transverse direction and every two adjacent second ends are staggered in the longitudinal direction perpendicular to the transverse direction;

the second sub-circuit layers have the same length and are arranged at intervals along the transverse direction, and every two adjacent third end parts and every two adjacent fourth end parts are arranged in a staggered manner along the longitudinal direction.

Preferably, the cross-sectional area of the second end of the first sub-line layer is larger than the cross-sectional area of other positions of the first sub-line layer; the cross-sectional area of the third end portion and the fourth end portion of the second sub-line layer is larger than the cross-sectional area of other positions of the second sub-line layer.

Preferably, the first surface of the ceramic substrate is provided with a plurality of blind holes, and the second end of the first sub-circuit layer, the third end of the second sub-circuit layer and the fourth end are provided with filling parts filled in the blind holes.

Preferably, the width of the recess is greater than the thickness of the bottom wall.

Preferably, the dividing area of the upper circuit layer is further provided with a plurality of connecting pieces arranged at intervals, each connecting piece is connected with one or more grooves, the connecting pieces are of plate-shaped structures, and the connecting pieces are connected with the semiconductor device or the adjacent ceramic heat sink through leads.

Preferably, the upper circuit layer is provided with a gold-tin alloy layer corresponding to the reserved area so as to be directly welded with the first electrode of the semiconductor device, the projected area of the reserved area on the ceramic substrate is larger than the projected area of the gold-tin alloy layer on the ceramic substrate, and the projected area of the gold-tin alloy layer on the ceramic substrate is larger than the projected area of the semiconductor device on the ceramic substrate.

Preferably, the upper circuit layer at least comprises a conductive layer, the conductive layer comprises a first copper layer, an aluminum layer and a second copper layer, the aluminum layer is arranged on the first copper layer, and the second copper layer is coated on the first copper layer and the aluminum layer.

Preferably, the circuit layer further includes a lower circuit layer disposed on the second side of the ceramic substrate.

A ceramic heat sink assembly comprising a ceramic heat sink as claimed in any one of the preceding claims and a semiconductor device connected to the ceramic heat sink, the upper wiring layer comprising a first upper wiring layer and a second upper wiring layer disposed at a first face of the ceramic substrate at a spaced apart relationship, the semiconductor device comprising a first pole and a second pole disposed opposite to each other, the first upper wiring layer being connected to the first pole of the semiconductor device, the second upper wiring layer being connected to the second pole of the semiconductor device by a lead.

Preferably, the semiconductor device comprises a plurality of ceramic heat sinks and a semiconductor device connected to the ceramic heat sinks, wherein two adjacent ceramic heat sinks are respectively connected with corresponding upper circuit layers through a plurality of leads.

Compared with the prior art, the invention has the beneficial effects that at least:

according to the ceramic heat sink and the combination thereof, the grooves are formed in the upper circuit layer, so that the surface area of the upper circuit layer can be increased, the increase of the equivalent resistance of the upper circuit layer caused by the skin effect when current passes through is reduced or avoided, the self heat loss of the upper circuit layer is further reduced, the current carrying capacity of the upper circuit layer is improved, the power of a semiconductor device is improved, the service life of the ceramic heat sink is prolonged, and the operation stability of the ceramic heat sink is improved.

Drawings

Fig. 1 is a schematic structural diagram of a view angle of a ceramic heat sink assembly according to embodiment 1 of the present invention.

Fig. 2 is a schematic structural view of another view of the ceramic heat sink assembly of embodiment 1 of the present invention.

Fig. 3 is a schematic cross-sectional view of fig. 2 along line A-A.

Fig. 4 is a schematic structural view of a ceramic heat sink assembly according to embodiment 2 of the present invention from one view.

Fig. 5 is a schematic structural view of another view of the ceramic heat sink assembly of embodiment 2 of the present invention.

Fig. 6 is a schematic cross-sectional view of fig. 5 taken along line A-A.

Fig. 7 is a schematic structural diagram of a view angle of a ceramic heat sink assembly of embodiment 3 of the present invention.

Fig. 8 is a schematic structural view of another view of the ceramic heat sink assembly of embodiment 3 of the present invention.

Fig. 9 is a schematic cross-sectional view of fig. 8 along line A-A.

Fig. 10 is a schematic structural diagram of a combined connection of two ceramic heat sinks in the present invention.

Fig. 11 is a schematic structural view of a ceramic heat sink assembly according to embodiment 4 of the present invention from one view.

Fig. 12 is a schematic diagram of a ceramic heat sink assembly according to another view of embodiment 4 of the present invention.

Fig. 13 is a schematic cross-sectional view of fig. 12 taken along line A-A.

Fig. 14 is a schematic view of a specific structure of a circuit layer according to the present invention.

In the figure: 100. a ceramic heat sink; 1. a ceramic substrate; 11. a first face; 111. a blind hole; 112. a filling part; 12. a second face; 2. a circuit layer; 21. an upper circuit layer; 211. a first upper wiring layer; 2110. a first sub-line layer; 21101. a first end; 21102. a second end; 2111. a first adhesive layer; 2112. a first conductive layer; 21121/21221, a first copper layer; 21122/21222, aluminium layer; 21123/21223, a second copper layer; 2113. a first isolation layer; 2114. a first protective layer; 212. a second upper wiring layer; 2120. a second sub-line layer; 21201. a third end; 21202. a fourth end; 2121. a second adhesive layer; 2122. a second conductive layer; 2123. a second isolation layer; 2124. a second protective layer; 213. a gold-tin alloy layer; 2131. a third adhesion layer; 2132. a barrier layer; 2133. a gold tin layer; 2134. a third protective layer; 214. a reserved area; 215. dividing the region; 2151. a first divided region; 2152. a second dividing region; 216. a connecting sheet; 2161. a first connecting piece; 2162. a second connecting piece; 217. a first wiring layer; 218. a second wiring layer; 22. a lower wiring layer; 221. a fourth adhesive layer; 222. a fourth conductive layer; 223. a fourth isolation layer; 224. a fourth protective layer; 3. a groove; 31. a first groove; 32. a second groove; 4. a semiconductor device; 41. a first pole; 42. a second pole; 5. a first lead; 6. and a second lead.

Detailed Description

Example embodiments will now be described more fully with reference to the accompanying drawings. However, the exemplary embodiments can be embodied in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and thus a repetitive description thereof will be omitted.

The words expressing the positions and directions described in the present invention are described by taking the drawings as an example, but can be changed according to the needs, and all the changes are included in the protection scope of the present invention.

Referring to fig. 1 to 14, the present invention provides a ceramic heat sink 100, the ceramic heat sink 100 being used for connecting a semiconductor device 4, the semiconductor device 4 may be a laser chip, the ceramic heat sink 100 comprising: a ceramic substrate 1 and a wiring layer 2, the wiring layer 2 being provided on the ceramic substrate 1.

Specifically, the ceramic base material 1 is entirely rectangular parallelepiped, and may be formed in other shapes as required. The ceramic substrate 1 has a first surface 11 and a second surface 12 which are disposed opposite to each other in the thickness direction or the height direction of the ceramic heat sink 100, and the first surface 11 and the second surface 12 are preferably two surfaces having a large area on the ceramic substrate 1. The ceramic substrate 1 may be any one or a combination of a plurality of silicon carbide, gallium nitride, diamond, gallium arsenide, gallium phosphide, gallium antimonide, beryllium oxide or silicon nitride materials, and other kinds of materials can be selected according to actual needs. In the embodiment of the present invention, the material of the ceramic substrate 1 is preferably diamond, and the thermal conductivity of diamond is high, so that the thermal conductivity of the ceramic heat sink 100 is improved.

The wiring layer 2 may include an upper wiring layer 21 disposed on the first face 11 of the ceramic substrate 1 to connect the semiconductor device 4. The upper wiring layer 21 may be provided to the first face 11 of the ceramic substrate 1 by means of an electroplating process, a direct copper bonding (DBC-Direct Bond Copper) process, an active brazing process (AMB-Active Metal Brazing), or the like.

Wherein, the upper circuit layer 21 comprises a plurality of grooves 3 which are arranged at intervals. The grooves 3 can greatly increase the circumference of the cross section of the upper wiring layer 21, thereby increasing the effective cross-sectional area of the upper wiring layer 21. By arranging the grooves 3 on the upper circuit layer 21, the surface area of the upper circuit layer 21 can be increased by the grooves 3, when direct current, alternating current or pulse current is loaded on the ceramic heat sink, the equivalent resistance of the upper circuit layer 21 is reduced or avoided from being increased due to the skin effect when the current passes through, the self heat loss of the upper circuit layer 21 is further reduced, the current carrying capacity of the upper circuit layer 21 is improved, the power of the semiconductor device 4 is improved, the service life of the ceramic heat sink 100 is prolonged, and the running stability of the ceramic heat sink 100 is improved. The current is, for example, continuous Wave (Continuous Wave) or pulse width modulation (Quasi-Continuous Wave).

In a specific embodiment, the upper circuit layer 21 may include a dividing area 215, and the plurality of grooves 3 disposed at intervals are disposed in the dividing area 215, and the dividing area 215 may increase the surface of the upper circuit layer 21.

The upper wiring layer 21 may further include a reserved area 214 corresponding to the semiconductor device 4, the reserved area 214 being of an integral plate-like structure, and the dividing area 215 being integrally connected with the corresponding reserved area 214. The area of the reserved area 214 is preferably larger than the area of the semiconductor device 4, so that the upper circuit layer 21 is in full contact with the semiconductor device 4, heat generated by the semiconductor device 4 can be completely conducted from the upper circuit layer 21 to the heat dissipation structure, the heat dissipation effect is improved, the service life of the ceramic heat sink 100 is prolonged, and the operation stability of the ceramic heat sink 100 is improved.

The upper circuit layer 21 may further be provided with a au-sn alloy layer 213 corresponding to the reserved area 214 for direct welding with the semiconductor device 4, where the projected area of the reserved area 214 on the ceramic substrate 1 is larger than the projected area of the au-sn alloy layer 213 on the ceramic substrate 1, so that the formation of the au-sn alloy layer 213 is facilitated, and meanwhile, the heat dissipation performance of the reserved area 214 is ensured, and the projected area of the au-sn alloy layer 213 on the ceramic substrate 1 is larger than the projected area of the semiconductor device 4 on the ceramic substrate 1, so that the difficulty of welding the semiconductor device 4 to the au-sn alloy layer 213 is reduced.

Preferably, the groove 3 may be elongated and divide the upper wiring layer 21 into a plurality of sub-wiring layers in a comb-tooth shape, and the elongated shape may be rectangular, curved, or the like. The grooves 3 may be formed in a hole shape such as round holes, square holes, polygonal holes, or the like, and divide the upper wiring layer 21 into a mesh shape. The grooves 3 may be provided through the upper wiring layer 21, or may not be provided through the upper wiring layer 21.

The upper wiring layer 21 may include a first upper wiring layer 211 and a second upper wiring layer 212 simultaneously provided at a spacing on the first face 11 of the ceramic substrate 1 and for connecting the semiconductor device 4, each of the first upper wiring layer 211 and the second upper wiring layer 212 including a dividing region 215. The grooves 3 may include a first groove 31 and a second groove 32, the first groove 31 being located at the dividing region 215 of the first upper wiring layer 211, the second groove 32 being located at the dividing region 215 of the second upper wiring layer 212, the first groove 31 and the second groove 32 being identical or similar in shape.

In one embodiment, the upper circuit layer 21 at least includes a conductive layer, the first conductive layer 2112 and the second conductive layer 2122 are collectively referred to as conductive layers, the conductive layer includes a first copper layer 21121/21221, an aluminum layer 21122/21222 and a second copper layer 21123/21223, which are disposed on the first upper circuit layer 211 and the second upper circuit layer 212, respectively, the aluminum layer 21122/21222 is disposed on the first copper layer 21121/21221, and the second copper layer 21123/21223 is coated on the first copper layer 21121/21221 and the aluminum layer 21122/21222. On the one hand, compared with the prior art that the conductive layers all adopt copper layers, the aluminum layers 21122/21222 increase the surface areas of the first copper layers 21121/21221 and the second copper layers 21123/21223, improve the effective area of current passing in the conductive layers, reduce or avoid the increase of equivalent resistance of the conductive layers due to the generation of skin effect when current passes, further reduce self heat loss of the upper circuit layer 21, and improve the current carrying capacity of the upper circuit layer 21; on the other hand, the density of copper is more than 3 times of that of aluminum, and compared with the prior art that all the conductive layers adopt copper layers, the weight of the ceramic heat sink is smaller after the aluminum layers 21122/21222 are arranged, so that the weight of the ceramic heat sink is reduced. The cross-sectional areas of the first copper layer 21121/21221 and the second copper layer 21123/21223 are preferably approximately the same as the skin effect area, so that the skin effect resistance of the conductive layer can be reduced to the greatest extent and the effect of the skin effect can be minimized.

Referring to fig. 14, the first upper line layer 211 may further include a first adhesive layer 2111, a first conductive layer 2112, a first separation layer 2113, and a first protective layer 2114, which are sequentially stacked, the first adhesive layer 2111 being disposed on the first face 11 of the ceramic substrate 1.

Specifically, the first adhesive layer 2111 may be a titanium layer, and the first adhesive layer 2111 increases the bonding force between the ceramic substrate 1 and the first conductive layer 2112. The first conductive layer 2112 is located between the first adhesion layer 2111 and the first isolation layer 2113, the first conductive layer 2112 is plated on the surface of the first adhesion layer 2111, the first conductive layer 2112 may include a first copper layer 21121, an aluminum layer 21122 and a second copper layer 21123, the aluminum layer 21122 is disposed on the first copper layer 21121, and the second copper layer 21123 is coated on the first copper layer 21121 and the aluminum layer 21122. The aluminum layer 21122 increases the surface area of the first copper layer 21121 and the second copper layer 21123, increases the effective area of the first conductive layer 2112, reduces or avoids the increase of the equivalent resistance of the first conductive layer 2112 due to the skin effect generated when the current passes through, further reduces the heat loss of the first upper circuit layer 211 and improves the current carrying capacity of the second upper circuit layer 212. The cross-sectional areas of the first copper layer 21121 and the second copper layer 21123 are preferably substantially the same as the skin effect area, so that the skin effect resistance of the first conductive layer 2112 can be reduced to the greatest extent, and the influence of the skin effect is minimized. The first isolation layer 2113 is located between the first conductive layer 2112 and the first protective layer 2114, the first isolation layer 2113 is plated on the surface of the first conductive layer 2112, the first isolation layer 2113 may be a nickel layer, the first isolation layer 2113 may be used to prevent copper ions of the first conductive layer 2112 from migrating into the subsequent first protective layer 2114, and in this embodiment, the thickness of the first isolation layer 2113 is preferably 2 to 5 micrometers, and when the first isolation layer 2113 is too thin, the barrier effect thereof is deteriorated. The first protection layer 2114 may be a gold layer, which is plated on the surface of the first isolation layer 2113, and the first protection layer 2114 may prevent the first upper wiring layer 211 from being oxidized and improve signal transmission quality, and preferably increases the thickness of the first protection layer 2114 according to actual conditions, so that a heat dissipation effect may be enhanced and a safety of a large current passing through may be ensured.

The second upper circuit layer 212 may further include a second adhesion layer 2121, a second conductive layer 2122, a second isolation layer 2123, and a second protection layer 2124 sequentially stacked, where the second adhesion layer 2121 is disposed on the first surface 11 of the ceramic substrate 1.

Specifically, the second adhesion layer 2121 may be a titanium layer, and the second adhesion layer 2121 increases the bonding force between the ceramic base material 1 and the second conductive layer 2122. The second conductive layer 2122 is located between the second adhesion layer 2121 and the second isolation layer 2123, the second conductive layer 2122 is plated on the surface of the second adhesion layer 2121, the second conductive layer 2122 may include a first copper layer 21221, an aluminum layer 21222 and a second copper layer 21223, the aluminum layer 21222 is disposed on the first copper layer 21221, and the second copper layer 21223 is coated on the first copper layer 21221 and the aluminum layer 21222. The aluminum layer 21222 increases the surface areas of the first copper layer 21221 and the second copper layer 21223, increases the effective area of the second conductive layer 2122, reduces or avoids an increase in the equivalent resistance of the second conductive layer 2122 due to the skin effect generated when current passes through, thereby reducing the heat loss of the second upper circuit layer 212 and improving the current carrying capacity of the second upper circuit layer 212. The cross-sectional areas of the first copper layer 21221 and the second copper layer 21223 are preferably approximately the same as the skin effect area, minimizing the skin effect resistance of the second conductive layer 2122 and minimizing the effect of the skin effect. The second isolation layer 2123 is located between the second conductive layer 2122 and the second protection layer 2124, the second isolation layer 2123 is plated on the surface of the second conductive layer 2122, the second isolation layer 2123 may be a nickel layer, the second isolation layer 2123 may be used to prevent copper ions of the second conductive layer 2122 from migrating into the subsequent second protection layer 2124, in this embodiment, the thickness of the second isolation layer 2123 is preferably 2 to 5 micrometers, and when the second isolation layer 2123 is too thin, the blocking effect is poor. The second protection layer 2124 may be a gold layer, and is plated on the surface of the second isolation layer 2123, where the second protection layer 2124 may prevent the second upper circuit layer 212 from oxidizing and improve signal transmission quality, and according to practical situations, it is preferable to increase the thickness of the second protection layer 2124, so as to enhance heat dissipation effect and ensure safe passing of large current.

The au—sn alloy layer 213 may include a third adhesion layer 2131, barrier layers 2132, jin Xiceng 2133, and a third protective layer 2134, the third adhesion layer 2131 being a titanium layer, the barrier layer 2132 being a platinum layer, the third protective layer 2134 being a au layer.

Specifically, the third adhesion layer 2131 is disposed on the upper surface of the first upper circuit layer 211, the barrier layer 2132 is disposed between the third adhesion layer 2131 and the tin layer 2133, and the barrier layer 2132 can prevent the inter-diffusion between the Jin Xiceng layer 2133 located above the barrier layer 2132 and the third adhesion layer 2131 located below the barrier layer 2132, so as to change the tin-gold ratio in the tin layer 2133, thereby affecting the soldering effect, forming eutectic between the tin and gold in the tin layer 2133, and enabling the first electrode 41 of the semiconductor device 4 and the tin layer 2133 to be soldered together by direct contact heating without solder, thereby improving the soldering convenience and the soldering production efficiency. The third protection layer 2134 is coated on the outer surface of the Jin Xiceng 2133, and the third protection layer 2134 is used for preventing the oxidation of the gold-tin layer 2133 and also can effectively prevent other coating layers on the surface of the ceramic heat sink 100 from being corroded, thereby playing a role in protecting the ceramic heat sink 100.

The wiring layer 2 may further include a lower wiring layer 22 disposed on the second face 12 of the ceramic substrate 1. The lower wiring layer 22 may also be provided to the second face 12 of the ceramic substrate 1 by means of an electroplating process, direct copper bonding (DBC-Direct Bond Copper), active brazing process (AMB-Active Metal Brazing), or the like. The lower circuit layer 22 can be used for welding the ceramic heat sink 100 to other components, or conducting the heat of the ceramic heat sink 100 to other components or conducting the heat of the ceramic heat sink 100 into the air, thereby playing a role in heat dissipation of the ceramic heat sink 100, improving the performance of the ceramic heat sink 100 and prolonging the service life of the ceramic heat sink 100.

The lower wiring layer 22 may include a fourth adhesive layer 221, a fourth conductive layer 222, a fourth isolation layer 223, and a fourth protective layer 224, which are sequentially stacked, the fourth adhesive layer 221 being disposed on the second face 12 of the ceramic substrate 1.

Specifically, the fourth adhesion layer 221 may be a titanium layer, and the fourth adhesion layer 221 increases the bonding force between the ceramic substrate 1 and the fourth conductive layer 222. The fourth conductive layer 222 is disposed between the fourth adhesion layer 221 and the fourth isolation layer 223, the fourth conductive layer 222 is plated on the surface of the fourth adhesion layer 221, and the fourth conductive layer 222 may be a copper layer. The fourth isolation layer 223 is located between the fourth conductive layer 222 and the fourth protection layer 224, the fourth isolation layer 223 is plated on the surface of the fourth conductive layer 222, the fourth isolation layer 223 may be a nickel layer, the fourth isolation layer 223 may be used to prevent copper ions of the fourth conductive layer 222 from migrating into the subsequent fourth protection layer 224, in this embodiment, the thickness of the fourth isolation layer 223 is preferably 2-5 micrometers, and when the fourth isolation layer 223 is too thin, the blocking effect is poor. The fourth protection layer 224 may be a gold layer, and is plated on the surface of the fourth isolation layer 223, and the fourth protection layer 224 may prevent the oxidation of the lower circuit layer 22 and improve the signal transmission quality, and according to the actual situation, it is preferable to increase the thickness of the fourth protection layer 224, so that the heat dissipation effect may be enhanced.

In embodiment 1, referring to fig. 1 to 3, the grooves 3 penetrate the upper wiring layer 21 to the first face 11 of the ceramic substrate 1. Specifically, the first elongated groove 31 penetrates the first upper circuit layer 211 to the first surface 11 of the ceramic substrate 1, and the second elongated groove 32 penetrates the second upper circuit layer 212 to the first surface 11 of the ceramic substrate 1. The sidewalls of the first grooves 31 increase the surface area of the first upper wiring layer 211, and the sidewalls of the second grooves 32 increase the surface area of the second upper wiring layer 212. The surface area of the upper circuit layer 21 is increased through the first grooves 31 and the second grooves 32, so that the equivalent resistance of the upper circuit layer 21 is reduced or prevented from being increased due to the skin effect when current passes through, the self heat loss of the upper circuit layer 21 is further reduced, the current carrying capacity of the upper circuit layer 21 is improved, the power of the semiconductor device 4 is improved, the service life of the ceramic heat sink 100 is prolonged, and the operation stability of the ceramic heat sink 100 is improved.

The grooves 3 are long and divide the upper circuit layer 21 into a plurality of comb-shaped sub-circuit layers, and the ends of the sub-circuit layers are connected with each other, so that the sub-circuit layers form a current loop with parallel circuits.

Specifically, the first grooves 31 divide at least part of the first upper wiring layer 211 into a plurality of first sub-wiring layers 2110. The ends of the first sub-line layers 2110 are connected to each other so that a plurality of the first sub-line layers 2110 are electrically connected. One end of each of the plurality of first sub-line layers 2110 is connected with the reserved area 214, and the other ends of the first sub-line layers 2110 are also connected with each other to form a current loop, so that the effect of parallel connection of the first sub-line layers 2110 is achieved.

The second groove 32 divides the second upper circuit layer 212 into a plurality of second sub-circuit layers 2120, and the plurality of second sub-circuit layers 2120 are independent from each other. The ends of the second sub-line layers 2120 are connected to each other so that a plurality of second sub-line layers 2120 are electrically connected to form a current loop, thereby achieving the effect of parallel connection of the second sub-line layers 2120.

In embodiment 1, the grooves 3 may be formed by exposure, development and etching, specifically, the entire upper wiring layer 21 may be formed by plating (electroplating or chemical plating, etc.), a protective film may be attached, exposure and development may be performed to remove the protective film in the area to be etched away, i.e., the groove 3, the upper wiring layer 21 may be dissolved and etched by a chemical solution to remove the wiring layer in the groove 3, leaving the upper wiring layer 21 around the grooves 3, and thus the comb-shaped upper wiring layer 21 may be formed.

In embodiment 2, referring to fig. 4 to 6, the depth of the groove 3 is smaller than the thickness of the upper circuit layer 21, the elongated groove 3 does not penetrate the upper circuit layer 21, the upper circuit layer 21 includes a bottom wall below the groove 3 and side walls on both sides of the groove 3, and the groove 3 is formed by surrounding the bottom wall and the side walls. That is, the first elongated groove 31 does not penetrate the first upper circuit layer 211, and the second elongated groove 32 does not penetrate the second upper circuit layer 212. The surface area of the first upper wiring layer 211 in embodiment 2 increases the surface area of the bottom of the first groove 31, and the surface area of the second upper wiring layer 212 increases the surface area of the bottom of the second groove 32, as compared with embodiment 1. The surface area of the upper circuit layer 21 is further increased, the increase of the equivalent resistance of the upper circuit layer 21 caused by the skin effect when current passes through is avoided, the self heat loss of the upper circuit layer 21 is further reduced, the current carrying capacity of the upper circuit layer 21 is improved, the power of the semiconductor device 4 is improved, the service life of the ceramic heat sink 100 is prolonged, and the operation stability of the ceramic heat sink 100 is improved. In addition, the grooves 3 do not penetrate through the upper circuit layer 21, so that the contact area of the upper circuit layer 21 and the ceramic substrate 1 is ensured, the binding force between the upper circuit layer 21 and the ceramic substrate 1 is improved, heat generated by the semiconductor device 4 can be completely conducted from the upper circuit layer 21 to a heat dissipation structure, and the heat dissipation effect is improved.

The depth of the groove 3 is preferably larger than the width of the groove 3 and the thickness of the bottom wall of the groove 3, so that the surface area of the upper circuit layer 21 can be increased to the greatest extent, the increase of the equivalent resistance of the upper circuit layer 21 caused by the skin effect when current passes through is avoided, the self heat loss of the upper circuit layer 21 is further reduced, the current carrying capacity of the upper circuit layer 21 is improved, the power of the semiconductor device 4 is improved, the service life of the ceramic heat sink 100 is prolonged, and the operation stability of the ceramic heat sink 100 is improved.

Since the overall thickness of the upper wiring layer 21 is too small, in embodiment 2, the width of the groove 3 in the lateral direction is preferably larger than the thickness of the bottom wall of the groove 3 in the height direction. That is, the width of the first groove 31 is greater than the thickness of the bottom wall of the first groove 31, and the width of the second groove 32 is greater than the thickness of the bottom wall of the second groove 32. Thus, the surface area of the upper circuit layer 21 can be increased, the grooves 3 can be easily formed, the cross-sectional area of the upper circuit layer 21 can be ensured to be approximately the same as the skin effect area, the skin effect resistance of the upper circuit layer 21 can be reduced to the greatest extent, and the influence of the skin effect is minimized.

In embodiment 2, the upper circuit layer 21 may be directly formed by one-time electroplating or electroless plating, and then the groove 3 may be formed by etching or CNC or laser processing.

The upper wiring layer 21 may further be composed of two wiring layers, and the upper wiring layer 21 may include a first wiring layer 217 located under the groove 3 and a second wiring layer 218 stacked on the first wiring layer 217. The bottom wall of the groove 3 is formed on the first wiring layer 217, and the side wall of the groove 3 is formed on the second wiring layer 218, and the first wiring layer 217 is in contact with the ceramic substrate 1 and is of a monolithic plate-like structure.

In embodiment 2, the upper wiring layer 21 may be formed by a secondary forming method, that is, the first wiring layer 217 is formed by plating, the first wiring layer 217 is a monolithic plate-like structure, and the second wiring layer 218 is formed by plating and etching through exposure and development. The second wiring layer 218 serves as a sidewall of the recess 3, and the first wiring layer 217 serves as a bottom wall of the recess 3.

In embodiment 3, referring to fig. 7 to 9, when the grooves 3 penetrate the upper wiring layer 21, the shape of the grooves 3 in embodiment 3 is square hole-shaped and divides the first upper wiring layer 211 into a mesh shape in comparison with embodiment 1, and other portions of the ceramic heat sink 100 in embodiment 3 are the same as the structure of the ceramic heat sink 100 in embodiment 1.

When the grooves 3 do not penetrate the upper wiring layer 21, the shape of the grooves 3 in embodiment 3 is square hole-like and divides the second upper wiring layer 212 into mesh shapes, as compared with embodiment 2, and other portions of the ceramic heat sink 100 in embodiment 3 are the same as the ceramic heat sink 100 in embodiment 2.

In embodiments 1 to 3, referring to fig. 1 to 10, the dividing region 215 of the upper wiring layer 21 may further be provided with a plurality of connecting pieces 216 arranged at intervals, each connecting piece 216 is connected to one or more grooves 3, the connecting pieces 216 have a plate-like structure, the connecting pieces 216 are connected to the semiconductor device 4 or the adjacent ceramic heat sink 100 by leads, and the first leads 5 and the second leads 6 described below are collectively referred to as leads.

Specifically, the split region 215 includes a first split region 2151 and a second split region 2152, the first split region 2151 is located on the first upper wiring layer 211, and the second split region 2152 is located on the second upper wiring layer 212.

The first split region 2151 may be provided with a plurality of first connecting tabs 2161 disposed at intervals, the first connecting tabs 2161 disposed at the first split region 2151 are connected to one or more first recesses 31, the second split region 2152 may be provided with a plurality of first connecting tabs 2161 disposed at intervals, the first connecting tabs 2161 disposed at the second split region 2152 are connected to one or more second recesses 32, and the first connecting tabs 2161 are connected to adjacent ceramic heat sinks 100 through second leads 6.

The area of the first connecting tab 2161 is relatively large, facilitating the welding of the second lead 6 to the first connecting tab 2161. The first connecting pieces 2161 are spaced apart, and the surface area of the upper wiring layer 21 can be further increased compared to the case where the plurality of first connecting pieces 2161 are provided as one body.

The first connection tab 2161 is preferably disposed at a side of the first split region 2151 remote from the semiconductor device 4, and the first connection tab 2161 is preferably disposed at a side of the second split region 2152 remote from the semiconductor device 4, so that the length of the second lead 6 connecting the adjacent ceramic heat sinks 100 can be shortened, thereby reducing heat loss of the second lead 6.

The second split region 2152 may further be provided with a second connecting tab 2162, the second connecting tab 2162 being provided on a side of the second split region 2152 adjacent to the semiconductor device 4, the second connecting tab 2162 preferably being of unitary plate-like construction, the second connecting tab 2162 connecting the plurality of second recesses 32. The second connecting piece 2162 is connected to the semiconductor device 4 through a first lead 5, for example, a gold wire. Because the number of the first leads 5 is large and the density is high, the area of the second connecting piece 2162 is larger than that of the first leads 5 arranged on the first sub-circuit layer 2110, the first leads 5 are easier to be welded to the second connecting piece 2162, the problem that the first leads 5 are difficult to be arranged is solved, the welding efficiency of the first leads 5 is improved, and meanwhile, the welding yield of the first leads 5 is also improved.

In embodiment 4, referring to fig. 11 to 13, the first upper circuit layer 211 is divided into a plurality of first sub-circuit layers 2110, and the gaps between adjacent first sub-circuit layers 2110 are first grooves 31, and the first grooves 31 penetrate through the first upper circuit layer 211 to the first face 11 of the ceramic substrate 1. The plurality of first sub-circuit layers 2110 are provided with a first end portion 21101 and a second end portion 21102 which are opposite, the plurality of first end portions 21101 are integrally connected to the reserved area 214, the plurality of second end portions 21102 are completely separated, the surface area of the first upper circuit layer 211 can be further increased, the increase of the equivalent resistance of the first upper circuit layer 211 caused by the skin effect when current passes through is avoided, the self heat loss of the first upper circuit layer 211 is further reduced, and the current carrying capacity of the first upper circuit layer 211 is improved.

The second end portions 21102 of the plurality of first sub-wiring layers 2110 are arranged in the lateral direction and each adjacent two of the second end portions 21102 are staggered in the longitudinal direction perpendicular to the lateral direction. The second end 21102 of the first sub-line layer 2110 is for connection with a second lead 6, which second lead 6 may electrically connect adjacent ceramic heat sinks 100, the second lead 6 being, for example, an aluminum wire. The second ends 21102 of the first sub-circuit layers 2110 are staggered, so that arrangement of the second leads 6 is facilitated, and the second leads 6 are prevented from being welded in disorder. The cross-sectional area of the first sub-line layer 2110 is approximately the same as the skin effect area, so that the skin effect resistance of the first sub-line layer 2110 can be reduced to the greatest extent, and the influence of the skin effect is minimized.

The cross-sectional area of the second end 21102 of the first sub-line layer 2110 is greater than the cross-sectional area of other locations of the first sub-line layer 2110. That is, the width of the second end portion 21102 of the first sub-wiring layer 2110 is larger, so that the welding of the second lead 6 is more facilitated, and the welding efficiency and yield of the second lead 6 are improved.

The second upper circuit layer 212 is divided into a plurality of second sub-circuit layers 2120, and gaps between adjacent second sub-circuit layers 2120 are second grooves 32, wherein the second grooves 32 penetrate through the second upper circuit layer 212 to the first face 11 of the ceramic substrate 1. The plurality of second sub-circuit layers 2120 are provided with a third end 21201 and a fourth end 21202 which are opposite, and the plurality of third end 21201 and the plurality of fourth end 21202 are all completely separated from each other, so that the surface area of the second upper circuit layer 212 can be further increased, the increase of the equivalent resistance of the second upper circuit layer 212 due to the generation of skin effect when current passes through is avoided, the self heat loss of the second upper circuit layer 212 is further reduced, and the current carrying capacity of the second upper circuit layer 212 is improved.

The second sub-circuit layers 2120 have the same length and are arranged at intervals in the lateral direction, and each adjacent two third end portions 21201 and each adjacent two fourth end portions 21202 are staggered in the longitudinal direction. The length of each second sub-line layer 2120 is the same, which ensures that the surface area of each second sub-line layer 2120 is the same. The end of the second sub-wiring layer 2120 near the semiconductor device 4 is used for soldering the first lead 5, and the end of the second sub-wiring layer 2120 remote from the semiconductor device 4 is used for soldering the second lead 6. The third end 21201 and the fourth end 21202 of the second sub-line layer 2120 are staggered, so that the arrangement of the first lead 5 and the second lead 6 is facilitated, and the first lead 5 and the second lead 6 are prevented from being welded in disorder.

The second sub-circuit layer 2120 is preferably connected to the first lead 5 in a one-to-one correspondence manner, and the cross-sectional area of the second sub-circuit layer 2120 is substantially the same as the skin effect area, so that the skin effect resistance of the second sub-circuit layer 2120 can be reduced to the greatest extent and the influence of the skin effect is minimized. The carrying capacity of each second sub-line layer 2120 is preferably greater than or equal to the carrying capacity of each first lead 5 to ensure that each second sub-line layer 2120 operates stably.

The cross-sectional area of the third end 21201 and the fourth end 21202 of the second sub-wiring layer 2120 is larger than the cross-sectional area of the other portions of the second sub-wiring layer 2120. That is, the third end 21201 and the fourth end 21202 of the second sub-wiring layer 2120 have larger widths, which facilitates the soldering of the first lead 5 and the second lead 6, and improves the soldering efficiency and yield of the first lead 5 and the second lead 6.

The first surface 11 of the ceramic substrate 1 may further be provided with a plurality of blind vias 111, and the second end portion 21102 of the first sub-wiring layer 2110 and the third end portion 21201 and the fourth end portion 21202 of the second sub-wiring layer 2120 may be provided with filling portions 112 filled in the blind vias 111. Of course, the blind via 111 may be disposed at other locations of the first sub-line layer 2110 and the second sub-line layer 2120. The blind holes 111 can improve the bonding force between the first sub-line layer 2110 and the second sub-line layer 2120 and the ceramic substrate 1, and prevent the first sub-line layer 2110 and the second sub-line layer 2120 from falling off from the ceramic substrate 1.

The invention also provides a ceramic heat sink assembly, which comprises the ceramic heat sink 100 and the semiconductor device 4 connected to the ceramic heat sink 100, wherein the upper circuit layer 21 comprises a first upper circuit layer 211 and a second upper circuit layer 212 which are arranged on the first surface 11 of the ceramic substrate 1 at intervals, the semiconductor device 4 comprises a first pole 41 and a second pole 42 which are oppositely arranged, the first upper circuit layer 211 is connected with the first pole 41 of the semiconductor device 4, and the second upper circuit layer 212 is connected with the second pole 42 of the semiconductor device 4 through a first lead 5. When the first pole 41 of the semiconductor device 4 is the positive pole or the P pole, the second pole 42 of the semiconductor device 4 is the negative pole or the N pole, and when the first pole 41 of the semiconductor device 4 is the negative pole or the N pole, the second pole 42 of the semiconductor device 4 is the positive pole or the P pole, and in the embodiment of the present invention, the first pole 41 of the semiconductor device 4 is the positive pole, and the second pole 42 of the semiconductor device 4 is the negative pole. When the semiconductor device 4 is connected to the ceramic heat sink 100, the first electrode 41 of the semiconductor device 4 is connected to the first upper wiring layer 211, and the second upper wiring layer 212 is connected to the second electrode 42 of the semiconductor device 4 through the first lead 5. The first electrode 41 of the semiconductor device 4 may be connected to the first upper wiring layer 211 by soldering, conductive adhesive bonding, or the like.

The ceramic heat sink assembly may include a plurality of ceramic heat sinks 100 and semiconductor devices 4 connected to the ceramic heat sinks 100, and two adjacent ceramic heat sinks 100 are respectively connected to the corresponding upper circuit layers 21 through a plurality of second leads 6, and the second leads 6 may be aluminum wires.

While embodiments of the present invention have been shown and described, it will be understood that the above embodiments are illustrative and not to be construed as limiting the invention, and that changes, modifications, substitutions and alterations may be made therein by those of ordinary skill in the art without departing from the spirit and scope of the invention, all such changes being within the scope of the appended claims.

Claims (20)

1. A ceramic heat sink for connecting a semiconductor device, comprising:

a ceramic substrate having a first face and a second face disposed opposite to each other in a thickness direction of the ceramic heat sink;

the circuit layer comprises an upper circuit layer arranged on the first surface of the ceramic substrate to be connected with the semiconductor device;

the upper circuit layer comprises a plurality of grooves which are arranged at intervals.

2. The ceramic heat sink of claim 1 wherein the upper circuit layer comprises a split region, the plurality of spaced apart grooves being disposed in the split region.

3. The ceramic heat sink of claim 2 wherein the upper wiring layer further comprises a reserved area corresponding to the semiconductor device, the reserved area having a monolithic plate-like structure, the dividing area being integrally connected with the corresponding reserved area.

4. A ceramic heat sink according to claim 3, wherein the grooves are elongated and divide the upper wiring layer into a plurality of sub-wiring layers in the shape of comb teeth, or wherein the grooves are hole-shaped and divide the upper wiring layer into a grid shape.

5. The ceramic heat sink of claim 4 wherein the grooves extend through the upper wiring layer to the first face of the ceramic substrate.

6. The ceramic heat sink of claim 4 wherein the recess does not extend through the upper circuit layer, the upper circuit layer comprising a bottom wall below the recess and side walls on either side of the recess, the recess being defined by the bottom wall and the side walls.

7. The ceramic heat sink of claim 6 wherein the upper wiring layer comprises a first wiring layer below the recess and a second wiring layer overlying the first wiring layer, the bottom wall being formed on the first wiring layer, the side wall being formed on the second wiring layer, the first wiring layer being in contact with the ceramic substrate and being of unitary plate-like construction.

8. The ceramic heat sink of claim 4 wherein ends of the plurality of sub-circuit layers are interconnected such that the plurality of sub-circuit layers form a circuit-parallel current loop.

9. The ceramic heat sink of claim 4 wherein the upper wiring layer comprises a first upper wiring layer and a second upper wiring layer simultaneously spaced apart on the first face of the ceramic substrate, the first upper wiring layer and the second upper wiring layer each comprising the split region.

10. The ceramic heat sink of claim 9 wherein the first upper wire layer is split to form a plurality of first sub-wire layers and the second upper wire layer is split to form a plurality of second sub-wire layers, the plurality of first sub-wire layers having opposite first and second ends, the plurality of first ends integrally connected to the retention region, the plurality of second ends disposed in a fully spaced apart relationship, the plurality of second sub-wire layers having opposite third and fourth ends, the plurality of third and fourth ends disposed in a fully spaced apart relationship.

11. The ceramic heat sink of claim 10 wherein the second ends of the plurality of first sub-circuit layers are arranged in a transverse direction and each adjacent two second ends are staggered in a longitudinal direction perpendicular to the transverse direction;

The second sub-circuit layers have the same length and are arranged at intervals along the transverse direction, and every two adjacent third end parts and every two adjacent fourth end parts are arranged in a staggered manner along the longitudinal direction.

12. The ceramic heat sink of claim 10 wherein the cross-sectional area of the second end of the first sub-circuit layer is greater than the cross-sectional area of other locations of the first sub-circuit layer; the cross-sectional area of the third end portion and the fourth end portion of the second sub-line layer is larger than the cross-sectional area of other positions of the second sub-line layer.

13. The ceramic heat sink of claim 10, wherein the first face of the ceramic substrate is provided with a plurality of blind holes, and the second end portion of the first sub-circuit layer and the third end portion and the fourth end portion of the second sub-circuit layer are each provided with a filling portion filled in the blind holes.

14. The ceramic heat sink of claim 6 wherein the width of the recess is greater than the thickness of the bottom wall.

15. The ceramic heat sink of claim 2 wherein said dividing region of said upper wiring layer is further provided with a plurality of spaced apart tabs, each of said tabs being connected to one or more of said recesses, said tabs being of plate-like configuration, said tabs being connected to said semiconductor device or adjacent said ceramic heat sink by leads.

16. The ceramic heat sink of claim 3 wherein the upper trace layer is provided with a gold-tin alloy layer corresponding to the reserved area for direct soldering with the first pole of the semiconductor device, the projected area of the reserved area on the ceramic substrate is greater than the projected area of the gold-tin alloy layer on the ceramic substrate, and the projected area of the gold-tin alloy layer on the ceramic substrate is greater than the projected area of the semiconductor device on the ceramic substrate.

17. The ceramic heat sink of claim 1 wherein the upper circuit layer comprises at least a conductive layer comprising a first copper layer, an aluminum layer disposed on the first copper layer, and a second copper layer clad on the first copper layer and the aluminum layer.

18. The ceramic heat sink of claim 1 wherein the wiring layer further comprises a lower wiring layer disposed on the second side of the ceramic substrate.

19. A ceramic heat sink assembly comprising the ceramic heat sink of any one of claims 1-18 and a semiconductor device connected to the ceramic heat sink, the upper wiring layer comprising a first upper wiring layer and a second upper wiring layer simultaneously spaced apart on a first side of the ceramic substrate, the semiconductor device comprising oppositely disposed first and second poles, the first upper wiring layer being connected to the first pole of the semiconductor device, the second upper wiring layer being connected to the second pole of the semiconductor device by a lead.

20. The ceramic heat sink assembly of claim 19, comprising a plurality of ceramic heat sinks and a semiconductor device connected to the ceramic heat sinks, wherein two adjacent ceramic heat sinks are respectively connected with corresponding upper circuit layers through a plurality of leads.