CN117239005A - Preparation method of silicon wafer and silicon wafer - Google Patents
Preparation method of silicon wafer and silicon wafer Download PDFInfo
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- CN117239005A CN117239005A CN202210638875.9A CN202210638875A CN117239005A CN 117239005 A CN117239005 A CN 117239005A CN 202210638875 A CN202210638875 A CN 202210638875A CN 117239005 A CN117239005 A CN 117239005A
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 267
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 267
- 239000010703 silicon Substances 0.000 title claims abstract description 267
- 238000002360 preparation method Methods 0.000 title claims abstract description 20
- 238000000151 deposition Methods 0.000 claims abstract description 179
- 230000008021 deposition Effects 0.000 claims abstract description 166
- 239000002210 silicon-based material Substances 0.000 claims abstract description 161
- 239000000758 substrate Substances 0.000 claims abstract description 138
- 238000000034 method Methods 0.000 claims abstract description 40
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims abstract description 25
- 230000008018 melting Effects 0.000 claims abstract description 5
- 238000002844 melting Methods 0.000 claims abstract description 5
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 15
- 229910052796 boron Inorganic materials 0.000 claims description 15
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 11
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 10
- 229910052698 phosphorus Inorganic materials 0.000 claims description 10
- 239000011574 phosphorus Substances 0.000 claims description 10
- 238000011282 treatment Methods 0.000 claims description 10
- 238000004381 surface treatment Methods 0.000 claims description 9
- 238000004140 cleaning Methods 0.000 claims description 8
- 238000001035 drying Methods 0.000 claims description 8
- 238000004519 manufacturing process Methods 0.000 claims description 8
- 238000005498 polishing Methods 0.000 claims description 7
- 238000009499 grossing Methods 0.000 claims description 6
- 229910005191 Ga 2 O 3 Inorganic materials 0.000 claims description 3
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 3
- 229910052787 antimony Inorganic materials 0.000 claims description 3
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 claims description 3
- 229910052785 arsenic Inorganic materials 0.000 claims description 3
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 3
- 229910052733 gallium Inorganic materials 0.000 claims description 3
- 238000000227 grinding Methods 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 84
- 239000013078 crystal Substances 0.000 description 11
- 238000005520 cutting process Methods 0.000 description 10
- 238000005137 deposition process Methods 0.000 description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 238000005229 chemical vapour deposition Methods 0.000 description 6
- 238000010248 power generation Methods 0.000 description 6
- 239000012495 reaction gas Substances 0.000 description 6
- 235000012239 silicon dioxide Nutrition 0.000 description 6
- 229910003902 SiCl 4 Inorganic materials 0.000 description 5
- 239000010432 diamond Substances 0.000 description 5
- 229910003460 diamond Inorganic materials 0.000 description 5
- 239000010453 quartz Substances 0.000 description 4
- 229910021419 crystalline silicon Inorganic materials 0.000 description 3
- 239000003929 acidic solution Substances 0.000 description 2
- 239000012670 alkaline solution Substances 0.000 description 2
- 239000008367 deionised water Substances 0.000 description 2
- 229910021641 deionized water Inorganic materials 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- SLLGVCUQYRMELA-UHFFFAOYSA-N chlorosilicon Chemical compound Cl[Si] SLLGVCUQYRMELA-UHFFFAOYSA-N 0.000 description 1
- 239000002346 layers by function Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 238000010792 warming Methods 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
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- Crystals, And After-Treatments Of Crystals (AREA)
Abstract
The invention provides a preparation method of a silicon wafer, which comprises the following steps: melting the silicon material, and drawing a monocrystalline silicon rod by using a Czochralski method; slicing the monocrystalline silicon rod to prepare a silicon wafer substrate; and depositing silicon material on the surface of the silicon wafer substrate to form a silicon material deposition layer. Compared with the prior art, the silicon wafer preparation method can reduce the silicon material loss in the slicing link and the cost in the deposition link, thereby reducing the preparation cost of the silicon wafer.
Description
Technical Field
The invention relates to the field of photovoltaics, in particular to a silicon wafer preparation method and a silicon wafer obtained by adopting the silicon wafer preparation method.
Background
From the 90 s of the 20 th century, the world began to seek to reduce carbon emissions, thereby controlling the global warming. From then on, clean energy has received increasing attention from countries around the world. As an important component of clean energy, photovoltaic power generation has also been rapidly developed. The types of photovoltaic power generation include dye-sensitized solar cell power generation, thin film solar cell power generation, silicon solar cell power generation and the like, wherein the related products of the silicon solar cell can provide optimal power generation cost, and the market share of the related products is the largest correspondingly.
The silicon solar cell is formed by processing a silicon wafer through a certain process, and the cost of the silicon wafer influences the cost of the silicon solar cell to a great extent. The cost of the silicon wafer is reduced, and the cost of the silicon solar cell is correspondingly reduced. The current mainstream silicon wafer preparation process comprises: silicon material feeding, silicon material melting back pulling rod, and slicing the crystal bar to prepare the silicon wafer. At present, the thickness of the sliced silicon wafer is about 150-180 mu m, and about 40% of silicon materials are wasted in the slicing step of the crystal bar.
It has been proposed by researchers that crystalline silicon is used as a substrate, a silicon material with a thickness of 150 μm to 200 μm is formed on the crystalline silicon substrate by deposition, and the silicon material is peeled off from the substrate to form a silicon wafer, and the peeled crystalline silicon substrate is reused for about 10 times per wafer. The method can reduce the loss of silicon materials in the slice, but deposits silicon materials with the thickness of 150-200 mu m, and the deposition cost is higher.
In view of the foregoing, there is a need for an improved silicon wafer manufacturing method and a silicon wafer, which solve the above-mentioned problems.
Disclosure of Invention
The invention aims to provide a silicon wafer preparation method and a silicon wafer obtained by the silicon wafer preparation method, so as to reduce the silicon material loss in a slicing link, reduce the cost of a deposition link and reduce the cost of the silicon wafer.
In order to solve one of the technical problems, the invention adopts the following technical scheme:
a preparation method of a silicon wafer comprises the following steps:
melting the silicon material, and drawing a monocrystalline silicon rod by using a Czochralski method;
slicing the monocrystalline silicon rod to prepare a silicon wafer substrate;
and depositing silicon material on the surface of the silicon wafer substrate to form a silicon material deposition layer.
Further, the silicon material is a polycrystalline silicon material, and boron is doped to form a P-type monocrystalline silicon rod or phosphorus is doped to form an N-type monocrystalline silicon rod in the process of drawing the monocrystalline silicon rod.
Further, the silicon wafer substrate and the silicon material deposition layer form a silicon wafer, and the thickness of the silicon wafer substrate is 35% -99% of the thickness of the silicon wafer.
Further, the thickness of the silicon wafer substrate ranges from 30 mu m to 160 mu m; and/or the thickness range of the silicon material deposition layer is 0.1-100 μm.
Further, the silicon material deposition layer is an intrinsic silicon material deposition layer;
or the silicon material deposition layer comprises an intrinsic silicon material deposition layer and a doped silicon material deposition layer;
or the silicon material deposition layer is a doped silicon material deposition layer.
Further, the doped elements in the doped silicon material deposition layer are gallium, boron, phosphorus, arsenic and antimony;
or, when the doped silicon material deposition layer is deposited, the sources of doping elements are as follows: PH value 3 、PCl 3 、TMGa、Ga 2 O 3 、AsH 3 、AsCl 3 、SbCl 3 、BCl 3 、BBr 3 Or B 2 H 6 。
Further, the silicon wafer deposition and the silicon material deposition layer form a silicon wafer with a PN junction together.
Further, the silicon wafer substrate is a P-type doped silicon wafer, and an N-type silicon material deposition layer is formed on the silicon wafer substrate by deposition;
or the silicon wafer substrate is a P-type doped silicon wafer, firstly, a silicon material deposition layer which is doped with the same group doping element and has the same doping concentration as the silicon wafer substrate is formed on the silicon wafer substrate by first deposition, and then an N-type silicon material deposition layer is formed by second deposition;
the silicon wafer substrate is an N-type doped silicon wafer, and a P-type silicon material deposition layer is formed on the silicon wafer substrate by deposition;
or the silicon wafer substrate is an N-type doped silicon wafer, a silicon material deposition layer which is doped with the same group doping element and has the same doping concentration as the silicon wafer substrate is formed on the silicon wafer substrate through first deposition, and then a P-type silicon material deposition layer is formed through second deposition.
Further, the silicon wafer deposition and the silicon material deposition layer form a silicon wafer with a PP+ high-low junction together.
Further, the silicon wafer substrate is a P-type doped silicon wafer, and a P-type silicon layer which has the same family doping elements as the silicon wafer substrate and has higher doping concentration than the silicon wafer substrate is deposited on the silicon wafer substrate so as to form a PP+ high-low junction;
or the silicon wafer substrate is a P-type doped silicon wafer, firstly, a silicon material deposition layer which is doped with the same group doping element and has the same doping concentration as the silicon wafer substrate is formed on the silicon wafer substrate by first deposition, and then, a P-type silicon material deposition layer which is doped with the same group doping element and has the doping concentration higher than the silicon wafer substrate is formed by second deposition, so that a PP+ high-low junction is formed.
Further, the silicon wafer deposition and the silicon material deposition layer form a silicon wafer with NN+ high-low junction together.
Further, the silicon wafer substrate is an N-type doped silicon wafer, and an N-type silicon layer which has the same family doping elements as the silicon wafer substrate and has higher doping concentration than the silicon wafer substrate is deposited on the silicon wafer substrate so as to form NN+ high-low junctions;
or the silicon wafer substrate is an N-type doped silicon wafer, firstly, a silicon material deposition layer which is doped with the same group doping element and has the same doping concentration as the silicon wafer substrate is formed on the silicon wafer substrate by first deposition, and then, an N-type silicon material deposition layer which is doped with the same group doping element as the silicon wafer substrate and has the doping concentration higher than that of the silicon wafer substrate is formed by second deposition, so that NN+ high-low junctions are formed.
Further, the method further comprises the step of carrying out surface treatment on the silicon wafer substrate before the silicon material deposition layer is deposited, wherein the surface treatment comprises smoothing treatment, cleaning and drying, and the smoothing treatment comprises grinding and/or polishing; or, the surface treatment includes cleaning and drying.
A silicon wafer is obtained by the preparation method of the silicon wafer.
The beneficial effects of the invention are as follows: compared with the prior art, the silicon wafer preparation method can reduce the silicon material loss in the slicing link and the cost in the deposition link, thereby reducing the preparation cost of the silicon wafer.
Drawings
FIG. 1 is a flow chart of a method for fabricating a silicon wafer in accordance with one embodiment of the present invention;
FIG. 2 is a flow chart of a method for fabricating a silicon wafer in accordance with another embodiment of the present invention;
FIG. 3 is a flow chart of a method for fabricating a silicon wafer in accordance with another embodiment of the present invention;
FIG. 4 is a flow chart of a method for fabricating a silicon wafer in accordance with another embodiment of the present invention;
FIG. 5 is a flow chart of a method for fabricating a silicon wafer in accordance with another embodiment of the present invention;
FIG. 6 is a flow chart of a method of fabricating a silicon wafer in accordance with another embodiment of the present invention;
FIG. 7 is a flow chart of a method of fabricating a silicon wafer in accordance with another embodiment of the present invention;
FIG. 8 is a flow chart of a method for fabricating a silicon wafer in accordance with another embodiment of the present invention;
FIG. 9 is a flow chart of a method of fabricating a silicon wafer in accordance with another embodiment of the present invention;
FIG. 10 is a flow chart of a method of fabricating a silicon wafer in another embodiment of the invention.
Detailed Description
The present invention will be described in detail below with reference to specific embodiments shown in the drawings. These embodiments are not intended to limit the invention and structural, methodological, or functional modifications of these embodiments that may be made by one of ordinary skill in the art are included within the scope of the invention.
Please refer to fig. 1-10, which illustrate a preferred embodiment of the present invention. The invention provides a silicon wafer preparation method, which comprises the following steps:
melting a silicon material in a single crystal pulling furnace, and pulling a single crystal silicon rod by using a Czochralski method;
slicing the monocrystalline silicon rod to prepare a silicon wafer substrate;
and depositing silicon material on the surface of the silicon wafer substrate to form a silicon material deposition layer.
In the preparation method of the silicon wafer, after the silicon material is deposited, the deposited silicon material deposition layer does not need to be peeled off from the silicon wafer substrate, and the silicon wafer substrate and the silicon material deposition layer are used together as an integrated silicon wafer. The waste of the substrate can be reduced, the silicon material loss in the slicing step can be reduced, the silicon wafer substrate bears a part of the thickness of the silicon wafer, and the cost of depositing the silicon material step is reduced, so that the preparation cost of the silicon wafer is reduced.
Wherein the silicon material is usually polysilicon material. Doping is carried out in the process of preparing the monocrystalline silicon rod, for example, boron is doped to obtain a P-type monocrystalline silicon rod, or phosphorus is doped to obtain an N-type monocrystalline silicon rod; the doping concentration is 1 multiplied by 10 16 cm -3 。
The slicing process adopts diamond wire cutting, and the specific slicing process can be omitted by referring to the prior art.
The inventor further researches and discovers that the larger the thickness of the silicon wafer substrate is used as a basic support of the whole silicon wafer, the smaller the damage rate in the subsequent process is, and the thickness of the deposited silicon material is relatively thinner, so that the cost of a silicon material depositing link can be further reduced. As a further improvement of the present invention, the thickness of the silicon wafer substrate formed by dicing is 35% to 99%, preferably 50% to 70%, preferably 60% of the thickness of the silicon wafer. For example, the thickness of the silicon wafer substrate ranges from 30 μm to 160 μm, preferably from 80 μm to 120 μm; preferably 100 μm.
The silicon material deposition layer deposited on the silicon wafer substrate can improve the performance of the silicon wafer substrate, is used as a functional base layer for manufacturing the solar cell, has the thickness ranging from 0.1 mu m to 100 mu m, cannot ensure the deposition uniformity and quality of the silicon material deposition layer, increases the deposition cost due to too much thickness, increases the thickness of the silicon wafer to a certain extent and prolongs the transmission distance of carriers. Preferably, the thickness of the silicon material deposition layer ranges from 45 μm to 85 μm; preferably 65 μm.
In the present invention, the thickness of the silicon wafer composed of the silicon wafer substrate and the silicon material deposition layer is 150 μm to 170 μm, preferably about 160 μm.
The deposition process adopts a vapor deposition mode, and a deposited silicon material deposition layer can be selected according to the requirements of the formed solar cell, can be used as a 'functional layer' for forming the solar cell, and can be doped in the deposition process if necessary. The silicon deposit layer includes but is not limited to the following:
in one embodiment, the silicon material during the deposition process is intrinsic silicon material, i.e., the silicon material deposition layer is an intrinsic silicon material deposition layer.
In another embodiment, the silicon material in the deposition process is intrinsic silicon material and partially doped silicon material, i.e. the silicon material deposition layer comprises a partially intrinsic silicon material deposition layer and a partially doped silicon material deposition layer. Preferably, the intrinsic silicon material deposition layer is close to the silicon wafer substrate, and the doped silicon material deposition layer is far away from the silicon wafer substrate.
In another embodiment, the silicon material during the deposition process is doped silicon material, i.e., the silicon material deposition layer is a doped silicon material deposition layer.
The silicon source used in the deposition process may be: siH (SiH) 4 、SiH 2 Cl 2 、SiHCl 3 And SiCl 4 The method comprises the steps of carrying out a first treatment on the surface of the The doped elements in the doped silicon material deposition layer are gallium, boron, phosphorus, arsenic, antimony and the like. The sources of doping elements are: PH value 3 、PCl 3 、TMGa、Ga 2 O 3 、AsH 3 、AsCl 3 、SbCl 3 、BCl 3 、BBr 3 And B 2 H 6 Etc.
As a further improvement of the present invention, referring to fig. 3 to 6, a PN junction may be formed by depositing a silicon material, that is, the silicon wafer substrate and the silicon material deposition layer together form a silicon wafer having a PN junction. And the PN junction is formed between the silicon wafer substrate and the silicon material deposition layer, or the PN junction is formed in the silicon material deposition layer.
Referring to fig. 3, if the silicon substrate is a P-type doped silicon wafer, an N-type silicon material deposition layer with a certain thickness and doping concentration can be deposited on the silicon substrate to form a PN junction. Or, referring to fig. 4, if the silicon wafer substrate is a P-type doped silicon wafer, a first deposition is performed to form a silicon material with a certain thickness and the same doping concentration as the silicon wafer substrate doped with the same doping element in the same group to form a buffer layer, and then a second deposition is performed to form an N-type silicon material deposition layer with a certain thickness and doping concentration to form a PN junction; in the method, the deposited silicon material deposition layer has strong bonding force with the silicon wafer substrate.
Referring to fig. 5, the silicon substrate is an N-doped silicon wafer, and a P-type silicon material deposition layer with a certain thickness and doping concentration can be deposited on the silicon substrate to form a PN junction. Or, referring to fig. 6, if the silicon wafer substrate is an N-doped silicon wafer, a first deposition may be performed to form a silicon material deposition layer with a certain thickness and the same doping concentration as the silicon wafer substrate, as a buffer layer; and then performing secondary deposition to form a P-type silicon material deposition layer with certain thickness and doping concentration so as to form a PN junction.
As a further improvement of the present invention, referring to fig. 7 and 8, pp+ high-low junction may be formed by depositing silicon material, that is, the silicon wafer substrate and the silicon material deposition layer together form a silicon wafer having pp+ high-low junction. Referring to fig. 7, the silicon substrate is a P-doped silicon wafer, and a P-type silicon material deposition layer with a certain thickness, same group doping elements and higher doping concentration than the silicon substrate is deposited on the silicon substrate to form a pp+ high-low junction. Or, referring to fig. 8, if the silicon wafer substrate is a P-type doped silicon wafer, a first deposition is performed on the silicon wafer substrate to form a silicon material deposition layer with a certain thickness and the same group doping element and the same doping concentration as the substrate, and then a second deposition is performed to form a P-type silicon material deposition layer with a certain thickness and the same group doping element and the doping concentration higher than the substrate, so as to form a pp+ high-low junction. In one embodiment, the doping elements of the silicon material deposition layer are the same as the doping elements of the silicon wafer substrate.
As a further improvement of the present invention, please refer to fig. 9 and 10, nn+ high-low junction may be formed by depositing silicon material, that is, the silicon wafer substrate and the silicon material deposition layer together form a silicon wafer having nn+ high-low junction. Referring to fig. 9, the silicon substrate is an N-doped silicon wafer, and an n+ silicon material deposition layer having a thickness of the same group doping element and a doping concentration higher than that of the silicon substrate is deposited on the silicon substrate to form an nn+ junction. Or, referring to fig. 10, if the silicon substrate is an N-doped silicon wafer, a first deposition is performed on the silicon substrate to form a silicon material deposition layer with a certain thickness and the same group doping element and the same doping concentration as those of the silicon substrate, and then a second deposition is performed to form an n+ silicon material deposition layer with a certain thickness and the same group doping element and the doping concentration higher than those of the silicon substrate, so as to form an nn+ junction. In one embodiment, the doping elements of the silicon material deposition layer are the same as the doping elements of the silicon wafer substrate.
In the above deposition process, the thickness of the silicon material deposition layer formed by the second deposition and the thickness of the silicon material deposition layer formed by the first deposition can be adjusted according to the needs. For example, the thickness of the silicon material deposited layer formed by the second deposition is smaller than that of the silicon material deposited layer formed by the first deposition. Specifically, the thickness of the silicon material deposition layer formed by the second deposition is less than 1% of the thickness of the silicon material deposition layer formed by the second deposition, and is preferably 0.5% -0.8%. In one embodiment, the first deposition is 65 μm thick and the second deposition is 0.5 μm thick.
When forming the PN junction, the PP+ high-low junction and the NN+ high-low junction, the silicon source and the doping element source adopted in the deposition process are the same as those described above, and the description is omitted.
Further, as shown in fig. 2, in order to improve the performance of the silicon wafer, the surface of the silicon wafer substrate may be subjected to a surface treatment before the silicon material deposition layer is deposited, where the surface treatment includes a smoothing treatment, a cleaning treatment and a drying treatment, and the smoothing treatment includes a grinding and/or polishing treatment. Or, the surface treatment may include only cleaning and drying.
It should be noted that the second deposition in the present invention is not necessary, and a PN junction or a high-low junction is not necessarily formed during the deposition.
The method for producing a silicon wafer according to the present invention and the silicon wafer obtained by the corresponding method will be described in detail below by means of several specific examples.
Example 1:
the first step: the silicon material is a polycrystalline silicon material, the polycrystalline silicon material is melted in a single crystal furnace, a P-type single crystal silicon rod is manufactured by pulling a single crystal straight, the doping element is boron, and the doping concentration is 1 multiplied by 10 16 cm -3 。
And a second step of: and cutting the P-type monocrystalline silicon rod into a plurality of silicon wafer substrates with the thickness of 100 mu m by adopting diamond wire cutting.
And a third step of: placing the silicon wafer substrate in a quartz tube, and using SiCl 4 To deposit a silicon source with H 2 To assist the reaction gas, BCl is used 3 Is a doping source. Depositing a boron doped silicon material deposition layer with the thickness of 65 mu m on the surface of the silicon wafer substrate by adopting a chemical vapor deposition mode, wherein the doping concentration is 1 multiplied by 10 16 cm -3 . Deposition temperature is 1300 ℃, siCl 4 The concentration is 0.1%, and the deposition speed is 1-2 μm/min.
The silicon wafer obtained in the embodiment is a P-type silicon wafer, and has no PN junction.
Example 2:
the first step: the silicon material is a polycrystalline silicon material, the polycrystalline silicon material is melted in a single crystal furnace, a P-type single crystal silicon rod is manufactured by pulling a single crystal straight, the doping element is boron, and the doping concentration is 1 multiplied by 10 16 cm -3 。
And a second step of: and cutting the P-type monocrystalline silicon rod into a plurality of silicon wafer substrates with the thickness of 100 mu m by adopting diamond wire cutting.
And a third step of: placing a silicon wafer substrate in a quartz tube, and using SiCl 4 To deposit a silicon source with H 2 To assist the reaction gas, B 2 H 6 Is a doping source. And depositing a boron doped silicon material deposition layer with the thickness of 65 mu m on the surface of the silicon wafer substrate by adopting a chemical vapor deposition mode. Deposition temperature is 1300 ℃, siCl 4 The concentration is 0.1%, and the deposition speed is 1-2 μm/min. This stepThe boron doping concentration of the silicon material deposition layer deposited in the step is the same as that of the silicon wafer substrate.
Fourth step: on the basis of the third step, siCl 4 To deposit a silicon source with H 2 To assist the reaction gas, PCl is used 3 As doping source, adopting chemical vapor deposition to continuously deposit phosphorus doped silicon material deposition layer with thickness of 0.5 μm and phosphorus doping concentration of 1×10 20 cm -3 ～8×10 20 cm -3 。
The silicon wafer obtained in this example has a PN junction.
Example 3:
the first step: the silicon material is a polycrystalline silicon material, the polycrystalline silicon material is melted in a single crystal furnace, a P-type single crystal silicon rod is manufactured by pulling a single crystal straight, the doping element is boron, and the doping concentration is 1 multiplied by 10 16 cm -3 。
And a second step of: and cutting the P-type monocrystalline silicon rod into a plurality of silicon wafer substrates with the thickness of 100 mu m by adopting diamond wire cutting.
And a third step of: and polishing the silicon wafer substrate by adopting silicon dioxide polishing solution.
Fourth step: and cleaning the polished silicon wafer substrate by adopting an alkaline solution, an acidic solution and deionized water.
Fifth step: and drying the silicon wafer substrate by adopting hot air.
Sixth step: placing a silicon wafer substrate in a quartz tube, and using SiCl 4 To deposit a silicon source with H 2 To assist the reaction gas, BCl is used 3 Is a doping source. Depositing a boron doped silicon material deposition layer with the thickness of 65 mu m on the surface of the silicon wafer substrate by adopting a chemical vapor deposition mode, wherein the doping concentration is 1 multiplied by 10 16 cm -3 . Deposition temperature is 1300 ℃, siCl 4 The concentration is 0.1%, and the deposition speed is 1-2 μm/min.
The silicon wafer obtained in the embodiment is a P-type silicon wafer, and has no PN junction.
Example 4:
the first step: the silicon material is a polycrystalline silicon material, the polycrystalline silicon material is melted in a single crystal furnace, a P-type single crystal silicon rod is manufactured by pulling up single crystals, the doping element is boron,the doping concentration is 1 multiplied by 10 16 cm -3 。
And a second step of: and cutting the P-type monocrystalline silicon rod into a plurality of silicon wafer substrates with the thickness of 100 mu m by adopting diamond wire cutting.
And a third step of: and polishing the silicon wafer substrate by adopting silicon dioxide polishing solution.
Fourth step: and cleaning the polished silicon wafer substrate by adopting an alkaline solution, an acidic solution and deionized water.
Fifth step: and drying the silicon wafer substrate by adopting hot air.
Sixth step: placing a silicon wafer substrate in a quartz tube, and using SiCl 4 To deposit a silicon source with H 2 To assist the reaction gas, BCl is used 3 Is a doping source. And depositing a boron doped silicon material deposition layer with the thickness of 65 mu m on the surface of the silicon wafer substrate by adopting a chemical vapor deposition mode. Deposition temperature is 1300 ℃, siCl 4 The concentration is 0.1%, and the deposition speed is 1-2 μm/min.
Seventh step: on the basis of the sixth step, siCl 4 To deposit a silicon source with H 2 To assist the reaction gas, PCl is used 3 As doping source, adopting chemical vapor deposition to continuously deposit phosphorus doped silicon material deposition layer with thickness of 0.5 μm and phosphorus doping concentration of 1×10 20 cm -3 ～8×10 20 cm -3 。
The silicon wafer obtained in this example has a PN junction, and the PN junction is located in the silicon material deposition layer.
Compared with the silicon material deposition thickness of 130 μm in the comparison method, the preparation method of the silicon wafer has the following advantages: the deposition thickness of the silicon material is not more than 100 mu m, so that the deposition thickness of the silicon material is reduced, and the cost of the deposition process is reduced; the process of stripping the silicon material from the silicon wafer substrate after deposition is reduced, and the negative influence of the process on the quality of the silicon wafer is avoided; the repeated use of the silicon wafer substrate is eliminated, and the influence of the repeated use of the substrate on the quality of the silicon wafer is avoided. Compared with the traditional slicing process of the silicon slice with the thickness of more than 150 mu m, the slicing thickness in the preparation method of the silicon slice is 30 mu m-160 mu m, and the cutting loss of silicon materials in the slicing process is reduced.
It should be understood that although the present disclosure describes embodiments, not every embodiment is provided with a separate embodiment, and that this description is for clarity only, and that the skilled artisan should recognize that the embodiments may be combined as appropriate to form other embodiments that will be understood by those skilled in the art.
The above list of detailed descriptions is only specific to practical embodiments of the present invention, and they are not intended to limit the scope of the present invention, and all equivalent embodiments or modifications that do not depart from the spirit of the present invention should be included in the scope of the present invention.
Claims (14)
1. The preparation method of the silicon wafer is characterized by comprising the following steps:
melting the silicon material, and drawing a monocrystalline silicon rod by using a Czochralski method;
slicing the monocrystalline silicon rod to prepare a silicon wafer substrate;
and depositing silicon material on the surface of the silicon wafer substrate to form a silicon material deposition layer.
2. The method for preparing a silicon wafer according to claim 1, wherein: the silicon material is a polycrystalline silicon material, and boron is doped to form a P-type monocrystalline silicon rod or phosphorus is doped to form an N-type monocrystalline silicon rod in the process of drawing the monocrystalline silicon rod.
3. The method for preparing a silicon wafer according to claim 1, wherein: the silicon wafer substrate and the silicon material deposition layer form a silicon wafer, and the thickness of the silicon wafer substrate is 35% -99% of the thickness of the silicon wafer.
4. A method of producing a silicon wafer according to claim 1 or 3, characterized in that: the thickness range of the silicon wafer substrate is 30-160 mu m; and/or the thickness range of the silicon material deposition layer is 0.1-100 μm.
5. The method for preparing a silicon wafer according to claim 1, wherein: the silicon material deposition layer is an intrinsic silicon material deposition layer;
or the silicon material deposition layer comprises an intrinsic silicon material deposition layer and a doped silicon material deposition layer;
or the silicon material deposition layer is a doped silicon material deposition layer.
6. The method for preparing a silicon wafer according to claim 5, wherein: the doped elements in the doped silicon material deposition layer are gallium, boron, phosphorus, arsenic and antimony;
or, when the doped silicon material deposition layer is deposited, the sources of doping elements are as follows: PH value 3 、PCl 3 、TMGa、Ga 2 O 3 、AsH 3 、AsCl 3 、SbCl 3 、BCl 3 、BBr 3 Or B 2 H 6 。
7. The method for preparing a silicon wafer according to claim 1, wherein: and the silicon wafer deposition and the silicon material deposition layer jointly form a silicon wafer with a PN junction.
8. The method for preparing a silicon wafer according to claim 7, wherein: the silicon wafer substrate is a P-type doped silicon wafer, and an N-type silicon material deposition layer is formed on the silicon wafer substrate by deposition;
or the silicon wafer substrate is a P-type doped silicon wafer, firstly, a silicon material deposition layer which is doped with the same group doping element and has the same doping concentration as the silicon wafer substrate is formed on the silicon wafer substrate by first deposition, and then an N-type silicon material deposition layer is formed by second deposition;
the silicon wafer substrate is an N-type doped silicon wafer, and a P-type silicon material deposition layer is formed on the silicon wafer substrate by deposition;
or the silicon wafer substrate is an N-type doped silicon wafer, a silicon material deposition layer which is doped with the same group doping element and has the same doping concentration as the silicon wafer substrate is formed on the silicon wafer substrate through first deposition, and then a P-type silicon material deposition layer is formed through second deposition.
9. The method for preparing a silicon wafer according to claim 1, wherein: and the silicon wafer deposition layer and the silicon material deposition layer jointly form a silicon wafer with a PP+ high-low junction.
10. The method for preparing a silicon wafer according to claim 9, wherein: the silicon wafer substrate is a P-type doped silicon wafer, and a P-type silicon layer which has the same family doping elements as the silicon wafer substrate and has higher doping concentration than the silicon wafer substrate is deposited on the silicon wafer substrate so as to form a PP+ high-low junction;
or the silicon wafer substrate is a P-type doped silicon wafer, firstly, a silicon material deposition layer which is doped with the same group doping element and has the same doping concentration as the silicon wafer substrate is formed on the silicon wafer substrate by first deposition, and then, a P-type silicon material deposition layer which is doped with the same group doping element and has the doping concentration higher than the silicon wafer substrate is formed by second deposition, so that a PP+ high-low junction is formed.
11. The method for preparing a silicon wafer according to claim 1, wherein: and the silicon wafer deposition layer and the silicon material deposition layer jointly form a silicon wafer with NN+ high-low junction.
12. The method for preparing a silicon wafer according to claim 11, wherein: the silicon wafer substrate is an N-type doped silicon wafer, and an N-type silicon layer which has the same family doping elements as the silicon wafer substrate and has higher doping concentration than the silicon wafer substrate is deposited on the silicon wafer substrate so as to form an NN+ high-low junction;
or the silicon wafer substrate is an N-type doped silicon wafer, firstly, a silicon material deposition layer which is doped with the same group doping element and has the same doping concentration as the silicon wafer substrate is formed on the silicon wafer substrate by first deposition, and then, an N-type silicon material deposition layer which is doped with the same group doping element as the silicon wafer substrate and has the doping concentration higher than that of the silicon wafer substrate is formed by second deposition, so that NN+ high-low junctions are formed.
13. The method for preparing a silicon wafer according to claim 1, wherein: the method further comprises the steps of carrying out surface treatment on the silicon wafer substrate before the silicon material deposition layer is deposited, wherein the surface treatment comprises smoothing treatment, cleaning and drying, and the smoothing treatment comprises grinding and/or polishing; or, the surface treatment includes cleaning and drying.
14. A silicon wafer obtained by the method for producing a silicon wafer according to any one of claims 1 to 13.
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