KR20110059366A - Single crystalline semiconductor substrate having isolation region, solar cell using the same and manufacturing method thereof - Google Patents

Abstract

PURPOSE: A single crystal semiconductor substrate with a separation region, a solar cell using the same, and a manufacturing method thereof are provided to prevent the recombination of electrons by preventing a short between a top electrode and a bottom electrode. CONSTITUTION: A semiconductor substrate includes a p type substrate area(110) and a p+ type separation area(120). The p+ type separation area is formed on the edge of the substrate area. The substrate area and the separation area are single crystal silicon.

Description

SINGLE CRYSTALLINE SEMICONDUCTOR SUBSTRATE HAVING ISOLATION REGION, SOLAR CELL USING THE SAME AND MANUFACTURING METHOD THEREOF}

The present invention relates to a single crystal semiconductor substrate having a separation region, a solar cell using the same, and a method of manufacturing the same. More specifically, a single crystal semiconductor substrate having a separation region formed at an edge by doping ingots and other conductive impurities on the surface of the single crystal ingot, and a solar cell which does not require an edge isolation process using the same. It relates to a manufacturing method.

In recent years, research on information technology and green technology has been actively conducted. The semiconductor manufacturing process technology is a core technology used in various fields such as memory, non-memory, flat panel display (FPD), and solar cell.

In particular, the depletion of existing fossil energy resources such as petroleum and coal is predicted, and as the interest on the environment increases, technology for solar cells, which are alternative energy that can solve this problem, is drawing attention. Such solar cells include solar cells that use steam to generate steam for rotating turbines, and solar cells that convert photons into electrical energy using the properties of semiconductors. It means a solar cell (hereinafter referred to as a "solar cell").

In this way, solar cells that can receive light and convert them into electrical energy are broadly divided into substrate type (bulk type) (single crystalline, poly crystalline) solar cells, thin film type (amorphous, polycrystalline). (poly crystalline)] may include a solar cell, a compound thin film solar cell such as CdTe or CIS (CuInSe ₂ ), group III-V solar cell, dye-sensitized solar cell and organic solar cell. In this case, the single crystal solar cell uses a wafer, which is a circular plate obtained by thinly cutting a single crystal semiconductor ingot grown in a cylindrical shape as a substrate.

1 to 5 are cross-sectional views showing a manufacturing process of a conventional single crystal solar cell.

First, referring to FIG. 1, a substrate 10, which is a circular wafer manufactured by cutting a p-type silicon single crystal ingot (not shown) to which boron is added, is prepared.

Next, referring to FIG. 2, n-type impurities may be implanted into the substrate 10 to dope the surface of the substrate 10 to n-type. For example, the surface portion of the substrate 10 is n-type region (n-type semiconductor) by injecting phosphorus, which is an n-type impurity of Group 5, into the substrate 10 formed of the p-type region 11 by doping impurities. Layer: 12) can be formed to obtain a pn junction structure.

Next, referring to FIG. 3, edge isolation may be performed to remove a portion 20 of the edge portion of the n-type semiconductor layer 12 formed in the upper region of the substrate 10. Usually, the edge separation process can be performed by irradiating a laser.

Next, referring to FIG. 4, the upper electrode 30 may be formed of silver (Ag) on the substrate 10 and more specifically on the n-type semiconductor layer 12. Subsequently, the lower electrode 40 may be formed on the lower surface of the substrate 10, in more detail, on the lower surface of the n-type semiconductor layer 12 from aluminum (Al).

Next, referring to FIG. 5, by heating the substrate 10, aluminum (Al) of the lower electrode 40 is diffused into the n-type semiconductor layer 12 formed on the bottom surface of the substrate 10 to form an n-type semiconductor layer ( 12) can be changed to the p + type semiconductor layer 13. As a result, it is possible to implement a single crystal solar cell in which p + type, p type, and n type semiconductor layers are stacked.

On the other hand, when the portion 20 of the n-type semiconductor layer 12 surrounding the p-type region 11 formed in FIG. 2 is not removed through the laser edge separation process as described above, the upper electrode 30 and the lower portion The electrode 40 is short circuited and the solar cell cannot operate normally. Therefore, the laser edge separation process is a necessary step in the manufacturing process of the single crystal solar cell using the silicon single crystal wafer.

However, when the laser edge separation process is performed, the manufacturing process of the solar cell becomes complicated and the manufacturing cost increases. In particular, since the edge separation process by the laser takes a lot of time, the productivity of the solar cell is reduced.

Accordingly, an object of the present invention is to provide a single crystal semiconductor substrate having a separation region formed on the substrate itself, and a method of manufacturing the same.

Another object of the present invention is to provide a solar cell and a method of manufacturing the same, which do not require an edge isolation process by using a single crystal semiconductor substrate having an isolation region formed on the substrate itself.

In addition, another object of the present invention is to provide a solar cell and a method of manufacturing the same, which have a simple manufacturing process, low manufacturing cost, and improved productivity.

Representative configuration of the present invention for achieving the above object is as follows.

The object of the present invention is to provide a substrate region having a predetermined conductivity type; And a separation region formed at an edge portion of the substrate region, the separation region being the same as the conductive type but having a high concentration.

In this case, the substrate region and the isolation region may be single crystal silicon.

The substrate region and the isolation region may be p type and p + type.

The substrate region and the isolation region may be n type or n + type.

In addition, the object of the present invention (a) providing an ingot; (b) forming a separation region at the edge of the ingot that is the same as the conductivity type at the center of the ingot but has a high concentration; And (c) slicing said ingot into a semiconductor substrate.

In this case, the ingot may be single crystal silicon.

Step (b) comprises the steps of: forming a coating film on the surface of the ingot containing impurities of the same conductivity type as the ingot; Heat-treating the ingot; And it may include the step of removing the coating film.

The step (b) may include the step of surface treating the ingot with a predetermined gas.

If the ingot is p-type, the coating film may include a Group 3 material. If the ingot is n-type, the coating film may include a Group 5 material.

If the ingot is p-type, the gas may include a Group 3 material. If the ingot is n-type, the gas may include a Group 5 material.

The step (a) comprises the steps of growing the ingot into a single crystal; Blocking the ingot; And planarizing the ingot.

The blocking step may include at least one of a cropping process or a squaring process.

The planarization step may include any one or more of an etching process and a grinding process.

In addition, the object of the present invention is to form a substrate region formed by stacking first, second, and third semiconductor layers in order, and formed at an edge of the substrate region, and having the same or intrinsic conductivity as the second semiconductor layer. a single crystal semiconductor substrate comprising an isolation region of type i); An insulating layer formed on the third semiconductor layer; An upper electrode formed on the insulating layer and in contact with the third semiconductor layer through the insulating layer; And it is also achieved by a solar cell comprising a lower electrode formed under the first semiconductor layer.

In this case, the single crystal semiconductor substrate may be single crystal silicon.

The first, second, and third semiconductor layers may be p + type, p type, n type.

The first, second, and third semiconductor layers may be n + type, n type, or p type.

The conductivity type of the first semiconductor layer may be determined according to the lower electrode.

The single crystal semiconductor substrate may have a roughness.

The object of the present invention is to provide a single crystal semiconductor substrate comprising (a) a substrate region having a predetermined conductivity type and an isolation region formed at an edge portion of the substrate region, the separation region being the same as the conductivity type but having a high concentration. ; And (b) doping an impurity of a conductivity type different from that of the substrate region to the surface of the substrate to form the substrate region as first, second, and third semiconductor layers stacked in order, and forming the separation region in the second region. Changing the conductivity type to the same or intrinsic (i-type) conductivity type of the semiconductor layer, wherein the conductivity type of the first and third semiconductor layers is the same as the impurity and the conductivity type of the second semiconductor layer is the substrate region. It is also achieved by a method for manufacturing a solar cell, characterized in that the same as.

At this time, (c) forming an insulating layer on the third semiconductor layer; (d) forming an upper electrode on the insulating layer; (e) forming a lower electrode under the first semiconductor layer; (f) heat treating the substrate to contact the upper electrode and the third semiconductor layer, and changing the conductivity of the first semiconductor layer.

According to the present invention, it is possible to collectively form the separation region during the ingot production process, and has the effect of obtaining a large amount of the single crystal semiconductor substrate having the separation region formed therein.

In addition, according to the present invention, since the isolation region is formed on the single crystal semiconductor substrate itself, it is possible to easily implement the solar cell without a separate edge isolation process.

In addition, according to the present invention, there is an effect that can solve the problem that the electron recombination path is formed by preventing the upper electrode and the lower electrode from being electrically shorted by using the separation region of the single crystal semiconductor substrate during solar cell manufacturing.

In addition, according to the present invention, the manufacturing process is simple, the manufacturing cost is low, and has the effect of providing a solar cell and a method of manufacturing the improved productivity.

DETAILED DESCRIPTION The following detailed description of the invention refers to the accompanying drawings that show, by way of illustration, specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. It should be understood that the various embodiments of the present invention are different but need not be mutually exclusive. For example, certain shapes, structures, and characteristics described herein may be embodied in other embodiments without departing from the spirit and scope of the invention with respect to one embodiment. It is also to be understood that the position or arrangement of the individual components within each disclosed embodiment may be varied without departing from the spirit and scope of the invention. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present invention, if properly described, is defined only by the appended claims, along with the full range of equivalents to which such claims are entitled. In the drawings, like reference numerals refer to the same or similar functions throughout the several aspects, and length, area, thickness, and the like may be exaggerated for convenience.

DETAILED DESCRIPTION Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the present invention.

[Preferred Embodiments of the Invention]

In the present specification, the single crystal semiconductor substrate in which the isolation region is formed means that the center portion (substrate region) and the edge portion (separation region) of the substrate, which are single crystal wafers, have the same conductivity type as each other, but the edge portion has a higher concentration than the center portion. do. In the following detailed description, for convenience of description, a single crystal semiconductor substrate having a separation region is a substrate sliced by doping p-type impurities (group III impurities) at the edges of the p-type ingot. Although the case of the p + type is described as an example, the single crystal semiconductor substrate in which the isolation region is formed according to the present invention has a different conductivity type (for example, the case where the center portion is n type and the edge portion is n + type using group 5 impurities). It should be understood to mean all inclusively.

In addition, in this specification, the single crystal semiconductor substrate having the isolation region will be described based on the most widely used silicon (Si), but other well-known materials such as germanium (Ge) and gallium arsenide (GaAs) are all comprehensively understood. It should be understood to do.

In addition, in the following detailed description, the solar cell is formed on the single crystal semiconductor substrate in which the isolation region is formed, for example. However, the single crystal semiconductor substrate in which the isolation region of the present invention is formed is generally used in the semiconductor technology field using the single crystal semiconductor substrate. It will be obvious that the same applies.

In addition, in the following detailed description, the meaning of + indicates a relative difference in the doping concentration of impurities, which means that the + has a higher concentration of doping concentration than the case of − or no indication.

Single Crystal Semiconductor Substrate with Isolation Regions

6 is a flowchart illustrating a manufacturing process of a single crystal semiconductor substrate having an isolation region according to an embodiment of the present invention.

7 to 11 are views showing in detail the process according to Figure 6 of the present invention.

Referring to FIG. 6, first, a raw material (for example, polycrystalline silicon) may be dissolved to grow a single ingot (IG) (S10). The ingot IG may be a known method such as a melt zone (FZ) method without limitation, but for example, a Czochralski (CZ) method that can easily grow a large diameter ingot is used. Can be.

In more detail, referring to FIG. 7, a raw material containing polycrystalline silicon may be put into a crucible and heated. For example, when growing ingot IG, boron may be added to grow a p-type single crystal silicon ingot.

Subsequently, a single crystal seed having the same crystal direction as the target crystal direction can be brought into contact with the surface center portion of the polycrystalline silicon melt.

Subsequently, the single crystal seed may be slowly moved upward to grow the silicon single crystal ingot IG. In this case, the single crystal seed and the crucible may be rotated in opposite directions. When the single crystal seed is pulled upwards of the polycrystalline silicon melt, surface tension is generated between the single crystal seed and the polycrystalline silicon melt surface so that the silicon single crystal ingot IG may grow while thin silicon films are formed and cooled. At this time, the silicon atoms in the polycrystalline silicon melt may be grown to the silicon single crystal ingot IG while having the same crystal orientation as the single crystal seed.

Referring back to FIG. 6, the ingot IG may be processed into a cylindrical shape through a blocking process of removing unnecessary portions such as upper and lower portions of the grown ingot IG (S20).

More specifically, referring to FIG. 8, the ingot IG grown through the Czochralski method as shown in FIG. 7 may have a pillar shape in which upper and lower portions protrude. Therefore, a cropping process may be performed to cut the protrusions to form one or a plurality of blocks (cylindrical single crystal silicon ingots).

In addition, in the blocking step (S20) according to an embodiment of the present invention, a squaring process of processing the outer circumferential surface of the ingot 100 into a square shape may be performed. Of course, the cropping process and the squaring process may be omitted as necessary.

Referring back to FIG. 6, a planarization process may be performed to planarize the surface of the blocked ingot IG (S30).

More specifically, referring to FIG. 9, an etching process of chemically polishing the surface of the ingot IG blocked as shown in FIG. 8 may be performed. This etching process can be performed using a wet method that can be easily processed in large quantities. In this case, the etching solution may be, for example, an alkali system including KOH or NaOH, but is not limited thereto, and a known etching solution including an acid system such as HNO ₃ may be used without limitation.

In addition, in the planarization process (S30) according to an embodiment of the present invention, it may be performed by using a grinding (grinding) method to physically polish the surface of the blocked ingot (IG). Such a grinding method may remove, but is not limited to, the surface roughness of the ingot IG blocked by the grinding wheel using a rotational force. For example, a known grinding method used in semiconductor wafer processing may be used without limitation.

Through the planarization process S30, various damages of the ingot IG, which are inevitably obtained in the blocking process S20 performed in the previous step, can be easily removed chemically and / or physically.

Referring back to FIG. 6, impurities of the same conductivity type as the ingot IG are implanted into the edges of the planarized ingot IG so that the center portion and the conductivity type of the ingot IG are the same but have a higher concentration. ) May be formed (S40).

More specifically, referring to FIG. 10A, a coating film C may be formed on the surface of the flattened ingot IG as shown in FIG. 9. For example, in the case of the p-type ingot (IG), the coating film (C) may be aluminum (Al), but is not limited thereto. Any material containing the same Group 3 material may be used without limitation. For example, borosilicate glass (BSG), aluminosilicate glass (Aluminosilicate Glass), etc., which is a compound containing alumina (Al ₂ O ₃ ) and silica (SiO ₂ ), may be used.

Subsequently, referring to FIG. 10B, a process in which aluminum (Al) of the coating film (C) is diffused to the surface of the p-type ingot (IG) by performing heat treatment on the ingot (IG) on which the coating film (C) is formed. Can be. As a result, aluminum (Al) may be doped at the edge of the p-type ingot IG to form a p + type isolation region 120.

Subsequently, referring to FIG. 10C, the coating layer C is removed to form a separation region 120 having an edge portion p + and a substrate region 110 having a central portion p-type. Ingot IG can be obtained.

Of course, the surface may be treated with a doping gas containing a Group 3 material instead of the solid coating layer. For example, the ingot IG may be doped with BH ₃ .

Referring back to FIG. 6, a slicing process of cutting an ingot IG into a plurality of substrates may be performed (S50).

More specifically, referring to FIG. 11, the ingot IG may be cut into a plate shape having a thin thickness through a sawing process using a predetermined cutting means. Such cutting means may be, for example, a wire, but is not limited thereto, and a known cutting means such as a diamond saw may be used. Although not shown, a cleaning process for removing particles and sludge generated in the slicing process may be further performed.

The single crystal semiconductor substrate 100 including the substrate region 100 and the isolation region 120 manufactured according to the above processes may be used as a substrate of various semiconductors. It will be understood from the following detailed description with reference to FIG. 12 or below. However, the following examples are only for clarity and are not limited thereto.

Solar cell using single crystal semiconductor substrate with separated region

12 to 16 are views illustrating a manufacturing process of a solar cell using a single crystal semiconductor substrate having an isolation region according to an embodiment of the present invention.

First, FIG. 12 is a cross-sectional view of regions I through I 'of the single crystal semiconductor substrate 100 of the present invention manufactured as described above with reference to FIG. 11, wherein the substrate region 110 and the separation region 120 are disposed at the center portion. The formed substrate 100 may be provided.

Next, referring to FIG. 13, a roughness may be formed on the surface of the substrate 100 by performing a texturing process. Texturing in the present invention is intended to prevent the phenomenon that the characteristics of the light is reduced by reflecting the light incident on the substrate surface of the solar cell is optically lost. That is, by making the surface of a substrate rough, it means forming an uneven | corrugated pattern (for example, a triangular structure as shown) on the surface of a substrate. As such, when the surface of the substrate is roughened by texturing, the light reflected once from the surface may be reflected back toward the solar cell, thereby reducing the loss of light and increasing the amount of light trapping, thereby improving the photoelectric conversion efficiency of the solar cell. You can.

In this case, a representative texturing method may be a sand blasting method, which includes both dry blasting for spraying etched particles with compressed air and wet blasting for etching etched particles with liquid. On the other hand, the etching particles used in the sand blasting of the present invention can be used without limitation, particles that can form irregularities on the substrate by physical impact, such as sand, small metal. Of course, the texturing process may be omitted if necessary.

Next, referring to FIG. 14, an impurity of a different conductivity type from the substrate region 110 may be implanted into the surface of the substrate 100 to form a p-n junction.

For example, when the substrate region 110 is p-type, phosphorus (P), which is an n-type impurity, is implanted into the surface of the substrate 100 so as to form an n-type first region (first semiconductor) at the lower and upper portions of the substrate region 110. Layer 111), an n-type third region (third semiconductor layer 113) can be formed. At this time, the second region (second semiconductor layer) 112, which is the intermediate layer, may maintain the original p-type as it is. At the same time, phosphorus (P) is also diffused in the isolation region 120 having the p + type at the edge of the substrate 100 to change from p + type to i type (intrinsic) or p type.

As a result, the isolation region 120 of the substrate 100 may be the first region 111 and / or the third region 113 of the i-type or substrate regions 110, 111, 112, and 113, which may perform an insulation function. By having a different conductivity type than the above, it is possible to prevent the short circuit between the upper electrode 140 and the lower electrode 150 to be formed later to solve the problem that the recombination path of the electron is formed.

Meanwhile, as the impurity implantation method, a method using a solid source and a gas source may be typically used. In the case of using a solid source, phosphorus (P) is introduced into the substrate 100 by, for example, depositing a material such as P ₂ O ₅ on the substrate 100 and then heating at about 900 ° C. for a predetermined time. It can be injected by diffusion. In the case of using a gas source, for example, by using a gas such as PH ₃ , POCl ₃ , phosphorus (P) is diffused into the substrate 100 for a predetermined time at a temperature of about 850 ° C. to 950 ° C. Can be injected.

Next, referring to FIG. 15, an insulating layer 130 may be formed on the third region 113 of the substrate 100. The insulating layer 130 may be, for example, a silicon oxide film (SiO _X ) or a silicon nitride film (SiN _X ), but may be used without limitation as long as the material may transmit light and have insulating properties.

As the method of forming the insulating layer 130, a known chemical vapor deposition (CVD) method may be used.

Subsequently, an upper electrode 140 of a conductive material may be formed on the insulating layer 130. For example, the upper electrode 140 may include silver, copper, aluminum, titanium, and alloys thereof, but a conventional conductive material may be used without limitation.

As the method of forming the upper electrode 140, known physical vapor deposition (PVD) and chemical vapor deposition (CVD) may be used, but the screen printing method is more simple and inexpensive. It is preferable to use screen printing.

Subsequently, a lower electrode 150 of a conductive material may be formed on the first region 111 of the substrate 100. The lower electrode 150 may use the same conductive material as the second region 112 without limitation. For example, aluminum (Al), which is the same Group 3 material as the p-type second region 112, may be used.

As the method of forming the lower electrode 150, known physical vapor deposition (PVD) and chemical vapor deposition (CCVD) may be used.

Next, referring to FIG. 16, the upper electrode 140 formed on the insulating layer 130 by heat-treating the substrate 100 is diffused through the insulating layer 130 to form the third region 113 of the substrate 100. It can form a direct contact with the.

At the same time, the material forming the lower electrode 150 may be diffused into the substrate 100 to change the conductivity of the first region 111. For example, aluminum (Al) forming the lower electrode 150 may be diffused into the n-type first region 111 to change the n-type to the p + type.

As a result, p + type, p type, n type (or n + type, n type, p type) semiconductor layers 111, 112, and 113, in which appropriate impurities are injected into the single crystal silicon wafer, are formed of photoelectric conversion elements stacked in this order. Single crystal solar cells can be implemented. In this case, a separation region 120 is formed at an edge portion to perform an insulation function, and thus, a short circuit between the upper electrode 140 and the lower electrode 150 may be performed without performing an edge isolation process. It is possible to implement a good solar cell in which a recombination path of electrons that does not occur is blocked.

As described above, the single crystal solar cell according to the present invention can be manufactured without omitting the laser edge separation process, which had to be inevitably performed in the prior art, thereby simplifying the manufacturing process of the solar cell, making manufacturing costs low, and improving productivity. Can be.

In the foregoing detailed description, the present invention has been described by specific embodiments such as specific components and the like, but the embodiments and drawings are provided only to help a more general understanding of the present invention, and the present invention is limited to the above embodiments. However, one of ordinary skill in the art can make various modifications and variations from this description. Therefore, the spirit of the present invention should not be construed as being limited to the above-described embodiments, and all of the equivalents or equivalents of the claims, as well as the following claims, I will say.

1 to 5 are cross-sectional views showing a manufacturing process of a conventional single crystal solar cell.

6 is a flowchart illustrating a manufacturing process of a single crystal semiconductor substrate having an isolation region according to an embodiment of the present invention.

7 to 11 are views showing in detail the process according to FIG.

12 to 16 are views illustrating a manufacturing process of a solar cell using a single crystal semiconductor substrate having an isolation region according to an embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

100: substrate

110: substrate region

111: first semiconductor layer

112: second semiconductor layer

113: third semiconductor layer

120: separation area

130: insulation layer

140: upper electrode

150: lower electrode

Claims (21)

A substrate region having a predetermined conductivity type; And An isolation region formed at an edge portion of the substrate region and having the same concentration as that of the conductive type Single crystal semiconductor substrate comprising a. The method of claim 1, Wherein said substrate region and said isolation region are single crystal silicon. The method of claim 1, And the substrate region and the isolation region are p-type and p + -type. The method of claim 1, Wherein said substrate region and said isolation region are n-type and n + -type. (a) providing an ingot; (b) forming a separation region at the edge of the ingot that is the same as the conductivity type at the center of the ingot but has a high concentration; And (c) slicing the ingot into a semiconductor substrate Method for producing a single crystal semiconductor substrate comprising a. The method of claim 5, The ingot is a single crystal silicon substrate manufacturing method, characterized in that. The method of claim 5, In step (b), Forming a coating film on the surface of the ingot including impurities of the same conductivity type as the ingot; Heat-treating the ingot; And Removing the coating film Method for producing a single crystal semiconductor substrate comprising a. The method of claim 5, In step (b), Surface-treating the ingot with a predetermined gas Method for producing a single crystal semiconductor substrate comprising a. The method of claim 7, wherein If the ingot is p-type, the coating film includes a Group 3 material; if the ingot is n-type, the coating film includes a Group 5 material. The method of claim 8, Wherein if the ingot is of p type, the gas comprises a Group 3 material; if the ingot is of n type, the gas includes a Group 5 material. The method of claim 5, In step (a), Growing the ingot into single crystals; Blocking the ingot; And Planarizing the ingot Method for producing a single crystal semiconductor substrate comprising a. The method of claim 11, The blocking step includes any one or more of a cropping process or a squaring process. The method of claim 11, And the planarization step includes any one or more of an etching process and a grinding process. A substrate region formed by sequentially stacking first, second, and third semiconductor layers, and an isolation region formed at an edge portion of the substrate region and having the same or intrinsic (i-type) conductivity as the second semiconductor layer. A single crystal semiconductor substrate; An insulating layer formed on the third semiconductor layer; An upper electrode formed on the insulating layer and in contact with the third semiconductor layer through the insulating layer; And A lower electrode formed under the first semiconductor layer Solar cell comprising a. The method of claim 14, The single crystal semiconductor substrate is a solar cell, characterized in that the single crystal silicon. The method of claim 14, The first, second and third semiconductor layers are p + type, p type, n type solar cell, characterized in that. The method of claim 14, The first, second, and third semiconductor layers are n + type, n type, p type solar cell. The method of claim 14, The conductivity type of the first semiconductor layer is determined according to the lower electrode. The method of claim 14, The single crystal semiconductor substrate has a roughness, characterized in that the solar cell. (a) providing a single crystal semiconductor substrate comprising a substrate region having a predetermined conductivity type and an isolation region formed at an edge portion of the substrate region, the separation region being the same as the conductivity type but having a high concentration; And (b) doping an impurity of a conductivity type different from that of the substrate region to the surface of the substrate to form the substrate region as first, second, and third semiconductor layers stacked in this order; Changing the layer to the same or intrinsic (type i) as the conductivity type Including; The conductive type of the first and third semiconductor layers is the same as the impurity and the conductive type of the second semiconductor layer is the same as the substrate region. 21. The method of claim 20, (c) forming an insulating layer on the third semiconductor layer; (d) forming an upper electrode on the insulating layer; (e) forming a lower electrode under the first semiconductor layer; (f) heat treating the substrate to contact the upper electrode and the third semiconductor layer, and varying the conductivity type of the first semiconductor layer. Method for manufacturing a solar cell further comprising a.

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