CN117236270A - Self-adaptive display method, electronic equipment and medium for chip design code annotation - Google Patents
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Abstract
The invention relates to the technical field of chips, in particular to a self-adaptive display method, electronic equipment and medium for annotating chip design codes. In addition, by acquiring the four-tuple information of the annotation codes to be displayed in the chip design codes displayed in the first display area, determining the display column boundary value of the annotation information which can be displayed in the second display area in the first display area, dividing the first display area into a code area capable of displaying the annotation information and a code area incapable of displaying the annotation information, and then displaying the annotation information of the annotation codes to be displayed in the code area capable of displaying the annotation information in the first display area in the second display area, the interface utilization rate and the display effect of chip design annotation display are improved.
Description
Technical Field
The present invention relates to the field of chip technologies, and in particular, to a chip design code annotation adaptive display method, an electronic device, and a medium.
Background
In the field of chip design verification, it is often necessary to verify the data values of the same design signal at different points in time. In order to view the corresponding signal value in the design code file, an Annotation (analysis) mode is generally adopted, and in the same display interface, the original design code file is displayed, and specific data values of the signal at the corresponding time point are displayed. In the prior art, the data values of the corresponding signal variables are typically displayed in the design code in a row-by-row fashion, with the signal variable names corresponding to the signal values on the columns. However, when the display length required by the signal value of one signal is longer than the signal variable name, the display interface cannot display the complete signal value data, and the display effect is poor. So that part of the tool will also display annotation information in a multi-line fashion. However, when the number of signal variables in the same row is too large, a large amount of annotation information exists in the display interface, so that enough chip design information cannot be displayed, and the interface utilization rate is low. Therefore, how to improve the interface utilization rate of the chip design annotation display and improve the display effect is a technical problem to be solved urgently.
Disclosure of Invention
The invention aims to provide a self-adaptive display method, electronic equipment and medium for chip design code annotation, which improve the interface utilization rate and display effect of chip design annotation display.
According to a first aspect of the present invention, there is provided an adaptive display method of chip design code annotation, comprising:
s1, longitudinally dividing a visual interface into a first display area and a second display area, wherein the first display area is used for displaying chip design codes, the second display area is used for displaying annotation information corresponding to the chip design codes, and the first display area comprises R lines of chip design codes, wherein the code lines needing to display the annotations are to be displayed with annotation code lines;
step S2, initializing a chip design code sequence number r=1, and displaying an annotation code line sequence number j=0Total number of annotation lines to be written W of the second display area up to the j-th annotation code line to be displayed j =0, step S3 is performed;
s3, acquiring an r-th row of design codes B in the chip design codes displayed in the first display area r If B r There is a signal variable in (B) and j=j+1 is set to B r Determining the j th annotation code A to be displayed in the chip design codes displayed for the first display area j Executing the step S4, otherwise, executing the step S7;
step S4, obtaining A j Corresponding quadruple information (T j ,x j ,Vx j ,W j ) Wherein T is i Is A j Corresponding physical line number, x in chip design code j Is A j The number of lines of the annotation to be written, vx, corresponding to the second display area j Is A j In the number of lines of the annotation to be displayed corresponding to the second display area, initially setting Vx j ＝x j ，W j To the j th annotation code line to be displayed, the total number of the annotation lines to be written in the second display area is A j Corresponding quadruple information (T j ,x j ,Vx j ,W j ) Storing in a preset storage area;
step S5, contrast W j And R, if W j <R, executing the step S7, otherwise, executing the step S6;
s6, comparing R with a preset minimum visible line number F of the chip design codes, if R is more than or equal to F, determining the current R as a display column boundary value Q, determining the chip design codes from the Q+1st line to the R line in the first display area as non-display annotation code lines, executing the step S8, and if R is less than F, executing the step S7;
step S7, if R < R, r=r+1 is set, and step S3 is executed, and if r=r, step S8 is executed;
step S8, based on all the generated A j Corresponding quadruple information (T j ,x j ,Vx j ,W j ) Displaying each A in the second display area j Corresponding to Vx j Line annotation information.
Compared with the prior art, the invention has obvious advantages and beneficial effects. By means of the technical scheme, the self-adaptive display method, the electronic equipment and the medium for annotating the chip design code can achieve quite technical progress and practicality, and have wide industrial utilization value, and the self-adaptive display method has at least the following beneficial effects:
according to the method, a visual interface is longitudinally divided into a first display area and a second display area, chip design codes and annotation information are decoupled, the display of the annotation information is more flexible and compact through the two areas, the four-element information of the annotation codes to be displayed in the chip design codes displayed in the first display area is obtained, the display column boundary value of the annotation information which can be displayed in the second display area in the first display area is determined, the first display area is divided into a code area capable of displaying the annotation information and a code area incapable of displaying the annotation information, then the annotation information of the annotation codes to be displayed in the code area capable of displaying the annotation information in the first display area is displayed in the second display area, and the interface utilization rate and the display effect of chip design annotation display are improved.
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In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flow chart of a method for adaptively displaying chip design code annotations according to an embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to fall within the scope of the invention.
The embodiment of the invention provides a self-adaptive display method for chip design code annotation, which is shown in fig. 1 and comprises the following steps:
s1, longitudinally dividing a visual interface into a first display area and a second display area, wherein the first display area is used for displaying chip design codes, the second display area is used for displaying annotation information corresponding to the chip design codes, and the first display area comprises R rows of chip design codes, wherein the code rows needing to display the annotations are to be displayed with annotation code rows.
The chip design code displayed in the first display area includes a code line that needs to display the annotation, and also includes a code line that does not need to display the annotation. The chip design code behavior with signal variable needs to display the annotated code line, namely the annotated code to be displayed. The line content of the chip design code may be divided into visible lines and physical lines, where the physical lines correspond to lines of the real text file and the visible lines correspond to lines visible on the interface. When the folding function exists in the interface, the physical line of the file cannot be obtained through simple line number addition and subtraction. Such as: visible rows 12, 13, 14 may be 12, 13, and 37 for physical rows, i.e., 23 physical rows are hidden from view after visible row 13. T obtained in step S2 j Is the physical line number.
It can be understood that the maximum number of lines that can be displayed in the first display area and the second display area is the same, and the total number of lines that can be displayed in the second display area is R.
Step S2, initializing a chip design code sequence number r=1, displaying an annotation code line sequence number j=0, and displaying the total number W of annotation lines to be written in the second display area until the j-th annotation code line to be displayed j =0, step S3 is performed.
S3, acquiring an r-th row of design codes B in the chip design codes displayed in the first display area r If B r Is present in (a)Signal variable, set j=j+1, will B r Determining the j th annotation code A to be displayed in the chip design codes displayed for the first display area j Step S4 is executed, otherwise step S7 is executed.
Step S4, obtaining A j Corresponding quadruple information (T j ,x j ,Vx j ,W j ) Wherein T is i Is A j Corresponding physical line number, x in chip design code j Is A j The number of lines of the annotation to be written, vx, corresponding to the second display area j Is A j In the number of lines of the annotation to be displayed corresponding to the second display area, initially setting Vx j ＝x j ，W j To the j th annotation code line to be displayed, the total number of the annotation lines to be written in the second display area is A j Corresponding quadruple information (T j ,x j ,Vx j ,W j ) Stored in a preset storage area.
The chip design code displayed in the first display area includes a code line that needs to display the annotation, and also includes a code line that does not need to display the annotation, and in step S4, only four-tuple information corresponding to the code line that needs to display the annotation is extracted.
Step S5, contrast W j And R, if W j <And R, executing the step S7, otherwise, executing the step S6.
Wherein if W j <R, the second display area is further provided with a space for increasing and displaying annotation information lines, so that the chip design code is continuously traversed, if W j And (3) not less than R, indicating that the second display area has no space to continue to increase annotation information lines, and therefore, entering step S6 to judge whether the number of the chip design code lines which have been traversed reaches the preset minimum visible number of the chip design code lines F.
And S6, comparing R with a preset minimum visible line number F of the chip design codes, if R is more than or equal to F, determining the current R as a display column boundary value Q, determining the chip design codes from the Q+1st line to the R line in the first display area as non-display annotation code lines, executing the step S8, and if R is less than F, executing the step S7.
If r is greater than or equal to F, the chip design code line which has been traversed at present is indicated to have satisfied the requirement of traversing at least the minimum visible line number F of the preset chip design code, and at this time, the second display area has no space to continue to add annotation information lines, so the display flow of step S8 is entered. If r < F, then the chip design code line needs to be traversed continuously.
Step S7, if R < R, r=r+1 is set, and the process returns to step S3, and if r=r, step S8 is executed.
Step S8, based on all the generated A j Corresponding quadruple information (T j ,x j ,Vx j ,W j ) Displaying each A in the second display area j Corresponding to Vx j Line annotation information.
According to the embodiment of the invention, the visual interface is longitudinally divided into the first display area and the second display area, the chip design codes and the annotation information are decoupled, the display of the annotation information is more flexible and compact through the two areas, the first display area is divided into the code area capable of displaying the annotation information and the code area incapable of displaying the annotation information through determining the display column boundary value Q, and then the annotation information of the annotation code to be displayed of the code area capable of displaying the annotation information in the first display area is displayed in the second display area, so that the interface utilization rate and the display effect of the chip design annotation display are improved.
As an embodiment, the step S4 includes:
step S41, acquisition of A j Corresponding physical line number T i Number of signals G j Sum signal variable list L j 。
It will be appreciated that A j Corresponding list of signal variables L j The number of signals in (a) is G j 。
Step S42, based on G j Acquisition A j The number of lines x of the annotation to be written corresponding to the second display area j ，Wherein m isThe number of notes that can be displayed per line of said second display area, is->Representing an upward rounding.
It should be noted that, each signal variable corresponds to a signal annotation, and the signal annotation specifically may include a signal variable identifier and a corresponding signal annotation identifier. Number of lines of annotations to be written x j For the expected number of annotation lines to be displayed corresponding to each annotation code to be displayed, but limited by the display lines of the second area, the lines may not be completely displayed, so that the number of annotation lines to be displayed corresponding to the second display area, that is, the number of annotation lines actually capable of being displayed in the display process, is set, and Vx can be set in the initial process j ＝x j And then the display is adjusted according to specific display requirements.
Step S43, setting Vx j ＝x j Setting W j ＝W j +x j Based on A j Corresponding T j ,x j ,Vx j ,W j Generation A j Corresponding quadruple information (T j ,x j ,Vx j ,W j )。
Through steps S41 to S43, it is possible to acquire four-tuple information of all annotation codes to be displayed in a code area where the first display area is divided into displayable annotation information.
After dividing the first display area into a code area capable of displaying the annotation information and a code area incapable of displaying the annotation information, different display modes can be adopted to distinguish the code area capable of displaying the annotation information and the code area incapable of displaying the annotation information, and the step S6 includes:
step S61, in the first display area, the first to the Q-th chip design codes are displayed in a first display mode, and the Q+1-th to the R-th chip design codes are displayed in a second display mode.
The background of the code areas from the first line of chip design codes to the Q line of chip design codes may be set to white, and the background of the code areas from the q+1th line of chip design codes to the R line of chip design codes may be set to gray. The first to the Q-th row chip design codes may be highlighted, and the q+1-th to the R-th row chip design codes may be normally displayed. It will be appreciated that other manners of distinguishing between two code regions may be used.
As an embodiment, the step S8 includes:
step S81, obtaining the total number W of annotation lines to be written in the second display area from the corresponding point to the J-th annotation code line to be displayed when J in the preset storage area takes the maximum value J J 。
Step S82, contrast W J And R, if W J And R is less than or equal to, directly executing the step S84, otherwise, executing the step S83.
It will be appreciated that if W J And R is less than or equal to R, the second display area is enough to display all annotation information lines, and the annotation information lines do not need to be hidden. If W is J >R, it is explained that the second display area is insufficient to display all the annotation information lines, and therefore a part of the annotation information lines needs to be hidden.
Step S83, updating at least one Vx j So that all Vx j Is equal to R, and then step S84 is performed.
Vx is updated by step S83 j And determining the number of lines of hidden annotation information corresponding to at least one annotation code to be displayed.
Step S84, displaying each A in the second display area j Corresponding to Vx j Line annotation information.
As an embodiment, the step S83 includes:
step S831, obtaining the number of lines h of the line annotation to be hidden, h=w J -R, set i=j, execute step S42.
Since the second display area is insufficient to display J lines of annotation information for which the lines of annotation code are to be displayed, it is necessary to hide a part of the lines of annotation information. Note that, in general, the note information line corresponding to the chip design code line having the front sequence number is more important, and therefore, it is preferable to hide the note information line from the line having the largest sequence number.
Step S832, if Vx i And (3) if L is less than or equal to L, executing the step S45, otherwise, executing the step S43, wherein L is the preset minimum annotation display line number corresponding to each annotation code to be displayed.
Wherein, if Vx i The number of lines of annotation information which are required to be displayed for indicating the lines of the annotation code to be displayed is less than the minimum number of lines of annotation information, so that the corresponding Vx is directly displayed subsequently i And annotating the information.
Step S833, if x-L is greater than or equal to h, setting Vx i ＝x i H, and set h=0, jump to step S5, otherwise, execute step S44.
Wherein if x i And L is larger than or equal to h, and the actual requirement can be met after the annotation line corresponding to the current annotation code line to be displayed is hidden.
Step S834, setting Vx i =l, set h=h- (x) i -L), if h=0, jump to step S5, if h>0, step S45 is performed.
Wherein, when x i When L, the current ith annotation code row to be displayed is insufficient to hide h rows on the premise of meeting the minimum annotation information row number, so x is hidden on the premise of meeting the minimum annotation information row number i L rows and updates the corresponding h value.
In step S835, if i >1, i=i-1 is set, and the process returns to step S41.
It should be noted that, through steps S831-S835, one may not traverse J Vx i H can be updated to 0, i.e. the display requirement is met by hiding part of the annotation line. However, in still another case, J Vx's are traversed i And h is still larger than 0, namely the second display area is still insufficient to display the hidden annotation information row on the premise of ensuring that the minimum annotation information row is met. As an example, if i=1 in the step S835, and h>0, the step S835 further comprises:
step S836, starting with j=1, according to the current Vx i Value the second display area displays A j Corresponding annotation informationWhen the total number of lines displaying the annotation information reaches R, the remaining A is no longer displayed j Is provided.
It will be appreciated that the annotation code line a to be displayed with the front sequence number is preferentially displayed on the premise that the second display area is insufficient to display the hidden annotation information line j Corresponding Vx i The lines annotate the information lines.
As an embodiment, the step S84 includes:
step S841, transversely dividing the second display area into J sub-areas A j And B is connected with j Associated, B j And J is a J-th subarea of the second display area, and the value range of J is 1 to J.
Wherein, A can be established by arranging connecting wires j And B is connected with j Is a relationship of association of the above. A is that j And B is connected with j Specifically, the A can be clearly displayed by adopting the association line association j And B is connected with j And the association relation between the two.
Step S842, at B j Middle display A j Corresponding Vx j Line annotation information.
As an embodiment, each sub-area of the second display area is provided with a corresponding horizontal scroll bar and a corresponding vertical scroll bar, the annotation information horizontally displayed in the corresponding sub-area is adjusted by operating the horizontal scroll bar, and the annotation information vertically displayed in the corresponding sub-area is adjusted by operating the vertical scroll bar. Note that, the length of the annotation information corresponding to different signal variables may be different, and for the annotation information that is too long, it may be impossible to completely display the annotation information in the second display area through one line, so a horizontal scroll bar may be set, and the annotation information that is horizontally displayed in the corresponding sub-area may be adjusted by operating the horizontal scroll bar. Further, by step S831 to step S835, a partial sub-area is made to hide a partial annotation information line, and thus a vertical scroll bar may be provided, and the annotation information displayed vertically in the corresponding sub-area is adjusted by operating the vertical scroll bar. Each sub-region of the second display area may be provided with a horizontal scroll bar and a vertical scroll bar separately according to display requirements.
According to the embodiment of the invention, the first display area is divided into a code area capable of displaying annotation information and a code area incapable of displaying the annotation information, and then the second area is used for displaying the annotation information corresponding to all the code lines to be displayed in the code area capable of displaying the annotation information.
It should be noted that some exemplary embodiments are described as a process or a method depicted as a flowchart. Although a flowchart depicts steps as a sequential process, many of the steps may be implemented in parallel, concurrently, or with other steps. Furthermore, the order of the steps may be rearranged. The process may be terminated when its operations are completed, but may have additional steps not included in the figures. The processes may correspond to methods, functions, procedures, subroutines, and the like.
The embodiment of the invention also provides electronic equipment, which comprises: at least one processor; and a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being configured to perform the methods of embodiments of the present invention.
The embodiment of the invention also provides a computer readable storage medium, and the computer instructions are used for executing the method of the embodiment of the invention.
According to the embodiment of the invention, the visual interface is longitudinally divided into the first display area and the second display area, the chip design code and the annotation information are decoupled, the display of the annotation information is more flexible and compact through the two areas, the display column boundary value of the annotation information which can be displayed in the second display area in the first display area is determined through acquiring the four-element information of the annotation code which is to be displayed in the chip design code displayed in the first display area, the first display area is divided into the code area which can display the annotation information and the code area which cannot display the annotation information, and then the annotation information of the annotation code which can be displayed in the code area which can display the annotation information in the first display area is displayed in the second display area, so that the interface utilization rate and the display effect of the chip design annotation display are improved.
The present invention is not limited to the above-mentioned embodiments, but is intended to be limited to the following embodiments, and any modifications, equivalents and modifications can be made to the above-mentioned embodiments without departing from the scope of the invention.
Claims (8)
1. An adaptive display method for chip design code annotation, comprising:
s1, longitudinally dividing a visual interface into a first display area and a second display area, wherein the first display area is used for displaying chip design codes, the second display area is used for displaying annotation information corresponding to the chip design codes, and the first display area comprises R lines of chip design codes, wherein the code lines needing to display the annotations are to be displayed with annotation code lines;
step S2, initializing a chip design code sequence number r=1, displaying an annotation code line sequence number j=0, and displaying the total number W of annotation lines to be written in the second display area until the j-th annotation code line to be displayed j =0, step S3 is performed;
s3, acquiring an r-th row of design codes B in the chip design codes displayed in the first display area r If B r There is a signal variable in (B) and j=j+1 is set to B r Determining the j th annotation code A to be displayed in the chip design codes displayed for the first display area j Executing the step S4, otherwise, executing the step S7;
step S4, obtaining A j Corresponding quadruple information (T j ,x j ,Vx j ,W j ) Wherein T is i Is A j Corresponding physical line number, x in chip design code j Is A j Corresponding to the second display area to be treatedWrite the number of annotation lines, vx j Is A j In the number of lines of the annotation to be displayed corresponding to the second display area, initially setting Vx j ＝x j ，W j To the j th annotation code line to be displayed, the total number of the annotation lines to be written in the second display area is A j Corresponding quadruple information (T j ,x j ,Vx j ,W j ) Storing in a preset storage area;
step S5, contrast W j And R, if W j <R, executing the step S7, otherwise, executing the step S6;
s6, comparing R with a preset minimum visible line number F of the chip design codes, if R is more than or equal to F, determining the current R as a display column boundary value Q, determining the chip design codes from the Q+1st line to the R line in the first display area as non-display annotation code lines, executing the step S8, and if R is less than F, executing the step S7;
step S7, if R < R, r=r+1 is set, and step S3 is executed, and if r=r, step S8 is executed;
step S8, based on all the generated A j Corresponding quadruple information (T j ,x j ,Vx j ,W j ) Displaying each A in the second display area j Corresponding to Vx j Line annotation information.
2. The method of claim 1, wherein the step of determining the position of the substrate comprises,
the step S4 includes:
step S41, acquisition of A j Corresponding physical line number T i Number of signals G j Sum signal variable list L j ；
Step S42, based on G j Acquisition A j The number of lines x of the annotation to be written corresponding to the second display area j ，Wherein m is the number of notes that each line of the second display area can display, ">Representing an upward rounding;
step S43, setting Vx j ＝x j Setting W j ＝W j +x j Based on A j Corresponding T j ,x j ,Vx j ,W j Generation A j Corresponding quadruple information (T j ,x j ,Vx j ,W j )。
3. The method of claim 1, wherein the step of determining the position of the substrate comprises,
the step S6 includes:
step S61, in the first display area, the first to the Q-th chip design codes are displayed in a first display mode, and the Q+1-th to the R-th chip design codes are displayed in a second display mode.
4. The method of claim 1, wherein the step of determining the position of the substrate comprises,
the step S8 includes:
step S81, obtaining the total number W of annotation lines to be written in the second display area from the corresponding point to the J-th annotation code line to be displayed when J in the preset storage area takes the maximum value J J ；
Step S82, contrast W J And R, if W J If R is less than or equal to R, directly executing the step S84, otherwise, executing the step S83;
step S83, updating at least one Vx j So that all Vx j Is equal to R, and then step S84 is performed;
step S84, displaying each A in the second display area j Corresponding to Vx j Line annotation information.
5. The method of claim 4, wherein the step of determining the position of the first electrode is performed,
the step S84 includes:
step S841, transversely dividing the second display area into J sub-areas A j And B is connected with j Associated, B j A J-th subarea of the second display area is provided with a value range of 1 to J;
step S842, at B j Middle display A j Corresponding Vx j Line annotation information.
6. The method of claim 5, wherein the step of determining the position of the probe is performed,
in the step S841, a is established by setting up a connection line j And B is connected with j Is a relationship of association of the above.
7. An electronic device, comprising:
at least one processor;
and a memory communicatively coupled to the at least one processor;
wherein the memory stores instructions executable by the at least one processor, the instructions being arranged to perform the method of any of the preceding claims 1-6.
8. A computer readable storage medium, characterized in that computer executable instructions are stored for performing the method of any of the preceding claims 1-6.
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