CN117234789A - Verification and error correction method and device, electronic equipment and storage medium - Google Patents
Verification and error correction method and device, electronic equipment and storage medium Download PDFInfo
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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Abstract
The application relates to the technical field of data storage, and discloses a verification and error correction method, a device, a server and a storage medium, wherein the method comprises the following steps: burning verification data and error correction data in the flash memory; performing software error injection on the verification data to obtain second verification data, generating an error correction test set based on the second verification data and the error correction data, or performing software error injection on the error correction data to obtain second error correction data, and generating the error correction test set based on the verification data and the second error correction data; based on the error correction test set, performing error correction test on the memory to be tested; when the error correction test of the error correction memory to be tested is successful, carrying out error correction check on the firmware data; when the firmware data passes the error correction verification, the firmware data is carried to the memory, and the error correction test is carried out by adding the memory to be tested, so that the reliability of the memory to be tested is ensured. By means of software fault injection, automatic testing of the error correction memory is achieved, and testing is enabled to be more reliable and real-time.
Description
Technical Field
The present application relates to the field of data storage technologies, and in particular, to a method and apparatus for checking and correcting errors, an electronic device, and a storage medium.
Background
ECC (Error Checking and Correcting) memory, i.e. a memory bank to which error checking and correction techniques (ECC) are applied. The method is generally applied to a server and a graphic workstation, which leads the whole computer system to be more safe and stable during working. The ECC is capable of tolerating errors and correcting errors in the memory, so that the system can continue normal operation without interruption due to errors, and the ECC has the capability of automatic correction, and can detect error bits which cannot be checked by parity check and correct errors.
In the related art, a common verification method is to verify whether the ECC check function and the ECC memory are reliable in an ECC function verification stage, and after release of the version, the ECC check function is not verified. Before functional verification, the data file is manually modified to perform a single verification test without reproduction capability, so that verification failure is caused by lack of instantaneity and easy occurrence of artificial errors, and whether an ECC memory is reliable cannot be ensured.
Disclosure of Invention
In view of this, the present application provides a method, apparatus, server and storage medium for checking and correcting errors, so as to solve the problem that whether the ECC memory is reliable or not cannot be ensured.
In a first aspect, the present application provides a method for checking and correcting errors, the method comprising:
burning verification data and error correction data in the flash memory;
performing software error injection on the verification data to obtain second verification data, generating an error correction test set based on the second verification data and the error correction data, or performing software error injection on the error correction data to obtain second error correction data, and generating the error correction test set based on the verification data and the second error correction data;
based on the error correction test set, performing error correction test on the memory to be tested;
when the error correction test of the error correction memory to be tested is successful, carrying out error correction check on the firmware data;
and when the firmware data passes the error correction check, carrying the firmware data to a memory.
In the application, the error correction test is carried out on the error correction memory to be tested before the ECC function verification stage, and the error correction verification is carried out after the error correction memory to be tested passes the error correction test, so that the reliability of the error correction memory to be tested is ensured, and the effectiveness and the reliability of the subsequent firmware data handling are further ensured. By means of software error injection, automatic testing of the error correction memory is achieved, error correction memory testing is conducted before data are carried each time, the testing is enabled to be more reliable and real-time, and reliability of the error correction memory eccengine can be effectively and repeatedly verified in real time.
In an alternative embodiment, performing software error injection on the verification data to obtain second verification data includes:
and modifying the data of a plurality of bits in the verification data to obtain second verification data and a modification position of the second verification data.
In the mode, the verification data is subjected to error injection, so that the subsequent automatic test flow is facilitated, and the reliability guarantee of the memory to be tested and corrected is further improved.
In an alternative embodiment, performing software error injection on the error correction data to obtain second error correction data, including:
and modifying the data of a plurality of bits in the error correction data to obtain second error correction data and a modification position of the second error correction data.
In the mode, the error correction data is subjected to error injection, so that the subsequent automatic test flow is facilitated, and the reliability guarantee of the memory to be tested is further improved.
In an alternative embodiment, based on the set of error correction tests, performing error correction tests on the memory to be tested includes:
the error correction test set is read by using the error correction memory to be tested to carry out error correction test, and whether the error correction memory to be tested triggers interruption is judged;
when the error correction memory to be tested triggers interruption, judging whether the error position determined by the memory to be tested accords with the modification position of the error correction test set;
and when the error correction memory to be tested triggers interruption and the error position determined by the memory to be tested accords with the modification position of the error correction test set, confirming that the error correction test of the memory to be tested is successful.
In the mode, whether the error correction test set is triggered to be interrupted or not through the error correction memory to be tested and whether the data modification position after error injection can be judged or not is achieved, error correction verification of the error correction memory to be tested is achieved, reliability of the error correction memory is guaranteed, subsequent error correction of firmware data is facilitated, and reliability and effectiveness of a firmware data carrying flow are guaranteed.
In an alternative embodiment, when the error correction memory to be tested does not trigger interruption or the error position determined by the memory to be tested does not accord with the modification position of the error correction test set, the error correction test of the memory to be tested is confirmed to fail, the problem of the memory to be tested is confirmed, and interruption reporting is triggered.
In the mode, when the error correction memory to be detected fails the error correction test, the subsequent error correction process of the firmware data is interrupted and reported, so that the reliability and the effectiveness of the firmware data carrying process are further ensured.
In an alternative embodiment, performing error correction verification on firmware data includes:
generating check data corresponding to the firmware data in the flash memory based on the firmware data;
and comparing the firmware data with the verification data by using the error correction memory to be tested, and confirming that the firmware data passes error correction verification when the comparison result is that the verification data is consistent with the firmware data.
In this way, the error correction memory is used to correct the firmware data, so that the reliability and effectiveness in the firmware data handling process are improved. And error correction memory test is carried out before each firmware data handling flow, so that the reliability of the error correction memory is timely ensured.
In an alternative embodiment, when the comparison result is that the verification data is inconsistent with the firmware data, it is confirmed that the firmware data does not pass the error correction verification, the carrying of the firmware data is interrupted, and the firmware data is reported without passing the error correction verification.
In the mode, when the firmware data does not pass the error correction verification, the firmware data carrying process is interrupted and reported, so that the reliability and the effectiveness in the firmware data carrying process are further ensured.
In a second aspect, the present application provides a verification and error correction apparatus, the apparatus comprising:
the data burning module is used for burning verification data and error correction data in the flash memory;
the data error injection module is used for performing software error injection on the verification data to obtain second verification data, generating an error correction test set based on the second verification data and the error correction data, or performing software error injection on the error correction data to obtain second error correction data, and generating the error correction test set based on the verification data and the second error correction data;
the error correction testing module is used for carrying out error correction testing on the memory to be tested based on the error correction testing set;
the error correction checking module is used for performing error correction checking on the firmware data when the error correction test of the memory to be tested is successful;
and the data handling module is used for handling the firmware data to the memory when the firmware data passes the error correction check.
In a third aspect, the present application provides a server comprising: the memory and the processor are in communication connection, computer instructions are stored in the memory, and the processor executes the computer instructions, so that the check and error correction method of the first aspect or any implementation manner corresponding to the first aspect is executed.
In a fourth aspect, the present application provides a computer readable storage medium having stored thereon computer instructions for causing a computer to perform the check and error correction method of the first aspect or any of its corresponding embodiments.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described, and it is obvious that the drawings in the description below are some embodiments of the present application, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flow chart of firmware fw handling in bootloader phase.
Fig. 2 is a flowchart of a method for checking and correcting errors according to an embodiment of the present application.
FIG. 3 is a flow chart of firmware data handling in bootloader phase according to an embodiment of the present application.
Fig. 4 is a flowchart of another check and error correction method according to an embodiment of the present application.
Fig. 5 is a flowchart of still another method for checking and correcting errors according to an embodiment of the present application.
Fig. 6 is a block diagram of a check and error correction apparatus according to an embodiment of the present application.
Fig. 7 is a schematic diagram of a hardware structure of a server according to an embodiment of the present application.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present application more apparent, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments of the present application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
The Flash stores the sram code and the hostboot code, and the corresponding ecc check data. In the Bootloader stage, one ecc check is required in the process of carrying fw out. If the ECC check fails, corresponding processing is performed, so that it is important to ensure the reliability of the ECC check function.
The inventors found that: in the related art, a common verification method is to verify whether the ECC check function and the ECC memory are reliable in an ECC function verification stage, and after release of the version, the ECC check function is not verified. Before functional verification, the data file is manually modified to perform a single verification test without reproduction capability, so that verification failure is caused by lack of instantaneity and easy occurrence of artificial errors, and whether an ECC memory is reliable cannot be ensured. FIG. 1 is a flow chart of firmware fw handling in bootloader phase.
As shown in fig. 1, the bootloader stage firmware fw handling flow includes:
loading firmware data;
loading firmware data into a data cache of an ECC engine from a flash, loading the ECC data into an ECC cache of the ECC engine from the flash, and performing ECC check on the ECC engine by using the firmware data and the ECC data to judge whether the ECC check is successful or not;
when the verification is successful, carrying the firmware data to the sram;
and when the verification fails, performing interrupt reporting.
The process can not realize software fault injection, can only adopt manual modification of the data file before functional verification, carry out single verification test without reproduction capability, have no real-time performance, and easily generate verification failure caused by artificial errors. Still has the following disadvantages:
1. the ECC file is manually modified without repeatability, sustainability and complexity.
2. Manual modification is prone to human error and is not representative.
3. The conventional scheme needs to manually modify a section of data in advance to perform the ECC test, and the data cannot be stored and the automatic test of the ECC cannot be realized, so that a certain security risk exists.
4. The accuracy and reliability of the ecc engine cannot be verified in real time.
In order to solve the above-mentioned problems, in the embodiments of the present application, a verification and error correction method is provided for a server, and it should be noted that an execution body of the verification and error correction method may be a verification and error correction device, and the device may be implemented in a manner of software, hardware or a combination of software and hardware to form part or all of the server, where the server may be a terminal, a client, or a server, and the server may be a server or a server cluster formed by multiple servers. In the following method embodiments, the execution subject is a server as an example.
The server in this embodiment is suitable for use in a use scenario in which firmware data is handled in a boot loader process, and the data is handled from flash memory to static memory or other storage. According to the verification error correction method provided by the application, the error correction test is carried out on the to-be-tested error correction memory before the ECC function verification stage, and the error correction verification is carried out after the to-be-tested error correction memory passes the error correction test, so that the reliability of the to-be-tested error correction memory is ensured, and the effectiveness and reliability of the subsequent firmware data handling are further ensured. By means of software error injection, automatic testing of the error correction memory is achieved, error correction memory testing is conducted before data are carried each time, the testing is enabled to be more reliable and real-time, and reliability of the error correction memory eccengine can be effectively and repeatedly verified in real time.
In accordance with an embodiment of the present application, a check error correction method embodiment is provided, it being noted that the steps illustrated in the flowchart of the figures may be performed in a computer system, such as a set of computer executable instructions, and, although a logical order is illustrated in the flowchart, in some cases, the steps illustrated or described may be performed in an order other than that illustrated herein.
In this embodiment, a method for checking and correcting errors is provided, which can be used for the above-mentioned flash memory, and fig. 2 is a flowchart of a method for checking and correcting errors according to an embodiment of the present application, as shown in fig. 2, where the flowchart includes the following steps:
step S201, the verification data and the error correction data are burned in the flash memory.
In an example, the data stored in the FLASH and the data that need to be encrypted by signature and the like can be burned, so that the data cannot be modified maliciously by the outside and has reliability.
Step S202, performing software error injection on the verification data to obtain second verification data, generating an error correction test set based on the second verification data and the error correction data, or performing software error injection on the error correction data to obtain second error correction data, and generating the error correction test set based on the verification data and the second error correction data.
In an example, the fault injection mode is software fault injection, and the reliability of the eccengine is verified by modifying data or ecco check data of any specified position in a software mode.
Step S203, based on the error correction test set, performing error correction test on the memory to be tested.
In an example, based on the original firmware data handling flow, an ECC engine check function is first verified to be reliable by performing an ECC test.
Step S204, when the error correction test of the memory to be tested is successful, error correction checking is carried out on the firmware data.
In an example, if ECC test is successful, it indicates that the ECC engine has reliability, and the following steps may be performed: the fw (firmware) firmware data starts to be transferred and the ecccheck is performed.
In step S205, when the firmware data passes the error correction check, the firmware data is transferred to the memory.
In one example, when the ecclock passes, fw firmware data is carried to the sram to complete a carrying flow of the firmware data.
In an implementation scenario, the Flash stores a sram code and a hostboot code, and their corresponding ecc check data. In the Bootloader stage, one ecc check is required in the process of carrying fw out. If the ECC check fails, corresponding processing is performed, so that it is important to ensure the reliability of the ECC check function.
Because the related art often adopts a mode of manually modifying the ECC file, the method has no repeatability and sustainability and is complex and laborious. Manual modification is prone to human error and is not representative. The conventional scheme needs to manually modify a section of data in advance to perform the ECC test, and the data cannot be stored and the automatic test of the ECC cannot be realized, so that a certain security risk exists. The accuracy and reliability of the ecc engine cannot be verified in real time. According to the application, by storing a part of verification data and corresponding ECC data in the flash, before formally carrying fw, the reliability of the ECC engine is verified for one time, or software error is performed in an automatic test flow, so that automatic verification is realized. FIG. 3 is a schematic diagram of a firmware data handling process in bootloader phase according to an embodiment of the present application, where the firmware data handling process may include:
and dividing an address storage verification data and a corresponding ECC data file in the flash, and advanced ECC test flow is performed before fw firmware data is carried out each time or during automatic testing (assuming that the position of flash0x15690 is one position in test data, the stored data is 0x30, and the corresponding ECC data is stored in the corresponding position of the flash).
The stored data 0x30 is modified to 0x33 (i.e. double bit modification) by software, and then the data is carried to the data cache of the ECC engine, and the corresponding ECC data is carried to the ECC cache. At this point the data has been modified.
And reading test data from the data cache, wherein if the data is modified, if the interrupt is triggered and the interrupt is displayed as a double-bit error, the error position also accords with the modified position, the reliability of the ecc engine is indicated, otherwise, the problem of the ecc engine is indicated, and the interrupt reporting needs to be triggered to carry out corresponding processing.
If the ecc engine has reliability, the next step is performed: starting to convey fw and carrying out ecclock, and if the ecclock passes, conveying the fw to the sram; if not, the reporting is interrupted to carry out corresponding processing.
According to the verification error correction method, the error correction test is carried out on the to-be-tested error correction memory before the ECC function verification stage, the error correction verification is carried out on the to-be-tested error correction memory after the to-be-tested error correction memory passes the error correction test, and the firmware data is carried, so that the reliability of the to-be-tested error correction memory is ensured, and the effectiveness and the reliability of the subsequent carrying of the firmware data are further ensured. By means of software error injection, automatic testing of the error correction memory is achieved, error correction memory testing is conducted before data are carried each time, the testing is enabled to be more reliable and real-time, and reliability of the error correction memory eccengine can be effectively and repeatedly verified in real time.
In this embodiment, a method for checking and correcting errors is provided, which can be used for the above-mentioned flash memory, and fig. 4 is a flowchart of another method for checking and correcting errors according to an embodiment of the present application, as shown in fig. 4, where the flowchart includes the following steps:
in step S401, the verification data and the error correction data are burned in the flash memory. Please refer to step S201 in the embodiment shown in fig. 2 in detail, which is not described herein.
Step S402, performing software error injection on the verification data to obtain second verification data, generating an error correction test set based on the second verification data and the error correction data, or performing software error injection on the error correction data to obtain second error correction data, and generating the error correction test set based on the verification data and the second error correction data.
Specifically, the step S402 includes:
step S4021, modifying the data of several bits in the verification data to obtain the second verification data and the modified position of the second verification data.
In the mode, the verification data is subjected to error injection, so that the subsequent automatic test flow is facilitated, and the reliability guarantee of the memory to be tested and corrected is further improved.
Step S4022, modifying the data of the bits in the error correction data to obtain the second error correction data and a modified position of the second error correction data.
In the mode, the error correction data is subjected to error injection, so that the subsequent automatic test flow is facilitated, and the reliability guarantee of the memory to be tested is further improved.
In one example, a single bit modification, a double bit modification, or more bit modifications may be performed on either the test data or the ECC check data to enable the injection of errors to the verification data or the error correction data.
Step S403, based on the error correction test set, performing error correction test on the memory to be tested.
Specifically, the step S403 includes:
step S4031, the error correction test set is read by using the error correction memory to be tested to perform error correction test, and whether the error correction memory to be tested triggers interruption is judged.
Step S4032, when the error correction memory to be tested triggers an interrupt, it is determined whether the error position determined by the memory to be tested accords with the correction test set modification position.
Step S4033, when the error correction memory to be tested triggers an interrupt and the error position determined by the memory to be tested accords with the modified position of the error correction test set, the error correction test of the memory to be tested is confirmed to be successful.
Step S4034, when the error correction memory to be tested is not triggered to be interrupted or the error position determined by the memory to be tested is not in accordance with the modified position of the error correction test set, the error correction test of the memory to be tested is confirmed to fail, the problem of the memory to be tested is confirmed, and the interrupt reporting is triggered.
In an example, the ecc test misclassification may include: the flash0x15690 is a position in test data, and the stored data is 0x30; corresponding ecc data are stored in corresponding positions of the flash. The stored data 0x30 is modified into 0x33 (double bit modification) in a software mode, and then the data is carried to the data cache of the ECC engine, and the corresponding ECC data is carried to the ECC cache. At this point the data has been modified.
And reading test data from the data cache, wherein if the data is modified, if the interrupt is triggered and the interrupt is displayed as a double-bit error, the error position also accords with the modified position, the reliability of the ecc engine is indicated, otherwise, the problem of the ecc engine is indicated, and the interrupt reporting needs to be triggered to carry out corresponding processing.
In the mode, whether the error correction test set is triggered to be interrupted or not through the error correction memory to be tested and whether the data modification position after error injection can be judged or not is achieved, error correction verification of the error correction memory to be tested is achieved, reliability of the error correction memory is guaranteed, subsequent error correction of firmware data is facilitated, and reliability and effectiveness of a firmware data carrying flow are guaranteed. When the error correction memory to be tested fails the error correction test, the subsequent error correction process of the firmware data is interrupted and reported, so that the reliability and the effectiveness of the firmware data carrying process are further ensured.
Step S404, when the error correction test of the memory to be tested is successful, error correction checking is performed on the firmware data. Please refer to step S204 in the embodiment shown in fig. 2 in detail, which is not described herein.
In step S405, when the firmware data passes the error correction check, the firmware data is transferred to the memory. Please refer to step S205 in the embodiment shown in fig. 2 in detail, which is not described herein.
According to the verification error correction method, the verification data is subjected to error injection, so that the subsequent automatic test flow is facilitated, and the reliability guarantee of the memory to be tested and corrected is further improved. By injecting errors into the error correction data, the subsequent automatic test flow is facilitated, and the reliability guarantee of the error correction memory to be tested is further improved. The error correction verification of the memory to be tested is realized by judging whether the memory to be tested triggers interruption to the error correction test set or not and whether the data modification position after error injection is judged, the reliability of the memory to be tested is ensured, the subsequent error correction of firmware data is facilitated, and the reliability and the effectiveness of the firmware data carrying flow are ensured. When the error correction memory to be tested fails the error correction test, the subsequent error correction process of the firmware data is interrupted and reported, so that the reliability and the effectiveness of the firmware data carrying process are further ensured.
In this embodiment, a method for checking and correcting errors is provided, which can be used for the above-mentioned flash memory, and fig. 5 is a flowchart of another method for checking and correcting errors according to an embodiment of the present application, as shown in fig. 5, where the flowchart includes the following steps:
in step S501, the verification data and the error correction data are burned in the flash memory. Please refer to step S401 in the embodiment shown in fig. 4 in detail, which is not described herein.
Step S502, performing software error injection on the verification data to obtain second verification data, generating an error correction test set based on the second verification data and the error correction data, or performing software error injection on the error correction data to obtain second error correction data, and generating the error correction test set based on the verification data and the second error correction data. Please refer to step S402 in the embodiment shown in fig. 4 in detail, which is not described herein.
Step S503, based on the error correction test set, performing error correction test on the memory to be tested. Please refer to step S403 in the embodiment shown in fig. 4 in detail, which is not described herein.
Step S504, when the error correction test of the memory to be tested is successful, the error correction check is carried out on the firmware data.
Specifically, the step S504 includes:
in step S5041, verification data corresponding to the firmware data is generated in the flash memory based on the firmware data.
Step S5042, comparing the firmware data with the verification data by using the error correction memory to be tested, and confirming that the firmware data passes the error correction verification when the comparison result is that the verification data is consistent with the firmware data.
In step S5043, when the comparison result is that the verification data is inconsistent with the firmware data, it is confirmed that the firmware data does not pass the error correction verification, the handling of the firmware data is interrupted, and the firmware data is reported without passing the error correction verification.
In an example, in the case that the eccengine has reliability, the fw is carried and the ecccheck is carried out, if the ecccheck passes, the fw is carried to the sram, and if the ecccheck does not pass, the reporting is interrupted to carry out corresponding processing. And respectively carrying the firmware data fw and the corresponding ecc check data into a data cache of the ecc engine and the ecc cache for ecc check by reading the firmware data and the corresponding ecc check data stored in the flash. When fw is identical to the ecc check data, it is confirmed that the firmware data fw passes the error correction check.
In this way, the error correction memory is used to correct the firmware data, so that the reliability and effectiveness in the firmware data handling process are improved. And error correction memory test is carried out before each firmware data handling flow, so that the reliability of the error correction memory is timely ensured. When the firmware data does not pass the error correction verification, the firmware data carrying process is interrupted and reported, so that the reliability and the effectiveness in the firmware data carrying process are further ensured.
In step S505, when the firmware data passes the error correction check, the firmware data is transferred to the memory. Please refer to step S405 in the embodiment shown in fig. 4 in detail, which is not described herein.
According to the verification error correction method, the error correction memory is utilized to correct the firmware data, so that the reliability and the effectiveness in the firmware data carrying process are improved. And error correction memory test is carried out before each firmware data handling flow, so that the reliability of the error correction memory is timely ensured. When the firmware data does not pass the error correction verification, the firmware data carrying process is interrupted and reported, so that the reliability and the effectiveness in the firmware data carrying process are further ensured.
In this embodiment, a device for checking and correcting errors is further provided, and the device is used for implementing the foregoing embodiments and preferred embodiments, and is not described in detail. As used below, the term "module" may be a combination of software and/or hardware that implements a predetermined function. While the means described in the following embodiments are preferably implemented in software, implementation in hardware, or a combination of software and hardware, is also possible and contemplated.
The present embodiment provides a check and error correction device, as shown in fig. 6, including:
the data writing module 601 is configured to write verification data and error correction data in the flash memory. Please refer to step S201 in the embodiment shown in fig. 2 in detail, which is not described herein.
The data error injection module 602 is configured to perform software error injection on the verification data to obtain second verification data, generate an error correction test set based on the second verification data and the error correction data, or perform software error injection on the error correction data to obtain second error correction data, and generate the error correction test set based on the verification data and the second error correction data. Please refer to step S202 in the embodiment shown in fig. 2, which is not described herein.
The error correction testing module 603 is configured to perform error correction testing on the memory to be tested based on the error correction testing set. Please refer to step S203 in the embodiment shown in fig. 2 in detail, which is not described herein.
The error correction checking module 604 is configured to perform error correction checking on the firmware data when the error correction test of the to-be-tested error correction memory is successful. Please refer to step S204 in the embodiment shown in fig. 2 in detail, which is not described herein.
The data handling module 605 is configured to handle the firmware data to the memory when the firmware data passes the error correction check. Please refer to step S205 in the embodiment shown in fig. 2 in detail, which is not described herein.
In some alternative embodiments, the data injection module 602 includes:
and the verification error injection unit is used for modifying the data of a plurality of bits in the verification data to obtain second verification data and a modification position of the second verification data.
In some alternative embodiments, the data injection module 602 includes:
and the error correction and injection unit is used for modifying the data of a plurality of bits in the error correction data to obtain second verification data and a modification position of the second verification data.
In some alternative embodiments, the error correction test module 603 includes:
the interruption judging unit is used for reading the error correction test set by using the error correction memory to be tested to carry out error correction test and judging whether the error correction memory to be tested triggers interruption or not;
the position judging unit is used for judging whether the error position determined by the memory to be tested accords with the correction testing set modification position when the memory to be tested is subjected to error correction to trigger interruption;
and the test success unit is used for confirming that the error correction test of the error correction memory to be tested is successful when the error correction memory to be tested triggers interruption and the error position determined by the memory to be tested accords with the modification position of the error correction test set.
In some alternative embodiments, the data error injection module 602 further includes:
and the test failure unit is used for confirming that the error correction test of the error correction memory to be tested fails when the error correction memory to be tested does not trigger interruption or the error position determined by the memory to be tested does not accord with the modification position of the error correction test set, confirming that the error correction memory to be tested has problems, and triggering interruption and reporting.
In some alternative embodiments, the error correction checking module 604 includes:
a check data generating unit for generating check data corresponding to the firmware data in the flash memory based on the firmware data;
and the error correction verification passing unit is used for comparing the firmware data with the verification data by utilizing the error correction memory to be detected, and confirming that the firmware data passes the error correction verification when the comparison result is that the verification data is consistent with the firmware data.
In some alternative embodiments, the error correction verification module 604 further includes:
and the error correction checking failing unit is used for confirming that the firmware data fails the error correction checking when the comparison result is that the check data is inconsistent with the firmware data, interrupting the carrying of the firmware data and reporting that the firmware data fails the error correction checking.
Further functional descriptions of the above respective modules and units are the same as those of the above corresponding embodiments, and are not repeated here.
The memory check and error correction means in this embodiment are presented in the form of functional units, here referred to as ASIC (Application Specific Integrated Circuit ) circuits, processors and memories executing one or more software or fixed programs, and/or other devices that can provide the above described functionality.
The embodiment of the application also provides a server which is provided with the memory verification error correction device shown in the figure 6.
Referring to fig. 7, fig. 7 is a schematic structural diagram of a server according to an alternative embodiment of the present application, as shown in fig. 7, the server includes: one or more processors 10, memory 20, and interfaces for connecting the various components, including high-speed interfaces and low-speed interfaces. The various components are communicatively coupled to each other using different buses and may be mounted on a common motherboard or in other manners as desired. The processor may process instructions executing within the server, including instructions stored in or on memory to display graphical information of the GUI on an external input/output device, such as a display apparatus coupled to the interface. In some alternative embodiments, multiple processors and/or multiple buses may be used, if desired, along with multiple memories and multiple memories. Also, multiple servers may be connected, with each device providing a portion of the necessary operations (e.g., as a server array, a set of blade servers, or a multiprocessor system). One processor 10 is illustrated in fig. 7.
The processor 10 may be a central processor, a network processor, or a combination thereof. The processor 10 may further include a hardware chip, among others. The hardware chip may be an application specific integrated circuit, a programmable logic device, or a combination thereof. The programmable logic device may be a complex programmable logic device, a field programmable gate array, a general-purpose array logic, or any combination thereof.
Wherein the memory 20 stores instructions executable by the at least one processor 10 to cause the at least one processor 10 to perform the methods shown in implementing the above embodiments.
The memory 20 may include a storage program area that may store an operating system, at least one application program required for functions, and a storage data area; the storage data area may store data created according to the use of the server, etc. In addition, the memory 20 may include high-speed random access memory, and may also include non-transitory memory, such as at least one magnetic disk storage device, flash memory device, or other non-transitory solid-state storage device. In some alternative embodiments, memory 20 may optionally include memory located remotely from processor 10, which may be connected to the server via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
Memory 20 may include volatile memory, such as random access memory; the memory may also include non-volatile memory, such as flash memory, hard disk, or solid state disk; the memory 20 may also comprise a combination of the above types of memories.
The server also includes a communication interface 30 for the server to communicate with other devices or communication networks.
The embodiments of the present application also provide a computer readable storage medium, and the method according to the embodiments of the present application described above may be implemented in hardware, firmware, or as a computer code which may be recorded on a storage medium, or as original stored in a remote storage medium or a non-transitory machine readable storage medium downloaded through a network and to be stored in a local storage medium, so that the method described herein may be stored on such software process on a storage medium using a general purpose computer, a special purpose processor, or programmable or special purpose hardware. The storage medium can be a magnetic disk, an optical disk, a read-only memory, a random access memory, a flash memory, a hard disk, a solid state disk or the like; further, the storage medium may also comprise a combination of memories of the kind described above. It will be appreciated that a computer, processor, microprocessor controller or programmable hardware includes a storage element that can store or receive software or computer code that, when accessed and executed by the computer, processor or hardware, implements the methods illustrated by the above embodiments.
Although embodiments of the present application have been described in connection with the accompanying drawings, various modifications and variations may be made by those skilled in the art without departing from the spirit and scope of the application, and such modifications and variations fall within the scope of the application as defined by the appended claims.
Claims (10)
1. A method of checking and correcting errors, the method comprising:
burning verification data and error correction data in the flash memory;
performing software error injection on the verification data to obtain second verification data, generating an error correction test set based on the second verification data and the error correction data, or performing software error injection on the error correction data to obtain second error correction data, and generating an error correction test set based on the verification data and the second error correction data;
performing error correction testing on the memory to be tested based on the error correction testing set;
when the error correction test of the to-be-tested error correction memory is successful, carrying out error correction check on the firmware data;
and carrying the firmware data to a memory when the firmware data passes the error correction check.
2. The method of claim 1, wherein performing software fault injection on the verification data to obtain second verification data comprises:
and modifying the data of a plurality of bits in the verification data to obtain the second verification data and a modification position of the second verification data.
3. The method of claim 1, wherein performing software error injection on the error correction data to obtain second error correction data comprises:
and modifying the data of a plurality of bits in the error correction data to obtain the second error correction data and a modification position of the second error correction data.
4. The method of claim 1, wherein performing an error correction test on the memory to be tested based on the set of error correction tests comprises:
the error correction test set is read by the error correction memory to be tested to carry out error correction test, and whether the error correction memory to be tested triggers interruption or not is judged;
when the error correction memory to be tested triggers interruption, judging whether the error position determined by the memory to be tested accords with the modification position of the error correction test set;
and when the to-be-tested error correction memory triggers interruption and the error position determined by the to-be-tested memory accords with the modification position of the error correction test set, confirming that the error correction test of the to-be-tested error correction memory is successful.
5. The method of claim 4, wherein when the error correction memory to be tested does not trigger an interrupt or the error location determined by the memory to be tested does not conform to the modified location of the error correction test set, confirming that the error correction test of the memory to be tested fails, confirming that the memory to be tested has a problem, and triggering an interrupt report.
6. The method of claim 1, wherein said error correction checking of firmware data comprises:
generating check data corresponding to the firmware data in the flash memory based on the firmware data;
and comparing the firmware data with the check data by using the to-be-tested error correction memory, and confirming that the firmware data passes error correction check when the comparison result is that the check data is consistent with the firmware data.
7. The method according to claim 1, wherein when the comparison result is that the verification data is inconsistent with the firmware data, confirming that the firmware data does not pass an error correction verification, interrupting the handling of the firmware data, and reporting that the firmware data does not pass the error correction verification.
8. A verification and error correction device, the device comprising:
the data burning module is used for burning verification data and error correction data in the flash memory;
the data error injection module is used for performing software error injection on the verification data to obtain second verification data, generating an error correction test set based on the second verification data and the error correction data, or performing software error injection on the error correction data to obtain second error correction data, and generating the error correction test set based on the verification data and the second error correction data;
the error correction testing module is used for carrying out error correction testing on the memory to be tested based on the error correction testing set;
the error correction checking module is used for carrying out error correction checking on the firmware data when the error correction test of the to-be-tested error correction memory is successful;
and the data handling module is used for handling the firmware data to the memory when the firmware data pass the error correction verification.
9. A server, comprising:
a memory and a processor, the memory and the processor being communicatively connected to each other, the memory having stored therein computer instructions, the processor executing the computer instructions to perform the method of checking and correcting errors of any one of claims 1 to 7.
10. A computer-readable storage medium having stored thereon computer instructions for causing a computer to perform the check and error correction method of any one of claims 1 to 7.
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