CN117233571A

CN117233571A - Test circuit, test system, test method and semiconductor chip

Info

Publication number: CN117233571A
Application number: CN202210641209.0A
Authority: CN
Inventors: 侯闯明
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2022-06-08
Filing date: 2022-06-08
Publication date: 2023-12-15

Abstract

The application provides a test circuit, a test system, a test method and a semiconductor chip, wherein the test circuit comprises a ring oscillation module, a bias module and a delay module; the ring oscillation module comprises an odd number of first reversing units, and each first reversing unit comprises a transistor; the signal input end of the delay module is used for receiving the enabling signal, and the delay module is used for delaying the received enabling signal by preset time and outputting the enabling signal to the enabling input end of the ring oscillation module through the signal output end of the delay module; the signal input end of the bias module is connected with the signal input end of the delay module; the bias module is used for generating a bias pulse signal according to the received enabling signal and outputting the bias pulse signal to a bias control end of the ring oscillation module through a bias output end, and the bias pulse signal is used for adjusting the threshold voltage of the transistor when the first reverse unit is subjected to level inversion. The application can improve the accuracy of the effective driving current test of the ring oscillation module.

Description

Test circuit, test system, test method and semiconductor chip

Technical Field

The present application relates to the field of integrated circuits, and more particularly, to a test circuit, a test system, a test method, and a semiconductor chip.

Background

The Ring Oscillator (RO) is applied to an integrated circuit, can provide high-frequency oscillation for the integrated circuit, and has the characteristics of simple circuit, easy oscillation starting and convenient integration.

The ring oscillator comprises a plurality of NOT circuits, the output ends and the input ends of the NOT circuits are sequentially connected end to form a ring circuit, and the number of the NOT circuits is generally an odd number. The NOT gate employs a CMOS (Complementary Metal Oxide Semiconductor ) structure that includes an N-type metal oxide transistor (NMOS) and a P-type metal oxide transistor (PMOS). After the input end of the ring oscillator inputs signals, the signals are subjected to multiple times of level and low level conversion to generate oscillation through a multi-stage NOT circuit. Testing the effective drive current and drive Voltage (VDD) of a ring oscillator is employed in the related art to determine the equivalent capacitance of the ring oscillator.

However, the accuracy of the effective drive current test in the related art is low, affecting the accuracy of the determined equivalent capacitance of the ring oscillator.

Disclosure of Invention

The test circuit, the test system, the test method and the semiconductor chip provided by the application can improve the accuracy of the effective driving current test of the ring oscillation module, thereby being beneficial to improving the accuracy of the equivalent capacitance of the determined ring oscillator.

In order to achieve the above object, in a first aspect, the present application provides a test circuit, including a ring oscillation module, a bias module, and a delay module;

the ring oscillation module comprises an enabling input end and a bias control end, the ring oscillation module comprises an odd number of first reversing units, the odd number of first reversing units are sequentially cascaded, and each first reversing unit comprises a transistor;

the delay module comprises a signal input end and a signal output end, wherein the signal input end of the delay module is used for receiving an enabling signal, and the delay module is used for delaying the received enabling signal by a preset time and outputting the enabling signal to the enabling input end of the ring oscillation module through the signal output end of the delay module;

the bias module comprises a signal input end and a bias output end, and the signal input end of the bias module is connected with the signal input end of the delay module and is used for receiving an enabling signal; the bias module is used for generating a bias pulse signal according to the received enabling signal and outputting the bias pulse signal to a bias control end of the ring oscillation module through a bias output end, and the bias pulse signal is used for adjusting the threshold voltage of the transistor when the first reverse unit is subjected to level inversion.

In the above test circuit, optionally, the bias module includes a ring oscillation unit and a pulse generation unit, and the pulse generation unit includes a bias output end;

The ring oscillation unit comprises a signal input end, the signal input end of the ring oscillation unit is connected with the signal input end of the delay module and is used for generating an oscillation signal when receiving an enabling signal, and the ring oscillation unit is used for outputting a modulation signal to the pulse generation unit when generating the oscillation signal;

the pulse generating unit comprises the bias output end, the pulse generating unit is used for generating a bias pulse signal according to the modulation signal and outputting the bias pulse signal to the bias control end of the ring oscillation module through the bias output end, and the body end of the transistor of the first reversing unit is used as the bias control end of the ring oscillation module.

In the above test circuit, optionally, the ring oscillation unit includes an odd number of second inversion units, and the odd number of second inversion units are cascaded in turn, and each second inversion unit includes a transistor.

In the above test circuit, optionally, the odd number of second inverting units include a second nand gate and an even number of second not gates cascaded in sequence, a first signal input end of the second nand gate is used as a signal input end of the ring oscillation unit, a signal output end of the second nand gate is connected with a signal input end of the first stage second not gate, and a second signal input end of the second nand gate is connected with a signal output end of the last stage second not gate;

In the above test circuit, optionally, each second nand gate includes a third transistor and a fourth transistor of different types, the first power supply terminal of the second nand gate and the first terminal of the third transistor are connected to the third voltage terminal, and the second power supply terminal of the second nand gate and the first terminal of the fourth transistor are connected to the fourth voltage terminal;

in the same second NOT gate, the second end of the third transistor is connected with the second end of the fourth transistor and is used as the signal output end of the corresponding second NOT gate, and the control end of the third transistor is connected with the control end of the fourth transistor and is used as the signal input end of the corresponding second NOT gate.

In the above test circuit, optionally, the odd number of first inverting units include a first nand gate and an even number of first not gates cascaded in sequence, a first signal input end of the first nand gate is used as an enabling input end of the ring oscillation module, a signal output end of the first nand gate is connected with a signal input end of the first stage first not gate, and a second signal input end of the first nand gate is connected with a signal output end of the last stage first not gate;

and the signal output end of the first NOT gate of the last stage is used as the signal output end of the ring oscillation module.

Wherein the number of the first NOT gates is equal to the number of the second NOT gates.

In the above test circuit, optionally, each of the first nand gates includes a first transistor and a second transistor of different types, a first power supply terminal of the first nand gate and a first terminal of the first transistor are connected to a first voltage terminal, and a second power supply terminal of the first nand gate and a first terminal of the second transistor are connected to a second voltage terminal;

in the same first NOT gate, the second end of the first transistor is connected with the second end of the second transistor and is used as the signal output end of the corresponding first NOT gate; the control end of the first transistor is connected with the control end of the second transistor and serves as a signal input end of the corresponding first NOT gate.

In the above-described test circuit, the pulse generating unit may optionally include an even number of pulse generating sub-units,

each pulse generation subunit is respectively connected with the second reversing unit and the first reversing unit in a one-to-one correspondence manner, and is used for generating a corresponding bias pulse signal according to a modulation signal generated by the correspondingly connected second reversing unit and outputting the bias pulse signal to the body end of the transistor of the correspondingly connected first reversing unit;

Wherein the number of pulse generating subunits, the number of first NOT gates and the number of second NOT gates are all equal.

In the above test circuit, optionally, each pulse generating subunit includes a pulse logic gate and a pulse not gate, where a first power supply end of the pulse logic gate and a first power supply end of the pulse not gate are both connected to the third voltage end, and a second power supply end of the pulse logic gate and a second power supply end of the pulse not gate are both connected to the fourth voltage end;

the first signal input end of the pulse logic gate is connected to the signal input end of the second NOT gate corresponding to the pulse generation subunit, and the second signal input end of the pulse logic gate is connected to the signal output end of the second NOT gate corresponding to the pulse generation subunit;

the signal output end of the pulse logic gate is connected with the signal input end of the pulse NOT gate, and the signal output end of the pulse NOT gate is used as the bias output end of the corresponding pulse generation subunit and is connected with the body end of the transistor of one first reversing unit corresponding to the pulse generation subunit.

In the above test circuit, optionally, the first transistor and the third transistor are PMOS transistors, and the second transistor and the fourth transistor are NMOS transistors.

In the above test circuit, optionally, the pulse logic gate is a nand gate, and the bias output terminal is connected to the body terminal of the first transistor;

the voltage value of the first voltage terminal is a, the voltage value of the third voltage terminal is a1, the voltage value of the fourth voltage terminal is a2, and the formulas are satisfied by a, a1 and a 2: a2 =a, a1=2a; the second voltage is grounded.

In the above test circuit, optionally, the pulse logic gate is a nor gate, and the bias output terminal is connected to the body terminal of the second transistor;

the voltage value of the first voltage terminal is b, the voltage value of the fourth voltage terminal is b1, and b1 satisfy the formula: b1 = -b, and b > 0; the second voltage terminal and the third voltage terminal are grounded.

In the above test circuit, optionally, the delay module includes at least two delay not gates, at least two delay not gates are cascaded in sequence, and a signal input end of the first stage delay not gate is connected with a signal input end of the bias module, and is used for receiving the enabling signal;

the signal output end of the last stage of delay NOT gate is connected with the enabling input end of the ring oscillation module;

the delay module is used for generating an enabling signal with preset delay time according to the enabling signal and outputting the enabling signal to the enabling input end, and the enabling signal with preset delay time is used for controlling an oscillating signal generated by the ring oscillating module to lag behind the oscillating signal generated by the ring oscillating unit so that when the first reverse unit of the ring oscillating module turns in level, the offset pulse signal is received.

In the above test circuit, optionally, the delay module further includes a delay capacitor, a first electrode of the delay capacitor is connected between any two delay not gates, and a second electrode of the delay capacitor is connected to the third voltage terminal.

In a second aspect, the present application provides a test system, including a signal generating circuit, a test device and the test circuit, where an enable signal output end of the signal generating circuit is connected to a signal input end of a bias module of the test circuit, and an enable signal output end is connected to an enable input end of a ring oscillation module of the test circuit through a delay module of the test circuit.

The test system described above, optionally, further includes a frequency dividing element, where the frequency dividing element is connected to the signal output end of the ring oscillation module of the test circuit.

The test system described above, optionally, further includes an output buffer element, where the output buffer element is connected to the signal output end of the frequency dividing element.

In a third aspect, the present application provides a testing method for the above testing system, where the testing method includes:

loading an enable signal to the test circuit;

acquiring a current value of a first voltage end of a ring oscillation module of a test circuit and an oscillation frequency of an oscillation signal generated by the ring oscillation module;

Determining an effective driving current of the ring oscillation module according to the current value of the first voltage end;

and determining the equivalent capacitance and the equivalent resistance of the transistor of the first reverse unit of the ring oscillation module according to the effective driving current and the oscillation frequency.

In a fourth aspect, the present application provides a semiconductor chip, including the test system described above.

According to the test circuit, the test system, the test method and the semiconductor chip, the bias module is arranged in the test circuit, the bias module is utilized to generate the bias pulse signal according to the enabling signal, and the bias pulse signal is output to the body end of the transistor of the first reverse unit of the ring oscillation module through the bias output end of the bias module. The delay module is arranged in the test circuit, the enabling signal of the bias module is delayed for a preset time and then is output to the ring oscillation module, the time of the bias pulse signal generated by enabling the bias module is earlier than the time of the ring oscillation module for generating the oscillation signal, the time of the bias pulse signal reaching the ring oscillation module can be controlled by controlling the delay time of the enabling signal, namely, when the first reverse unit of the ring oscillation module turns over in level, the bias pulse signal reaches the transistor of the first reverse unit of the ring oscillation module, the threshold voltage of the transistor is regulated through the received bias pulse signal, and the problem of leakage current caused by simultaneous conduction of the transistor in the first reverse unit during level turning over is avoided, so that the condition that the effective driving current of the tested ring oscillation module is larger is avoided, the accuracy of a test result is ensured, and the accuracy of the equivalent capacitance of the ring oscillation module determined according to the test result is further ensured.

The construction of the present application and other objects and advantages thereof will be more readily understood from the description of the preferred embodiment taken in conjunction with the accompanying drawings.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic diagram of a test system according to an embodiment of the present application;

FIG. 2 is a schematic diagram of a ring oscillator module and a signal generating circuit of a test system according to an embodiment of the present application;

FIG. 3 is a schematic diagram illustrating a first NOT gate of a ring oscillator module of a test system according to an embodiment of the present application;

FIG. 4 is a schematic diagram of a test circuit according to an embodiment of the present application;

FIG. 5 is a schematic diagram of another circuit connection between a bias module and a first NOT in a test circuit according to an embodiment of the present application;

FIG. 6 is a schematic diagram of a bias module of a test circuit according to an embodiment of the present application;

FIG. 7 is a schematic diagram of circuit connection of a first NOT of a test circuit according to an embodiment of the present application;

FIG. 8 is a schematic diagram of circuit connection of a pulse generation subunit of a test circuit according to an embodiment of the present application;

FIG. 9 is a timing diagram of a test circuit according to an embodiment of the present application;

FIG. 10 is a schematic diagram of a delay module of a test circuit according to an embodiment of the present application;

FIG. 11 is a schematic diagram of another test circuit according to an embodiment of the present application;

FIG. 12 is a schematic diagram of a bias module of another test circuit according to an embodiment of the present application;

FIG. 13 is a schematic diagram illustrating a circuit connection of a first NOT of another test circuit according to an embodiment of the present application;

FIG. 14 is a schematic diagram showing the circuit connection of pulse generation subunits of another test circuit according to an embodiment of the present application;

FIG. 15 is a timing diagram of another test circuit according to an embodiment of the present application;

FIG. 16 is a schematic diagram of an oscillation signal output by a ring oscillation module according to an embodiment of the present application;

fig. 17 is a flow chart of a test method according to an embodiment of the present application.

Reference numerals illustrate:

100. a ring oscillation module; 101. a first NAND gate; 102. a first NOT gate; 102a, a first transistor; 102b, a second transistor; 200. a bias module; 201. a ring oscillation unit; 2011. a second NAND gate; 2012. a second NOT gate; 202. a pulse generation unit; 2021. a pulse generation subunit; 2021a, pulsed logic gates; 2021b, pulsed NOT; 300. a delay module; 301. a delay NOT gate; 302. a delay capacitor; 302a, a first electrode; 302b, a second electrode; A. a first voltage terminal; B. a second voltage terminal; C. a third voltage terminal; D. a fourth voltage terminal; 400. a signal generating circuit; 500. a testing device; 600. a frequency dividing element; 700. an output buffer element; 800. and an oscillation signal output terminal.

Detailed Description

The inventors of the present application found in the course of practical studies that a ring oscillator includes a plurality of inverter circuits connected end to end in sequence and forming a ring circuit. The NOT circuit includes NMOS and PMOS. In the related art, an enable signal (EN signal) is generated by an Address circuit (Address circuit), and the enable signal is used to control a corresponding ring oscillator to generate oscillation. By measuring a first current flowing into a driving voltage end of the ring oscillator when the ring oscillator is static and generating a second current flowing into the driving voltage end when the ring oscillator is oscillating, the difference value of the first current and the second current is the effective driving current of the ring oscillator. And determining the equivalent resistance of the ring oscillator according to the effective driving current and the driving voltage value of the driving voltage end, and further determining the equivalent capacitance of the ring oscillator according to the driving current, the period of the oscillating alternating current signal and the equivalent resistance. In some embodiments, the equivalent capacitance in CMOS of a single not gate in a ring oscillator may be analyzed based on the equivalent capacitance of the ring oscillator, thereby analyzing the relationship of the equivalent capacitance of CMOS to the ion doping of CMOS. According to the method, guidance significance is provided for the preparation of the actual ring oscillator.

However, in the ring oscillator in the related art, when level inversion occurs, there is an additional driving current for the transistor in the not gate. Specifically, when the input end level of the preceding stage of NOT gate in the multi-stage NOT gate is changed from high to low, the PMOS in the preceding stage of NOT gate is gradually turned on, and current flows in the PMOS. The current passing through the PMOS drives the gate of the NMOS of the next stage of the not gate circuit to a high level. However, in the process that the input terminal level of the previous stage NOT circuit is changed from high to low, the PMOS in the previous stage NOT circuit is turned on, but the NMOS is not completely turned off, and there is a part of extra leakage current that enters the ground GND through the NMOS that is not turned off yet. The current through the NMOS will be superimposed in the effective drive current driving the next stage of the not gate, resulting in an effective drive current detected at the VDD terminal that is higher than the actual effective drive current required to drive the next stage of the not gate. The measured value of the effective driving current is larger, so that the equivalent resistance of the ring oscillator is smaller, the equivalent capacitance is larger, and the influence of ion doping of the CMOS on the equivalent capacitance cannot be accurately analyzed according to the equivalent capacitance.

Or when the level of the input end of the preceding stage NOT circuit in the multi-stage NOT circuits is changed from low to high, the NMOS in the preceding stage NOT circuit is gradually started, and current flows in the NMOS. The current passing through the NMOS drives the high level of the common gate of the next stage of the not gate gradually down to zero. However, in the process that the level of the input end of the previous stage NOT gate is changed from low to high, the NMOS in the previous stage NOT gate is turned on, but the PMOS is not completely turned off, and a part of extra leakage current passes through the PMOS which is not turned off and enters the ground GND through the NMOS. The current through the PMOS will be superimposed in the effective drive current driving the next stage of the not gate, resulting in an effective drive current detected at the VDD terminal that is higher than the actual effective drive current required to drive the next stage of the not gate. The measured value of the effective driving current is larger, so that the equivalent resistance of the ring oscillator is smaller, the equivalent capacitance is larger, and the influence of ion doping of the CMOS on the equivalent capacitance cannot be accurately analyzed according to the equivalent capacitance.

In view of this, the test circuit, the test system, the test method and the semiconductor chip provided in the embodiments of the present application are configured such that a bias module is disposed in the test circuit, a bias pulse signal is generated by using the bias module according to an enable signal, and the bias pulse signal is output to a body terminal of a transistor of a first inverting unit of the ring oscillation module through a bias output terminal of the bias module. And the delay module is arranged in the test circuit, and the enabling signal of the bias module is delayed for a preset time and then output to the ring oscillation module. The time of the bias pulse signal which is enabled to be generated by the bias module is earlier than the time of the oscillation signal which is generated by the ring oscillation module, the time when the bias pulse signal reaches the ring oscillation module can be controlled by controlling the delay time of the enabling signal, namely, when the first reverse unit of the ring oscillation module turns over in level, the bias pulse signal reaches the transistor of the first reverse unit of the ring oscillation module, the threshold voltage of the transistor is regulated by the received bias pulse signal, and the leakage current which is generated by the simultaneous conduction of the transistor in the first reverse unit during the level turning over is avoided, so that the condition that the effective driving current of the tested ring oscillation module is larger is avoided, the accuracy of a test result is ensured, and the accuracy of the equivalent capacitance test of the ring oscillation module which is determined according to the test result is further ensured. In this way, the effect of ion doping of the CMOS on the equivalent capacitance can be determined from the detected equivalent capacitance.

In order to make the objects, technical solutions and advantages of the present application more apparent, the technical solutions in the preferred embodiments of the present application will be described in more detail with reference to the accompanying drawings in the preferred embodiments of the present application. In the drawings, the same or similar reference numerals refer to the same or similar components or components having the same or similar functions throughout. The described embodiments are some, but not all, embodiments of the application. The embodiments described below by referring to the drawings are illustrative and intended to explain the present application and should not be construed as limiting the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application. Embodiments of the present application will be described in detail below with reference to the accompanying drawings.

Fig. 1 is a schematic structural diagram of a test system according to an embodiment of the present application, fig. 2 is a schematic structural diagram of a ring oscillation module and a signal generating circuit of the test system according to an embodiment of the present application, and fig. 3 is a schematic structural diagram of a first not gate of the ring oscillation module of the test system according to an embodiment of the present application. Referring to fig. 1 to 3, an embodiment of the present application provides a test system, which includes an enable signal generating circuit 400, a test device 500 and a test circuit, wherein an enable signal end of the signal generating circuit 400 is connected to a signal input end of a bias module 200 of the test circuit, and the enable signal end is connected to an enable input end of a ring oscillation module 100 of the test circuit through a delay module 300 of the test circuit; the test device 500 is connected to the first voltage terminal VDD of the test circuit.

The Signal generating circuit 400 may be an Address circuit (Address circuit) shown in fig. 1, and the Address circuit may generate an enable Signal (EN Signal) from the Address Signal after acquiring the Address Signal (Address Signal). The enable signal may be output to the test circuit through an enable signal terminal of the signal generating circuit 400. Referring to fig. 2, the enable signal terminal is connected to the enable input terminal of the ring oscillator module 100 of the test circuit. In some embodiments, the signal generation circuit 400 may also be a command decoding module.

Fig. 4 is a schematic structural diagram of a test circuit according to an embodiment of the present application, and referring to fig. 4, an enable signal end is connected to a signal input end of a bias module 200 of the test circuit, the enable signal end is connected to an enable input end of a ring oscillation module 100 of the test circuit through a delay module 300 of the test circuit, and an enable signal of the enable signal end is output to the ring oscillation module 100 after being delayed by a preset time by the delay module 300. In the test circuit, the ring oscillation module 100 generates an oscillation signal according to the delayed enable signal.

The first voltage terminal VDD of the test circuit is connected to the test device 500, and the test device 500 may be a current measuring device, such as a current sensor. The test device 500 may measure the current flowing through the first voltage terminal VDD to determine the effective driving current of the ring oscillator module 100 in the test circuit during operation according to the current of the first voltage terminal VDD. The test device 500 may be a test apparatus external to the test circuit or may be a current test circuit integrated in the test circuit.

In some embodiments, the test system may further include a frequency dividing element 600 (Frequency divider), where the frequency dividing element 600 is connected to the signal output end of the ring oscillator module 100 of the test circuit. The signal output terminal of the ring oscillation module 100 outputs an oscillation signal, and the frequency dividing element 600 may be used to perform a frequency division process on the oscillation signal. The first power supply terminal of the frequency dividing element 600 is connected to the power supply terminal VCC.

In some embodiments, the test system may further include an output buffer element 700, where the output buffer element 700 is connected to the signal output end of the frequency dividing element 600. The output buffer element 700 may be used to adjust the waveform of the oscillation signal subjected to the frequency division process. Fig. 16 is a schematic diagram of an oscillating signal output by a ring oscillation module according to an embodiment of the present application, and fig. 16 shows waveforms of an oscillating signal processed by a frequency dividing element 600 and an output buffer element 700 according to the present application.

The output buffer element 700 may include two buffers connected in series to the signal output terminal of the frequency dividing element 600. The first power terminals of both buffers are connected to the power supply terminal VCC, and the signal output terminal of the output buffer element 700 is connected to the oscillation signal output terminal 800 (Frequency output) of the test system.

Further, the oscillation frequency (oscillation period) of the oscillation signal output from the oscillation signal output terminal 800 may be tested, and the equivalent capacitance and the equivalent resistance of the transistor in the ring oscillation module 100 may be computationally determined based on the oscillation frequency (oscillation period) and the effective driving current. The oscillation frequency (oscillation period) of the oscillation signal can also be obtained by the test device 500.

The following describes the test circuit in the test system in detail.

The embodiment of the application provides a test circuit, which comprises a ring oscillation module 100, a bias module 200 and a delay module 300. The ring oscillation module 100 includes an enable input terminal and a bias control terminal, and the ring oscillation module 100 includes an odd number of first inversion units, each including a transistor, which are sequentially cascaded.

The delay module 300 includes a signal input end and a signal output end, the signal input end of the delay module 300 is used for receiving an enable signal, and the delay module 300 is used for delaying the received enable signal by a preset time and outputting the delayed enable signal to the enable input end of the ring oscillation module 100 through the signal output end of the delay module 300.

The bias module 200 includes a signal input end and a bias output end, and the signal input end of the bias module 200 is connected with the signal input end of the delay module 300, and is used for receiving an enabling signal; the bias module 200 is configured to generate a bias pulse signal according to the received enable signal, and output the bias pulse signal to a bias control terminal of the ring oscillation module 100 through a bias output terminal, where the bias pulse signal is used to adjust a threshold voltage of the transistor when the first inversion unit performs level inversion.

It should be noted that, as shown in fig. 2, 3 and 4, the odd number of first inverting units in the ring oscillation module 100 includes a first NAND gate 101 (NAND 2) and an even number of first NAND gates 102 (INV) cascaded in sequence, and a first signal input terminal 101c (shown in fig. 4) of the first NAND gate 101 is used as an enable input terminal of the ring oscillation module 100, and the enable input terminal is connected to a signal output terminal of the delay module 300 and is used for receiving an enable signal delayed by the delay module 300 for a delay preset time. The signal output end of the first nand gate 101 is connected with the signal input end of the first nand gate 102 of the first stage, and the signal output end of the first nand gate 102 of the last stage is connected with the second signal input end of the first nand gate 101, so that the oscillating signal output by the first nand gate 102 of the last stage is output to the second signal input end of the first nand gate 101 to form a loop cycle of the oscillating signal. It should be noted that the first not gate 102 may be replaced by a controllable not gate or a nand gate.

And, the signal output end of the first NOT gate 102 of the last stage is used as the signal output end of the ring oscillation module 100 for outputting the oscillation signal of the ring oscillation module 100.

It should be noted that "first-stage first not gate 102" refers to a first not gate 102 connected at the first position among the plurality of first not gates 102 in the sequential cascade order, and "last-stage not gate" refers to a first not gate 102 connected at the last position among the plurality of first not gates 102 in the sequential cascade order. The explanation of the "first stage" and "last stage" in the following is similar to this, and will not be repeated. The even number of the first not gates 102 may be 6 as shown in fig. 2 or 4 as shown in fig. 4, and the specific number of the first not gates 102 is not limited in this embodiment.

Fig. 7 is a schematic circuit connection diagram of a first not gate of a test circuit according to an embodiment of the present application. Referring to fig. 4 and 7, the structure of the first not gate 102 may be as follows: each of the first not gates 102 includes a first transistor 102a and a second transistor 102B of different types, the first power supply terminal 101a of the first not gate 101 and the first terminal 102aa of the first transistor 102a are connected to the first voltage terminal a, and the second power supply terminal 101B of the first not gate 101 and the first terminal 102bb of the second transistor 102B are connected to the second voltage terminal B. In the test circuit, the voltage value of the first voltage terminal a may be VCC1.

Referring to fig. 7, in the ring oscillation module 100, the first transistor 102a is a PMOS transistor, and the second transistor 102b is an NMOS transistor. In the same first not gate 102, the second terminal 102ab of the first transistor 102a (PMOS) is connected to the second terminal 102ba of the second transistor 102b (NMOS) and serves as a signal output terminal 102d of the corresponding first not gate 102, and the signal output terminal 102d of the first not gate 102 may be used to connect to a signal input terminal 102c (shown in fig. 4) of a first not gate 102 of a next stage or to the second signal input terminal 101d of the first not gate 101 and serves as a signal output terminal of the ring oscillation module 100. The control terminal 102ac of the first transistor 102a is connected to the control terminal 102bc of the second transistor 102b and serves as a signal input terminal 102c of the corresponding first not gate 102, which may be used to connect to the signal output terminal of the first not gate 102 of the previous stage or to the signal output terminal 101e of the first not gate 101.

Illustratively, referring to fig. 4, the present embodiment is illustrated with four first not gates 102 cascaded in sequence, where the four first not gates 102 are the first not gate 102-1 of the first stage, the first not gate 102-2 of the second stage, the first not gate 102-3 of the third stage, and the first not gate 102-4 of the fourth stage, respectively. The signal input terminal 102c of the first NOT gate 102-1 of the first stage and the signal output terminal 101e of the first NAND gate 101, the signal output terminal 102d of the first NOT gate 102-1 of the first stage is connected to the signal input terminal 102c of the first NOT gate 102-2 of the second stage, and so on, the signal output terminal 102d of the first NOT gate 102-4 of the fourth stage is connected to the second signal input terminal 101d of the first NAND gate 101 and serves as the signal output terminal of the ring oscillation module 100.

Referring to fig. 4, the bias module 200 in this embodiment includes a bias output terminal, where a signal input terminal of the bias module 200 is connected to a signal input terminal of the delay module 300, that is, to an enable signal terminal of the signal generating circuit 400, and the signal input terminal of the bias module 200 is configured to receive an enable signal. The signal output of the bias module 200 is connected to the bias control terminal of the ring oscillation module 100. Based on having multiple stages of first NOT gates 102 in the ring oscillation module 100, each first NOT gate 102 may be provided with a bias control terminal.

In this embodiment, the connection manner between the signal output end of the bias module 200 and the bias control end of the multi-stage first not gate 102 may include the following two ways:

referring to fig. 4, as a first connection method, the number of signal output terminals of the bias module 200 may be correspondingly plural, and the signal output terminals of the bias modules 200 are connected to each other and then correspondingly connected to the bias control terminals of the multi-stage first not gate 102, and the multi-stage first not gate 102 receives the bias pulse signal output by the bias module 200. In the first connection, the signals at the signal outputs of the plurality of bias modules 200 are shared, and the multi-stage first NOT gate 102 is controlled.

Fig. 5 is a schematic diagram of another circuit connection between a bias module and a first not gate in a test circuit according to an embodiment of the present application. Referring to fig. 5, as a second connection method, a plurality of signal output terminals of the bias modules 200 may be correspondingly provided, and the signal output terminals of the bias modules 200 are connected to the bias control terminals of the multi-stage first not gate 102 in a one-to-one correspondence manner, so as to respectively receive the bias pulse signals output by the bias modules 200. In the second connection, the signals at the signal outputs of the bias modules 200 are not shared, and the multi-stage first NOT gates 102 are controlled respectively.

The delay module 300 in this embodiment is connected between the signal generating circuit 400 and the ring oscillation module 100, and is configured to delay the enable signal output by the enable signal to generate an enable signal delayed by a preset time, and output the enable signal to an enable input end of the ring oscillation module 100. The enable signal delayed by a preset time is used to control the oscillation signal generated by the ring oscillation module 100 to lag behind the oscillation signal generated by the ring oscillation unit 201, so that the bias pulse signal is received when the first inversion unit of the ring oscillation module 100 performs level inversion.

When the test circuit works, the enable input end of the ring oscillation module 100 receives an enable signal with a delay preset time which is subjected to delay processing by the delay module 300, and the enable signal with the delay preset time forms an oscillation signal through the first NAND gate 101 and the multi-stage first NAND gate 102. In the generation of the oscillation signal, the first inverting unit may undergo a plurality of level flipping processes. At each level inversion, the multi-stage first not gate 102 may not only receive the output signal of the previous stage first not gate 102 to ensure that the level inversion is completed, but also may receive the bias pulse signal of the bias unit through the bias control unit. The bias pulse signal may be output to a bias control terminal of the first not gate 102, for adjusting a threshold voltage of a transistor in the first not gate 102 during a period when the level of the first not gate 102 is inverted.

It should be explained that, during the level inversion of the first not gate 102, one of the two transistors (e.g. NMOS) is gradually turned on, and the other of the two transistors (e.g. PMOS) is turned off in advance due to the increase of the threshold voltage, so that the two transistors are prevented from being turned on simultaneously during the level inversion, and the problem of leakage current is avoided.

Based on that the first transistor 102a and the second transistor 102b are both MOS transistors, the threshold voltage of the adjustment transistor in this embodiment may be an absolute value of the threshold voltage of the increase transistor, when the bias pulse signal reaches the non-conductive transistor (the transistor that is gradually turned off in the level inversion process), the absolute value of the threshold voltage of the non-conductive transistor increases, and when the conductive transistor (the transistor that is gradually turned on in the level inversion process) is gradually turned on, the absolute value of the gate-source bias voltage Vgs of the non-conductive transistor is in the off state in advance because it is smaller than the absolute value of the increased threshold voltage, and no leakage current passes through the conductive transistor and the non-conductive transistor.

For example, as shown in fig. 7, for the process of the level of the first not gate 102 being turned over from 1 to 0, the first transistor 102a (PMOS) is turned on gradually, the second transistor 102b (NMOS) is turned off gradually, when VCC1 is 2V and the threshold voltages of the first transistor 102a (PMOS) and the second transistor 102b (NMOS) are both 0.7V, when the voltages of the control terminal 102ac of the first transistor 102a and the control terminal 102bc of the second transistor 102b are gradually reduced from high level 1 (2V) to low level 0 (0V), there is a moment when the first transistor 102a (PMOS) and the second transistor 102b (NMOS) are simultaneously turned on, specifically, when the input terminal voltage is reduced from 1.3V to 0.7V, the absolute values of the gate voltages Vgs of the first transistor 102a (PMOS) and the second transistor 102b (NMOS) with respect to the bias voltage Vgs of the source are both greater than the threshold voltages 0.7V, PMOS 102a and NMOS 102b are simultaneously turned on, resulting in leakage current.

According to the present application, when the bias pulse signal generated by the bias module 200 reaches the transistor at the time of level inversion, specifically, when the level of the first not gate 102 is inverted from 1 to 0, the bias pulse signal lower than 0V reaches the body terminal of the second transistor 102b (NMOS) when the level starts to be inverted, the threshold voltage of the second transistor 102b (NMOS) gradually increases from 0.7V to 1.4V, and during the process of the input terminal level of the first not gate 102 being inverted from 1 to 0, it is ensured that the first transistor 102a (PMOS) is turned on (the input terminal voltage is 1.3V), and the second transistor 102b (NMOS) is already in the off state (the input terminal voltage is 1.3V less than the adjusted threshold voltage of 1.4V).

In the present application, the process of inverting the level from 0 to 1 for the first NOT gate 102 is similar to the process of inverting the level from 1 to 0 described above. Specifically, as shown in fig. 13, when the level of the first not gate 102 is inverted from 0 to 1, the bias pulse signal higher than 2V has reached the body terminal of the first transistor 102a (PMOS) when the level starts to be inverted, and the threshold voltage of the first transistor 102a (PMOS) gradually increases from 0.7V to 1.4V. When the input voltage rises to 0.7V and the second transistor 102b (NMOS) is turned on, the first transistor 102a (PMOS) is already turned off (the difference between the input voltage and the power supply voltage VCC1 is 1.3V and less than the threshold voltage 1.4V).

Thus, in some embodiments, by adjusting the threshold voltage of the transistor, it is achieved that a pass transistor (e.g., PMOS) has current passing therethrough, but a non-pass transistor (e.g., NMOS) has no current passing therethrough, depending on the actual requirements of the level inversion. Thus, leakage current in non-conducting transistors (e.g., NMOS) in the first not gate 102 at the time of level inversion, which additional current is a short circuit current, is avoided. Furthermore, the present embodiment can prevent the leakage current from affecting the measurement of the effective driving current of the ring oscillation module 100, so that the accuracy of the measurement of the effective driving current of the ring oscillation module 100 and the first NOT gate 102 thereof can be improved.

Further, the equivalent resistance of the ring oscillation module 100 may be determined according to the effective driving current and the driving voltage value of the first voltage terminal a. The equivalent capacitance of the ring oscillation module 100 may be determined according to the effective driving current, the period of the oscillation signal of the ring oscillation module 100, and the equivalent resistance. In this embodiment, the structures of the plurality of first NOT gates 102 of the ring oscillation module 100 are the same, and the equivalent capacitance of a single first NOT gate 102 can be determined according to the equivalent capacitance of the ring oscillation module 100. The first transistor 102a and the second transistor 102b in the first not gate 102 form a CMOS structure, and ion doping in the CMOS structure affects the equivalent capacitance.

The term "ion doping" herein may include, but is not limited to, parameters such as the species of dopant ions, the amount of dopant, the ion doping angle, the implantation temperature of the ion doping process, and the like. "equivalent capacitance" may include, but is not limited to, direct coupling capacitance (Cdo) between the source and drain and gate in CMOS, junction capacitance (Cj) between the drain and body of the transistor, and the like.

Therefore, in this embodiment, the equivalent capacitance of the first not gate 102 is accurately determined, which can be used to analyze the effect of ion doping of CMOS on the equivalent capacitance, and improve the accuracy of the analysis result.

Next, the structures of the bias module 200 and the delay module 300 in this embodiment will be described in detail.

Fig. 6 is a schematic structural diagram of a bias module of a test circuit according to an embodiment of the present application. As shown in connection with fig. 4 and 6, the bias module 200 comprises a ring oscillation unit 201 and a pulse generation unit 202, the pulse generation unit 202 comprising a bias output.

The body terminal of the transistor of the first inverting unit serves as the bias control terminal of the ring oscillation module 100.

The ring oscillator 201 includes a signal input terminal, the signal input terminal of the ring oscillator 201 is connected to the signal input terminal of the delay module 300, for generating an oscillation signal when receiving the enable signal, and the ring oscillator 201 is configured to output a modulation signal to the pulse generator 202 when generating the oscillation signal.

The pulse generating unit 202 includes the bias output terminal, and the pulse generating unit 202 is configured to generate a bias pulse signal according to the modulation signal, and output the bias pulse signal to the bias control terminal of the ring oscillation module 100 through the bias output terminal, where the body terminal of the transistor of the first inverting unit is used as the bias control terminal of the ring oscillation module 100.

It should be noted that the ring oscillator 201 includes an odd number of second inverting units, and the odd number of second inverting units are cascaded in turn, and each of the second inverting units includes a transistor. The odd number of second inverting units include a second NAND gate 2011 (NAND 2) and an even number of second NAND gates 2012 (INV) cascaded in sequence, a first signal input end of the second NAND gate 2011 is used as a signal input end of the ring oscillating unit 201, a signal output end of the second NAND gate 2011 is connected with a signal input end of the first stage second NAND gate 2012, and a signal output end of the last stage second NAND gate 2012 is connected with a second signal input end of the second NAND gate 2011.

The ring oscillator 201 and the ring oscillator 100 have the same structure, and the number of the first not gates 102 is equal to the number of the second not gates 2012. In this way, the difficulty in manufacturing the test circuit can be reduced, and meanwhile, since the two oscillating circuits have the same structure, when the plurality of second not gates 2012 in the second inverting unit can be connected to the corresponding first not gates 102 in a one-to-one correspondence through the pulse generating unit 202, it can be ensured that each first not gate 102 can receive a stable bias pulse signal during level inversion only by controlling the delay time of the delay module 300.

Specifically, the structure of the second not gate 2012 may be as follows: each second not gate 2012 includes a third transistor and a fourth transistor of different types, the first power supply terminal of the second not gate 2011 and the first terminal of the third transistor are connected to the third voltage terminal C, and the second power supply terminal of the second not gate 2011 and the first terminal of the fourth transistor are connected to the fourth voltage terminal D.

In the same second not gate 2012, the second end of the third transistor is connected to the second end of the fourth transistor and serves as a signal output end of the corresponding second not gate 2012, and the control end of the third transistor is connected to the control end of the fourth transistor and serves as a signal input end of the corresponding second not gate 2012. In the ring oscillation unit 201, the third transistor is a PMOS transistor, and the fourth transistor is an NMOS transistor. The first terminal of the third transistor and the first terminal of the fourth transistor may be respective corresponding source terminals, and the second terminal of the third transistor and the second terminal of the fourth transistor may be respective corresponding drain terminals.

It should be noted that, in the present embodiment, the performance parameters of the first transistor 102a and the third transistor are the same, and the performance parameters of the second transistor 102b and the fourth transistor are the same. The "performance parameter" herein may refer to a channel size of a transistor, a kind of a doping ion, a doping process parameter, a doping concentration, and the like. In this way, the time required for the first inverting unit and the second inverting unit at the time of level inversion can be ensured to be the same, and therefore, the threshold voltage of the transistor in the first inverting unit can be ensured to be adjusted when the first NOT gate in the first inverting unit at the time of level inversion occurs.

Wherein the first terminal 102aa of the first transistor 102a and the first terminal 102bb of the second transistor 102b may be respective corresponding source terminals, and the second terminal 102ab of the first transistor 102 and the second terminal 102ba of the second transistor 102b may be respective corresponding drain terminals.

The pulse generating unit 202 includes an even number of pulse generating sub-units 2021, where each pulse generating sub-unit 2021 is connected to the second inverting unit and the first inverting unit in a one-to-one correspondence manner, and each pulse generating sub-unit 2021 is configured to generate a corresponding bias pulse signal according to a modulation signal generated by the corresponding connected second inverting unit, and output the bias pulse signal to a body terminal of a transistor of the corresponding connected first inverting unit.

The signal output of a second inverting unit is connected to the body of the transistor of a first inverting unit through a pulse generating subunit 2021. The pulse generation unit 202 may be configured to generate a bias pulse signal from the oscillation signal of the ring oscillation unit 201.

Wherein the number of pulse generating subunits 2021, the number of first not gates 102 and the number of second not gates 2012 are all equal. In this way, the plurality of second not gates 2012 can be connected to the plurality of first not gates 102 in one-to-one correspondence by the plurality of pulse generation sub-units 2021.

As an example, referring to fig. 4, 5 and 6, the number of pulse generating sub-units 2021 in the present embodiment is four, which are respectively a first pulse generating sub-unit 2021-1, a second pulse generating sub-unit 2021-2, a third pulse generating sub-unit 2021-3 and a fourth pulse generating sub-unit 2021-4. The number of the second not gates 2012 is four, namely a second not gate 2012-1 of the first stage, a second not gate 2012-2 of the second stage, a second not gate 2012-3 of the third stage and a second not gate 2012-4 of the fourth stage. The second NOT gate 2012-1 of the first stage is coupled to the first NOT gate 102-1 of the first stage through the first pulse generating subunit 2021-1, and so forth, and is not further described.

Specifically, fig. 8 is a schematic circuit connection diagram of a pulse generating subunit of a test circuit according to an embodiment of the present application. As shown in fig. 6 to 8, the pulse generating subunit 2021 includes a pulse logic gate 2021a and a pulse not gate 2021b, the first power supply terminal 2021aa of the pulse logic gate 2021a and the first power supply terminal 2021ba of the pulse not gate 2021b are both connected to the third voltage terminal C, and the second power supply terminal 2021ab of the pulse logic gate 2021a and the second power supply terminal 2021bb of the pulse not gate 2021b are both connected to the fourth voltage terminal D.

The first signal input terminal 2021ac of the pulse logic gate 2021a is connected to the signal input terminal of the second not gate 2012 corresponding to the pulse generating subunit 2021, and the second signal input terminal 2021ad of the pulse logic gate 2021a is connected to the signal output terminal of the second not gate 2012 corresponding to the pulse generating subunit 2021. The signal output terminal 2021ae of the pulse logic gate 2021a is connected to the signal input terminal of the pulse not gate 2021b, and the signal output terminal of the pulse not gate 2021b serves as the bias output terminal of the corresponding pulse generating subunit 2021 and is connected to the body terminal of the transistor of one of the first inverting units corresponding to the pulse generating subunit 2021.

In this embodiment, the pulse generating subunit 2021 has two configurations, which are described below.

Fig. 9 is a timing diagram of a test circuit according to an embodiment of the present application, and in conjunction with fig. 4 to 9, as an implementation manner, the pulse logic gate 2021a is a nor gate, and the bias output terminal is connected to the body terminal of the second transistor 102 b.

At this time, the voltage value of the first voltage terminal a is b, the voltage value of the fourth voltage terminal D is b1, and b1 satisfy the formula: b1 = -b, and b > 0; the second voltage terminal B and the third voltage terminal C are both grounded. The voltage value b of the first voltage terminal a is VCC1 shown in fig. 4.

During operation of the test circuit, the body terminals of the second transistors 102b (NMOS) of all the first not gates 102 in the first inverting unit are connected to the bias output terminals of the corresponding pulse generating sub-unit 2021. For the nor gate of the pulse logic gate 2021a, when the Input terminal is unchanged, the signal Output terminal Vb is always at the low potential-VCC 1, and after passing through the pulse nor gate 2021b, the Output terminal outputs the high potential 0. At time t1, when the Input terminal level is changed from high to low, the Va terminal needs to be changed to high 0 after a short delay, and in the short delay of t1-t2, the Input terminal of the nor gate and the Va terminal have a short time at which the Input terminal is simultaneously at low, that is, the signal output terminal Vb of the nor gate will be temporarily gradually increased from low potential-VCC 1. In the period of t2-t3, when the Input terminal signal change is completely output to the Va terminal, the signal output terminal Vb returns to the stable low potential-VCC 1. In this process, based on the pulse not gate 2021b being connected to the signal Output terminal Vb, the pulse not gate 2021b receives the signal from the signal Output terminal Vb and outputs a bias pulse signal, and when the Input terminal changes from high to low-VCC 1, the Output terminal will briefly decrease from high 0 and then return to high 0.

The Output end is a bias Output end, and based on the delay module 300, the signal of the bias Output end can be aligned with the input signal of the first not gate 102 of each corresponding stage in the ring oscillation module 100 in time sequence, that is, when the level of each first not gate 102 is turned over, the body end of the second transistor 102b (NMOS) of the first not gate 102 can receive the Output pulse signal Output by the bias Output end, and the substrate voltage of the second transistor 102b (NMOS) is increased by the pulse signal, so that the threshold voltage of the second transistor 102b (NMOS) is increased, and the turn-off time of the second transistor 102b (NMOS) is controlled to be advanced.

Thus, when the level of the signal input terminal of the first not gate 102 of each stage of the ring oscillation module 100 is changed from high to low, the second transistor 102b (NMOS) is turned off. At this time, the first transistor 102a (PMOS) will gradually turn on to generate a reverse current, and output the reverse current to the first not gate 102 of the next stage. In this process, the potential of the bias output terminal becomes lower than 0, and based on that the body terminals of all the second transistors 102b (NMOS) have a certain resistance, so that the local body terminal potential of the second transistors 102b (NMOS) will become lower than the potential value of 0, resulting in that the potential difference between the body terminal and the source terminal of the second transistors 102b (NMOS) is negative, so that the turn-on voltage of the second transistors 102b (NMOS) will be significantly increased, and thus the additional short-circuit current flowing through the second transistors 102b (NMOS) when the level of the first transistors 102a (PMOS) is turned over can be greatly reduced.

In other timings, the signals at the bias output terminals are all at 0 potential, so that the body of the second transistor 102b (NMOS) of the first not gate 102 receives the 0 potential, and the inversion current of the second transistor 102b (NMOS) is not affected. This results in a more accurate and efficient drive current for the ring oscillation module 100 from the first voltage terminal a.

Fig. 11 is a schematic diagram of a structure of another test circuit according to an embodiment of the present application, fig. 12 is a schematic diagram of a bias module of another test circuit according to an embodiment of the present application, fig. 13 is a schematic diagram of a circuit connection of a first not gate of another test circuit according to an embodiment of the present application, fig. 14 is a schematic diagram of a circuit connection of a pulse generation subunit of another test circuit according to an embodiment of the present application, and fig. 15 is a timing chart of another test circuit according to an embodiment of the present application.

As another implementation, as shown in fig. 11 to 15, the pulse logic gate 2021a is a nand gate, and the bias output terminal is connected to the body terminal of the first transistor 102 a.

At this time, the voltage value of the first voltage terminal a is a, the voltage value of the third voltage terminal C is a1, the voltage value of the fourth voltage terminal D is a2, and the formulas are satisfied by a, a1 and a 2: a2 =a, a1=2a; the second voltage terminal B is grounded. In this embodiment, the voltage value a of the first voltage terminal a is VCC1 in fig. 11.

During operation of the test circuit, the body terminals of the first transistors 102a (PMOS) of all the first not gates 102 in the first inverting unit are connected to the bias output terminals of the corresponding pulse generating sub-unit 2021. For the pulse logic gate 2021a is a nand gate, when the Input terminal potential is unchanged, the potential of the signal Output terminal Vb is always the high potential VCC3, and after passing through the pulse not gate 2021b, the Output terminal outputs the low potential VCC2. At time t1, when the Input terminal level changes from low to high, the Va terminal needs to be delayed briefly before changing to the low potential VCC2. In the short delay of t1-t2, there is a short moment when the Input and Va ends of the nand gate are at high potential at the same time, i.e. the signal output Vb of the nand gate will briefly decrease gradually from high potential VCC3. In the period of t2-t3, when the Input terminal signal change is completely output to the Va terminal, the signal output terminal Vb returns to the stable high potential VCC3. In this process, based on the connection of the pulse not gate 2021b to the signal Output terminal Vb, the pulse not gate 2021b receives the signal from the signal Output terminal Vb and outputs a bias pulse signal, and when the Input terminal is changed from the low potential VCC2 to the high potential VCC3, the Output terminal will be briefly raised from the low potential VCC2 and then return to the low potential VCC2.

The Output terminal is used as a bias Output terminal, and based on the delay module 300, the signal of the bias Output terminal can be aligned with the input signal of the first not gate 102 of each corresponding stage in the ring oscillation module 100 in time sequence, so that when the level of each first not gate 102 is inverted, the first transistor 102a (PMOS) body terminal of the first not gate 102 can receive the signal of the bias Output terminal.

Thus, the first transistor 102a (PMOS) is turned off when the level of the signal input terminal of the first not gate 102 of each stage of the ring oscillation module 100 changes from low to high. At this time, the second transistor 102b (NMOS) will gradually turn on to generate a reverse current, and output the reverse current to the first not gate 102 of the next stage. In this process, the potential of the bias output terminal becomes higher than VCC2 (=vcc 1), and based on that the body terminal of all the first transistors 102a (PMOS) has a certain resistance, so that the local body terminal potential of the first transistors 102a (PMOS) will become higher than the potential value of VCC1, resulting in that the potential difference between the body terminal and the source terminal of the first transistors 102a (PMOS) is positive, so that the turn-on voltage of the first transistors 102a (PMOS) will be significantly increased, and thus the additional short circuit current flowing through the first transistors 102a (PMOS) when the second transistors 102b (NMOS) are turned over in level can be greatly reduced.

In other timings, the signal at the bias output terminal is VCC2 (=vcc 1), and the body terminal and the source terminal of the first transistor 102a (PMOS) are equal in potential, so that the inversion current of the first transistor 102a (PMOS) is not affected. This results in a more accurate and efficient drive current for the ring oscillation module 100 from the first voltage terminal a.

Fig. 10 is a schematic structural diagram of a delay module of a test circuit according to an embodiment of the present application, and referring to fig. 4 and 10, the delay module 300 includes an even number of delay not gates 301, the even number of delay not gates 301 are cascaded in sequence, and a signal input end of a first stage of delay not gate 301 is connected to a signal input end of the bias module 200, and is used for receiving an enable signal; the signal output of the last stage delay NOT 301 is coupled to the enable input of the ring oscillator module 100. In the present embodiment, two delay not gates 301 are shown, and in some embodiments, the number of delay not gates 301 may be adjusted according to the setting of the test circuit, which is not limited in this embodiment.

The delay module 300 further includes a delay capacitor 302, where a first electrode 302a of the delay capacitor 302 is connected between any two delay not gates 301, and a second electrode 302b of the delay capacitor 302 is connected to the third voltage terminal C, so that charging and discharging time of a circuit when an input enable signal changes can be controlled by changing a capacitance value of the delay capacitor 302, thereby realizing accurate control of delay time of the delay module 300.

Based on the above test system, the embodiment of the application provides a test method for the above test system. Fig. 17 is a flow chart of a test method according to an embodiment of the present application, and referring to fig. 17, the test method includes:

s100: an enable signal is loaded to the test circuit.

It should be noted that, based on the signal generating circuit 400 being connected to the test circuit, the signal generating circuit 400 may write an enable signal into the test circuit, and the enable signal may be output to the bias module 200, so as to generate a bias pulse signal, where the bias pulse signal is output to the body terminal of the transistor of the first inverting unit of the ring oscillation module 100. The enable signal may also be output to the delay circuit to generate an enable signal delayed by a predetermined time, and output to the ring oscillation module 100 for operation to generate an oscillation signal.

S200: and acquiring a current value of a first voltage end of the ring oscillation module of the test circuit and an oscillation frequency of an oscillation signal generated by the ring oscillation module.

It should be noted that the above-mentioned process may be completed by the test device 500 connected to the first voltage terminal.

S300: and determining the effective driving current of the ring oscillation module according to the current value of the first voltage end.

It should be noted that, in the present embodiment, in the process of level inversion based on the first inversion unit in the ring oscillation module 100, the threshold voltage of the transistor of the first inversion unit may be adjusted by the bias pulse signal generated by the bias module 200, so as to avoid the existence of an additional driving current in the non-conductive transistor in the first inversion unit during level inversion. Therefore, the current value obtained from the first voltage terminal is the effective driving current of the ring oscillation module 100.

S400: and determining the equivalent capacitance and the equivalent resistance of the transistor of the first reverse unit of the ring oscillation module according to the effective driving current and the oscillation frequency.

It should be noted that, the equivalent resistance can be determined according to the effective driving current and the oscillation frequency, and the equivalent capacitance can be determined according to the equivalent resistance and the delay of the ring oscillation module. In some embodiments, the equivalent capacitances of the first NOT gates 102 of each stage are equal, so that the relationship between the equivalent capacitance of the CMOS and the ion doping of the CMOS can be determined by analyzing the equivalent capacitance of the CMOS in the single first NOT gate 102 according to the equivalent capacitance of the ring oscillation module in an equipartition manner.

The embodiment of the application also provides a semiconductor chip, which comprises the testing system. The semiconductor chip further comprises a substrate layer, which may be a PCB (Printed Circuit Board ). The signal generating circuit 400, the testing device 500, the testing circuit, the frequency dividing element 600 and the output buffer element 700 of the above-mentioned testing system may be disposed on the substrate layer. Other technical features of the test circuit of the semiconductor chip of the present application are the same as those of the embodiment of the test circuit, and the same technical effects can be achieved, and will not be described in detail herein.

In the foregoing description, it should be understood that the terms "mounted," "connected," and "coupled" are to be construed broadly, as well as indirectly, through intermediaries, or in communication between two elements, or in interaction with each other, unless explicitly stated and limited otherwise. In the description of the present application, the meaning of "a plurality" is two or more, unless specifically stated otherwise.

The terms "first," "second," "third," "fourth" and the like in the description and in the claims and in the above drawings, if any, are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the application described herein may be implemented, for example, in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present application, and not for limiting the same; although the application has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the application.

Claims

1. The test circuit is characterized by comprising a ring oscillation module, a bias module and a delay module;

the ring oscillation module comprises an enabling input end and a bias control end, and comprises an odd number of first reversing units which are sequentially cascaded, wherein each first reversing unit comprises a transistor;

The bias module comprises a signal input end and a bias output end, and the signal input end of the bias module is connected with the signal input end of the delay module and is used for receiving the enabling signal; the bias module is used for generating a bias pulse signal according to the received enabling signal and outputting the bias pulse signal to the bias control end of the ring oscillation module through the bias output end, and the bias pulse signal is used for adjusting the threshold voltage of the transistor when the first reverse unit is subjected to level inversion.

2. The test circuit of claim 1, wherein the bias module comprises a ring oscillation unit and a pulse generation unit;

the ring oscillation unit comprises a signal input end, the signal input end of the ring oscillation unit is connected with the signal input end of the delay module and is used for generating an oscillation signal when receiving the enabling signal, and the ring oscillation unit is used for outputting a modulation signal to the pulse generation unit when generating the oscillation signal;

the pulse generation unit comprises the bias output end, the pulse generation unit is used for generating the bias pulse signal according to the modulation signal and outputting the bias pulse signal to the bias control end of the ring oscillation module through the bias output end, and the body end of the transistor of the first reversing unit is used as the bias control end of the ring oscillation module.

3. The test circuit of claim 2, wherein an odd number of the first inverting units include a first nand gate and an even number of first nand gates cascaded in sequence, a first signal input terminal of the first nand gate being used as the enable input terminal of the ring oscillation module, a signal output terminal of the first nand gate being connected to a signal input terminal of the first nand gate of a first stage, a second signal input terminal of the first nand gate being connected to a signal output terminal of the first nand gate of a last stage;

4. A test circuit according to claim 3, wherein the ring oscillator unit comprises an odd number of second inverting units, the odd number of second inverting units being cascaded in turn, each of the second inverting units comprising a transistor.

5. The test circuit of claim 4, wherein each of the first not gates comprises a first transistor and a second transistor of different types, a first power supply terminal of the first not gate and a first terminal of the first transistor are each connected to a first voltage terminal, and a second power supply terminal of the first not gate and a first terminal of the second transistor are each connected to a second voltage terminal;

In the same first NOT gate, the second end of the first transistor is connected with the second end of the second transistor and is used as a signal output end of the corresponding first NOT gate; the control end of the first transistor is connected with the control end of the second transistor and is used as the signal input end of the corresponding first NOT gate.

6. The test circuit of claim 5, wherein an odd number of the second inverting units comprises a second nand gate and an even number of second nand gates cascaded in sequence, a first signal input end of the second nand gate is used as a signal input end of the ring oscillation unit, a signal output end of the second nand gate is connected with a signal input end of the second nand gate of a first stage, and a second signal input end of the second nand gate is connected with a signal output end of the second nand gate of a last stage;

7. The test circuit of claim 6, wherein each of the second nand gates includes a third transistor and a fourth transistor of different types, the first power supply terminal of the second nand gate and the first terminal of the third transistor are each connected to a third voltage terminal, and the first power supply terminal of the second nand gate and the first terminal of the fourth transistor are each connected to a fourth voltage terminal;

In the same second not gate, the second end of the third transistor is connected to the second end of the fourth transistor and is used as a signal output end of the corresponding second not gate, and the control end of the third transistor is connected to the control end of the fourth transistor and is used as a signal input end of the corresponding second not gate.

8. The test circuit of claim 7, wherein the pulse generating unit comprises an even number of pulse generating subunits;

wherein the number of pulse generation subunits, the number of first NOT gates, and the number of second NOT gates are all equal.

9. The test circuit of claim 8, wherein each of the pulse generation subunits comprises a pulse logic gate and a pulse not gate, a first power supply terminal of the pulse logic gate and a first power supply terminal of the pulse not gate are both connected to the third voltage terminal, and a second power supply terminal of the pulse logic gate and a second power supply terminal of the pulse not gate are both connected to the fourth voltage terminal;

the signal output end of the pulse logic gate is connected with the signal input end of the pulse NOT gate, and the signal output end of the pulse NOT gate is used as the bias output end of the pulse generation subunit and is connected with the body end of the transistor of the first reversing unit corresponding to the pulse generation subunit.

10. The test circuit of claim 7, wherein the first transistor and the third transistor are PMOS transistors and the second transistor and the fourth transistor are NMOS transistors.

11. The test circuit of claim 9, wherein the pulsed logic gate is a nand gate and the bias output is connected to the body terminal of the first transistor;

the voltage value of the first voltage end is a, the voltage value of the third voltage end is a1, the voltage value of the fourth voltage end is a2, and the a, the a1 and the a2 satisfy the formula: a2 =a, a1=2a; the second voltage is grounded.

12. The test circuit of claim 9, wherein the pulsed logic gate is a nor gate, the bias output terminal being connected to a body terminal of the second transistor;

the voltage value of the first voltage end is b, the voltage value of the fourth voltage end is b1, and the b1 satisfy the formula: b1 = -b, and b > 0; the second voltage end and the third voltage end are grounded.

13. The test circuit according to any one of claims 2-12, wherein the delay module comprises at least two delay not gates, at least two delay not gates being cascaded in sequence, a signal input of a first stage of the delay not gates being connected to a signal input of the bias module for receiving the enable signal;

the signal output end of the delay NOT gate of the last stage is connected with the enabling input end of the ring oscillation module;

the delay module is used for generating an enabling signal with preset delay time according to the enabling signal and outputting the enabling signal to the enabling input end, the enabling signal with preset delay time is used for controlling an oscillating signal generated by the ring oscillating module to lag behind the oscillating signal generated by the ring oscillating unit, and therefore when the first reversing unit of the ring oscillating module turns in level, the offset pulse signal is received.

14. The test circuit of claim 13, wherein the delay module further comprises a delay capacitor, a first electrode of the delay capacitor being connected between any two of the delay not gates, a second electrode of the delay capacitor being connected to a third voltage terminal.

15. A test system comprising an enable signal generating circuit, a test device and the test circuit of any one of claims 1-14, the enable signal output of the enable signal generating circuit being connected to a signal input of a bias module of the test circuit, the enable signal output being connected to an enable input of a ring oscillator module of the test circuit via a delay module of the test circuit.

16. The test system of claim 15, further comprising a frequency dividing element coupled to the signal output of the ring oscillator module of the test circuit and an output buffer element coupled to the signal output of the frequency dividing element.

17. A test method for the test system of claim 15 or 16, the test method comprising:

Loading an enable signal to the test circuit;

acquiring a current value of a first voltage end of a ring oscillation module of the test circuit and an oscillation frequency of an oscillation signal generated by the ring oscillation module;

and determining the equivalent capacitance and the equivalent resistance of the transistor of the first reversing unit of the ring oscillation module according to the effective driving current and the oscillation frequency.

18. A semiconductor chip comprising the test system of claim 15 or 16.