CN117217157A - Common centroid layout of current mirror group and layout method thereof - Google Patents
Common centroid layout of current mirror group and layout method thereof Download PDFInfo
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Abstract
The invention provides a common centroid layout of a current mirror group, which is improved on the basis of the traditional common centroid layout, so that compared with the traditional common centroid layout, the matching of each transistor and the layout of a plurality of wirings connected with each transistor can be realized by fewer metal layers; further, only the wiring needs to be provided in one of the row directions, so that the area of the entire layout of the current mirror group in plan view can be made small.
Description
Technical Field
The invention relates to a scheme for optimizing a common centroid layout of a current mirror group circuit.
Background
Current mirrors are a standard component that is ubiquitous in analog integrated circuits, and are also found in some digital circuits. In conventional voltage mode op amp designs, a current mirror is used to generate the bias current. In the design of a novel current mode analog integrated circuit, besides being used for generating bias current, a current mirror is widely used for realizing the duplication or multiplication of current signals, and a current mirror with complementary polarities can also realize the transformation of differential-single-ended current signals. The current mirror is not only a basic unit circuit for designing an integrated circuit, but also is a typical current mode circuit, and is directly applied to some current mode systems (such as high-frequency continuous time filters and artificial neural networks).
In general, a current mirror group (CMB: current Mirror Bank) has a plurality of transistors, the layout modes of which include a common centroid layout, a mirror layout, an inter-digital layout, and the like. Fig. 1A is a schematic diagram showing a general common centroid layout when the number of transistors is 4. Fig. 1B is a schematic diagram showing a mirror layout when the number of transistors is 3. Fig. 1C is a schematic diagram showing an interdigital layout when the number of transistors is 7.
In addition, fig. 2A is a schematic diagram of a current mirror group, and fig. 2B is a schematic diagram showing a specific structure of M1 and M2 in fig. 2A. For the case that the number ratio of the different types of transistors is 1:2:4:8:16:32, the mirror image layout shown in fig. 1B and the interdigital layout shown in fig. 1C need to align a plurality of transistors, and the length direction size of the transistors is larger, which has obvious problems. From an overall layout on the chip, it is desirable that the layout overall approach a square, and it is apparent that a common centroid layout is more consistent with this. In addition, the common centroid layout is also better performing than the mirror layout or the interdigital layout from the viewpoint of the replica current ratio (copying current ratio), so that the common centroid layout is preferentially adopted for the layout of a plurality of transistors of the current mirror group.
Disclosure of Invention
However, conventional common centroid layout focuses on the location of the centroid and not on the layout of the wiring. That is, in the conventional common centroid layout, more metal layers are required to be used in order to achieve matching of the respective transistors and layout of a plurality of wirings connected to the respective transistors. Further, since wiring is required not only in the row direction but also in the column direction, that is, in both the row and column directions, the area of the entire layout of the current mirror group is large in plan view.
The present invention has been made in view of the above-described circumstances, and an object thereof is to provide a common centroid layout of a current mirror group, which is capable of realizing matching of individual transistors and layout of a plurality of wirings connected to the individual transistors with fewer metal layers than a conventional common centroid layout by improving the conventional common centroid layout; further, only the wiring needs to be provided in one of the row directions, so that the area of the entire layout of the current mirror group in plan view can be made small.
Technical proposal for solving the technical problems
In order to solve the above problem, a common centroid layout of a current mirror group according to a first aspect of the present invention includes:
a first transistor group including a dummy transistor and a 1 st transistor;
a second transistor group including a 2 nd transistor and a 3 rd transistor;
a third transistor group including a 4 th transistor, a 5 th transistor, a 6 th transistor, and a 7 th transistor;
a fourth transistor group including an 8 th transistor, a 9 th transistor, a 10 th transistor, an 11 th transistor, a 12 th transistor, a 13 th transistor, a 14 th transistor, and a 15 th transistor;
a fifth transistor group including 16 th to 23 th transistors and 24 th to 31 th transistors; and
a sixth transistor group including 32 th to 47 th transistors and 48 th to 63 th transistors,
the 1 st transistor and the dummy transistor in the first transistor group are respectively arranged in a fourth row, a fourth column and a fifth row, and a fifth column,
the 2 nd transistor and the 3 rd transistor in the second transistor group are respectively arranged in a fifth row and a fifth column of a fourth row,
the 4 th transistor and the 5 th transistor in the third transistor group are arranged in a fourth row and a third column respectively,
the 6 th transistor and the 7 th transistor in the third transistor group are respectively arranged in a sixth column of a fifth row and a seventh column of the fifth row,
the 8 th transistor, the 9 th transistor, the 10 th transistor and the 11 th transistor in the fourth transistor group are respectively arranged in a fourth row first column, a fifth row second column and a fifth row third column,
the 12 th transistor, the 13 th transistor, the 14 th transistor, and the 15 th transistor in the fourth transistor group are arranged in a fourth row sixth column, a fourth row seventh column, a fourth row eighth column, and a fifth row eighth column, respectively,
the 16 th to 23 th transistors in the fifth transistor group are arranged in first to eighth columns of a third row,
the 24 th to 31 th transistors in the fifth transistor group are arranged in the first to eighth columns of the sixth row,
the 32 th to 47 th transistors in the sixth transistor group are arranged in the first to eighth columns of the first row and the first to eighth columns of the second row respectively,
the 48 th to 63 th transistors in the sixth transistor group are arranged in the seventh row first to eighth column and the eighth row first to eighth column, respectively.
Further, the 1 st transistor in the first transistor group is connected to a first wiring, the dummy transistor in the first transistor group is connected to a dummy wiring,
the 2 nd transistor and the 3 rd transistor in the second transistor group are both connected to a second wiring,
the 4 th transistor, the 5 th transistor, the 6 th transistor, and the 7 th transistor in the third transistor group are all connected to a third wiring,
the 8 th transistor, the 9 th transistor, the 10 th transistor, the 11 th transistor, the 12 th transistor, the 13 th transistor, the 14 th transistor, and the 15 th transistor in the fourth transistor group are connected to a fourth wiring,
the 16 th to 23 th transistors and the 24 th to 31 th transistors in the fifth transistor group are connected to a fifth wiring,
the 32 th to 47 th transistors and the 48 th to 63 th transistors in the sixth transistor group are connected to a sixth wiring,
the dummy transistors and the 1 st to 63 th transistors are disposed in a first layer,
the dummy wiring, the first wiring, the second wiring, the third wiring, the fourth wiring, and the fifth wiring are provided in a second layer different from the first layer,
the sixth wiring is provided in a third layer different from the first layer and the second layer.
Further, in a plan view, the dummy wirings, the first wirings, the second wirings, the third wirings, the fourth wirings, the fifth wirings are located between a third row and a fourth row and between a fifth row and a sixth row, and the sixth wirings are located between a first row and a second row and between a seventh row and an eighth row.
Further, the type 1 transistor in the first transistor group is type 1,
the type of the 2 nd transistor and the 3 rd transistor in the second transistor group are the same type 2,
the types of the 4 th transistor, the 5 th transistor, the 6 th transistor and the 7 th transistor in the third transistor group are the same 3 rd type,
the types of the 8 th transistor, the 9 th transistor, the 10 th transistor, the 11 th transistor, the 12 th transistor, the 13 th transistor, the 14 th transistor, and the 15 th transistor in the fourth transistor group are the same 4 th type,
the types of the 16 th to 23 th transistors and the 24 th to 31 th transistors in the fifth transistor group are the same type 5,
the types of the 32 th to 47 th transistors and the 48 th to 63 th transistors in the sixth transistor group are the same type 6,
the 1 st type, the 2 nd type, the 3 rd type, the 4 th type, the 5 th type, and the 6 th type are different from each other.
Further, the dummy transistor and the dummy wiring do not operate.
In the layout method of the common centroid layout of the current mirror group according to the second aspect of the present invention, the common centroid layout of the current mirror group includes:
a first transistor group including a dummy transistor and a 1 st transistor;
a second transistor group including a 2 nd transistor and a 3 rd transistor;
a third transistor group including a 4 th transistor, a 5 th transistor, a 6 th transistor, and a 7 th transistor;
a fourth transistor group including an 8 th transistor, a 9 th transistor, a 10 th transistor, an 11 th transistor, a 12 th transistor, a 13 th transistor, a 14 th transistor, and a 15 th transistor;
a fifth transistor group including 16 th to 23 th transistors and 24 th to 31 th transistors; and
a sixth transistor group including 32 th to 47 th transistors and 48 th to 63 th transistors,
the layout method is characterized in that,
the 1 st transistor and the dummy transistor in the first transistor group are respectively arranged in a fourth row, a fourth column and a fifth row, and a fifth column,
the 2 nd transistor and the 3 rd transistor in the second transistor group are respectively arranged in a fifth row and a fourth column and a fifth row,
the 4 th transistor and the 5 th transistor in the third transistor group are arranged in a fourth row and a third column respectively,
the 6 th transistor and the 7 th transistor in the third transistor group are respectively arranged in a sixth column of a fifth row and a seventh column of the fifth row,
disposing the 8 th transistor, the 9 th transistor, the 10 th transistor, and the 11 th transistor in the fourth transistor group in a fourth row first column, a fifth row second column, and a fifth row third column, respectively,
disposing the 12 th transistor, the 13 th transistor, the 14 th transistor, and the 15 th transistor in the fourth transistor group in a fourth row sixth column, a fourth row seventh column, a fourth row eighth column, and a fifth row eighth column, respectively,
the 16 th to 23 th transistors in the fifth transistor group are arranged in first to eighth columns of a third row,
the 24 th to 31 th transistors in the fifth transistor group are arranged in the sixth row first to eighth columns respectively,
the 32 th to 47 th transistors in the sixth transistor group are arranged in the first row first to eighth column and the second row first to eighth column respectively,
the 48 th to 63 th transistors in the sixth transistor group are arranged in the seventh row first to eighth column and the eighth row first to eighth column, respectively.
Further, the 1 st transistor in the first transistor group is connected to a first wiring, the dummy transistor in the first transistor group is connected to a dummy wiring,
connecting both the 2 nd transistor and the 3 rd transistor in the second transistor group to a second wiring,
the 4 th transistor, the 5 th transistor, the 6 th transistor, and the 7 th transistor in the third transistor group are all connected to a third wiring,
connecting the 8 th transistor, the 9 th transistor, the 10 th transistor, the 11 th transistor, the 12 th transistor, the 13 th transistor, the 14 th transistor, and the 15 th transistor in the fourth transistor group to a fourth wiring,
the 16 th to 23 th transistors and the 24 th to 31 th transistors in the fifth transistor group are connected to a fifth wiring,
the 32 th to 47 th transistors and the 48 th to 63 th transistors in the sixth transistor group are connected to a sixth wiring,
the dummy transistors and the 1 st to 63 th transistors are disposed in a first layer,
the dummy wiring, the first wiring, the second wiring, the third wiring, the fourth wiring, and the fifth wiring are provided in a second layer different from the first layer,
the sixth wiring is provided in a third layer different from the first layer and the second layer.
Further, in a plan view, the dummy wirings, the first wirings, the second wirings, the third wirings, the fourth wirings, the fifth wirings are positioned between a third row and a fourth row and between a fifth row and a sixth row, and the sixth wirings are positioned between a first row and a second row and between a seventh row and an eighth row.
Further, the type 1 transistor in the first transistor group is type 1,
the type of the 2 nd transistor and the 3 rd transistor in the second transistor group are the same type 2,
the types of the 4 th transistor, the 5 th transistor, the 6 th transistor and the 7 th transistor in the third transistor group are the same 3 rd type,
the types of the 8 th transistor, the 9 th transistor, the 10 th transistor, the 11 th transistor, the 12 th transistor, the 13 th transistor, the 14 th transistor, and the 15 th transistor in the fourth transistor group are the same 4 th type,
the types of the 16 th to 23 th transistors and the 24 th to 31 th transistors in the fifth transistor group are the same type 5,
the types of the 32 th to 47 th transistors and the 48 th to 63 th transistors in the sixth transistor group are the same type 6,
the 1 st type, the 2 nd type, the 3 rd type, the 4 th type, the 5 th type, and the 6 th type are different from each other.
Further, the dummy transistor and the dummy wiring do not operate.
Effects of the invention
According to the common centroid layout of the current mirror group and the layout method thereof, the traditional common centroid layout is improved, so that compared with the traditional common centroid layout, the matching of each transistor and the layout of a plurality of wirings connected with each transistor can be realized by fewer metal layers; further, only the wiring needs to be provided in one of the row directions, so that the area of the entire layout of the current mirror group in plan view can be made small.
Drawings
Fig. 1A is a schematic diagram showing a general common centroid layout when the number of transistors is 4.
Fig. 1B is a schematic diagram showing a mirror layout when the number of transistors is 3.
Fig. 1C is a schematic diagram showing an interdigital layout when the number of transistors is 7.
Fig. 2A is a schematic diagram of a current mirror set.
Fig. 2B is a schematic diagram showing a specific structure of M1 and M2 in fig. 2A.
Fig. 3 is a schematic top view illustrating a conventional common centroid layout.
Fig. 4 is a schematic diagram showing a common centroid layout of current mirror groups and numbering the intervals between each group of row pairs according to an embodiment of the present invention.
Fig. 5 is a schematic diagram showing a common centroid layout of a current mirror group and a layout of a plurality of wirings connected to respective transistors according to an embodiment of the present invention.
Description of the reference numerals
0 virtual transistor group
1 first transistor group
2 second transistor group
3 third transistor group
4 fourth transistor group
5 fifth transistor group
6 sixth transistor group
S0 virtual wiring
S1 first wiring
S2 second wiring
S3 third wiring
S4 fourth wiring
S5 fifth wiring
S6 sixth wiring
Detailed Description
The invention will be described in detail below with reference to the drawings and the detailed description. The present embodiment is implemented on the premise of the technical scheme of the present invention, and a detailed embodiment and a specific operation process are given, but the protection scope of the present invention is not limited to the following embodiments.
Spatially relative terms, such as "under," "below," "lower," "over," "upper," and the like, may be used herein for convenience of description to describe one element or feature's relationship to another element or feature as illustrated. It will be understood that spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "under" or "beneath" other elements or features would then be oriented "over" the other elements or features.
Unless otherwise defined, terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present invention pertains. The terms are to be understood to have meanings consistent with the context of the relevant art and are not to be construed as idealized or overly formal unless expressly so defined herein.
< common centroid layout of Current mirror group >
The common centroid layout of the current mirror group according to the embodiment of the present invention will be described in detail with reference to the accompanying drawings.
First, referring to fig. 3, a common centroid layout of a conventional current mirror group will be described. Fig. 3 is a schematic top view illustrating a conventional common centroid layout.
As shown in fig. 3, in this conventional common centroid layout, there are 6 types of transistors. A smaller number of types of transistors are placed in a region near the origin, and a larger number of types of transistors are placed in a peripheral region, and the individual transistors are placed symmetrically with respect to the origin such that the common centroid of all the transistors is on the origin. However, conventional common centroid layout focuses on the location of the centroid and not on the layout of the wiring. That is, in the conventional common centroid layout, more metal layers are required to be used in order to achieve matching of the respective transistors and layout of a plurality of wirings connected to the respective transistors. Further, since wiring is required not only in the row direction but also in the column direction, that is, in both the row and column directions, the area of the entire layout of the current mirror group is large in plan view.
The common centroid layout of the current mirror group according to the embodiment of the invention is obtained by modifying the conventional common centroid layout. Next, a common centroid layout of the current mirror group according to the embodiment of the present invention will be described in detail with reference to fig. 4 and 5.
Fig. 4 is a schematic diagram showing a common centroid layout of current mirror groups and numbering the intervals between each group of row pairs according to an embodiment of the present invention. Fig. 5 is a schematic diagram showing a common centroid layout of a current mirror group and a layout of a plurality of wirings connected to respective transistors according to an embodiment of the present invention.
As shown in fig. 4, the common centroid layout of the current mirror group according to the embodiment of the present invention includes: a first transistor group including a dummy transistor 0 and a 1 st transistor 1; a second transistor group 2 including a 2 nd transistor and a 3 rd transistor; a third transistor group 3 including a 4 th transistor, a 5 th transistor, a 6 th transistor, and a 7 th transistor; a fourth transistor group 4 including an 8 th transistor, a 9 th transistor, a 10 th transistor, an 11 th transistor, a 12 th transistor, a 13 th transistor, a 14 th transistor, and a 15 th transistor; a fifth transistor group 5 including 16 th to 23 th transistors and 24 th to 31 th transistors; and a sixth transistor group 6 including 32 th to 47 th transistors and 48 th to 63 th transistors.
Wherein, the 1 st transistor 1 and the virtual transistor 0 in the first transistor group are respectively configured in a fourth row, a fourth column and a fifth row and a fifth column; the 2 nd transistor and the 3 rd transistor in the second transistor group 2 are respectively arranged in a fourth column of the fifth row and a fifth column of the fourth row; the 4 th transistor and the 5 th transistor in the third transistor group 3 are respectively arranged in the fourth row, the second column and the fourth row, the third column, and the 6 th transistor and the 7 th transistor in the third transistor group 3 are respectively arranged in the fifth row, the sixth column and the seventh column; the 8 th, 9 th, 10 th and 11 th transistors in the fourth transistor group 4 are arranged in the fourth row first column, the fifth row second column and the fifth row third column, respectively, and the 12 th, 13 th, 14 th and 15 th transistors in the fourth transistor group 4 are arranged in the fourth row sixth column, the fourth row seventh column, the fourth row eighth column and the fifth row eighth column, respectively; the 16 th to 23 th transistors in the fifth transistor group 5 are respectively arranged in the first to eighth columns of the third row, and the 24 th to 31 th transistors in the fifth transistor group 5 are respectively arranged in the first to eighth columns of the sixth row; the 32 th to 47 th transistors in the sixth transistor group 6 are arranged in the first row first to eighth column and the second row first to eighth column, respectively, and the 48 th to 63 th transistors in the sixth transistor group 6 are arranged in the seventh row first to eighth column and the eighth row first to eighth column, respectively.
Further, as shown in fig. 5, the 1 st transistor 1 in the first transistor group is connected to the first wiring S1, and the dummy transistor 0 in the first transistor group is connected to the dummy wiring S0; the 2 nd transistor and the 3 rd transistor in the second transistor group 2 are both connected to the second wiring S2; the 4 th transistor, the 5 th transistor, the 6 th transistor, and the 7 th transistor in the third transistor group 3 are all connected to the third wiring S3; the 8 th, 9 th, 10 th, 11 th, 12 th, 13 th, 14 th, and 15 th transistors in the fourth transistor group 4 are all connected to the fourth wiring S4; the 16 th to 23 th transistors and the 24 th to 31 th transistors in the fifth transistor group 5 are connected to a fifth wiring S5; the 32 th to 47 th transistors and the 48 th to 63 th transistors in the sixth transistor group 6 are connected to the sixth wiring S6.
And, the dummy transistor 0 and the 1 st to 63 th transistors are provided in the first layer; the dummy wirings S0, the first wirings S1, the second wirings S2, the third wirings S3, the fourth wirings S4, and the fifth wirings S5 are provided in a second layer different from the first layer; the sixth wiring S6 is provided in a third layer different from the first layer and the second layer.
Thus, the common centroid layout of the current mirror group according to the embodiment of the present invention improves the conventional common centroid layout, so that the matching of each transistor and the layout of a plurality of wirings connected to each transistor can be realized with fewer metal layers (two layers, namely, the second layer and the third layer in fig. 4 and 5) than the conventional common centroid layout (fig. 3).
In addition, as shown in fig. 4, the intervals between each group of row pairs are numbered for convenience of explanation. Specifically, the interval between the fourth row and the fifth row (i.e., the most intermediate) is set to 0', the interval between the third row and the fourth row is set to 1', the interval between the second row and the third row is set to 2', the interval between the first row and the second row is set to 3', the interval above the first row is set to 4', the interval between the fifth row and the sixth row is set to-1 ', the interval between the sixth row and the seventh row is set to-2 ', the interval between the seventh row and the eighth row is set to-3 ', and the interval below the eighth row is set to-4 '.
As shown in fig. 5, the dummy wirings S0, the first wirings S1, the second wirings S2, the third wirings S3, the fourth wirings S4, and the fifth wirings S5 are located between the third and fourth rows and between the fifth and sixth rows, that is, at the above-mentioned interval 1 'and the above-mentioned interval-1', in a plan view. The sixth wiring S6 is located between the first row and the second row and between the seventh row and the eighth row, i.e., at the above-described interval 3 'and the above-described interval-3'.
That is, for the layout of the respective wirings connected to the respective transistors, only the space needs to be reserved at the odd horizontal intervals (1 ', 3', -1', -3'), not at the even horizontal intervals (0, 2', 4', -2', -4'), and not at the vertical intervals. Further, the number of wirings provided in the odd-numbered horizontal intervals requiring the reserved space is the same as the number of transistor types on both sides of the intervals.
Thus, according to the common centroid layout of the current mirror group according to the embodiment of the present invention, the conventional common centroid layout is improved, and thus, compared with the conventional common centroid layout (fig. 3), only the wirings need to be provided in one direction (particularly, the odd horizontal intervals in fig. 4 and 5) of the row direction, so that the area of the entire layout of the current mirror group in a plan view can be made smaller.
Further, as one example, the type of the 1 st transistor 1 in the first transistor group is the 1 st type; the type of the 2 nd transistor and the 3 rd transistor in the second transistor group 2 are the same type 2; the types of the 4 th transistor, the 5 th transistor, the 6 th transistor, and the 7 th transistor in the third transistor group 3 are the same 3 rd type; the types of the 8 th transistor, the 9 th transistor, the 10 th transistor, the 11 th transistor, the 12 th transistor, the 13 th transistor, the 14 th transistor, and the 15 th transistor in the fourth transistor group 4 are the same 4 th type; the types of the 16 th to 23 th transistors and the 24 th to 31 th transistors in the fifth transistor group 5 are the same type 5; the types of the 32 th to 47 th transistors and the 48 th to 63 th transistors in the sixth transistor group are the same 6 th type; and the 1 st type, the 2 nd type, the 3 rd type, the 4 th type, the 5 th type, and the 6 th type are different from each other.
In the present invention, the dummy transistor 0 and the dummy wiring S0 are provided for matching (i.e., symmetry), but the dummy transistor 0 and the dummy wiring S0 do not actually operate.
< layout method of common centroid layout of Current mirror group >
Next, a layout method of the common centroid layout of the current mirror group according to the embodiment of the present invention will be described.
The common centroid layout of the current mirror group according to the embodiment of the present invention includes: a first transistor group including a dummy transistor 0 and a 1 st transistor 1; a second transistor group 2 including a 2 nd transistor and a 3 rd transistor; a third transistor group 3 including a 4 th transistor, a 5 th transistor, a 6 th transistor, and a 7 th transistor; a fourth transistor group 4 including an 8 th transistor, a 9 th transistor, a 10 th transistor, an 11 th transistor, a 12 th transistor, a 13 th transistor, a 14 th transistor, and a 15 th transistor; a fifth transistor group 5 including 16 th to 23 th transistors and 24 th to 31 th transistors; and a sixth transistor group 6 including 32 th to 47 th transistors and 48 th to 63 th transistors.
In the layout method of the common centroid layout of the current mirror group according to the embodiment of the present invention, the 1 st transistor 1 and the virtual transistor 0 in the first transistor group are arranged in the fourth row, the fourth column, and the fifth row, the fifth column, respectively; disposing the 2 nd transistor and the 3 rd transistor in the second transistor group 2 in the fourth column of the fifth row and the fifth column of the fourth row, respectively; the 4 th transistor and the 5 th transistor in the third transistor group 3 are respectively arranged in the fourth row, the second column and the fourth row, the third column, and the 6 th transistor and the 7 th transistor in the third transistor group 3 are respectively arranged in the fifth row, the sixth column and the seventh column; the 8 th, 9 th, 10 th and 11 th transistors in the fourth transistor group 4 are arranged in the fourth row first column, the fifth row second column and the fifth row third column, respectively, and the 12 th, 13 th, 14 th and 15 th transistors in the fourth transistor group 4 are arranged in the fourth row sixth column, the fourth row seventh column, the fourth row eighth column and the fifth row eighth column, respectively; the 16 th to 23 th transistors in the fifth transistor group 5 are respectively arranged in the first to eighth columns of the third row, and the 24 th to 31 th transistors in the fifth transistor group 5 are respectively arranged in the first to eighth columns of the sixth row; the 32 th to 47 th transistors in the sixth transistor group 6 are arranged in the first row first to eighth column and the second row first to eighth column, respectively, and the 48 th to 63 th transistors in the sixth transistor group 6 are arranged in the seventh row first to eighth column and the eighth row first to eighth column, respectively.
Further, the 1 st transistor 1 in the first transistor group is connected to the first wiring S1, and the dummy transistor 0 in the first transistor group is connected to the dummy wiring S0; connecting both the 2 nd transistor and the 3 rd transistor in the second transistor group 2 with the second wiring S2; connecting the 4 th transistor, the 5 th transistor, the 6 th transistor, and the 7 th transistor in the third transistor group 3 to the third wiring S3; connecting the 8 th, 9 th, 10 th, 11 th, 12 th, 13 th, 14 th, and 15 th transistors in the fourth transistor group 4 to the fourth wiring S4; connecting the 16 th to 23 th transistors and the 24 th to 31 th transistors in the fifth transistor group 5 to the fifth wiring S5; the 32 th to 47 th transistors and the 48 th to 63 th transistors in the sixth transistor group 6 are connected to the sixth wiring S6.
And, disposing a dummy transistor 0 and the 1 st to 63 st transistors in the first layer; the dummy wirings S0, the first wirings S1, the second wirings S2, the third wirings S3, the fourth wirings S4, and the fifth wirings S5 are provided in a second layer different from the first layer; the sixth wiring S6 is provided in a third layer different from the first layer and the second layer.
In a plan view, the dummy wirings S0, the first wirings S1, the second wirings S2, the third wirings S3, the fourth wirings S4, and the fifth wirings S5 are located between the third row and the fourth row and between the fifth row and the sixth row, that is, at the above-mentioned interval 1 'and the above-mentioned interval-1'. The sixth wiring S6 is located between the first row and the second row and between the seventh row and the eighth row, that is, at the above-described interval 3 'and the above-described interval-3'.
According to the layout method of the common centroid layout of the current mirror group, the conventional common centroid layout is improved, so that matching of each transistor and layout of a plurality of wirings connected with each transistor can be realized by using fewer metal layers (two layers, namely a second layer and a third layer in fig. 4 and 5) compared with the conventional common centroid layout (fig. 3); further, only the wiring needs to be provided in one direction of the row direction (in particular, in the odd horizontal intervals in fig. 4 and 5), and thus the area of the entire layout of the current mirror group in plan view can be made small.
It is to be understood that the above description is intended to be illustrative, and not restrictive. For example, the above-described embodiments (and/or aspects thereof) may be used in combination with one another. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the various embodiments of the invention without departing from the scope thereof. While the dimensions and types of materials described herein are intended to define the parameters of the various embodiments of the invention, the various embodiments are not meant to be limiting and are exemplary embodiments. Many other embodiments will be apparent to those of skill in the art upon reading the above description. The scope of the various embodiments of the invention should, therefore, be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.
Industrial applicability
The common centroid layout of the current mirror set of the present invention is applicable to the matching and layout of individual transistors in the current mirror set and the layout of individual wires.
Claims (10)
1. A common centroid layout for a current mirror set, comprising:
a first transistor group including a dummy transistor and a 1 st transistor;
a second transistor group including a 2 nd transistor and a 3 rd transistor;
a third transistor group including a 4 th transistor, a 5 th transistor, a 6 th transistor, and a 7 th transistor;
a fourth transistor group including an 8 th transistor, a 9 th transistor, a 10 th transistor, an 11 th transistor, a 12 th transistor, a 13 th transistor, a 14 th transistor, and a 15 th transistor;
a fifth transistor group including 16 th to 23 th transistors and 24 th to 31 th transistors; and
a sixth transistor group including 32 th to 47 th transistors and 48 th to 63 th transistors,
the 1 st transistor and the dummy transistor in the first transistor group are respectively arranged in a fourth row, a fourth column and a fifth row, and a fifth column,
the 2 nd transistor and the 3 rd transistor in the second transistor group are respectively arranged in a fifth row and a fifth column of a fourth row,
the 4 th transistor and the 5 th transistor in the third transistor group are arranged in a fourth row and a third column respectively,
the 6 th transistor and the 7 th transistor in the third transistor group are respectively arranged in a sixth column of a fifth row and a seventh column of the fifth row,
the 8 th transistor, the 9 th transistor, the 10 th transistor and the 11 th transistor in the fourth transistor group are respectively arranged in a fourth row first column, a fifth row second column and a fifth row third column,
the 12 th transistor, the 13 th transistor, the 14 th transistor, and the 15 th transistor in the fourth transistor group are arranged in a fourth row sixth column, a fourth row seventh column, a fourth row eighth column, and a fifth row eighth column, respectively,
the 16 th to 23 th transistors in the fifth transistor group are arranged in first to eighth columns of a third row,
the 24 th to 31 th transistors in the fifth transistor group are arranged in the first to eighth columns of the sixth row,
the 32 th to 47 th transistors in the sixth transistor group are arranged in the first to eighth columns of the first row and the first to eighth columns of the second row respectively,
the 48 th to 63 th transistors in the sixth transistor group are arranged in the seventh row first to eighth column and the eighth row first to eighth column, respectively.
2. The common centroid layout of a set of current mirrors according to claim 1, wherein,
the 1 st transistor in the first transistor group is connected to a first wiring, the dummy transistor in the first transistor group is connected to a dummy wiring,
the 2 nd transistor and the 3 rd transistor in the second transistor group are both connected to a second wiring,
the 4 th transistor, the 5 th transistor, the 6 th transistor, and the 7 th transistor in the third transistor group are all connected to a third wiring,
the 8 th transistor, the 9 th transistor, the 10 th transistor, the 11 th transistor, the 12 th transistor, the 13 th transistor, the 14 th transistor, and the 15 th transistor in the fourth transistor group are connected to a fourth wiring,
the 16 th to 23 th transistors and the 24 th to 31 th transistors in the fifth transistor group are connected to a fifth wiring,
the 32 th to 47 th transistors and the 48 th to 63 th transistors in the sixth transistor group are connected to a sixth wiring,
the dummy transistors and the 1 st to 63 th transistors are disposed in a first layer,
the dummy wiring, the first wiring, the second wiring, the third wiring, the fourth wiring, and the fifth wiring are provided in a second layer different from the first layer,
the sixth wiring is provided in a third layer different from the first layer and the second layer.
3. The common centroid layout of a set of current mirrors according to claim 2, wherein,
the dummy wirings, the first wirings, the second wirings, the third wirings, the fourth wirings, and the fifth wirings are located between a third row and a fourth row and between a fifth row and a sixth row in a plan view, and the sixth wirings are located between a first row and a second row and between a seventh row and an eighth row.
4. A common centroid layout of a set of current mirrors according to any one of claims 1 to 3,
the type 1 transistor in the first transistor group is type 1,
the type of the 2 nd transistor and the 3 rd transistor in the second transistor group are the same type 2,
the types of the 4 th transistor, the 5 th transistor, the 6 th transistor and the 7 th transistor in the third transistor group are the same 3 rd type,
the types of the 8 th transistor, the 9 th transistor, the 10 th transistor, the 11 th transistor, the 12 th transistor, the 13 th transistor, the 14 th transistor, and the 15 th transistor in the fourth transistor group are the same 4 th type,
the types of the 16 th to 23 th transistors and the 24 th to 31 th transistors in the fifth transistor group are the same type 5,
the types of the 32 th to 47 th transistors and the 48 th to 63 th transistors in the sixth transistor group are the same type 6,
the 1 st type, the 2 nd type, the 3 rd type, the 4 th type, the 5 th type, and the 6 th type are different from each other.
5. The common centroid layout of a set of current mirrors according to claim 2, wherein,
the dummy transistor and the dummy wiring do not operate.
6. A layout method of a common centroid layout of a current mirror set, the common centroid layout of a current mirror set comprising:
a first transistor group including a dummy transistor and a 1 st transistor;
a second transistor group including a 2 nd transistor and a 3 rd transistor;
a third transistor group including a 4 th transistor, a 5 th transistor, a 6 th transistor, and a 7 th transistor;
a fourth transistor group including an 8 th transistor, a 9 th transistor, a 10 th transistor, an 11 th transistor, a 12 th transistor, a 13 th transistor, a 14 th transistor, and a 15 th transistor;
a fifth transistor group including 16 th to 23 th transistors and 24 th to 31 th transistors; and
a sixth transistor group including 32 th to 47 th transistors and 48 th to 63 th transistors,
the layout method is characterized in that,
the 1 st transistor and the dummy transistor in the first transistor group are respectively arranged in a fourth row, a fourth column and a fifth row, and a fifth column,
the 2 nd transistor and the 3 rd transistor in the second transistor group are respectively arranged in a fifth row and a fourth column and a fifth row,
the 4 th transistor and the 5 th transistor in the third transistor group are arranged in a fourth row and a third column respectively,
the 6 th transistor and the 7 th transistor in the third transistor group are respectively arranged in a sixth column of a fifth row and a seventh column of the fifth row,
disposing the 8 th transistor, the 9 th transistor, the 10 th transistor, and the 11 th transistor in the fourth transistor group in a fourth row first column, a fifth row second column, and a fifth row third column, respectively,
disposing the 12 th transistor, the 13 th transistor, the 14 th transistor, and the 15 th transistor in the fourth transistor group in a fourth row sixth column, a fourth row seventh column, a fourth row eighth column, and a fifth row eighth column, respectively,
the 16 th to 23 th transistors in the fifth transistor group are arranged in first to eighth columns of a third row,
the 24 th to 31 th transistors in the fifth transistor group are arranged in the sixth row first to eighth columns respectively,
the 32 th to 47 th transistors in the sixth transistor group are arranged in the first row first to eighth column and the second row first to eighth column respectively,
the 48 th to 63 th transistors in the sixth transistor group are arranged in the seventh row first to eighth column and the eighth row first to eighth column, respectively.
7. The method of claim 6, wherein the common centroid layout of the current mirror set,
connecting the 1 st transistor in the first transistor group with a first wiring, connecting the dummy transistor in the first transistor group with a dummy wiring,
connecting both the 2 nd transistor and the 3 rd transistor in the second transistor group to a second wiring,
the 4 th transistor, the 5 th transistor, the 6 th transistor, and the 7 th transistor in the third transistor group are all connected to a third wiring,
connecting the 8 th transistor, the 9 th transistor, the 10 th transistor, the 11 th transistor, the 12 th transistor, the 13 th transistor, the 14 th transistor, and the 15 th transistor in the fourth transistor group to a fourth wiring,
the 16 th to 23 th transistors and the 24 th to 31 th transistors in the fifth transistor group are connected to a fifth wiring,
the 32 th to 47 th transistors and the 48 th to 63 th transistors in the sixth transistor group are connected to a sixth wiring,
the dummy transistors and the 1 st to 63 th transistors are disposed in a first layer,
the dummy wiring, the first wiring, the second wiring, the third wiring, the fourth wiring, and the fifth wiring are provided in a second layer different from the first layer,
the sixth wiring is provided in a third layer different from the first layer and the second layer.
8. The method of claim 7, wherein the common centroid layout of the current mirror set,
in a plan view, the dummy wirings, the first wirings, the second wirings, the third wirings, the fourth wirings, and the fifth wirings are positioned between a third row and a fourth row and between a fifth row and a sixth row, and the sixth wirings are positioned between a first row and a second row and between a seventh row and an eighth row.
9. A method for placement of a common centroid layout for a set of current mirrors according to any one of claims 6 to 8,
the type 1 transistor in the first transistor group is type 1,
the type of the 2 nd transistor and the 3 rd transistor in the second transistor group are the same type 2,
the types of the 4 th transistor, the 5 th transistor, the 6 th transistor and the 7 th transistor in the third transistor group are the same 3 rd type,
the types of the 8 th transistor, the 9 th transistor, the 10 th transistor, the 11 th transistor, the 12 th transistor, the 13 th transistor, the 14 th transistor, and the 15 th transistor in the fourth transistor group are the same 4 th type,
the types of the 16 th to 23 th transistors and the 24 th to 31 th transistors in the fifth transistor group are the same type 5,
the types of the 32 th to 47 th transistors and the 48 th to 63 th transistors in the sixth transistor group are the same type 6,
the 1 st type, the 2 nd type, the 3 rd type, the 4 th type, the 5 th type, and the 6 th type are different from each other.
10. The method of claim 7, wherein the common centroid layout of the current mirror set,
the dummy transistor and the dummy wiring do not operate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311169463.6A CN117217157A (en) | 2023-09-11 | 2023-09-11 | Common centroid layout of current mirror group and layout method thereof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311169463.6A CN117217157A (en) | 2023-09-11 | 2023-09-11 | Common centroid layout of current mirror group and layout method thereof |
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| CN202311169463.6A Pending CN117217157A (en) | 2023-09-11 | 2023-09-11 | Common centroid layout of current mirror group and layout method thereof |
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