CN117214845B - Radar receiver testing arrangement - Google Patents
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- CN117214845B CN117214845B CN202311476083.7A CN202311476083A CN117214845B CN 117214845 B CN117214845 B CN 117214845B CN 202311476083 A CN202311476083 A CN 202311476083A CN 117214845 B CN117214845 B CN 117214845B
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Abstract
The invention provides a radar receiver testing device, which belongs to the technical field of electronic information, and consists of a testing main board, an FPGA core board and an external expansion board, wherein the FPGA core board comprises a core control device FPGA and a required external configuration circuit, the testing main board comprises a voltage stabilizing protection circuit, a data input circuit, an independent logic output circuit and a plurality of external interfaces, and the expansion board is internally provided with a corresponding interface/level conversion circuit according to the requirements of functions. The invention has small system scale, convenient manufacture and maintenance, low realization cost and good reliability.
Description
Technical Field
The invention belongs to the technical field of electronic information, and particularly relates to a radar receiver testing device.
Background
The radar receiver testing device is necessary equipment in the development process, and is mainly used for providing power supply and various control signals for the radar receiver in ground test. At present, a radar receiver testing device is mostly developed based on a microcomputer. The user should configure control signal in the upper computer software, then send to the computer through the internet access, the computer will get the configuration information to the radar receiver through various data interfaces and level conversion circuits of the testing device, and supply power to the radar receiver, finally realize the control to the radar receiver, the system overall architecture is as shown in figure 1. The current universal ground detector for the space science experimental instrument adopts an ARM7 hardware platform (the core processor is LPC 2290), a real-time operating system mu COS-II is transplanted on the platform, the bottom driving function of each interface is realized, corresponding upper computer software is developed, and a data interface commonly used in a space science experiment effective load is provided. However, the prior art has the following disadvantages: the system has large scale and redundancy, is inconvenient to manufacture and maintain, and has high realization cost; is not easy to operate and has higher requirements for users; the expansion is not easy, the hardware development platform is limited, the external interface is fixed, and the universality is poor; the lack of a power supply protection device has serious consequences of misoperation of a user.
Disclosure of Invention
In order to solve the technical problems, the invention provides a radar receiver testing device, which consists of a testing main board, an FPGA core board and an external expansion board, wherein the FPGA core board comprises a core control device FPGA and a required external configuration circuit, the testing main board comprises a voltage stabilizing protection circuit, a data input circuit, an independent logic output circuit and a plurality of external interfaces, and the expansion board is internally provided with a corresponding interface/level conversion circuit according to the requirements of functions. The system of the invention has small scale, convenient manufacture and maintenance, low realization cost and good reliability.
In order to achieve the above purpose, the invention adopts the following technical scheme:
the radar receiver testing device consists of a testing main board, an FPGA core board and an external expansion board, wherein the FPGA core board and the external expansion board are respectively connected to the testing main board; the FPGA core board comprises a core control device FPGA and an external configuration circuit which is required, so that external input data and control signals are read, and the external input data are sent to the data input circuit on the test main board according to corresponding time sequences; the test main board comprises a voltage stabilizing protection circuit, a data input circuit, an independent logic output circuit and a plurality of external interfaces, and is used for receiving an externally input control signal and transmitting the externally input control signal to the FPGA core board, and providing a stable power supply and an independent TTL level signal for the tested radar receiver; the expansion board comprises an interface/level conversion circuit for converting interface levels and converting differential/single-ended signals.
Further, the voltage stabilizing protection circuit is a 5V voltage stabilizing overvoltage and overcurrent protection circuit.
Further, in the 5V voltage-stabilizing overvoltage and overcurrent protection circuit, the input of an external power supply is stabilized by a voltage-stabilizing chip LM7805 at first and then passes through an overvoltage and overcurrent protection chip MAX14586; if the voltage is higher than the set protection threshold, the overvoltage and overcurrent protection chip MAX14586 breaks the circuit, so that damage to the subsequent-stage circuit and components is avoided; the threshold value for overvoltage protection is set by two external resistors.
Further, the data input circuit consists of four groups of 8-bit dial switches and parallel-serial chips, the required control signals are realized by configuring the dial switches, and the control signals of each channel are at most 32 bits; when the device works, a control signal configured by the dial switch is converted into serial codes by the parallel-serial chip, and then the serial codes are spliced into 32 bits by cascading.
Further, the independent logic output circuit outputs a high level or low level signal according to the requirement and indicates the signal through the light emitting diode; when the switch is closed, a high level is output, the triode is conducted, and the diode emits light; when the switch is turned off, a low level is output, the triode is turned off, and the diode does not emit light.
Further, the internal program of the FPGA core board comprises a key detection module, a channel/working mode selection module, a parallel-serial chip driving module, a data transmission module and a transmission completion indication module.
Further, the key detection module is used for detecting whether an external key is pressed down or not so as to trigger the subsequent module to generate time sequence read data; the channel/working mode selection module is used for determining whether the data of the two channels are independently transmitted or are transmitted after being spliced; the parallel-serial chip driving module is used for generating required time to read external data; the data transmission module is used for transmitting the read data to the external circuit module according to the required time sequence, and the external circuit module is a control circuit in the radar receiver to be tested; and the sending completion indication module generates a signal after the data sending is completed so as to complete homing of the FPGA internal state machine.
Further, the external expansion board is flexibly configured according to the requirement.
Further, the external expansion board comprises an RS422 receiving and driving circuit, so that the conversion of the RS422 signal and the TTL signal is realized.
The beneficial effects are that:
1. the device is internally provided with the power supply protection device, so that the damage to tested equipment caused by misoperation of a user can be avoided.
2. The system has small scale, convenient manufacture and maintenance, low realization cost and good reliability.
3. The operation is simple, and the requirement on operators is low.
4. The function is abundant, and most of test requirements can be met.
5. Compatibility designs, which have two modes of operation, can provide test signals for the multichannel receiver and the TR module.
6. The reserved expansion interface has good expansibility, and the external expansion board can be flexibly configured according to the requirement.
7. The core control device is separated from the main board, so that the disassembly, the assembly and the reuse are convenient.
Drawings
FIG. 1 is a system architecture diagram of a radar receiver testing apparatus of the present invention;
FIG. 2 is a system block diagram of a radar receiver testing apparatus according to the present invention;
FIG. 3 is a 5V voltage stabilizing overvoltage and overcurrent protection circuit diagram;
FIG. 4 is a diagram of an independent logic output circuit;
fig. 5 is a program architecture diagram of an FPGA.
Detailed Description
The present invention will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present invention more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention. In addition, the technical features of the embodiments of the present invention described below may be combined with each other as long as they do not collide with each other.
As shown in fig. 2, the radar receiver testing device of the present invention is composed of a testing main board, an FPGA core board, and an external expansion board. The FPGA core board comprises a core control device FPGA and a required external configuration circuit, the test main board comprises a voltage stabilizing protection circuit, a data input circuit, an independent logic output circuit and a plurality of external interfaces, and the expansion board is provided with a corresponding interface/level conversion circuit according to the function requirement and comprises a TTL and 0/-5V level conversion circuit (12 paths in total), an RS422 differential receiving circuit and an RS422 differential driving circuit. The voltage stabilizing protection circuit is a 5V voltage stabilizing overvoltage and overcurrent protection circuit. The data input circuit consists of four groups of 8-bit dial switches and parallel-serial chips, the required control signals are realized by configuring the dial switches, and the control signals of each channel are at most 32 bits. When the device works, a control signal configured by the dial switch is converted into serial codes by the parallel-serial chip, and then the serial codes are spliced into 32 bits by cascading. Two sending buttons are designed on the testing main board, and after being pressed, the two sending buttons can generate level signals, so that the FPGA core board sends control signals of the first channel or the second channel. A mode switch is designed on the test main board, and the FPGA core board is enabled to work in different working modes through the toggle switch. The FPGA core board sends out the control signal of the first channel or the second channel by receiving the control signal on the test main board, and mainly comprises data, latch and clock signals. The external interface is a general IO port.
As shown in fig. 3, in the 5V voltage-stabilizing overvoltage and overcurrent protection circuit, the input of the external power supply is stabilized by the voltage-stabilizing chip LM7805 first, and then passes through the overvoltage and overcurrent protection chip MAX14586. If the voltage is higher than the set protection threshold, the overvoltage and overcurrent protection chip MAX14586 can break the circuit, and damage to the subsequent-stage circuit and components is avoided. The threshold value for the overvoltage protection can be set by an external circuit.
As shown in fig. 4, the independent logic output circuit may output a high level signal or a low level signal as required and indicated by the light emitting diode. When the switch is closed, a high level is output, the triode is conducted, and the diode emits light; when the switch is turned off, a low level is output, the triode is turned off, and the diode does not emit light.
As shown in fig. 5, the FPGA core board mainly realizes reading of external input data and control signals, and sends the external input data to the corresponding circuit module according to the corresponding time sequence. The FPGA internal program mainly comprises a key detection module, a channel/working mode selection module, a parallel-serial chip driving module, a data transmission module, a transmission completion indication module and the like.
The key detection module is used for detecting whether an external key is pressed or not so as to trigger the subsequent module to generate time sequence read data. The channel/working mode selection module is used for determining whether the data of the two channels are independently transmitted or are transmitted after being spliced. The parallel-serial chip driving module is used for generating required time to read external data. The data transmitting module is used for transmitting the read data to the external circuit module according to the required time sequence. The external circuit module refers to a control circuit inside the receiver device under test. And the sending completion indication module generates a signal after the data sending is completed so as to complete homing of the FPGA internal state machine.
The external expansion board can be flexibly configured as required, and the RS422 receiving and driving circuit is taken as an example only. The RS422 receiving and driving circuits respectively adopt corresponding chips to realize the conversion of the RS422 signal and the TTL signal.
The first channel and the second channel send signals to the key detection module, and the working mode is selected through the channel/working mode selection module. The channel clock signals, the channel selection signals and the channel data input of the first channel and the second channel are respectively input into the parallel-serial chip driving module, and then whether the transmission is completed is displayed through the transmission completion indication module. And transmitting data through the data transmitting module according to the selected working mode. And finally, realizing channel latching (rising edge/falling edge), channel clock (rising edge/falling edge) and channel data output contents of the first channel and the second channel according to a specific working mode.
It will be readily appreciated by those skilled in the art that the foregoing description is merely a preferred embodiment of the invention and is not intended to limit the invention, but any modifications, equivalents, improvements or alternatives falling within the spirit and principles of the invention are intended to be included within the scope of the invention.
Claims (8)
1. The radar receiver testing device is characterized by comprising a testing main board, an FPGA core board and an external expansion board, wherein the FPGA core board and the external expansion board are respectively connected to the testing main board; the test main board comprises a voltage stabilizing protection circuit, a data input circuit, an independent logic output circuit and a plurality of external interfaces, and is used for receiving an externally input control signal and transmitting the externally input control signal to the FPGA core board, and providing a stable power supply and an independent TTL level signal for the tested radar receiver; the FPGA core board comprises an FPGA and an external configuration circuit which is required, so that external input data and control signals are read, and the external input data are sent to the data input circuit on the test main board according to corresponding time sequences; the expansion board comprises an interface/level conversion circuit, a signal conversion circuit and a signal conversion circuit, wherein the interface/level conversion circuit is used for converting interface levels and converting differential/single-ended signals;
in the 5V voltage-stabilizing overvoltage and overcurrent protection circuit, the input of an external power supply is stabilized through a voltage-stabilizing chip LM7805 at first and then passes through an overvoltage and overcurrent protection chip MAX14586; if the voltage is higher than the set protection threshold, the overvoltage and overcurrent protection chip MAX14586 breaks the circuit, so that damage to the subsequent-stage circuit and components is avoided; the protection threshold for overvoltage protection is set by two external resistors.
2. The radar receiver testing apparatus of claim 1, wherein the voltage stabilizing protection circuit is a 5V voltage stabilizing overvoltage overcurrent protection circuit.
3. The radar receiver testing device according to claim 1, wherein the data input circuit is composed of four groups of 8-bit dial switches and parallel-serial chips, the required control signals are realized by the configured dial switches, and the control signals of each channel are at most 32 bits; when the device works, a control signal configured by the dial switch is converted into serial codes by the parallel-serial chip, and then the serial codes are spliced into 32 bits.
4. The radar receiver testing apparatus according to claim 1, wherein the independent logic output circuit outputs a high level signal or a low level signal as required and is indicated by the light emitting diode; when the switch is closed, a high level is output, the triode is conducted, and the diode emits light; when the switch is turned off, a low level is output, the triode is turned off, and the diode does not emit light.
5. The radar receiver testing apparatus according to claim 1, wherein the internal program of the FPGA core board includes a key detection module, a channel/operation mode selection module, a parallel-serial chip driving module, a data transmission module, and a transmission completion indication module.
6. The radar receiver testing apparatus of claim 5, wherein the key detection module is configured to detect whether an external key is pressed to trigger a subsequent module to generate time-series read data; the channel/working mode selection module is used for determining whether the data of the two channels are independently transmitted or are transmitted after being spliced; the parallel-serial chip driving module is used for generating required time and reading external data; the data transmission module is used for transmitting the read data to the external circuit module according to the required time sequence, and the external circuit module is a control circuit in the radar receiver to be tested; and the sending completion indication module generates a signal after the data sending is completed so as to complete homing of an internal state machine of the FPGA.
7. A radar receiver testing apparatus according to claim 1, wherein the external expansion board is flexibly configured as required.
8. The radar receiver testing apparatus of claim 1, wherein the external expansion board includes an RS422 receiving and driving circuit to convert an RS422 signal to a TTL signal.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311476083.7A CN117214845B (en) | 2023-11-08 | 2023-11-08 | Radar receiver testing arrangement |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202311476083.7A CN117214845B (en) | 2023-11-08 | 2023-11-08 | Radar receiver testing arrangement |
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| CN117214845A CN117214845A (en) | 2023-12-12 |
| CN117214845B true CN117214845B (en) | 2024-01-26 |
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE4231311A1 (en) * | 1992-09-18 | 1994-03-24 | Siemens Ag | Ascertaining transmission channel pulse response - filtering received test signal to eliminate noise component before evaluation |
| CN102323573A (en) * | 2011-06-17 | 2012-01-18 | 哈尔滨工业大学 | Linux-based radar simulating device and method |
| CN206331109U (en) * | 2016-12-13 | 2017-07-14 | 九江精密测试技术研究所 | A kind of radar range finding circuit |
| CN107015212A (en) * | 2017-06-13 | 2017-08-04 | 中国电子科技集团公司第三十八研究所 | Universal interface board of the radar wave control based on VPX buses with monitoring platform of testing oneself |
| CN213023604U (en) * | 2020-10-23 | 2021-04-20 | 青岛中电众益智能科技发展有限公司 | High-speed high-precision intelligent ground penetrating radar system |
| CN116609737A (en) * | 2023-04-28 | 2023-08-18 | 四创电子股份有限公司 | FPGA-based radar monitoring system and method |
-
2023
- 2023-11-08 CN CN202311476083.7A patent/CN117214845B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE4231311A1 (en) * | 1992-09-18 | 1994-03-24 | Siemens Ag | Ascertaining transmission channel pulse response - filtering received test signal to eliminate noise component before evaluation |
| CN102323573A (en) * | 2011-06-17 | 2012-01-18 | 哈尔滨工业大学 | Linux-based radar simulating device and method |
| CN206331109U (en) * | 2016-12-13 | 2017-07-14 | 九江精密测试技术研究所 | A kind of radar range finding circuit |
| CN107015212A (en) * | 2017-06-13 | 2017-08-04 | 中国电子科技集团公司第三十八研究所 | Universal interface board of the radar wave control based on VPX buses with monitoring platform of testing oneself |
| CN213023604U (en) * | 2020-10-23 | 2021-04-20 | 青岛中电众益智能科技发展有限公司 | High-speed high-precision intelligent ground penetrating radar system |
| CN116609737A (en) * | 2023-04-28 | 2023-08-18 | 四创电子股份有限公司 | FPGA-based radar monitoring system and method |
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