CN117200904A - PCMA signal and APCMA signal non-cooperative processing system - Google Patents

Abstract

A PCMA signal and APCMA signal non-cooperative processing system comprising: the signal receiving subsystem is used for receiving signals of multiple paths of preset frequency bands; a down-conversion subsystem for performing frequency conversion processing on the received signal to form an intermediate frequency signal; the intermediate frequency acquisition subsystem is used for carrying out ADC acquisition on the intermediate frequency signals and carrying out high-fidelity preprocessing on the acquired data so as to obtain digital signals with high sampling rate and high resolution; the data processing subsystem is used for carrying out parameter estimation on the digital signals, respectively carrying out self-signal estimation on the basis of the communication signals of the two parties so as to finish interference cancellation, and separating and demodulating PCMA main small signal data; and the data storage subsystem is used for storing PCMA main small signal data. Meanwhile, PCMA signals and APCMA signals of the frequency bands of 950 MHz-2150 MHz are collected, processed, analyzed and stored in real time, and useful signals are rapidly and efficiently identified and managed.

Description

PCMA signal and APCMA signal non-cooperative processing system

Technical Field

The application belongs to the technical field of satellite communication and non-cooperative communication, and particularly relates to a PCMA signal and APCMA signal non-cooperative processing system.

Background

The satellite communication network is closely related to the life and work of human beings, and is highly dependent on television broadcasting, mobile signals, remote data receiving and transmitting and navigation and early warning in the military field in daily life, thereby bringing great economic and military benefits to the human beings. With the increase of the number of transmitted satellites, the frequency band resources are gradually exhausted, and the competition of each country for the frequency band enters a white thermalization stage.

The PCMA (Paired Carrier Multiple Access ) technology is used as a satellite communication multiple access multiplexing technology, which allows two terminals to use completely the same uplink frequency and downlink frequency, and the two-way satellite communication links are completely overlapped in the time domain and the frequency domain, so that approximately half of broadband resources can be saved based on the PCMA technology, and the utilization efficiency of the frequency band is obviously improved, so that the PCMA technology is widely applied in a satellite communication system. PCMA signals belong to time-frequency aliasing signals, and the two modulation signals are in the same frequency, have the same modulation mode, have different time delays, have fine carrier frequency deviation, and have stronger anti-interception capability.

The APCMA (Asymmetric Paired Carrier Multiple Access) signal is one application of the paired carrier multiple access technique in an asymmetric mode. The APCMA signal is mainly characterized in that multipath small-bandwidth low-power small-station weak signals and large-bandwidth high-power main station strong signals are overlapped in a time-frequency domain, the frequency spectrums of all the small-station weak signals are in the main station strong signal frequency band, the frequency spectrums of all the small-station weak signals are not overlapped, so that the frequency spectrum resources are effectively saved, and the anti-interception performance of the small-station weak signals is improved.

In non-cooperative communication (also called "blind demodulation or third party reception, monitoring"), it is difficult to accurately identify the modulation mode, symbol rate and carrier frequency of the received PCMA signal and APCMA signal in a conventional signal processing system, and a correspondingly powerful system is also required as a support.

Disclosure of Invention

In order to solve the defects of the related prior art, the application provides a PCMA signal and APCMA signal non-cooperative processing system, and simultaneously, the PCMA signal and the APCMA signal are collected, processed, analyzed and stored in real time, and useful signals are quickly and efficiently identified and managed.

In order to achieve the object of the application, the following scheme is adopted:

a PCMA signal and APCMA signal non-cooperative processing system comprising:

the signal receiving subsystem is used for receiving signals of multiple paths of preset frequency bands;

a down-conversion subsystem for performing frequency conversion processing on the received signal to form an intermediate frequency signal;

the intermediate frequency acquisition subsystem is used for carrying out ADC acquisition on the intermediate frequency signals and carrying out high-fidelity preprocessing on the acquired data so as to obtain digital signals with high sampling rate and high resolution;

the data processing subsystem is used for carrying out parameter estimation on the digital signals, respectively carrying out self-signal estimation on the basis of the communication signals of the two parties so as to finish interference cancellation, and separating and demodulating PCMA main small signal data;

and the data storage subsystem is used for storing PCMA main small signal data.

Further, the signal receiving subsystem comprises an antenna unit for receiving signals through the phased array antenna and a low noise amplifier for amplifying and filtering the received signals and inputting the amplified signals to the down-conversion subsystem.

Further, the down-conversion subsystem comprises a plurality of down-conversion modules for converting the input multipath signals into intermediate frequency signals and providing the intermediate frequency signals to the intermediate frequency acquisition subsystem, for receiving multipath external reference inputs, for outputting sampling clocks for providing to the intermediate frequency acquisition subsystem for sampling external clocks, and for performing work setting and status reading through an SPI interface provided by the down-conversion modules.

Further, the down-conversion module comprises a down-conversion channel, a local oscillation part and a control circuit, wherein the control circuit is connected with the down-conversion channel and the local oscillation part, and the down-conversion channel is connected with the local oscillation part;

the control circuit comprises an FPGA and an accessory circuit thereof;

the local oscillator part comprises a reference circuit, a first local oscillator and a second local oscillator, wherein the reference circuit is used for automatically synchronizing an internal constant-temperature crystal oscillator when an external reference clock is input, outputting 4 paths of clock signals, 2 paths of clock signals are respectively used as the reference clock signals of the first local oscillator and the second local oscillator, 1 path of clock signals is used as an FPGA (field programmable gate array) of the control circuit, and 1 path of clock signals is amplified and filtered and then is output as a sampling clock to be provided for the intermediate frequency acquisition subsystem for sampling the external clock; the first local oscillator is used for carrying out large-step frequency sweep on the reference clock signal to generate a first local oscillator signal, and the first local oscillator signal is used as a first driving local oscillator after being amplified and filtered; the second local oscillator is used for carrying out small stepping frequency sweep on the reference clock signal to generate a second local oscillator signal, and the second local oscillator signal is used as a second driving local oscillator after being amplified and filtered;

the down-conversion channel is used for limiting amplitude of an input signal, passing through a gating pre-amplifying circuit controlled by an FPGA of the control circuit, then passing through a two-way switch, band-pass filtering, low-pass filtering, amplifying, digital-control attenuating and re-filtering, mixing with a first driving local oscillator to form a first intermediate frequency signal, mixing the first intermediate frequency signal with a second driving local oscillator to form a second intermediate frequency signal after filtering, amplifying and digital-control attenuating, intermediate frequency filtering, amplifying, digital-control attenuating and filtering, and outputting the second intermediate frequency signal to the intermediate frequency acquisition subsystem.

Still further, the first local oscillator adopts an independent phase-locked loop and a wide frequency VCO to realize large stepping frequency sweep of 4.33 GHz-5.53 GHz, and the second local oscillator adopts an independent phase-locked loop and a narrow frequency VCO to realize small stepping frequency sweep of two point frequency signals of 3.24GHz and 3.28 GHz.

Still further, the down-conversion channel includes a limiter, a gating pre-amplification circuit, two switches, a band-pass filter, a first low-pass filter, a first amplifier, a first digital control attenuator, a first filter, a first mixer, a second filter, a second amplifier, a second digital control attenuator, a second mixer, a second low-pass filter, a third amplifier, a third digital control attenuator, an intermediate frequency filter, a fourth amplifier, a fourth digital control attenuator, and a third filter that are sequentially connected.

Further, the intermediate frequency acquisition subsystem includes:

the ADC is used for carrying out ADC sampling on the input intermediate frequency signal to realize analog-to-digital conversion;

the FPGA is connected with the ADC and used for carrying out high-fidelity pretreatment on the data after analog-digital conversion;

a switching chip for selecting one from an external reference/external clock, or a local clock;

the DDS is connected with the switching chip and is used for being configured into a direct mode when the switching chip selects the external reference/external clock, and the clock is directly output; when the switching chip selects the local clock, the corresponding sampling rate clock is configured according to the local clock and then output;

and the clock distribution chip is connected with the DDS, FPGA, ADC and used for distributing the clock output by the DDS to the ADC and the FPGA.

Further, the data processing subsystem comprises a GPU array card group, the data storage subsystem comprises a RAID card and a plurality of magnetic disks connected with the RAID, and each GPU card and the RAID card of the GPU array card group are respectively connected with the bus slot through PCIe interfaces.

Further, the system also comprises a software control subsystem for executing the instruction issued by the client, transmitting the instruction to each subsystem, and collecting data from each subsystem and feeding back the state to the client.

The software control subsystem comprises down-conversion embedded software for the down-conversion subsystem, intermediate frequency acquisition embedded software for the intermediate frequency acquisition subsystem and control software connected with the storage subsystem.

The control software is used for executing the instruction issued by the client and collecting information from the storage subsystem and the intermediate frequency acquisition embedded software for returning, the issued instruction is transmitted to the intermediate frequency acquisition embedded software connected through the PCIe interface through the Windows system, the intermediate frequency acquisition embedded software controls ADC acquisition and preprocessing of the intermediate frequency acquisition subsystem according to the issued instruction, issues the instruction for controlling and acquiring the state of the down-conversion subsystem through the SPI interface, and the down-conversion embedded software performs down-conversion processing according to the instruction of the SPI interface and feeds back the state.

The application has the beneficial effects that:

1. the PCMA signals and the APCMA signals of the frequency bands of the multipaths 950 MHz-2150 MHz can be simultaneously collected, processed and stored in real time;

2. the PCMA and APCMA signals can be identified quickly and efficiently.

Drawings

Fig. 1 shows a system configuration block diagram of an embodiment of the present application.

Fig. 2 shows a block diagram of a signal receiving subsystem according to an embodiment of the application.

Fig. 3 shows a block diagram of a down-conversion module according to an embodiment of the application.

Fig. 4 shows a block diagram of the down-conversion channel structure of an embodiment of the present application.

Fig. 5 shows a block diagram of the intermediate frequency acquisition subsystem according to an embodiment of the application.

FIG. 6 is a block diagram of a data processing subsystem and a data storage subsystem according to an embodiment of the present application.

FIG. 7 shows a block diagram of a software control subsystem according to an embodiment of the application.

FIG. 8 shows a data processing subsystem processing flow diagram of an embodiment of the present application.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present application more apparent, the following detailed description of the embodiments of the present application will be given with reference to the accompanying drawings, but the described embodiments of the present application are some, but not all embodiments of the present application.

The embodiment of the application provides a PCMA signal and APCMA signal non-cooperative processing system which is used for collecting, processing, analyzing and storing PCMA and APCMA signals in a multipath 950 MHz-2150 MHz frequency band in real time, so that useful signals can be identified and managed quickly and efficiently.

As shown in fig. 1, the system includes a signal receiving subsystem, a down-conversion subsystem, an intermediate frequency acquisition subsystem, a data processing subsystem, a data storage subsystem, and the like.

The signal receiving subsystem is used for receiving signals in multiple paths of frequency bands of 950 MHz-2150 MHz; the down-conversion subsystem is used for carrying out frequency conversion processing on the received signals to form intermediate frequency signals, wherein the intermediate frequency signals are 70MHz plus or minus 18MHz or 140MHz plus or minus 36MHz; the intermediate frequency acquisition subsystem is used for carrying out ADC acquisition on the intermediate frequency signals and carrying out high-fidelity preprocessing on the acquired data so as to obtain digital signals with high sampling rate and high resolution; the data processing subsystem is used for carrying out parameter estimation on the digital signals, respectively carrying out self-signal estimation on the basis of the communication signals of the two parties so as to finish interference cancellation, and separating and demodulating PCMA main small signal data; the data storage subsystem is used for storing PCMA main small signal data.

As shown in fig. 2, the signal receiving subsystem of the present example mainly includes an antenna unit for receiving a signal through a phased array antenna, and a low noise amplifier LNA for amplifying and filtering the received signal and inputting the amplified signal to the down-conversion subsystem.

The shape of the directional diagram can be changed through the feed phase of the radiation unit in the phased array antenna, the control phase can change the direction of the maximum value of the directional diagram of the antenna so as to achieve the purpose of beam scanning, and parameters such as the level of a side lobe, the position of the minimum value and the like can be controlled through weighting optimization. The LNA has high amplification gain and low noise coefficient, and can effectively amplify weak signals to a large enough amplitude so as to effectively process the signals subsequently. The LNA mainly comprises an amplifier, a filter and a voltage stabilizing circuit, wherein the amplifier is a core component of the LNA, and has the function of amplifying an input signal to a large enough amplitude, the filter is used for filtering clutter and noise of the input signal, the quality of an output signal is ensured, and the voltage stabilizing circuit is used for stabilizing voltage and ensuring the stable operation of the amplifier.

The down-conversion subsystem of the embodiment comprises a plurality of down-conversion modules, and adopts a standard PCIe card structure to realize the frequency conversion of the input signals with the frequency range of 950MHz to 2150MHz to the intermediate frequency of 70MHz plus or minus 18MHz or 140MHz plus or minus 36MHz; meanwhile, the system can receive a plurality of paths of external reference inputs, can output a sampling clock to be provided for an intermediate frequency acquisition subsystem for sampling the external clock, and can finish the setting of the working function of the module and the acquisition of the state through an SPI interface.

As shown in fig. 3, the down-conversion module includes a down-conversion channel, a local oscillation section, a control circuit, and a power supply section, wherein the control circuit is connected to the down-conversion channel and the local oscillation section, the down-conversion channel is connected to the local oscillation section, and the power supply section is used for supplying power to the module.

One implementation form of the down-conversion channel is shown in fig. 4, and includes a limiter, a gating pre-amplification circuit, two switches, a band-pass filter, a first low-pass filter, a first amplifier, a first digital control attenuator, a first filter, a first mixer, a second filter, a second amplifier, a second digital control attenuator, a second mixer, a second low-pass filter, a third amplifier, a third digital control attenuator, an intermediate frequency filter, a fourth amplifier, a fourth digital control attenuator, and a third filter, which are sequentially connected.

The source part converts the 12V power supply provided by the PCIe interface into +5V, +3.3V, -3.3V, +1.0V and other voltages required by each circuit/part in the module through DC/DC and LDO.

The control circuit comprises an FPGA and an accessory circuit thereof, and is used for completing operations such as protocol analysis, device initialization, frequency calculation, calibration data reading and writing and the like.

The local oscillator part comprises a reference circuit, a first local oscillator and a second local oscillator. The reference circuit part mainly realizes automatic detection of an external 10MHz reference signal, and automatically synchronizes an internal 93.3/186.6MHz constant-temperature crystal oscillator when the external reference signal is input; the 186.6MHz clock signal is output in 4 paths, two paths are used as reference signals of a first local oscillator and a second local oscillator, one path is used as a clock signal of the FPGA, and the other path is output as a sampling clock after amplification and filtering and is used for sampling an external clock by the intermediate frequency acquisition subsystem.

The first local oscillator realizes large stepping frequency sweep of 4.33 GHz-5.53 GHz, is realized by adopting an independent phase-locked loop and a VCO with wide frequency, and the generated first local oscillator signal is used as a first driving local oscillator of a first mixer after being amplified and filtered; the second local oscillator realizes two point frequency signals of 3.24GHz and 3.28GHz, but the point frequency signal can realize small steps in a range of a few M (such as a range of 1M) to cover the step frequency of the first local oscillator so as to ensure the step requirement of the whole board card for 1kHz frequency, and the second local oscillator signal is also realized by adopting an independent phase-locked loop and a VCO with narrow frequency and is used as a second driving local oscillator of a second mixer after being amplified and filtered.

The down-conversion channel carries out amplitude limiting on an input signal in the frequency range of 950 MHz-2150 MHz, the signal passes through a gating pre-amplification circuit controlled by an FPGA of a control circuit, then sequentially passes through two paths of switches, a band-pass filter, a first low-pass filter, a first amplifier and a first numerical control attenuator, after the signal is filtered by the first filter, the first intermediate frequency signal is mixed with a first driving local oscillator of 4.33 GMHz-5.53 GMHz to form a first intermediate frequency signal of 3380MHz or 3350MHz, after the first intermediate frequency signal sequentially passes through a second filter, a second amplifier and a second numerical control attenuator, the second intermediate frequency signal is mixed with a second driving local oscillator to form a second intermediate frequency signal with 70MHz/36MHz bandwidth or 140MHz/72MHz bandwidth, and the second intermediate frequency signal passes through a second low-pass filter, a third amplifier and a third numerical control attenuator, and then sequentially passes through a fourth amplifier, a fourth numerical control attenuator and a third filter after the corresponding intermediate frequency signal provided by the first-stage gating circuit is mixed with a first driving local oscillator of 70MHz or 140MHz, and the second intermediate frequency signal is output to an intermediate frequency collecting subsystem.

In the non-cooperative monitoring field of this example, it is necessary to process signals superimposed by main small signals such as PCMA/APCMA, so that it is necessary to ensure that the sampling rate of intermediate frequency preprocessing is high and the resolution is high, and only then a high-fidelity digital signal can be provided for the subsequent data processing subsystem, so that the main small station signal can be successfully separated from the PCMA/APCM, and because of the high complexity of the signals, this example provides a high-fidelity intermediate frequency acquisition subsystem, mainly performs ADC acquisition on the intermediate frequency signal output by the down-conversion module, digitally processes the acquired data, and transmits the acquired data to the data processing subsystem through a high-speed PCIe interface. Specifically, as an implementation form, as shown in fig. 5, an ADC, an FPGA, a switching chip, a DDS, a clock distribution chip, a buffer chip, and the like are included.

The FPGA can select XC7VX690T type products, and the cache chip is connected with the FPGA and used for providing a cache space, and particularly, a plurality of DDR3-1600 cache chips can be selected. The ADC chip can be a single-channel, 16-bit and 250MSPS analog-to-digital converter (ADC), the digital interface is an LVDS data interface, and the on-chip buffer and the sample hold circuit are arranged in the chip, and the ADC chip is designed specifically for low power consumption, small size and usability and has the characteristics of high performance, high bandwidth and usability. The chip is optimized for high performance, high bandwidth and ease of use. The DDS adopts a 2.5GSPS direct digital frequency synthesizer AD9915, the device can output a 1.25GHz analog signal, and the frequency control word is adjustable; its DDS output provides a reference clock to the clock chip.

ADC samples the input intermediate frequency signal to realize analog-to-digital conversion; the FPGA is connected with the ADC, and high-fidelity preprocessing is carried out on the data after the analog-to-digital conversion; the switching chip selects one from an external reference/external clock, or a local clock, where the external clock may be provided by a down-conversion subsystem; the DDS is connected with the switching chip, and is configured into a through mode when the switching chip selects an external reference/external clock, and the clock is directly output; when the switching chip selects the local clock, the corresponding sampling rate clock is configured according to the local clock and then output; the clock distribution chip is connected with DDS, FPGA, ADC and distributes the clock output by the DDS to the ADC and the FPGA.

In order to separate main small signal data and extract information from PCMA/APCMA signals, and analyze the PCMA signals under the non-cooperative condition (signal blind demodulation), PCMA is used as a self-interference signal, accurate time delay, frequency, phase, amplitude and other parameter estimation is needed, and self-signal estimation is respectively carried out on the basis of the included communication signals of the two parties so as to finish interference cancellation, thereby realizing the separation demodulation of the PCMA signals, ensuring that the construction of an operation amount and a separation model becomes complex, and processing the PCMA signals for blind demodulation, and constructing the data processing subsystem according to the embodiment of the application.

The data processing subsystem of the embodiment of the application comprises a GPU array card group, and the processing of special signals is realized by utilizing the computing processing capacity of the GPU array card, as shown in fig. 6.

As shown in fig. 8, the specific data processing subsystem performs the following processing: signal detection is carried out to obtain signals such as frequency, bandwidth, signal-to-noise ratio, level and the like of the signals; a debugging mode of obtaining signals by debugging and identification; demodulating the signal to IQ data to obtain a constellation diagram of the signal; the coding mode and the code rate of the signal are analyzed through coding identification; and then signal decoding and signal system identification are carried out to obtain the signal system type, and finally a signal characteristic database is formed.

In this example, the data storage subsystem includes a RAID card and a plurality of disks connected to the RAID, as shown in fig. 6, where each GPU card and the RAID card of the GPU array card set are connected to the bus slot through PCIe interfaces, respectively.

The present example utilizes disk array RAID techniques to increase the transfer rate by using multiple disks simultaneously, and to substantially increase the data throughput of the storage system by storing and reading data on multiple disks simultaneously.

The disk drive, the down-conversion module, the intermediate frequency acquisition module and the data processing system are connected into an integrated system through a RAID array card inserted in a host bus slot. After the data processing system processes the data, the generated data is stored in a computer disk array through a RAID array card, so that the research is convenient.

As a further embodiment of the present application, the system further includes a software control subsystem, configured to execute the instruction issued by the client, transmit the instruction to each subsystem, and collect data from each subsystem, and feed back the status to the client.

The software control subsystem architecture can adopt a C/S architecture, namely a server and a client, wherein the server is responsible for executing instructions issued by the client, collecting data, processing the data and feeding back the state of the server; the client is in charge of communicating with the user, and the user sends an instruction through the client to check the states of tasks of the server. The adoption of the C/S architecture is convenient for remote control, realizes separation of a control end and a data processing end, and is convenient for centralized deployment of the system. And the service software is designed in a layered manner, each module is independent as far as possible, the coupling between the software and the hardware is reduced, and the data transmission efficiency and the system stability are improved.

As shown in fig. 7, the software control subsystem includes down-conversion embedded software for the down-conversion subsystem, intermediate frequency acquisition embedded software for the intermediate frequency acquisition subsystem, and control software coupled to the storage subsystem.

The control software is used for executing the instructions issued by the client, collecting information from the storage subsystem and the intermediate frequency acquisition embedded software for feedback, realizing PCIe interface drive and interface API, storing data and the like, transmitting the issued instructions with the intermediate frequency acquisition embedded software connected through the PCIe interface through the Windows system, controlling ADC acquisition and preprocessing of the intermediate frequency acquisition subsystem according to the issued instructions, issuing instructions for controlling and acquiring the state of the down-conversion subsystem through the SPI interface, and performing down-conversion processing and feeding back the state by the down-conversion embedded software according to the instructions of the SPI interface.

The control software is communicated with the FPGA of the down-conversion module through an SPI protocol, the FPGA of the down-conversion module receives the control software data and then analyzes the control software data, and the data is written into the register in a parallel bus mode.

The software part of the specific data processing subsystem is also designed in the intermediate frequency acquisition embedded software, and the data processing subsystem performs the processing shown in fig. 8 through the cooperation of the embedded software, including performing signal detection to obtain signals such as frequency, bandwidth, signal-to-noise ratio, level and the like of the signals; a debugging mode of obtaining signals by debugging and identification; demodulating the signal to IQ data to obtain a constellation diagram of the signal; the coding mode and the code rate of the signal are analyzed through coding identification; and then signal decoding and signal system identification are carried out to obtain the signal system type, and finally a signal characteristic database is formed.

Specifically, the signal characteristic database formed by processing by the data processing subsystem is stored in the storage subsystem, and the formed signal characteristic data is stored in the storage subsystem through PCIe interface, windows system and control software after being packaged.

The foregoing description of the preferred embodiments of the application is merely exemplary and is not intended to be exhaustive or limiting of the application. It will be understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof without departing from the scope of the application.

Claims (10)

1. A PCMA signal and APCMA signal non-cooperative processing system, comprising:

the signal receiving subsystem is used for receiving signals of multiple paths of preset frequency bands;

a down-conversion subsystem for performing frequency conversion processing on the received signal to form an intermediate frequency signal;

the intermediate frequency acquisition subsystem is used for carrying out ADC acquisition on the intermediate frequency signals and carrying out high-fidelity preprocessing on the acquired data so as to obtain digital signals with high sampling rate and high resolution;

the data processing subsystem is used for carrying out parameter estimation on the digital signals, respectively carrying out self-signal estimation on the basis of the communication signals of the two parties so as to finish interference cancellation, and separating and demodulating PCMA main small signal data;

and the data storage subsystem is used for storing PCMA main small signal data.

2. The PCMA signal and APCMA signal non-cooperative processing system of claim 1, wherein the signal receiving subsystem comprises an antenna unit for receiving the signal via a phased array antenna and a low noise amplifier for amplifying and filtering the received signal and inputting the amplified signal to the down conversion subsystem.

3. The PCMA signal and APCMA signal non-cooperative processing system of claim 1, wherein the down-conversion subsystem includes a plurality of down-conversion modules for converting the input multiplexed signals to intermediate frequency signals for provision to the intermediate frequency acquisition subsystem, for receiving multiplexed external reference inputs, and for outputting a sampling clock for provision to the intermediate frequency acquisition subsystem for sampling the external clock, and for operating settings and status readings via an SPI interface provided thereby.

4. The PCMA signal and APCMA signal non-cooperative processing system of claim 3, wherein the down-conversion module comprises a down-conversion channel, a local oscillator section, and a control circuit, the control circuit being connected to the down-conversion channel and the local oscillator section, the down-conversion channel being connected to the local oscillator section;

the control circuit comprises an FPGA and an accessory circuit thereof;

the local oscillator part comprises a reference circuit, a first local oscillator and a second local oscillator, wherein the reference circuit is used for automatically synchronizing an internal constant-temperature crystal oscillator when an external reference clock is input, outputting 4 paths of clock signals, 2 paths of clock signals are respectively used as the reference clock signals of the first local oscillator and the second local oscillator, 1 path of clock signals is used as an FPGA (field programmable gate array) of the control circuit, and 1 path of clock signals is amplified and filtered and then is output as a sampling clock to be provided for the intermediate frequency acquisition subsystem for sampling the external clock; the first local oscillator is used for carrying out large-step frequency sweep on the reference clock signal to generate a first local oscillator signal, and the first local oscillator signal is used as a first driving local oscillator after being amplified and filtered; the second local oscillator is used for carrying out small stepping frequency sweep on the reference clock signal to generate a second local oscillator signal, and the second local oscillator signal is used as a second driving local oscillator after being amplified and filtered;

the down-conversion channel is used for limiting amplitude of an input signal, passing through a gating pre-amplifying circuit controlled by an FPGA of the control circuit, then passing through a two-way switch, band-pass filtering, low-pass filtering, amplifying, digital-control attenuating and re-filtering, mixing with a first driving local oscillator to form a first intermediate frequency signal, mixing the first intermediate frequency signal with a second driving local oscillator to form a second intermediate frequency signal after filtering, amplifying and digital-control attenuating, intermediate frequency filtering, amplifying, digital-control attenuating and filtering, and outputting the second intermediate frequency signal to the intermediate frequency acquisition subsystem.

5. The non-cooperative processing system of PCMA and APCMA signals of claim 4, wherein the first local oscillator uses an independent phase-locked loop and a wide frequency VCO to achieve a large step sweep of 4.33GHz to 5.53GHz, and the second local oscillator uses an independent phase-locked loop and a narrow frequency VCO to achieve a small step sweep of two point frequency signals at 3.24GHz and 3.28 GHz.

6. The non-cooperative processing system of PCMA and APCMA signals of claim 4, wherein the down-conversion channel comprises a limiter, a gated pre-amplifier circuit, a two-way switch, a bandpass filter, a first low-pass filter, a first amplifier, a first digitally controlled attenuator, a first filter, a first mixer, a second filter, a second amplifier, a second digitally controlled attenuator, a second mixer, a second low-pass filter, a third amplifier, a third digitally controlled attenuator, an intermediate frequency filter, a fourth amplifier, a fourth digitally controlled attenuator, a third filter, and a third filter, all connected in sequence.

7. The PCMA signal and APCMA signal non-cooperative processing system of claim 1, wherein the intermediate frequency acquisition subsystem comprises:

the ADC is used for carrying out ADC sampling on the input intermediate frequency signal to realize analog-to-digital conversion;

the FPGA is connected with the ADC and used for carrying out high-fidelity pretreatment on the data after analog-digital conversion;

a switching chip for selecting one from an external reference/external clock, or a local clock;

the DDS is connected with the switching chip and is used for being configured into a direct mode when the switching chip selects the external reference/external clock, and the clock is directly output; when the switching chip selects the local clock, the corresponding sampling rate clock is configured according to the local clock and then output;

and the clock distribution chip is connected with the DDS, FPGA, ADC and used for distributing the clock output by the DDS to the ADC and the FPGA.

8. The PCMA signal and APCMA signal non-cooperative processing system of claim 1, wherein the data processing subsystem comprises a GPU array card set, the data storage subsystem comprises a RAID card and a plurality of disks connected to the RAID, and each GPU card and RAID card of the GPU array card set are respectively connected to the bus slot through a PCIe interface.

9. The PCMA signal and APCMA signal non-cooperative processing system of claim 1, further comprising a software control subsystem for executing instructions issued by the client and transmitting to each subsystem, and for collecting data from each subsystem and feeding back status to the client.

10. The PCMA signal and APCMA signal non-cooperative processing system of claim 9, wherein the software control subsystem includes down-conversion embedded software for the down-conversion subsystem, intermediate frequency acquisition embedded software for the intermediate frequency acquisition subsystem, and control software coupled to the storage subsystem;

the control software is used for executing the instruction issued by the client and collecting information from the storage subsystem and the intermediate frequency acquisition embedded software for returning, the issued instruction is transmitted to the intermediate frequency acquisition embedded software connected through the PCIe interface through the Windows system, the intermediate frequency acquisition embedded software controls ADC acquisition and preprocessing of the intermediate frequency acquisition subsystem according to the issued instruction, issues the instruction for controlling and acquiring the state of the down-conversion subsystem through the SPI interface, and the down-conversion embedded software performs down-conversion processing according to the instruction of the SPI interface and feeds back the state.