CN117200832A

CN117200832A - Analog front-end circuit and near field communication chip

Info

Publication number: CN117200832A
Application number: CN202311469079.8A
Authority: CN
Inventors: 王德明; 李德智; 吴劲; 黄鑫; 钟清华
Original assignee: Development Research Institute Of Guangzhou Smart City; South China Normal University
Current assignee: Development Research Institute Of Guangzhou Smart City; South China Normal University
Priority date: 2023-11-07
Filing date: 2023-11-07
Publication date: 2023-12-08
Anticipated expiration: 2043-11-07
Also published as: CN117200832B

Abstract

The invention provides an analog front-end circuit and a near-field communication chip, which relate to the technical field of analog circuits, wherein a direct-current voltage circuit is respectively connected with an antenna and a voltage stabilizing circuit, the voltage stabilizing circuit is respectively connected with a load modulation circuit and a digital back-end circuit, and the load modulation circuit, a clock extraction circuit and a demodulation circuit are respectively connected with the antenna and the digital back-end circuit; the antenna is used for receiving the carrier signal sent by the reader; the carrier signal generates input voltage through a direct-current voltage circuit, and generates power supply voltage inside the chip through a voltage stabilizing circuit to be supplied to a load modulation circuit and a demodulation circuit, so that the normal operation of the load modulation circuit and the demodulation circuit is ensured; the clock extraction circuit and the demodulation circuit receive carrier signals transmitted by the antenna, respectively generate clock signals and data demodulation signals, and send the clock signals and the data demodulation signals to the digital back-end circuit; the load modulation circuit receives the response signal generated by the digital back-end circuit, modulates the response signal as a subcarrier into a carrier signal of the antenna, and outputs the carrier signal via the antenna.

Description

Analog front-end circuit and near field communication chip

Technical Field

The present invention relates to the field of analog circuits, and in particular, to an analog front-end circuit and a near field communication chip.

Background

The deeply developed internet of things is urgent to implement larger-range, wider-coverage and more comprehensive perception on complex scenes, and the NFC tag can effectively collect, analyze and report previously unavailable massive real-time data from physical objects in combination with the Internet terminal, so that large-range perception and data exchange are realized. A light and thin sticker embedded with an NFC tag chip can be used as a low-cost node of the Internet of things, the passive non-contact characteristic of the node enables near field communication to cover a wider physical object, supports connection of a plurality of objects without battery power supply conditions, covers billions or even billions of the nodes of the Internet of things, is widely applied to various fields of medical systems, postal systems, access control systems, mobile payment and the like, and promotes development of the industry of the Internet of things. NFC tag is widely demanded by markets as an important means for information acquisition of the Internet of things, and the low-power consumption and low-cost design of NFC tag chips are widely studied by academia and industry at home and abroad in consideration of the passive non-contact characteristic of NFC tag chips.

In the ISO/IEC14443A protocol, the NFC tag can only obtain limited energy from a 13.56MHz carrier wave transmitted by a reader through antenna coupling, and the carrier wave obtained by coupling under 100% ask modulation is discontinuous, and cannot be coupled to obtain energy in carrier gap time. Meanwhile, in the electromagnetic field emitted by the reader, the carrier wave amplitude of the tag antenna end can be changed along with the difference of field intensity, and the carrier wave is discontinuous under 100% ASK modulation, so that the stability of a power supply is insufficient, and a voltage stabilizing circuit is also needed for the tag chip.

Disclosure of Invention

The invention provides an analog front-end circuit and a near field communication chip, which are used for solving the defect of insufficient power supply stability in the prior art.

The invention provides an analog front-end circuit for a near field communication chip, comprising:

the antenna comprises a direct-current voltage circuit, a voltage stabilizing circuit, a clock extraction circuit, a demodulation circuit and a load modulation circuit;

the direct-current voltage circuit is respectively connected with the antenna and the voltage stabilizing circuit, the voltage stabilizing circuit is respectively connected with the load modulation circuit and the digital back-end circuit, and the load modulation circuit, the clock extraction circuit and the demodulation circuit are respectively connected with the antenna and the digital back-end circuit;

the antenna is used for receiving a carrier signal sent by the reader;

the carrier signal generates an input voltage VHD through a direct-current voltage circuit, and the input voltage VHD generates a stable chip internal power supply voltage VDD through a voltage stabilizing circuit and is supplied to a load modulation circuit and a demodulation circuit for ensuring the normal work of the load modulation circuit and the demodulation circuit;

the clock extraction circuit and the demodulation circuit receive carrier signals transmitted by the antenna, respectively generate a clock signal CLK and a data demodulation signal d_in, and send the clock signal CLK and the data demodulation signal d_in to the digital back-end circuit;

The load modulation circuit receives a response signal d_out generated by the digital back-end circuit based on the clock signal CLK and the data demodulation signal d_in, modulates the response signal as a subcarrier into a carrier signal of the antenna, and outputs the modulated response signal to the reader via the antenna.

According to the analog front-end circuit provided by the invention, the direct-current voltage circuit comprises a rectifying circuit and a limiting circuit, wherein the limiting circuit is respectively connected with an antenna and the rectifying circuit, and the rectifying circuit is respectively connected with the antenna and a voltage stabilizing circuit;

and after the carrier signal is processed by the rectifying circuit and the amplitude limiting circuit, the input voltage VHD is generated and sent to the voltage stabilizing circuit.

According to the invention, the rectification circuit comprises a first inverter, a second inverter, a third inverter, a first bleeder and a second bleeder;

the first inverter, the second inverter, the third inverter and the first bleeder are all connected with an antenna;

the first inverter generates an input voltage to the voltage stabilizing circuit;

the first bleeder pipe and the second bleeder pipe are connected by adopting a cross gate connection method and serve as switching pipes;

the second inverter generates a limiting voltage Vlimit-in to the limiting circuit;

The third inverter generates a demodulation voltage Vdemod-in to the demodulation circuit.

According to the present invention, there is provided an analog front-end circuit, the load modulation circuit comprising:

the binary coding control circuit comprises a fourth inverter and a fifth inverter, wherein the fourth inverter and the fifth inverter are both connected with the voltage stabilizing circuit, the fourth inverter receives the response signal d_out, and the fourth inverter and the fifth inverter are mutually connected and are used for outputting a control signal to the level conversion circuit;

the level conversion circuit comprises a PMOS tube MP3, a PMOS tube MP4, an NMOS tube MN11 and an NMOS tube MN12;

the source electrode of the PMOS tube MP3 is connected with the voltage stabilizing circuit, and the grid electrode of the PMOS tube MP3 is connected with the drain electrode of the PMOS tube MP4 and the drain electrode of the NMOS tube MN12;

the source electrode of the PMOS tube MP4 is connected with the voltage stabilizing circuit, and the grid electrode of the PMOS tube MP3 is connected with the drain electrode of the PMOS tube MP3 and the drain electrode of the NMOS tube MN 11;

the source electrode of the NMOS tube MN11 is grounded, and the grid electrode of the NMOS tube MN11 is connected with the output of the fourth inverter;

the source electrode of the NMOS tube MN12 is grounded, and the grid electrode of the NMOS tube MN12 is connected with the output of the fifth inverter;

the drain pipe MN13 and the drain pipe MN14, the source electrode of the drain pipe MN13 and the source electrode of the drain pipe MN14 are grounded, and the grid electrode of the drain pipe MN13 and the grid electrode of the drain pipe MN14 are connected with the drain electrode of the PMOS pipe MP 4;

The drain electrode of the bleeder tube MN13 is connected with the antenna through a resistor R1, and the drain electrode of the bleeder tube MN14 is connected with the antenna through a resistor R2;

when the response signal d_out is at a low level, the NMOS transistor MN11 is turned on with the PMOS transistor MP4, the bleeder transistor MN13 is turned on with the bleeder transistor MN14, and current flows from the antenna to the resistor R1 and the resistor R2, and the voltage across the antenna decreases, so that the response signal is modulated as a subcarrier into the carrier signal of the antenna.

According to the invention, the analog front-end circuit comprises: drain pipe MN15, drain pipe MN16, and control circuit;

the control circuit comprises a PMOS tube MP5, a PMOS tube MP6, a PMOS tube MP7, a resistor R3, a resistor R4 and a capacitor C1;

the source electrode of the bleeder tube MN15 is grounded, the drain electrode of the bleeder tube MN15 is connected with the antenna, and the grid electrode of the bleeder tube MN15 is connected with the drain electrode of the PMOS tube MP 7;

the source electrode of the bleeder tube MN16 is grounded, the drain electrode of the bleeder tube MN16 is connected with the antenna, and the grid electrode of the bleeder tube MN16 is connected with the drain electrode of the PMOS tube MP 7;

the source electrode of the PMOS tube MP5 is connected with the second inverter and is used for receiving the limiting voltage, the grid electrode of the PMOS tube MP5 is connected with the grid electrode of the PMOS tube MP3, and the drain electrode of the PMOS tube MP5 is connected with the drain electrode of the PMOS tube MP 6;

The source electrode of the PMOS tube MP6 is connected with the second inverter and is used for receiving the limiting voltage, and the grid electrode of the PMOS tube MP6 is connected with the drain electrode of the PMOS tube MP 6;

the source electrode of the PMOS tube MP7 is connected with the drain electrode of the PMOS tube MP6, the grid electrode of the PMOS tube MP7 is connected with the drain electrode of the PMOS tube MP7, and the drain electrode of the PMOS tube MP7 is grounded through a resistor R3;

the source electrode of the PMOS tube MP6 is connected with the drain electrode of the PMOS tube MP7 through a resistor R4 and a capacitor C1 which are connected in series;

the PMOS transistor MP5 is controlled by the level of the limiting voltage d_out, and when the load modulation circuit is turned on, the PMOS transistor MP5 is turned on and the diode-connected PMOS transistor MP6 is short-circuited, and the limiting circuit is turned on.

According to the invention, the analog front-end circuit comprises: the device comprises a starting circuit, a reference circuit, a mirror circuit, a feedback regulating circuit and a MOS capacitor;

the starting circuit, the reference circuit, the mirror circuit, the feedback regulating circuit and the MOS capacitor are sequentially connected, the starting circuit is connected with the direct-current voltage circuit and used for receiving input voltage, and the feedback regulating circuit is connected with the output end and used for outputting stable chip internal power supply voltage VDD to supply to the load modulating circuit and the demodulating circuit.

According to the invention, the start-up circuit comprises: resistor R4, PMOS tube MP8, NMOS tube MN17 and NMOS tube MN18;

the source electrode of the PMOS tube MP8 is connected with the rectifying circuit through a resistor R4 to receive the input voltage, the grid electrode of the PMOS tube MP8 is connected with the grid electrode of the NMOS tube MN17, and the drain electrode of the PMOS tube MP8 is respectively connected with the grid electrode of the NMOS tube MN18 and the drain electrode of the NMOS tube MN 17;

the source of NMOS tube MN17 and the source of NMOS tube MN18 are grounded;

the reference circuit includes: the PMOS tube MP9, the PMOS tube MP10, the NMOS tube MN19, the NMOS tube MN20, the triode Q1 and the resistor R5 are used for generating reference current and inputting the reference current into the mirror circuit and the feedback regulating circuit;

the source electrode of the PMOS tube MP9 is connected with the first inverter so as to receive the input voltage, the grid electrode of the PMOS tube MP9 is connected with the drain electrode of the NMOS tube MN18, and the drain electrode of the PMOS tube MP9 is respectively connected with the drain electrode of the NMOS tube MN19 and the grid electrode of the PMOS tube MP 8;

the source electrode of the PMOS tube MP10 is connected with the first inverter so as to receive the input voltage, the grid electrode of the PMOS tube MP10 is connected with the drain electrode of the NMOS tube MN18, and the drain electrode of the PMOS tube MP10 is respectively connected with the drain electrode of the NMOS tube MN20 and the drain electrode of the NMOS tube MN18;

the source electrode of the NMOS tube MN19 is connected with the emitter electrode of the triode Q1, and the grid electrode of the NMOS tube MN19 is connected with the grid electrode of the NMOS tube MN 20;

The source electrode of the NMOS tube MN20 is grounded through a resistor R5; the drain electrode of the NMOS tube MN20 is connected with the bias voltage output end and is used for outputting bias voltage;

the base electrode and the collector electrode of the triode Q1 are grounded;

the mirror circuit includes: PMOS tube MP11, PMOS tube MP12, NMOS tube MN21, NMOS tube MN22 and NMOS tube MN23;

the source electrode of the PMOS tube MP11 is connected with the first inverter so as to receive the input voltage, the grid electrode of the PMOS tube MP11 is respectively connected with the grid electrode of the PMOS tube MP12 and the drain electrode of the PMOS tube MP10, and the drain electrode of the PMOS tube MP11 is connected with the drain electrode of the NMOS tube MN 22;

the source electrode of the PMOS tube MP12 is connected with the first inverter so as to receive the input voltage, and the drain electrode of the PMOS tube MP12 is connected with the drain electrode of the NMOS tube MN 21;

the source electrode of the NMOS tube MN21 is connected with the drain electrode of the NMOS tube MN23, and the grid electrode of the NMOS tube MN21 is connected with the drain electrode of the PMOS tube MP 11;

the source electrode of the NMOS tube MN22 is grounded, and the grid electrode of the NMOS tube MN22 is connected with the grid electrode of the NMOS tube MN23 and the drain electrode of the NMOS tube MN 22;

the source electrode of the NMOS tube MN23 is grounded;

the feedback conditioning circuit includes: PMOS tube MP13, PMOS tube MP14, PMOS tube MP15 and PMOS tube MP16;

the source electrode of the PMOS tube MP13 is connected with the first inverter to receive the input voltage, the grid electrode of the PMOS tube MP13 is connected with the drain electrode of the PMOS tube MP12, and the drain electrode of the PMOS tube MP13 is respectively connected with the source electrode and the output end of the PMOS tube MP14 and is used for outputting stable chip internal power supply voltage VDD to be supplied to the load modulation circuit and the demodulation circuit;

The grid electrode of the PMOS tube MP14 is connected with the grid electrode of the NMOS tube MN22, and the drain electrode of the PMOS tube MP14 is connected with the drain electrode of the NMOS tube MN 23;

the source electrode of the PMOS tube MP15 is connected with the drain electrode of the PMOS tube MP13, the grid electrode of the PMOS tube MP15 is connected with the control end and used for receiving the control signal, and the drain electrode of the PMOS tube MP15 is connected with the source electrode of the PMOS tube MP 16;

the grid electrode of the PMOS tube MP16 is connected with the grid electrode of the PMOS tube MP14, and the drain electrode of the PMOS tube MP16 is connected with the drain electrode of the PMOS tube MP 14;

one end of the MOS capacitor is grounded, and the other end of the MOS capacitor is connected with the drain electrode of the PMOS tube MP 13.

According to the present invention, there is provided an analog front-end circuit, the demodulation circuit including: the envelope extraction circuit, the sixth inverter and the seventh inverter are sequentially connected;

the envelope extraction circuit includes: PMOS tube MP19, PMOS tube MP20, NMOS tube MN28, NMOS tube MN29 and capacitor C3;

the source electrode of the PMOS tube MP19 is connected with the first inverter and is used for receiving the input voltage, the grid electrode of the PMOS tube MP19 is connected with the bias voltage output end and is used for receiving the bias voltage, and the drain electrode of the PMOS tube MP19 is connected with the drain electrode of the NMOS tube MN 28;

the grid electrode of the PMOS tube MP20 is respectively connected with the bias voltage output end and the first inverter and is used for receiving the bias voltage and the input voltage, the source electrode of the PMOS tube MP20 is connected with the third inverter and is used for receiving the demodulation voltage, and the drain electrode of the PMOS tube MP20 is connected with the drain electrode of the NMOS tube MN 29;

The source electrode of the NMOS tube MN28 is grounded, and the grid electrode of the NMOS tube MN28 is connected with the drain electrode of the NMOS tube MN 28;

the source electrode of the NMOS tube MN29 is grounded, and the grid electrode of the NMOS tube MN29 is connected with the grid electrode of the NMOS tube MN 28;

the source electrode of the PMOS tube MP20 is grounded through the capacitor C3;

the source electrode of the PMOS tube MP20 is connected with the sixth inverter;

the seventh inverter is connected with the sixth inverter, and the seventh inverter is connected with the output end of the voltage stabilizing circuit and is used for receiving the power supply voltage VDD inside the chip, and the seventh inverter outputs a data demodulation signal d_in to the digital back-end circuit.

According to the analog front-end circuit provided by the invention, the clock extraction circuit comprises: NMOS tube MN26, NMOS tube MN27, eighth inverter, ninth inverter and shaping output circuit;

the source electrode of the NMOS tube MN26 is grounded, the grid electrode of the NMOS tube MN26 is connected with one end of the antenna, and the drain electrode of the NMOS tube MN26 is respectively connected with the input end of the eighth inverter and the input end of the ninth inverter;

the source electrode of the NMOS tube MN27 is grounded, the grid electrode of the NMOS tube MN27 is connected with the other end of the antenna, and the drain electrode of the NMOS tube MN27 is respectively connected with the output end of the eighth inverter and the output end of the ninth inverter;

the output ends of the eighth inverter and the ninth inverter are connected with the input end of the shaping output circuit, and the output end of the shaping output circuit is connected with the digital back end circuit and is used for outputting the generated clock signal CLK to the digital back end circuit.

The invention also provides a near field communication chip which comprises the analog front-end circuit, the digital back-end circuit and the memory; the analog front-end circuit is connected with the digital back-end circuit, and the digital back-end circuit is connected with the memory.

The invention provides an analog front-end circuit and a near-field communication chip, which convert an alternating current carrier signal of an antenna into a direct current input voltage through a direct current voltage circuit, and the direct current input voltage is not directly supplied to a modulation and demodulation circuit, but is supplied to a load modulation circuit and a demodulation circuit after the input voltage is generated into a stable chip internal power voltage through a voltage stabilizing circuit so as to ensure the stability of the power supply in the circuit, and then a clock signal and a data demodulation signal are sent to a digital back-end circuit through the demodulation circuit and a clock extraction circuit, and a response signal generated by the digital back-end circuit is received through the load modulation circuit and is modulated into a carrier signal of the antenna as a subcarrier, so that the signal interaction between the near-field communication chip and the antenna is realized, and meanwhile, the voltage stability in the circuit is ensured through the voltage stabilizing circuit.

In addition, the analog front-end circuit provided by the invention realizes electrostatic protection by arranging the bleeder tube in the rectifying circuit, the amplitude limiting circuit and the load modulation circuit, and the electrostatic protection performance of the chip is enhanced, and meanwhile, a separate electrostatic protection circuit is not required to be arranged in a device multiplexing mode, so that the area of the chip is reduced, and the cost of the chip is reduced.

Drawings

In order to more clearly illustrate the invention or the technical solutions of the prior art, the following description will briefly explain the drawings used in the embodiments or the description of the prior art, and it is obvious that the drawings in the following description are some embodiments of the invention, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic structural diagram of a near field communication chip provided by the present invention;

FIG. 2 is a schematic diagram of an RF antenna coupling model provided by the present invention;

fig. 3 is a schematic diagram of the structure of the rectifying circuit, the clipping circuit and the modulating circuit provided by the invention;

FIG. 4 is a schematic diagram of a voltage stabilizing circuit according to the present invention;

FIG. 5 is a schematic diagram of transient response simulation waveforms of VHD and VDD under ASK modulation provided by the invention;

fig. 6 is a schematic diagram of a demodulation circuit according to the present invention;

fig. 7 is a schematic diagram of a 100% ask modulation circuit according to the present invention.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the present invention more apparent, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is apparent that the described embodiments are some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

An embodiment of the present invention provides an analog front end circuit for a near field communication chip, referring to fig. 1, including: the device comprises an antenna, a direct-current voltage circuit, a voltage stabilizing circuit, a clock extraction circuit, a demodulation circuit and a load modulation circuit.

The antenna comprises two pins, and 13.56MHz carrier energy sent by the reader and Miller coded data modulated in a carrier by a 100% ASK modulation circuit can be obtained through an external antenna in an inductive coupling mode.

the antenna is used for receiving a carrier signal sent by the reader;

Specifically, in this embodiment, the carrier signal enters from a PADs composed of a large-size MOS transistor connected to an antenna in a rectifying circuit, a limiting circuit and a load modulation circuit, an input voltage VHD with a large ripple wave modulated by ASK is generated through the rectifying circuit and the limiting circuit, and the VHD generates a stable chip internal power voltage VDD and a power-on reset signal POR through LDO to supply to the digital circuit and the EEPROM. The carrier signal carrying modulation information is generated by a clock extraction circuit and an ASK demodulation circuit and is sent to a digital circuit, after a series of data processing such as improved Miller pulse position decoding, manchester encoding, EEPROM reading and writing and the like is carried out by the digital circuit, a response signal d_out is generated and is transmitted to a load modulation circuit, and 848kHz subcarrier of Manchester encoding is modulated into an antenna carrier.

The analog front-end circuit provided by the embodiment of the invention converts the alternating current carrier signal of the antenna into the direct current input voltage through the direct current voltage circuit, and does not directly supply the direct current input voltage to the modulation and demodulation circuit, but generates the stable power supply voltage inside the chip through the voltage stabilizing circuit and then supplies the stable power supply voltage inside the circuit to the load modulation circuit and the demodulation circuit, then sends the clock signal and the data demodulation signal to the digital back-end circuit through the demodulation circuit and the clock extraction circuit, receives the response signal generated by the digital back-end circuit through the load modulation circuit, and modulates the response signal into the carrier signal of the antenna as a subcarrier, thereby realizing the signal interaction between the near field communication chip and the antenna and simultaneously ensuring the voltage stability inside the circuit through the voltage stabilizing circuit.

For low power consumption design, an accurate RF antenna coupling model is firstly established, the size of an optimal resonant capacitor is determined, a multi-path parallel output cross gate rectifying structure is established under the process condition of SMIC 0.13CMOS, high-efficiency rectifying input is provided, an 18.52 mu A low-power consumption small-area voltage stabilizing circuit LDO based on a current mirror is provided, and the voltage stabilizing output of a tag chip under 100% ASK modulation is ensured. Finally, a clock extraction circuit and an ASK modulation demodulation circuit with low power consumption are designed, and the average power consumption is about 10 mu W. The power consumption of the analog front end is 47.81 mu W under the lowest antenna coupling voltage for ensuring stable function, and the power consumption of the whole chip under EEPROM reading operation is less than 100 mu W.

Referring to fig. 2, fig. 2 is a schematic diagram of the RF antenna coupling model mentioned in the present embodiment.

The energy transfer between the NFC tag and the reader is typically by inductive coupling, where the reader emits a small portion of the magnetic field lines of the magnetic field through the antenna coil of the NFC tag, creating a voltage across the antenna coil of the NFC tag by electromagnetic induction. The voltage at two ends of the tag antenna is determined by the magnetic field emitted by the reader-writer, the parameters of the tag antenna (self inductance, equivalent internal resistance, area, parasitic capacitance and the like) and the current consumed by the internal circuit of the tag. In order to simulate the voltages at two ends of a tag antenna under inductive coupling of different distances between the tag and the reader, an RF simulation model of an antenna interface between the reader and the tag needs to be established.

At the reader end, the tag signal received by the antenna enters a demodulation circuit after passing through a high-pass filter formed by C1, R1 and R2, and the direct current level of the signal received by the demodulation circuit is V _mid C2 is V _mid Filter capacitor L of (1) _EMC And C _EMC Form EMC low pass filtering, C _p And C _s Respectively being parallel and series matching capacitors, rr being resonance resistance, C _p 、C _s 、R _r Maximum power transfer to form 50 omega impedance match with antennas L1, L2, and current through the reader coil is I _R The method comprises the steps of carrying out a first treatment on the surface of the L1, L2 and L3 are respectively reader and tag antenna inductance, the coupling coefficient between the antennas is k, the distance between the centers of the two antennas is d,the intermediate magnetic field is H; at the tag end, R _T For parasitic resistance, C _res C for resonance capacitance inside the tag chip _res And L3 to form a parallel resonant circuit, and the current flowing through the coil of the reader is IT. NFC tags obtain more energy from the antenna by resonance, the resonance frequency f is set according to the ISO/IEC14443A protocol _res Tuned to a carrier frequency of 13.56MHz. Fixed antenna size, change C _res The resonant capacitance value of 13.56MHz can be obtained by frequency scanning of the circuit, the resonant capacitance of the design is 50pF, and the calculation formula is shown as formula (1).

(1)

The layout of the resonant capacitor needs to pay attention to matching, the MIM capacitor is used as the resonant capacitor, the capacitance density is less affected by frequency, and the MIM capacitor is symmetrically distributed on devices between antennas PADs at two ends of the layout by high-layer metal.

The quality factor Q of the tag antenna parallel resonant circuit characterizes the conversion efficiency of the tag antenna end energy. The higher the quality factor, the smaller the energy loss in the resonant circuit, the longer the oscillation of the circuit can last, and the higher the voltage induced at resonance. If the quality factor is too low, the antenna impedance portion consumes too much energy, thereby affecting the transmission distance. Meanwhile, the quality factor affects the bandwidth BW, so that in order for the tag chip to completely and correctly demodulate the ASK signal sent by the reader, the bandwidth of the tag antenna resonant circuit must be greater than twice the data rate, so there is an upper limit on the Q value, and the design sets Q at 60. Let the tag circuit of the antenna end be the load RL, the calculation formula of the quality factor Q be formula (2).

(2)

The ISO/IEC14443-A protocol specifies a minimum operating field strength H _min 1.5A/m, maximum field strength H _max The maximum recognition distance can be obtained according to the minimum working field intensity after the antenna interface parameters are fixed at 7.5A/m. After the RF simulation model of the antenna interface is establishedThe voltage at the two ends of the antenna, which is generated by the tag at different distances, can be simulated only by changing the coupling coefficient k.

In the analog front-end circuit, the direct-current voltage circuit comprises a rectifying circuit and a limiting circuit, wherein the limiting circuit is respectively connected with an antenna and the rectifying circuit, and the rectifying circuit is respectively connected with the antenna and a voltage stabilizing circuit;

Specifically, the rectifying circuit comprises a first inverter, a second inverter, a third inverter, a first bleeder tube and a second bleeder tube;

the first bleeder tube MN3 and the second bleeder tube MN4 are connected by adopting a cross gate connection method and serve as switching tubes;

Referring to fig. 3, the first inverter includes NMOS transistors MN1 and MN2; the grid electrode and the drain electrode of the NMOS tube MN1 are connected with the antenna ant1, and the source electrode of the NMOS tube MN2 is connected with the antenna ant1 through a capacitor C _VHD Grounding; the grid electrode and the drain electrode of the NMOS tube MN2 are connected with the antenna ant2, and the source electrode of the NMOS tube MN2 is connected with the antenna ant2 through a capacitor C _VHD And (5) grounding.

The second inverter comprises NMOS transistors MN5 and MN6; the grid electrode and the drain electrode of the NMOS tube MN5 are connected with the antenna ant1, and the grid electrode and the drain electrode of the NMOS tube MN6 are connected with the antenna ant 2; the source of NMOS tube MN5 and the source of NMOS tube MN6 are connected with the limiting voltage output end for outputting limiting voltage Vlimit-in.

The third inverter comprises NMOS transistors MN7 and MN8; the grid electrode and the drain electrode of the NMOS tube MN7 are connected with the antenna ant1, the grid electrode and the drain electrode of the NMOS tube MN8 are connected with the antenna ant2, and the source electrode of the NMOS tube MN7 and the source electrode of the NMOS tube MN8 are connected with a demodulation voltage output end and used for outputting demodulation voltage Vdemod-in.

Still referring to fig. 3, the lower right hand corner of fig. 3 shows a schematic diagram of a clipping circuit.

The clipping circuit includes: drain pipe MN15, drain pipe MN16, and control circuit;

Referring to the lower left part of fig. 3, the disclosed load modulation circuit comprises:

Specifically, ant1, ant2 are differential ac inputs to the antenna, and passive tags require high energy efficient rectifier circuits to output dc signals. In the present embodiment, a full-wave rectifying circuit composed of PMOS by a series diode connection method and NMOS by a parallel diode connection method is proposed. The design adopts a full-wave bridge rectifying circuit of the MOS tube with 4 diode connection methods, and the structure can generate VGS voltage drops of 2 MOS tubes at output, so that the voltage consumption coupled to an antenna is large. And because the load mounted on the antenna also comprises a limiting circuit, a clock extraction circuit, a demodulation circuit and a modulation circuit, the load change of a single module can influence other modules through the antenna.

The embodiment adopts NMOS gate cross-connection rectifying circuitThe loss of the output voltage is reduced from 2 VGS to 1 VGS, and a multipath parallel output circuit structure is adopted, so that fluctuation of the power supply voltage and mutual interference among all modules are effectively reduced. MN3, MN4 adopt cross gate connection as the switching tube, MN1, MN2, MN5, MN6, MN7, MN8 adopt diode connection to multiplex and output input voltage VHD, limiting voltage vlimit_in, demodulation voltage vdemod_in to voltage stabilizing circuit LDO, load modulation circuit, limiting circuit and demodulation circuit in parallel. The channel resistance of NMOS is smaller than that of PMOS under the same size, the voltage drop is smaller, and the load carrying capacity is stronger. C (C) _VHD Is a storage capacitor which on the one hand can stabilize the VHD to a certain extent and on the other hand can supply power to the subsequent digital circuit during the occurrence of a 100% ask modulation notch. Analyzing one path of rectifying circuit, when in half period of high level of ant1 and low level of ant2, MN1 and MN4 are conducted, and starting to butt joint C of VHD _VHD Charging a capacitor; in addition, in half period, ant2 is high level, ant1 is low level, MN2 and MN3 are conducted to C _VHD And (5) charging. The cross gate rectifier circuit generates only 1 VGS voltage drop in the carrier period, which saves a lot of voltage redundancy compared with the connection form of non-cross gates. In the presence of a carrier wave, a relatively stable voltage is formed on the VHD, at C _VHD In the process of charging and discharging the capacitor, the VHD is always direct current, so that the aim of converting an alternating current signal into a direct current signal is fulfilled. The rectified voltage value may still exceed the threshold value of the MOS breakdown voltage, so that a clipping circuit still needs to be further designed. The limiter circuit consists of two bleeder tubes MN15, MN16 and control circuits MP5, MP6, MP7, R4, C1. R3 is a resistor with a larger resistance value, so that the consumed quiescent current is small when the amplitude limiting circuit does not need to work. R4 and C1 provide frequency compensation, adjusting the appropriate bleed rate. Let the threshold voltages of MN15 and MN16 be VTHN, and the gate-source voltages of diode-connected MP6 and MP7 be V _GS6 、V _GS7 Setting the limiting voltage as V _lm ：

V _lm = V _THN + |V _GS6 | + |V _GS7 | (3)

When vlimit_in reaches Vlm, MN17 and MN18 conduct excess current to ground. The tag rectifies the output Vlimit in at smaller magnetic fields without reaching the clipping voltage Vlm limiter turn off. MP5 is controlled by d_out level, when load modulation is turned on, MP5 is turned on and short-circuits MP6 connected with diode, vlm reduces VGS6, limiting circuit is turned on, and leakage current is increased.

The principle of the load modulation circuit is the same as that of the amplitude limiting circuit, and the load modulation circuit is controlled by the digital signal d_out, so that the current at the rectifying output end is discharged, and the voltage of the antenna is reduced. On the tag, the antenna interface is a parallel resonant circuit, for example, the parallel resistance becomes small, the quality factor will decrease, and the voltage across the antenna resonant circuit will decrease. The design adopts a resistance load modulation mode, and MP1, MP2, MN9 and MN10 form a binary coding control circuit consisting of two inverters, so as to provide control signals for the later level conversion circuits (MP 3, MP4, MN11 and MN 12). When d_out is low, MN11 and MP4 are on, MN13 and MN14 are on, current flows from the antenna to R1 and R2, the voltage across the antenna drops, and a modulated signal is applied to the carrier. MP6 is short-circuited when the load modulation circuit is started, and the amplitude limiting circuit increases the leakage current and deepens the amplitude of load modulation.

The design utilizes NMOS tubes to construct a high-energy-efficiency cross gate rectifying circuit, and converts alternating voltage signals coupled at two ends of an antenna into direct current signals; adding a clipping circuit to prevent the induced voltage from being excessive and then breaking down a transistor connected with the antenna; the on-off of the MOS tube is controlled by the coding signal to change the load connected in parallel with the antenna, and then the voltage values at two ends of the antenna are regulated by controlling the leakage current, so that the purposes of load modulation and signal transmission are realized; and an ESD protection circuit is constructed by using a bleeder tube with larger size connected with an antenna in rectification, amplitude limiting and load modulation, so that the purposes of multiplexing devices, effectively improving the ESD protection capability and reducing the chip area are realized. The circuit can realize high-performance and high-energy-efficiency rectification, amplitude limiting and load modulation, and can provide higher ESD electrostatic protection capability.

The rectified and limited voltage signal VHD is still not stable enough and requires a voltage regulator to power the subsequent circuit. The analog front-end circuit of this embodiment further includes a voltage stabilizing circuit, see fig. 4, including: the device comprises a starting circuit, a reference circuit, a mirror circuit, a feedback regulating circuit and a MOS capacitor. Providing an output voltage of 1.2V-1.8V, and a power consumption current of 18.52uA. The transient response simulation waveforms of VHD and VDD under ASK modulation are shown in fig. 5, and ripple generated by ASK modulation is effectively suppressed.

Referring to fig. 4, the starting circuit, the reference circuit, the mirror circuit, the feedback adjustment circuit and the MOS capacitor are sequentially connected, and the starting circuit is connected with the dc voltage circuit and is used for receiving the input voltage, and the feedback adjustment circuit is connected with the output end and is used for outputting the stable power supply voltage VDD inside the chip to supply to the load modulation circuit and the demodulation circuit.

The start-up circuit includes: resistor R4, PMOS tube MP8, NMOS tube MN17 and NMOS tube MN18;

the source of NMOS tube MN17 and the source of NMOS tube MN18 are grounded;

The source electrode of the PMOS tube MP10 is connected with the first inverter so as to receive the input voltage, the grid electrode of the PMOS tube MP10 is connected with the drain electrode of the NMOS tube MN18, and the drain electrode of the PMOS tube MP10 is respectively connected with the drain electrode of the NMOS tube MN20 and the drain electrode of the NMOS tube MN 18;

the base electrode and the collector electrode of the triode Q1 are grounded;

the source electrode of the NMOS tube MN23 is grounded;

the source electrode of the PMOS tube MP15 is connected with the drain electrode of the PMOS tube MP13, the grid electrode of the PMOS tube MP15 is connected with the control end and used for receiving the control signal, and the drain electrode of the PMOS tube MP15 is connected with the source electrode of the PMOS tube MP16;

the MOS capacitor C _VDD Is grounded at one end of theMOS capacitor C _VDD The other end of the transistor is connected with the drain electrode of the PMOS tube MP 13.

When the chip is electrified, a starting circuit is needed to give a definite working state to the reference source, and R4, MP8, MN17 and MN18 form the starting circuit. R4 is used for preventing the starting circuit from generating excessive current in the instant conduction process, the grid voltage of MP8 is 0 at the beginning, MP8 is conducted at the moment, as the chip is electrified slowly, the grid voltage of MP8 reaches the threshold voltage of MN17, MN17 and MP8 form an inverter, the grid voltage of MN18 is pulled to high level instantly, MN18 is started, the grid voltages of MP9 and MP10 are immediately reduced to 0, an initial value is given to the reference circuit, MP9 and MP10 are conducted to enter a known state at the moment, the reference source starts to work, the grid voltage of MP8 is pulled high, the grid voltage of MN18 is pulled low after inversion, and the MN18 tube is closed.

In order to keep VDD stable, the voltage stabilizing circuit of this embodiment further includes a reference circuit based on emitter voltage, and the circuit structure is composed of MP9, MP10, MN19, MN20, Q1 and R5, so as to generate a reference current I1 independent of voltage, and by adjusting the width-to-length ratio of the MOS transistor and R5, a precise current I1 can be obtained, and in an actual chip, I1 may slightly vary with process deviation and temperature, but such deviation is completely acceptable in an RFID chip. MP11, MP12, MN21, MN22 and MN23 form a mirror circuit, the width-to-length ratio of the three MOS transistors MP11, MP12, MN22 is (W/L), the width-to-length ratio of MN23 is 3 (W/L), and i4=3i2 and i1=2i2 are known as i5=i4-i2=2i2=i1.

MP13, MP14, MP15, and MP16 together form a feedback regulation circuit that regulates voltage based on changes in VHD and load current. Wherein MP13 is PMOS adjusting tube, once VDD changes, it can be dynamically adjusted by feedback circuit, so that VDD is stabilized in the set interval. Assuming that VDD increases, the current I5 through MP14 increases, since i4=3i2 and is constant, an increase in I5 means a decrease in I2 and I3, and the source-drain voltage VDS of the MP12 tube also decreases, where VDS is equal to VGS of the MP13 tube, meaning that VGS also decreases, and VDD decreases, for regulation purposes. The value of VDD can be determined by MN22 and MP 14.

The tag chip does not have any peak current during 100% ask modulation because the clock is not present, but still has a certain leakage current, so the filter capacitor needs to be used as the energy storage capacitor to prevent power supply jitter during the groove. Because the filter capacitor and the energy storage capacitor are mainly connected to the VDD power supply, the VDD is operated at 1.8V, which is completely consistent with the NMOS tube of 1.8V, the embodiment adopts the NMOS capacitor with larger capacitance value per unit area than PIP and MIM capacitors as the energy storage capacitor, and the occupied area of the capacitor is obviously reduced. Finally, the power-on reset block provides a reset signal POR for judging whether enough power supply voltage works.

The demodulation circuit of the present embodiment, referring to fig. 6, includes: the envelope extraction circuit, the sixth inverter and the seventh inverter are sequentially connected. The sixth inverter is a waveform shaping circuit Wave shaper, and the seventh inverter is a Load driver.

The signal received by the antenna is rectified by the MOS diode, and then enveloped by the parallel capacitor and the resistor to obtain the basic shape of the signal, and then the DC component is removed by the blocking capacitor. The high and low voltages of the 100% ask modulated signal differ greatly, and the envelope thereof substantially corresponds to the variation of the full swing of the input signal. In view of this feature, the present embodiment uses an inverter to shape the extracted envelope, and the inverter functions as a voltage comparator, so that the step of sampling decision can be omitted. As shown in fig. 6, after the antenna signal is rectified, the antenna signal enters an RC low-pass filter to obtain a modulated signal envelope, wherein a current source is designed as an active resistor, so that the occupied area of the resistor is reduced. After the signal is enveloped, the signal can be directly shaped by an inverter, so that a demodulation signal can be obtained. The inverter Wave shaping realizes the preliminary demodulation and shaping of ASK100% modulation signals, and then the inverter Load driver not only plays a shaping role, but also mainly increases the Load capacity of demodulation output signals and performs level conversion to enable the high and low levels of data to correspond to VDD and GND.

Referring to fig. 7, the clock extraction circuit disclosed in the present embodiment includes: NMOS tube MN26, NMOS tube MN27, eighth inverter, ninth inverter and shaping output circuit;

the output ends of the eighth inverter and the ninth inverter are connected with the input end of the shaping output circuit shaping output, and the output end of the shaping output circuit shaping output is connected with the digital back-end circuit for outputting the generated clock signal CLK to the digital back-end circuit.

Wherein, the eighth inverter comprises a PMOS tube MP17 and an NMOS tube MN24,

the ninth inverter includes a PMOS transistor MP18 and an NMOS transistor MN25.

The embodiment also discloses a near field communication chip, as shown in fig. 1, comprising the analog front-end circuit, the digital back-end circuit and the memory as described above; the analog front-end circuit is connected with the digital back-end circuit, and the digital back-end circuit is connected with the memory.

Specifically, the digital back-end circuit includes: clock circuit CLK decoder, memory Interface EEPROM Interface, encoding circuit Manchester Encoder, and decoding circuit PPM decoder.

The memory includes: read/write Circuit R/W Circuit and memory cell Array EEcell Array.

The EEPROM Interface is connected with the R/W Circuit of the read-write Circuit;

the EEPROM Interface is connected with the output end of the LDO and is used for receiving the stable voltage VDD;

the decoding circuit PPM decoder is connected with the ASK demodulation circuit and is used for receiving a data demodulation signal d_in;

the encoding circuit Manchester Encoder is connected to the Load Modulator, and receives the response signal d_out, modulates the response signal as a subcarrier into a carrier signal of the antenna, and outputs the modulated signal to the reader via the antenna.

The NFC tag chip disclosed by the embodiment is realized by adopting an SMIC 0.13 mu m EEPROM 2P6M CMOS process, the area is 631.5 mu m multiplied by 579.3 mu m, and the static power consumption is less than 100 mu W. According to the embodiment, an IO Buffer is omitted through multiplexing of the ESD device, a CMOS capacitor is used as an energy storage capacitor, LDO design of a divider-free resistor is omitted, a current source is used as an active resistor, an MIM capacitor is paved on high-level metal above the device, and the area of a tag chip is effectively reduced by a reasonable layout design method; the rectification, amplitude limiting and load modulation circuit integrated with the ESD is designed, so that the area of a chip is reduced and ESD protection is provided; the small-area low-power LDO based on the current mirror is designed, so that the power supply jitter is effectively inhibited, and the power consumption current of the LDO is 18.52 mu A; finally, stable modem communication of the low-cost low-power-consumption high-frequency passive NFC tag chip under the ISO/IEC14443A protocol standard is realized through the design of the low-power-consumption clock extraction circuit and the ASK modem circuit.

Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and are not limiting; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. An analog front-end circuit for a near field communication chip, the analog front-end circuit comprising:

the antenna is used for receiving a carrier signal sent by the reader;

2. The analog front-end circuit of claim 1, wherein,

the direct-current voltage circuit comprises a rectifying circuit and a limiting circuit, the limiting circuit is respectively connected with the antenna and the rectifying circuit, and the rectifying circuit is respectively connected with the antenna and the voltage stabilizing circuit;

3. The analog front-end circuit of claim 2, wherein,

the rectifying circuit comprises a first inverter, a second inverter, a third inverter, a first bleeder tube and a second bleeder tube;

4. An analog front-end circuit according to claim 3, wherein the load modulation circuit comprises:

5. The analog front-end circuit of claim 4, wherein the clipping circuit comprises: drain pipe MN15, drain pipe MN16, and control circuit;

6. The analog front-end circuit of claim 3, wherein,

the voltage stabilizing circuit includes: the device comprises a starting circuit, a reference circuit, a mirror circuit, a feedback regulating circuit and a MOS capacitor;

7. The analog front-end circuit of claim 6, wherein,

the source of NMOS tube MN17 and the source of NMOS tube MN18 are grounded;

the base electrode and the collector electrode of the triode Q1 are grounded;

the source electrode of the NMOS tube MN23 is grounded;

the feedback conditioning circuit includes: PMOS tube MP13, PMOS tube MP 14, PMOS tube MP 15 and PMOS tube MP 16;

8. The analog front-end circuit of claim 7, wherein,

the demodulation circuit includes: the envelope extraction circuit, the sixth inverter and the seventh inverter are sequentially connected;

9. The analog front-end circuit of claim 2, wherein,

The clock extraction circuit includes: NMOS tube MN26, NMOS tube MN27, eighth inverter, ninth inverter and shaping output circuit;

10. A near field communication chip comprising the analog front end circuitry of any of claims 1-9, digital back end circuitry, and memory;

the analog front-end circuit is connected with the digital back-end circuit, and the digital back-end circuit is connected with the memory.