CN117200750A - Structure for reducing threshold detection time of three-stage SINC filter and implementation method - Google Patents
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Abstract
The invention discloses a structure and an implementation method for reducing threshold detection time of a three-stage SINC filter, which relate to the technical field of filter threshold detection, and the technical scheme is characterized in that the implementation method for reducing threshold detection time of the three-stage SINC filter is provided by the invention, and a threshold comparator and/or a logic module are inserted into a filtering module of each stage; setting detection threshold values for the threshold value comparators of each stage respectively; thereby sending the quantized data to a filtering module of the next stage or triggering a subsequent system to respond; furthermore, the delay of the SINC filter of the first order is required, and the worst delay is three times that of the SINC filter of the first order. The method solves the problem that in the threshold detection process of the three-stage SINC filter in the prior art, if the voltage or the current is too large, the delay is large, so that the system response is delayed for the component to be responded, and the service life of the response system component is further influenced.
Description
Technical Field
The invention relates to the technical field related to threshold detection of filters, in particular to a structure and an implementation method for reducing threshold detection time of a three-stage SINC filter.
Background
SINC (Sine-based function) filters are often used in the digital demodulation and quantization portion of a ΣΔ ADC (Analog-to-Digital Converter) circuit, where the demodulated and quantized data is typically used for over/under voltage, over/under current detection and protection of a component (e.g., a motor system).
In practical situations, if the requirement on the chip area utilization rate is higher, the SINC filter is generally defined as a third order in design, and only one pair of comparators is needed after the three-order filtering decoding in the traditional structure and implementation mode, so that the detection accuracy can be improved. In this case, the actual input voltage/current is too large or too small, and three-stage SINC processing is still adopted, which inevitably causes a certain delay to obtain data. If the voltage or current is too large, the larger delay causes a system response lag to the component to be responded, which in turn may affect the service life thereof.
Disclosure of Invention
Aiming at the defects existing in the prior art, the invention aims to provide a structure and an implementation method for reducing threshold detection time of a three-stage SINC filter, and aims to solve the technical problems.
In order to achieve the above purpose, the present invention provides the following technical solutions: the implementation method for reducing the threshold detection time by the three-stage SINC filter comprises the following steps of:
in the filtering module of the SINC filter body, a threshold comparator and a logic module are inserted into the filtering module of each stage;
setting a detection threshold T for a threshold comparator of the series i i ，i＝1,2,3；
SINC circuit of stage number i receives input data X i-1 Quantization is carried out to obtain quantized data X i The method comprises the steps of carrying out a first treatment on the surface of the Wherein i is the number of stages of the filtering module;
the threshold comparator of progression i will quantize the data X i Threshold T of number of stages i i Comparing; and outputting a comparison result; the comparison result comprises lower threshold detection information or threshold detection ending information;
when the output comparison result includes lower threshold detection information, the data X is quantized i The filtering module is sent to the stage number i+1;
when the output comparison result comprises threshold detection ending information, triggering a subsequent system to respond by a logic module of the series i;
when the quantized data X of the series i is received by the series i+1 i At the time of quantizing data X i Re-quantizing as input data Xi;
when the OR logic module triggers the subsequent system to respond or triggers the last-stage threshold comparator to output a comparison result, the threshold detection of the SINC filter body is finished.
As a further scheme of the invention: the threshold comparator comprises an over-threshold comparator and an under-threshold comparator; the detection threshold preset by the over-threshold comparator is different from the detection threshold preset by the under-threshold comparator;
the comparison result comprises an over-threshold comparison result output by the over-threshold comparator and an under-threshold comparison result output by the under-threshold comparator;
the OR logic module comprises an over-threshold or logic module and an under-threshold or logic module;
the threshold value passing or logic module is used for analyzing the threshold value passing comparison result and outputting a threshold value passing analysis result;
the underthreshold value or logic module is used for analyzing the underthreshold value comparison result and outputting an underthreshold value analysis result;
the threshold analysis result and the threshold analysis result comprise the step of sending lower threshold detection information or threshold detection ending information;
when threshold detection ending information exists in the over-threshold analysis result and the under-threshold analysis result, the threshold detection ending information is sent to a subsequent system to respond;
otherwise, the data X will be quantized i And sending the filtered signal to a filtering module with the stage number of i+1.
As a further scheme of the invention: when the equivalent data is larger than a detection threshold preset by the threshold crossing comparator or the equivalent data is smaller than a detection threshold preset by the threshold undershooting comparator; the over-threshold analysis result or the under-threshold analysis result comprises threshold detection ending information; when the equivalent data is smaller than the detection threshold preset by the threshold crossing comparator and larger than the detection threshold preset by the threshold undershooting comparator, the threshold crossing analysis result or the threshold undershooting analysis result comprises sending lower threshold detection information.
As a further scheme of the invention: the implementation method for reducing the threshold detection time of the three-stage SINC filter further comprises the following steps:
the detection threshold precision preset by the threshold comparator of each stage is consistent with the quantization precision;
calculating the quantization accuracy Q of the series i according to the following formula i ：
Wherein D is i Quantizing data X for series i i Is a quantized data bit wide.
As a further scheme of the invention: calculating the number of stages i quantized data X according to the following formula i Quantized data bit width D of (2) i ；
D i ＝d+i*log 2 M；
Where d is the original input data bit width; m is a preset downsampling decimation factor.
As a further scheme of the invention: the desired thresholds of the plurality of threshold comparators increase as the number of stages increases.
The invention also provides a structure for reducing the threshold detection time of the three-stage SINC filter, which is applied to the implementation method for reducing the threshold detection time of the three-stage SINC filter, wherein the structure for reducing the threshold detection time of the three-stage SINC filter comprises an SINC filter body, a threshold comparator and or a logic module;
the SINC filter body takes the output of the modulator as an input signal; wherein, a threshold comparator and a logic module are inserted in the filtering module of each stage of the SINC filter body;
the filtering module of the first stage quantizes the output data of the modulator to obtain quantized data;
the filtering module of the next stage re-quantizes the quantized data received by the previous stage;
the threshold comparator is used for comparing the quantized data of the current level with a detection threshold preset by the current level and outputting a comparison result;
the OR logic module is used for triggering a filtering module of the next stage according to the comparison result of the stage; the OR logic module is also used for triggering a subsequent system to respond according to the comparison result of the stage.
As a further scheme of the invention: the threshold comparator comprises an over-threshold comparator and an under-threshold comparator; the OR logic module comprises an over-threshold or logic module and an under-threshold or logic module; the comparison result comprises an over-threshold comparison result output by the over-threshold comparator and an under-threshold comparison result output by the under-threshold comparator;
the threshold value passing or logic module is used for analyzing the threshold value passing comparison result and outputting a threshold value passing analysis result;
the underthreshold value or logic module is used for analyzing the underthreshold value comparison result and outputting an underthreshold value analysis result;
the over-threshold analysis result and the under-threshold analysis result each include transmitting lower threshold detection information or threshold detection end information.
As a further scheme of the invention: the over-threshold comparison result and the under-threshold comparison result both comprise a high level or a low level;
outputting threshold detection ending information when the threshold crossing or logic module analyzes that the threshold crossing comparison result is at a high level; outputting and transmitting lower threshold detection information when the threshold comparison result is low level through the threshold crossing or the logic module;
when the undershoot value or the logic module analyzes that the undershoot value comparison result is at a high level, outputting threshold detection ending information; and outputting and transmitting lower threshold detection information when the undershoot value or the logic module analyzes that the undershoot value comparison result is low level.
Compared with the prior art, the invention has the following beneficial effects:
1. according to the implementation method for reducing the threshold detection time of the three-stage SINC filter, a threshold comparator and a logic module are inserted into a filtering module of each stage; setting detection threshold values for the threshold value comparators of each stage respectively; quantizing the received input data to obtain quantized data X i The method comprises the steps of carrying out a first treatment on the surface of the Will quantize the data X i Threshold T of number of stages i i Comparing; and outputting a comparison result; thereby enabling to quantize the data X when the output comparison result includes lower threshold detection information i The filtering module is sent to the stage number i+1; when the output comparison result comprises threshold detection ending information, triggering a subsequent system to respond by a logic module of the series i; therefore, when the threshold value is exceeded or undershot, the delay of the SINC filter of the first order is only needed in the best case, and the worst case delay is three times of the delay of the SINC filter of the first order. Compared with the prior art that the threshold comparator is only connected at the third stage, the method can quickly detect the input signal with the larger expected value and transmit the input signal to a subsequent system to respond. The method solves the problem that in the threshold detection process of the three-stage SINC filter in the prior art, if the voltage or the current is too large, the delay is large, so that the system response is delayed for the component to be responded, and the service life of the response system component is further influenced.
2. According to the structure for reducing the threshold detection time of the three-stage SINC filter, the threshold comparison module is inserted into each stage of the filtering module of each stage of the three-stage SINC filter, so that the condition of exceeding or undershooting the threshold can be rapidly detected when input quantized data is larger or smaller, and the response time of a subsequent system is saved. Thus, the threshold detection result can be obtained in the first-stage filter at the highest speed when the difference between the threshold detection quantized value and the expected target value is too large. Compared with the traditional method that the result is obtained only after three steps, the OR logic module can respond quickly.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, it being obvious that the drawings described below are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a control architecture diagram of a three stage SINC filter structure for reducing threshold detection time;
FIG. 2 is a diagram showing the structure of SINC filter body in a structure of three-stage SINC filter for reducing threshold detection time;
FIG. 3 is a workflow diagram of a method for implementing a three stage SINC filter to reduce threshold detection time;
FIG. 4 is a schematic diagram of threshold detection triggered by a first stage SINC filter in a method for implementing a three stage SINC filter to reduce threshold detection time;
FIG. 5 is a schematic diagram of a third stage SINC filter triggering threshold detection in a method for implementing the reduction of threshold detection time by the third stage SINC filter;
fig. 6 is a block diagram of a transfer function Z of a third order SINC filter according to the prior art.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is evident that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
In the description of the present invention, it should be understood that the terms "length," "width," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like indicate orientations or positional relationships based on the orientation or positional relationships shown in the drawings, merely to facilitate describing the present invention and simplify the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and therefore should not be construed as limiting the present invention.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present invention, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
Embodiments of a structure and implementation method for reducing threshold detection time of a three-stage SINC filter according to the present invention will be further described with reference to fig. 1 to 6.
In one embodiment of the present invention, a method for implementing a three-stage SINC filter to reduce threshold detection time includes the steps of:
in the filtering module of the SINC filter body, a threshold comparator and a logic module are inserted into the filtering module of each stage;
setting a detection threshold T for a threshold comparator of the series i i ，i＝1,2,3；
SINC circuit of stage number i receives input data X i-1 Quantization is carried out to obtain quantized data X i The method comprises the steps of carrying out a first treatment on the surface of the Wherein i is the number of stages of the filtering module;
the threshold comparator of progression i will quantize the data X i Threshold T of number of stages i i Comparing; and outputting a comparison result; the comparison result comprises lower threshold detection information or threshold detection ending information;
when the output comparison result includes lower threshold detection information, the data X is quantized i Filtering mode sent to series i+1A block;
when the output comparison result comprises threshold detection ending information, triggering a subsequent system to respond by a logic module of the series i;
when the quantized data X of the series i is received by the series i+1 i At the time of quantizing data X i Re-quantizing as input data Xi;
when the OR logic module triggers the subsequent system to respond or triggers the last-stage threshold comparator to output a comparison result, the threshold detection of the SINC filter body is finished. Response operations that may trigger subsequent systems include ePWM (enhanced pulse width modulation) tripping, MCU (Microcontroller Unit) interrupt handling, etc.
In this embodiment, the threshold comparator includes an over-threshold comparator and an under-threshold comparator; the detection threshold preset by the over-threshold comparator is different from the detection threshold preset by the under-threshold comparator;
the comparison result comprises an over-threshold comparison result output by the over-threshold comparator and an under-threshold comparison result output by the under-threshold comparator;
the OR logic module comprises an over-threshold or logic module and an under-threshold or logic module;
the threshold value passing or logic module is used for analyzing the threshold value passing comparison result and outputting a threshold value passing analysis result;
the underthreshold value or logic module is used for analyzing the underthreshold value comparison result and outputting an underthreshold value analysis result;
the threshold analysis result and the threshold analysis result comprise the step of sending lower threshold detection information or threshold detection ending information;
when threshold detection ending information exists in the over-threshold analysis result and the under-threshold analysis result, the threshold detection ending information is sent to a subsequent system to respond;
otherwise, the data X will be quantized i And sending the filtered signal to a filtering module with the stage number of i+1.
In this embodiment, when the equivalent data is greater than the detection threshold preset by the threshold crossing comparator or the equivalent data is less than the detection threshold preset by the threshold undershooting comparator; the over-threshold analysis result or the under-threshold analysis result comprises threshold detection ending information; i.e. high level; when the equivalent data is smaller than the detection threshold preset by the threshold crossing comparator and larger than the detection threshold preset by the threshold undershooting comparator, the threshold crossing analysis result or the threshold undershooting analysis result comprises sending lower threshold detection information, namely a low level.
In this embodiment, the implementation method for reducing the threshold detection time of the three-stage SINC filter further includes the following steps:
the detection threshold precision preset by the threshold comparator of each stage is consistent with the quantization precision;
calculating the quantization accuracy Q of the series i according to the following formula i ：
Wherein D is i Quantizing data X for series i i Is a quantized data bit wide.
In the present embodiment, the progression i quantized data X is calculated according to the following formula i Quantized data bit width D of (2) i ；
D i ＝d+i*log 2 M；
Where d is the original input data bit width; m is a preset downsampling decimation factor.
It is necessary to say that the desired threshold values of the plurality of threshold value comparators increase with an increase in the number of stages.
As still another embodiment of the present invention, the present invention further provides a structure for reducing threshold detection time of a three-stage SINC filter, which is applied to a method for implementing the reduction of threshold detection time of a three-stage SINC filter, where the structure for reducing threshold detection time of a three-stage SINC filter includes a SINC filter body, a threshold comparator, and/or a logic module;
the SINC filter body takes the output of the modulator as an input signal; wherein, a threshold comparator and a logic module are inserted in the filtering module of each stage of the SINC filter body;
the filtering module of the first stage quantizes the output data of the modulator to obtain quantized data;
the filtering module of the next stage re-quantizes the quantized data received by the previous stage;
the threshold comparator is used for comparing the quantized data of the current level with a detection threshold preset by the current level and outputting a comparison result;
the OR logic module is used for triggering a filtering module of the next stage according to the comparison result of the stage; the OR logic module is also used for triggering a subsequent system to respond according to the comparison result of the stage.
In this embodiment, the threshold comparator includes an over-threshold comparator and an under-threshold comparator; the OR logic module comprises an over-threshold or logic module and an under-threshold or logic module; the comparison result comprises an over-threshold comparison result output by the over-threshold comparator and an under-threshold comparison result output by the under-threshold comparator;
the threshold value passing or logic module is used for analyzing the threshold value passing comparison result and outputting a threshold value passing analysis result;
the underthreshold value or logic module is used for analyzing the underthreshold value comparison result and outputting an underthreshold value analysis result;
the over-threshold analysis result and the under-threshold analysis result each include transmitting lower threshold detection information or threshold detection end information.
The over-threshold comparison result and the under-threshold comparison result both comprise a high level or a low level;
outputting threshold detection ending information when the threshold crossing or logic module analyzes that the threshold crossing comparison result is at a high level; outputting and transmitting lower threshold detection information when the threshold comparison result is low level through the threshold crossing or the logic module;
when the undershoot value or the logic module analyzes that the undershoot value comparison result is at a high level, outputting threshold detection ending information; and outputting and transmitting lower threshold detection information when the undershoot value or the logic module analyzes that the undershoot value comparison result is low level.
To clearly illustrate the method of implementing the present invention, the following conventional or conventional methods are first understoodIn a relatively easy implementation manner, fig. 6 is a block diagram of a three-order SINC filter Z transfer function in the prior art, where a single SINC filter is formed by an integrator, a decimator and a differentiator, M is the downsampling factor of the decimator, and a basic delay factor is Z -1 Representing a delay of one D flip-flop, i.e. one clock cycle, then Z -M， Then M D flip-flops are required. If the SINC filter is implemented according to the implementation principle of fig. 6, the implementation is simpler, and in order to implement the architecture of fig. 1, only two comparators need to be inserted into the quantization result of each stage. There are two problems, however, one is that the resource consumption is large. When M is large, for example, 256, the number of flip-flops is 771 for the third-order SINC filter D. And secondly, the power consumption overhead is increased. In fig. 2, the operating clock of the entire module is only at a fast frequency, which necessarily results in a large power consumption.
Therefore, the present invention transforms the Z transfer function in the prior art to obtain a new Z transfer function structure as shown in FIG. 2. The structure can be realized by using a lower frequency when the D triggers are used for differentiating, namely, finally quantizing output data, so that certain power consumption can be reduced. In order to realize the method for reducing the threshold detection time of the three-stage SINC filter, when the bottom hardware design is needed to realize, the fact that a comparator (an undershreshold comparator and an overshreshold comparator) is inserted into a node where the quantization of each stage is completed is considered, so that quantized values of the first stage, the second stage and the third stage SINC obtained through quantization are sent to the comparators of corresponding stages for further processing.
When the first stage comparator output is high, the OR logic block is triggered and its output is high.
When the output of the first-stage comparator is at a low level, the second-stage SINC is entered, and after the second-stage SINC filter is quantized, data is sent to the second-stage comparator.
When the second stage comparator output is high, the OR logic block is triggered and its output is high.
When the output of the second-stage comparator is low, the third-stage SINC is entered, after the quantization of the third-stage SINC filter is completed, the data is sent to the third-stage comparator,
when the third stage comparator output is high, the or logic block is triggered and its output is high.
When the third stage comparator output is low, the logic block output is not triggered or high. Indicating that the quantized data is within a threshold range.
The design mode can be realized only by inserting a comparator into each stage of SINC filter, and the number of D triggers is 134 when M=256 for the three stages of SINC filters.
Compared with the prior art, the invention can save area and reduce certain power consumption.
The SINC filter body is a three-stage SINC filter, the number of stages is three, and if the input data of the first-stage SINC filter is 1bit data, the bit width of quantized data is calculated according to the following formula: d (D) 1 ＝d+1*log 2 M；
d is the original input data bit width; m is a downsampling decimation factor. The output sampling frequency was set to 20mhz and the m value was set to 64.
The first stage quantized bit width is 7 bits, the quantization accuracy is 1/2^7, the second stage filter quantized bit width is 13 bits, the quantization accuracy is 1/2≡13, the third stage filter quantized bit width is 19 bits, the quantization accuracy is 1/2≡19.
When the threshold detection comparison is performed, the expected threshold setting relationship of each level of threshold comparator is that
Th H1 /2^7>Th H2 /2^13>Th H3 /2^19。Th H3 2A 19 is the final required or desired high desired threshold. Here set Th H1 ＝7`h3C，Th H2 ＝13`hD99,Th H3 ＝19`h3_0000；
In one case of this embodiment, for a 64-bit single bit input sequence, there are only three levels of SINC filters, assuming the original input is
`
### Calculating to obtain first-stage quantization of SINC filterThe data is 7 ' h3F, the second-level quantized data is 13 ' h0FC0, and the third-level quantized data is 19 ' h3_F000; in this case, as shown in FIG. 4, when the sinc_cnt count is 63, the quantized data of the first-stage SINC filter is 7 'h 3F, and 7' h3F is larger than the set Th H1 =7h3c, in which case the first level threshold Comparator comparator_h1 outputs a high level, triggering the high threshold or logic block to output bit_flag_h high.
In another case of this embodiment, the worst is the third stage SINC filter when the threshold is detectable. Assume that the input 1-bit data stream is 64' -b 1111_1111_1111_1111_1111_1111_1111_1111_1111_1111_1111_1111_1111_1111_1111_1111_1111_1111_0000_0000_0000 the method comprises the steps of carrying out a first treatment on the surface of the the method comprises the steps of carrying out a first treatment on the surface of the; calculating to obtain 7 ' h34 of first-stage quantized data of the SINC filter, 13 ' h0D00 of second-stage quantized data and 19 ' h3_4000 of third-stage quantized data; in this case, as shown in FIG. 5, when the sinc_cnt count is 63, the quantized data 7' h34 of the first-stage SINC filter is smaller than the set Th H1 =7h3c, in which case the first-stage threshold comparator_h1 outputs a low level and enters the second stage for quantization, e.g. the quantized data after the second stage quantization is smaller than Th H2 =13' hd99, the second-stage threshold Comparator comparator_h2 outputs a low level, and enters the third stage for quantization, when quantized data after the third stage quantization is larger than Th H3 The output of the comparator_h3 of this stage is high, which triggers the high threshold or logic block output bit_flag_h to be high, =19' h3_0000.
When the third level threshold comparator output is low, the logic block output is not triggered or high. Indicating that the quantized data is within a threshold range.
The design mode can be realized by only inserting a threshold comparator into each stage of SINC filter, and the number of D triggers is 134.
From the above, the structure of reducing the threshold detection time of the three-stage SINC filter of the present invention can obtain the threshold detection result in the first-stage filter when the difference between the threshold detection quantized value and the expected target value is too large. Compared with the traditional method that the result is obtained only after three steps, the OR logic module can respond quickly.
The above list two cases of high threshold triggering, and the low threshold case is similar to the above case and is not listed again
In summary, for three-stage SINC filters, when detecting an over-threshold or an under-threshold, the delay of the SINC filter of the first order is only required in the best case, and the worst case delay is three times the delay of the SINC filter of the first order. Compared with the prior art that the threshold comparator is only connected at the third stage, the method can quickly detect the input signal with the larger expected value and transmit the input signal to a subsequent system to respond.
In summary, in the filtering module of each stage of the three-stage SINC filter, the threshold comparison module is inserted into each stage, so that the condition of over-threshold or under-threshold can be rapidly detected when input data is bigger or smaller, and the response time of a subsequent system is saved.
The above description is only a preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above examples, and all technical solutions belonging to the concept of the present invention belong to the protection scope of the present invention. It should be noted that modifications and adaptations to the present invention may occur to one skilled in the art without departing from the principles of the present invention and are intended to be within the scope of the present invention.
Claims (9)
1. The implementation method for reducing the threshold detection time by the three-stage SINC filter is characterized by comprising the following steps of:
in the filtering module of the SINC filter body, a threshold comparator and a logic module are inserted into the filtering module of each stage;
setting a detection threshold T for a threshold comparator of the series i i ，i＝1,2,3；
SINC circuit of stage number i receives input data X i-1 Quantization is carried out to obtain quantized data X i The method comprises the steps of carrying out a first treatment on the surface of the Wherein i is the number of stages of the filtering module;
the threshold comparator of progression i will quantize the data X i Threshold T of number of stages i i Comparing; and outputting a comparison result; the comparison result comprises lower threshold detection information or threshold detection ending information;
when the output comparison result includes lower threshold detection information, the data X is quantized i The filtering module is sent to the stage number i+1;
when the output comparison result comprises threshold detection ending information, triggering a subsequent system to respond by a logic module of the series i;
when the quantized data X of the series i is received by the series i+1 i At the time of quantizing data X i Re-quantizing as input data Xi;
when the OR logic module triggers the subsequent system to respond or triggers the last-stage threshold comparator to output a comparison result, the threshold detection of the SINC filter body is finished.
2. The method for reducing threshold detection time of a three-stage SINC filter according to claim 1, wherein the threshold comparator comprises an over-threshold comparator and an under-threshold comparator; the detection threshold preset by the over-threshold comparator is different from the detection threshold preset by the under-threshold comparator;
the comparison result comprises an over-threshold comparison result output by the over-threshold comparator and an under-threshold comparison result output by the under-threshold comparator;
the OR logic module comprises an over-threshold or logic module and an under-threshold or logic module;
the threshold value passing or logic module is used for analyzing the threshold value passing comparison result and outputting a threshold value passing analysis result;
the underthreshold value or logic module is used for analyzing the underthreshold value comparison result and outputting an underthreshold value analysis result;
the threshold analysis result and the threshold analysis result comprise the step of sending lower threshold detection information or threshold detection ending information;
when threshold detection ending information exists in the over-threshold analysis result and the under-threshold analysis result, the threshold detection ending information is sent to a subsequent system to respond;
otherwise, the data X will be quantized i And sending the filtered signal to a filtering module with the stage number of i+1.
3. The method for reducing threshold detection time of a three-stage SINC filter according to claim 2, wherein when the quantized data is greater than a detection threshold preset by an over-threshold comparator or the quantized data is less than a detection threshold preset by an under-threshold comparator; the over-threshold analysis result or the under-threshold analysis result comprises threshold detection ending information; when the equivalent data is smaller than the detection threshold preset by the threshold crossing comparator and larger than the detection threshold preset by the threshold undershooting comparator, the threshold crossing analysis result or the threshold undershooting analysis result comprises sending lower threshold detection information.
4. The method for reducing threshold detection time by a three-stage SINC filter according to claim 1, further comprising the steps of:
the detection threshold precision preset by the threshold comparator of each stage is consistent with the quantization precision;
calculating the quantization accuracy Q of the series i according to the following formula i ：
Wherein D is i Quantizing data X for series i i Is a quantized data bit wide.
5. The method for reducing threshold detection time of a three-stage SINC filter as recited in claim 4, wherein the number of stages i quantized data X is calculated according to the formula i Quantized data bit width D of (2) i ；
D i ＝d+i*log 2 M；
Where d is the original input data bit width; m is a preset downsampling decimation factor.
6. The method of claim 5, wherein the desired threshold of the plurality of threshold comparators increases with increasing number of stages.
7. A three-stage SINC filter threshold detection time reducing structure, applied to the implementation method of reducing threshold detection time of a three-stage SINC filter according to any one of claims 1 to 6, characterized in that the three-stage SINC filter threshold detection time reducing structure comprises a SINC filter body, a threshold comparator and or a logic module;
the SINC filter body takes the output of the modulator as an input signal; wherein, a threshold comparator and a logic module are inserted in the filtering module of each stage of the SINC filter body;
the filtering module of the first stage quantizes the output data of the modulator to obtain quantized data;
the filtering module of the next stage re-quantizes the quantized data received by the previous stage;
the threshold comparator is used for comparing the quantized data of the current level with a detection threshold preset by the current level and outputting a comparison result;
the OR logic module is used for triggering a filtering module of the next stage according to the comparison result of the stage; the OR logic module is also used for triggering a subsequent system to respond according to the comparison result of the stage.
8. The structure for reducing threshold detection time of a three-stage SINC filter of claim 7 wherein the threshold comparator comprises an over-threshold comparator and an under-threshold comparator; the OR logic module comprises an over-threshold or logic module and an under-threshold or logic module; the comparison result comprises an over-threshold comparison result output by the over-threshold comparator and an under-threshold comparison result output by the under-threshold comparator;
the threshold value passing or logic module is used for analyzing the threshold value passing comparison result and outputting a threshold value passing analysis result;
the underthreshold value or logic module is used for analyzing the underthreshold value comparison result and outputting an underthreshold value analysis result;
the over-threshold analysis result and the under-threshold analysis result each include transmitting lower threshold detection information or threshold detection end information.
9. The structure for reducing threshold detection time of a three-stage SINC filter of claim 8 wherein the over-threshold comparison result and the under-threshold comparison result each comprise a high level or a low level;
outputting threshold detection ending information when the threshold crossing or logic module analyzes that the threshold crossing comparison result is at a high level; outputting and transmitting lower threshold detection information when the threshold comparison result is low level through the threshold crossing or the logic module;
when the undershoot value or the logic module analyzes that the undershoot value comparison result is at a high level, outputting threshold detection ending information; and outputting and transmitting lower threshold detection information when the undershoot value or the logic module analyzes that the undershoot value comparison result is low level.
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