CN117200001A - Addressable VCSEL chip and lidar - Google Patents

Abstract

An addressable VCSEL chip and a lidar are disclosed. The addressable VCSEL chip comprises: a plurality of VCSEL light emitting cells electrically isolated from each other and arranged in an array, and an addressing circuit structure electrically connected to the plurality of VCSEL light emitting cells. Each VCSEL light emitting unit comprises at least one VCSEL light emitting point, and each VCSEL light emitting point comprises from bottom to top: a substrate layer, a negative conductive layer, an N-DBR layer, an active region, a confinement layer having a confinement hole, a P-DBR layer, and a positive conductive layer. And all substrate layers of the VCSEL luminous points are integrally connected to form a common substrate layer, and an anti-conduction structure configuration is arranged between the common substrate layer and the negative electric conduction layer and used for preventing mutual electric conduction among a plurality of VCSEL luminous units.

Description

Addressable VCSEL chip and lidar

Technical Field

The present application relates to the field of semiconductor lasers, and more particularly to addressable VCSEL chips and lidars.

Background

A VCSEL (Vertical-Cavity Surface Emitting Laser) refers to a semiconductor Laser that forms a resonator in a Vertical direction of a substrate and emits Laser light in the Vertical direction. VCSEL has the characteristics of stable light beam quality, single longitudinal mode output, high photoelectric conversion efficiency and the like, and is widely applied to the fields of communication, consumption, vehicle-mounted and the like. For example, VCSEL technology can be applied as an in-vehicle lidar at present.

It is worth mentioning that, in the application of the laser radar, the VCSEL addressing technology can be used to realize laser scanning, without any rotating component, compared with the mechanical laser radar that realizes laser scanning through the rotating component, the method can avoid the influence of stability (such as structural stability and rotation precision stability) and reliability of the rotating component on the accuracy of the scanning result in the operation process, simplify the production process, and reduce the production cost.

Specifically, the area lighting of the VCSEL chip can be realized through an addressing technology, and the projection range and the projection direction of laser are controlled through controlling the lighting area and the lighting sequence, so that the laser emitted from different areas of the VCSEL chip is gradually projected to each part of the tested target area according to a specific sequence, and the laser scanning is realized.

However, currently, VCSEL addressing techniques still have some problems. For example, in controlling the zone lighting process, the zone that is expected to be lit is lit while other zones are lit.

Thus, there is a need for an optimized VCSEL addressing scheme to meet the real industry requirements for VCSEL addressing.

Disclosure of Invention

An advantage of the present application is that it provides an addressable VCSEL chip and lidar in which the addressable VCSEL chip has an anti-turn-on configuration that prevents electrical conduction between individual VCSEL light emitting cells, and that contemplates that the illuminated sub-regions be illuminated while other sub-regions are illuminated.

To achieve at least one of the above or other advantages and objects, according to one aspect of the present application, there is provided an addressable VCSEL chip comprising:

a plurality of VCSEL light emitting cells electrically isolated from each other and arranged in an array, each of said VCSEL light emitting cells comprising at least one VCSEL light emitting point, each of said VCSEL light emitting points comprising from bottom to top: a substrate layer, a negative conductive layer, an N-DBR layer, an active region, a confinement layer having a confinement hole, a P-DBR layer, and a positive conductive layer; and

an addressing circuit structure comprising a plurality of positive electrical connection lines and a plurality of negative electrical connection lines, wherein each positive electrical connection line is electrically connected to a positive electrical conduction layer of at least two of the VCSEL light emitting cells, each negative electrical connection line is electrically connected to a negative electrical conduction layer of at least two of the VCSEL light emitting cells, in such a way that the addressing circuit structure forms an addressing circuit for the plurality of VCSEL light emitting cells such that any of the plurality of VCSEL light emitting cells is adapted to be electrically conductive by conducting a pair of the positive electrical connection lines and the negative electrical connection lines;

the substrate layers of all the VCSEL luminous points are integrally connected to form a common substrate layer, and an anti-conduction structure configuration is arranged between the common substrate layer and the negative electricity conduction layer and used for preventing mutual electric conduction among a plurality of VCSEL luminous units.

In the addressable VCSEL chip of the present application, the anti-turn-on structure is configured such that a PN diode structure is formed between the common substrate layer and the negative conductive layer.

In the addressable VCSEL chip of the present application, the addressable VCSEL chip comprises a P-type doped layer between the common substrate layer and the negative conducting layer, the negative conducting layer and the P-type doped layer forming the PN diode structure.

In the addressable VCSEL chip of the present application, the addressable VCSEL chip further comprises an undoped insulating layer between the P-doped layer and the common substrate layer.

In the addressable VCSEL chip of the present application, the common substrate layer is a P-type doped substrate layer, and the negative conducting layer and the common substrate layer form the PN diode structure.

In the addressable VCSEL chip of the present application, the anti-conduction structure is configured such that an undoped insulating structure is formed between the common substrate layer and the negative conduction layer.

In the addressable VCSEL chip of the present application, the addressable VCSEL chip further comprises an undoped insulating layer between the common substrate layer and the negative conducting layer, and the common substrate layer is an N-doped layer.

In the addressable VCSEL chip of the present application, the addressable VCSEL chip further comprises an undoped insulating layer between the common substrate layer and the negative conducting layer, and the common substrate layer is a P-doped layer.

In the addressable VCSEL chip of the present application, the common substrate layer is an undoped substrate layer.

According to another aspect of the present application, there is provided a lidar comprising:

a laser projection device for projecting laser light, wherein the laser projection device comprises any of the addressable VCSEL chips described above;

a laser receiving device for receiving a laser signal; and

a processor communicatively coupled to the laser projection device and the laser receiving device.

Further objects and advantages of the present application will become fully apparent from the following description and the accompanying drawings.

These and other objects, features and advantages of the present application will become more fully apparent from the following detailed description, the accompanying drawings and the appended claims.

Drawings

These and/or other aspects and advantages of the present application will become more apparent and more readily appreciated from the following detailed description of the embodiments of the application, taken in conjunction with the accompanying drawings, wherein:

fig. 1 illustrates a perspective view of a conventional VCSEL chip.

Figure 2 illustrates a partial schematic of a cross-sectional view of a prior art VCSEL chip.

Fig. 3 illustrates a perspective view of a VCSEL chip according to an embodiment of the present application.

Figure 4 illustrates a cross-sectional schematic view of an implementation of a VCSEL chip according to an embodiment of the present application.

Figure 5 illustrates a cross-sectional schematic view of another implementation of a VCSEL chip according to an embodiment of the present application.

Figure 6 illustrates a cross-sectional schematic view of yet another implementation of a VCSEL chip according to an embodiment of the present application.

Figure 7 illustrates a cross-sectional schematic view of yet another implementation of a VCSEL chip according to an embodiment of the present application.

Figure 8 illustrates a cross-sectional schematic view of yet another implementation of a VCSEL chip according to an embodiment of the present application.

Figure 9 illustrates a cross-sectional schematic view of yet another implementation of a VCSEL chip according to an embodiment of the present application.

Detailed Description

The terms and words used in the following description and claims are not limited to literal meanings, but are used only by the inventors to enable a clear and consistent understanding of the application. It will be apparent to those skilled in the art, therefore, that the following description of the various embodiments of the application is provided for illustration only and not for the purpose of limiting the application as defined by the appended claims and their equivalents.

It will be understood that the terms "a" and "an" should be interpreted as referring to "at least one" or "one or more," i.e., in one embodiment, the number of elements may be one, while in another embodiment, the number of elements may be plural, and the term "a" should not be interpreted as limiting the number.

Although ordinal numbers such as "first," "second," etc., will be used to describe various components, those components are not limited herein. The term is used merely to distinguish one component from another. For example, a first component may be referred to as a second component, and likewise, a second component may be referred to as a first component, without departing from the teachings of the present inventive concept. The term "and/or" as used herein includes any and all combinations of one or more of the associated listed items.

The terminology used herein is for the purpose of describing various embodiments only and is not intended to be limiting. As used herein, the singular is intended to include the plural as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, or groups thereof.

Summary of the application: in the application of the laser radar, the laser scanning can be realized by using a VCSEL addressing technology without any rotating component, specifically, the zone lighting of the VCSEL chip can be realized by using the addressing technology, and the projection range and the projection direction of laser are controlled by controlling the lighting area and the lighting sequence, so that the laser emitted from different areas of the VCSEL chip is gradually projected to each part of the tested target area according to a specific sequence, thereby realizing the laser scanning.

However, currently, VCSEL addressing techniques still have some problems. For example, in controlling the zone lighting process, the zone that is expected to be lit is lit while other zones are lit.

Analysis of existing addressable VCSEL chips reveals that the above problems are related to the structure of existing addressed VCSEL chips. Specifically, the substrate P0 of each VCSEL light emitting unit is common, as shown in fig. 1 and 2, wherein at least part of the VCSEL light emitting units share an anode P1 and the cathodes are independent, respectively. For example, the addressable VCSEL chip comprises a first VCSEL light emitting unit P3 and a second VCSEL light emitting unit P4, wherein the first VCSEL light emitting unit P3 and the second VCSEL light emitting unit P4 share an anode P1, and a cathode P2 of the first VCSEL light emitting unit P3 and a cathode P5 of the second VCSEL light emitting unit P4 are independent from each other.

When a current (V > 0) is input to the common anode P1 and 0V is applied to the cathode of the first VCSEL light emitting unit P3 or grounded, a current flows through the first VCSEL light emitting unit P3, and the first VCSEL light emitting unit P3 is lighted.

When the insulation property of the substrate P0 is high, the second VCSEL light emitting unit P4 shares the anode P1 with the first VCSEL light emitting unit P3, but the cathode P5 thereof is not biased, so that current does not flow into the second VCSEL light emitting unit P4, and the second VCSEL light emitting unit P4 is not lighted, so that each VCSEL light emitting unit can realize an independent addressing function.

When the insulation of the substrate P0 is low, a current (V > 0) is input to the common anode P1, and then flows into the second VCSEL light emitting unit P4, and flows out to the cathode P2 of the first VCSEL light emitting unit P3 through the substrate P0, so that a current loop is formed, and the second VCSEL light emitting unit P4 is also turned on. In this way, the individual VCSEL light emitting cells lose the function of independent addressing.

Based on this, the inventors of the present application have proposed that an anti-conduction structure capable of preventing cathodes of individual VCSEL units from being conducted to each other is formed in an addressable VCSEL chip, and current is prevented from flowing into a plurality of VCSEL units after current is input to a common anode of the individual VCSEL units, so that VCSEL units which are not intended to be lighted are lighted.

Accordingly, the present application proposes an addressable VCSEL chip comprising: a plurality of VCSEL light emitting cells electrically isolated from each other and arranged in an array, and an addressing circuit structure electrically connected to the plurality of VCSEL light emitting cells. Each VCSEL light emitting unit comprises at least one VCSEL light emitting point, and each VCSEL light emitting point comprises from bottom to top: a substrate layer, a negative conductive layer, an N-DBR layer, an active region, a confinement layer having a confinement hole, a P-DBR layer, and a positive conductive layer. The addressing circuit structure comprises a plurality of positive electrical connection lines and a plurality of negative electrical connection lines, wherein each positive electrical connection line is electrically connected to a positive electrical conduction layer of at least two VCSEL light emitting units, and each negative electrical connection line is electrically connected to a negative electrical conduction layer of at least two VCSEL light emitting units. And all substrate layers of the VCSEL luminous points are integrally connected to form a common substrate layer, and an anti-conduction structure configuration is arranged between the common substrate layer and the negative electric conduction layer and used for preventing mutual electric conduction among a plurality of VCSEL luminous units.

Having described the basic principles of the present application, various non-limiting embodiments of the present application will now be described in detail with reference to the accompanying drawings.

Schematic addressable VCSEL chip: as shown in fig. 3 to 9, an addressable VCSEL chip according to an embodiment of the present application is illustrated, wherein the addressable VCSEL chip comprises a plurality of VCSEL light emitting cells 10 spaced apart from each other and an addressing circuit structure 20 electrically connected to a plurality of the VCSEL light emitting cells 10, each VCSEL light emitting cell 10 comprising at least one VCSEL light emitting point 60, i.e. each VCSEL light emitting cell 10 comprises one or more VCSEL light emitting points 60. Each VCSEL emission point 60 comprises a light emitting body 61 and positive and negative electrically conductive layers 62, 63 electrically connected to the light emitting body 61. Specifically, the light emitting body 61 includes a substrate layer 611, an N-DBR layer 612, an active region 613, a confinement layer 614 having a confinement hole 101, and a P-DBR layer 615. In the embodiment of the present application, each VCSEL emission point 60 includes, from bottom to top, a substrate layer 611, a negative conductive layer 63, an N-DBR layer 612, an active region 613, a confinement layer 614 having a confinement aperture 101, a P-DBR layer 615, and a positive conductive layer 62.

The N-DBR layer 612 is made of N-type doped Al with high aluminum content _x Ga _1-x As (x= 1~0) and N-doped low aluminum content Al _x Ga _1-x Alternate layers of As (x= 1~0) are formed. The P-DBR layer 615 is composed of P-doped high aluminum content Al _x Ga _1-x As (x= 1~0) and P-doped low aluminum content Al _x Ga _1-x Alternate layers of As (x= 1~0) are formed. In some examples of the application, the N-DBR layer 612 and the P-DBR layer 615 may even be made of materials that do not include aluminum, i.e., aluminum. It is worth mentioning that the material selection of the alternating layersThe optical thickness of the alternating layers is equal to or approximately equal to 1/4 of the operating wavelength of the laser light, depending on the operating wavelength of the laser light emitted by the VCSEL emission point 60.

The active region 613 is sandwiched between the N-DBR layer 612 and the P-DBR layer 615 to form a resonant cavity, wherein photons are repeatedly amplified by being reflected back and forth within the resonant cavity after being excited to form laser oscillation, thereby forming laser light. It will be appreciated by those skilled in the art that the direction of the laser light emission, for example, from the N-DBR layer 612 or from the P-DBR layer 615 can be selectively controlled by configuring and designing the N-DBR layer 612 and the P-DBR layer 615. Accordingly, the N-DBR layer 612 and the P-DBR layer 615 are configured such that, after the VCSEL light emitting point 60 is turned on, laser light generated by the active region 613 is reflected multiple times in a resonant cavity formed between the N-DBR layer 612 and the P-DBR layer 615 and then exits the P-DBR layer 615, or the N-DBR layer 612.

When the N-DBR layer 612 and the P-DBR layer 615 are configured such that laser light generated by the active region 613 is emitted from the P-DBR layer 615 after being reflected multiple times within a resonant cavity formed between the N-DBR layer 612 and the P-DBR layer 615 after the VCSEL light emitting point 60 is turned on, the positive electricity conducting layer 62 has a ring shape, and the positive electricity conducting layer 62 has a light emitting hole 102 corresponding to the confinement hole 101.

During operation, an operating voltage/current is applied to the addressable VCSEL chip to generate a current in the VCSEL emission point 60. After the VCSEL emission point 60 is turned on, a current is limited in flow direction by the confinement layer 614, which is finally introduced into the middle region of the VCSEL emission point 60, so that the middle region of the active region 613 generates laser light. More specifically, in the embodiment of the present application, the confinement layer 614 has a confinement region surrounding the confinement holes 101, the confinement region having a higher resistivity to confine carriers flowing into the middle region of the VCSEL emission point 60, and a lower refractive index of the confinement region to laterally confine photons, the carriers and optical lateral confinement increasing the density of carriers and photons within the active region 613, increasing the efficiency of light generation within the active region 613.

In some embodiments of the present application, the confinement layer 614 is implemented as an oxidation confinement layer formed above and/or below the active region 613 by an oxidation process. In the embodiment of the present application, the oxidation limiting layer may be formed as a separate layer above the active region 643, or may be formed above the active region 613 by oxidizing at least a portion of the lower region of the P-DBR layer 615, which is not limited to the present application. In other embodiments of the present application, the confinement layer 614 is implemented as other forms, for example, implemented as an ion confinement layer 614 (not shown) formed above and/or below the active region 613 by an ion implantation process, which is not limited to the present application.

In the embodiment of the present application, a separation structure 103 is disposed between every two VCSEL emission points 60, and the separation structure 103 extends from the upper surface of the VCSEL emission point 60 to below the active region 613. The isolation structure 103 may be implemented as a recess or as an ion implantation layer made of a high-resistance material, which is not limited to the present application.

As shown in fig. 3, the addressing circuit structure 20 includes a plurality of positive connection lines 21 and a plurality of negative connection lines 22, wherein each positive connection line 21 is electrically connected to a positive conductive layer 62 of at least two of the VCSEL light emitting units 10, and each negative connection line 22 is electrically connected to a negative conductive layer 63 of at least two of the VCSEL light emitting units 10, in such a way that the addressing circuit structure 20 forms an addressing circuit of the plurality of VCSEL light emitting units 10 such that any one of the VCSEL light emitting units 10 of the plurality of VCSEL light emitting units 10 is adapted to be electrically conductive by conducting a pair of the positive connection lines 21 and the negative connection lines 22.

In the embodiment of the present application, the plurality of positive connection lines 21 and the plurality of negative connection lines 22 form a heterogeneous electrode structure of the addressable VCSEL chip, so as to implement conduction of the plurality of VCSEL light emitting points 60 in the addressable VCSEL chip, and further implement independent control of the plurality of VCSEL light emitting units 10.

Specifically, the positive electrical connection line 21 and the negative electrical connection line 22 are cross-paired, that is, at least two VCSEL light emitting units 10 electrically connected to the same positive electrical connection line 21 are respectively electrically connected to two different negative electrical connection lines 22, and are not electrically connected to the same negative electrical connection line 22, so as to realize independent control of each VCSEL light emitting unit 10.

More specifically, as shown in fig. 3, each of the positive electric connection lines 21 is electrically connected to the positive electric conduction layers 62 of one row of the VCSEL light emitting cells 10 arranged in a first direction set by the chip body 10, and each of the negative electric connection lines 22 is electrically connected to the negative electric conduction layers 63 of one column of the VCSEL light emitting cells 10 arranged in a second direction set by the chip body 10, wherein the first direction and the second direction have an included angle, and the included angle between the first direction and the second direction is not equal to 0 ° or 180 °.

A plurality of positive electrical connection lines 21 define a plurality of light emitting segments in the addressable VCSEL chip extending along the first direction, each light emitting segment extending along the first direction comprising a row of VCSEL light emitting cells 10 defining a plurality of groups of arrays of VCSEL light emitting cells. The groups of VCSEL light emitting unit arrays of the respective light emitting sections extending in the first direction are connected in parallel by a plurality of the positive connection lines 21, for example, the groups of VCSEL light emitting unit arrays of the first section extending in the first direction are connected in parallel with the groups of VCSEL light emitting unit arrays of the second section extending in the first direction by a first positive connection line 21 and a second positive connection line 21.

A plurality of negative electrical connection lines 22 define a plurality of light emitting segments in the addressable VCSEL chip extending along the second direction, each light emitting segment extending along the second direction comprising a plurality of columns of VCSEL light emitting cells 10 defining a plurality of groups of arrays of VCSEL light emitting cells. A plurality of groups of VCSEL light emitting unit arrays of respective light emitting sections extending in the second direction are connected in parallel by a plurality of the negative electrical connection lines 22, for example, a plurality of groups of VCSEL light emitting unit arrays of a third section extending in the second direction are connected in parallel with a plurality of groups of VCSEL light emitting unit arrays of a fourth section extending in the second direction by a first negative electrical connection line 22 and a second negative electrical connection line 22. The positive connection line 21 and the negative connection line 22 form a net-shaped crossed design structure, and each VCSEL light emitting unit 10 can be independently controlled to light up the VCSEL light emitting unit arrays in different areas in a partitioned manner.

In a specific example of the present application, the angle between the first direction and the second direction is 90 °. In the created X-Y two-dimensional coordinate system, each positive electric connection line 21 extends longitudinally in the X direction, and a plurality of negative electric connection lines 22 are arranged at intervals from each other in the Y direction perpendicular to the X direction. Each of the negative electric connection lines 22 extends longitudinally in the Y direction, and a plurality of the positive electric connection lines 21 are arranged at intervals from each other in the X direction. The positive electrode connection lines 21 define a plurality of light emitting areas extending along the X direction, each light emitting area extending along the X direction defines a plurality of groups of VCSEL light emitting unit arrays along the X direction, and the positive electrode connection lines 21 are arranged at intervals along the Y direction and connect the plurality of groups of VCSEL light emitting unit arrays of the light emitting areas extending along the X direction in parallel. The negative electrical connection lines 22 define a plurality of light emitting areas extending along the Y direction, each light emitting area extending along the Y direction defines a plurality of groups of VCSEL light emitting unit arrays along the Y direction, and the negative electrical connection lines 22 are arranged at intervals along the Y direction and connect the plurality of groups of VCSEL light emitting unit arrays of the light emitting areas extending along the Y direction in parallel.

In the embodiment of the present application, the same positive connection line 21 to which a plurality of the VCSEL light emitting units 10 are electrically connected forms a common anode of the VCSEL light emitting units 10, that is, the plurality of VCSEL light emitting units 10 to which each positive connection line 21 is electrically connected share the anode. The negative electrical connection lines 22 to which the plurality of VCSEL light emitting cells 10 electrically connected to each positive electrical connection line 21 are electrically different and respectively form cathodes of the plurality of VCSEL light emitting cells 10, that is, the cathodes of the plurality of VCSEL light emitting cells 10 electrically connected to each positive electrical connection line 21 are independent of each other.

It should be noted that in the embodiment of the present application, the substrate layers 611 of all VCSEL light emitting points 60 are integrally connected to form the common substrate layer 50. When the insulation property of the common substrate layer 50 is low, a common anode input current (V > 0) formed by the same positive connection line 21 to which the plurality of VCSEL light emitting units 10 are electrically connected is applied to 0V or grounded to the negative connection line 22 to which one of the VCSEL light emitting units 10 is electrically connected, and current flows into the VCSEL light emitting units 10 through the common substrate layer 50 while current flows into other VCSEL light emitting units 10, and other VCSEL light emitting units 10 are also lit. In this way, the individual VCSEL light emitting cells 10 lose the function of independent addressing.

Based on this, the present application proposes to form an anti-conduction structure capable of preventing the individual VCSEL light emitting cells 10 from being mutually conducted in an addressable VCSEL chip, and to prevent a current from flowing into the plurality of VCSEL light emitting cells 10 after a current is inputted to a common anode of the individual VCSEL light emitting cells 10, so that the VCSEL light emitting cells 10 that are not expected to be lighted are lighted.

Accordingly, in the embodiment of the present application, the common substrate layer 50 and the negative conductive layer 63 have an anti-conductive structure configured to prevent the plurality of VCSEL light emitting cells 10 from being electrically conductive to each other.

In some embodiments of the application, the anti-conduction structure is configured to: a PN diode structure 70 is formed between the common substrate layer 50 and the negative conductive layer 63. In one specific example of the present application, the addressable VCSEL chip further comprises a P-doped layer 80 between the common substrate layer 50 and the negative conducting layer 63, the negative conducting layer 63 and the P-doped layer 80 forming the PN diode structure 70, as shown in fig. 4.

Thus, when a common anode input current (V > 0) is formed by the same positive connection line 21 electrically connected to a plurality of VCSEL light emitting units 10, and 0V is applied to or grounded to the negative connection line 22 electrically connected to one of the VCSEL light emitting units 10, after the current flows into the VCSEL light emitting unit 10, the reverse bias voltage is applied to the PN diode structure 70 formed by the negative conductive layer 63 and the P-type doped layer 80, so that the current is prevented from flowing to other VCSEL light emitting units 10, and in this way, the other VCSEL light emitting units 10 are prevented from being lighted, so that the individual VCSEL light emitting units 10 can be addressed independently.

In another specific example of the present application, as shown in fig. 6, the common substrate layer 50 is a P-type doped substrate layer, and the negative conductive layer 63 and the common substrate layer 50 form the PN diode structure 70. The current flow can be prevented as well.

In other embodiments of the present application, the anti-conduction structure is configured to: an undoped insulating structure is formed between the common substrate layer 50 and the negative conductive layer 63. In one specific example of the present application, as shown in fig. 7, the addressable VCSEL chip further comprises an undoped insulating layer 90 between the common substrate layer 50 and the negative conducting layer 63. In this particular example, the substrate layer 50 is an N-type doped substrate layer.

Thus, the common anode formed by the same positive connection line 21 electrically connected to a plurality of the VCSEL light emitting units 10 inputs a current (V > 0), and the negative connection line 22 electrically connected to one of the VCSEL light emitting units 10 is applied with 0V or grounded, and after the current flows into the VCSEL light emitting unit 10, the undoped insulating layer 90 prevents the current from flowing into other VCSEL light emitting units 10, in such a way that the other VCSEL light emitting units 10 are prevented from being lighted, and the individual VCSEL light emitting units 10 are ensured to be addressed independently.

As shown in fig. 8, in another specific example of the present application, the addressable VCSEL chip further comprises an undoped insulating layer 90 between the common substrate layer 50 and the negative conducting layer 63. In this particular example, the substrate layer 50 is a P-type doped substrate layer.

In yet another specific example of the present application, as shown in fig. 9, the common substrate layer 50 is an undoped substrate layer, and the undoped structure is formed.

In some embodiments of the application, the anti-conduction structure is configured to: a PN diode structure 70 and an undoped insulating structure are formed between the common substrate layer 50 and the negative conductive layer 63. In one specific example of the present application, as shown in fig. 5, the addressable VCSEL chip further comprises a P-doped layer 80 located between the common substrate layer 50 and the negative conducting layer 63, an undoped insulating layer 90 located between the P-doped layer 80 and the common substrate layer 50, the negative conducting layer 63 and the P-doped layer 80 forming the PN diode structure 70.

In summary, an addressable VCSEL chip according to an embodiment of the present application is illustrated, which has an anti-turn-on structure configuration, which prevents the individual VCSEL light emitting cells from being electrically turned on to each other, and the areas that are expected to be turned on are turned on at the same time as other areas are also turned on.

Schematic vehicle-mounted lidar: according to yet another aspect of the present application, there is also provided a lidar. The working principle of the laser radar is as follows: the laser is used as a medium to emit laser to the measured target, the laser reflected by the measured target is received, and the relative position and distance between the measured target and the laser radar are obtained based on the time difference between the emitted laser and the received laser pulse (or the phase difference between the emitted laser and the received reflected laser), so that the detection, tracking and identification of the object to be measured in the target area are realized.

Accordingly, the lidar includes: a laser projection device for projecting laser light, a laser receiving device for receiving a laser signal, and a processor communicatively connected to the laser projection device and the laser receiving device, wherein the laser projection device comprises an addressable VCSEL chip as described above. The specific structure and function of the addressable VCSEL chip have been described in detail in the description of the addressable VCSEL chip illustrated above with reference to fig. 1 to 9, and thus, repetitive descriptions thereof will be omitted.

The basic principles of the present application have been described above in connection with specific embodiments, however, it should be noted that the advantages, benefits, effects, etc. mentioned in the present application are merely examples and not intended to be limiting, and these advantages, benefits, effects, etc. are not to be considered as essential to the various embodiments of the present application. Furthermore, the specific details disclosed herein are for purposes of illustration and understanding only, and are not intended to be limiting, as the application is not necessarily limited to practice with the above described specific details.

Claims (10)

1. An addressable VCSEL chip comprising:

a plurality of VCSEL light emitting cells electrically isolated from each other and arranged in an array, each of said VCSEL light emitting cells comprising at least one VCSEL light emitting point, each of said VCSEL light emitting points comprising from bottom to top: a substrate layer, a negative conductive layer, an N-DBR layer, an active region, a confinement layer having a confinement hole, a P-DBR layer, and a positive conductive layer; and

an addressing circuit structure comprising a plurality of positive electrical connection lines and a plurality of negative electrical connection lines, wherein each positive electrical connection line is electrically connected to a positive electrical conduction layer of at least two of the VCSEL light emitting cells, each negative electrical connection line is electrically connected to a negative electrical conduction layer of at least two of the VCSEL light emitting cells, in such a way that the addressing circuit structure forms an addressing circuit for the plurality of VCSEL light emitting cells such that any of the plurality of VCSEL light emitting cells is adapted to be electrically conductive by conducting a pair of the positive electrical connection lines and the negative electrical connection lines;

the substrate layers of all the VCSEL luminous points are integrally connected to form a common substrate layer, and an anti-conduction structure configuration is arranged between the common substrate layer and the negative electricity conduction layer and used for preventing mutual electric conduction among a plurality of VCSEL luminous units.

2. The addressable VCSEL chip of claim 1, wherein the anti-turn-on structure is configured such that a PN diode structure is formed between the common substrate layer and the negative conducting layer.

3. The addressable VCSEL chip of claim 2, wherein the addressable VCSEL chip comprises a P-type doped layer between the common substrate layer and the negative conducting layer, the negative conducting layer and the P-type doped layer forming the PN diode structure.

4. The addressable VCSEL chip of claim 3, further comprising an undoped insulating layer between the P-doped layer and the common substrate layer.

5. The addressable VCSEL chip of claim 2, wherein the common substrate layer is a P-type doped substrate layer, the negative conducting layer and the common substrate layer forming the PN diode structure.

6. An addressable VCSEL chip as claimed in claim 2, wherein the anti-conduction structure is configured with an undoped insulating structure formed between the common substrate layer and the negative conducting layer.

7. The addressable VCSEL chip of claim 6, further comprising an undoped insulating layer between the common substrate layer and the negative conducting layer, and the common substrate layer is an N-doped layer.

8. The addressable VCSEL chip of claim 6, further comprising an undoped insulating layer between the common substrate layer and the negative conducting layer, and the common substrate layer is a P-doped layer.

9. The addressable VCSEL chip of claim 6, wherein the common substrate layer is an undoped substrate layer.

10. A lidar, comprising:

a laser projection device for projecting laser light, wherein the laser projection device comprises an addressable VCSEL chip according to any of claims 1 to 9;

a laser receiving device for receiving a laser signal; and

a processor communicatively coupled to the laser projection device and the laser receiving device.