CN117199139A - Semiconductor device, NLDMOS structure and manufacturing method thereof - Google Patents

Abstract

The invention provides a semiconductor device, an NLDMOS structure and a manufacturing method thereof, wherein the NLDMOS structure comprises the following components: a substrate; a gate structure; the first N-type doped region is arranged in the substrate below the grid structure and is coated with first field oxygen; a P-type doped region; the first N-type heavily doped region is arranged in the substrate of the first field oxide far away from the grid structure; the second N-type doped region is connected with the first N-type doped region and is positioned on one side of the substrate far away from the P-type doped region, wherein the doping depth of the second N-type doped region is smaller than that of the first N-type doped region, and at least partially coats the first N-type heavily doped region. In the invention, the second N-type doped region and the first N-type doped region are used as drift regions of the NLDMOS structure to cover the gate structure and the substrate under the first field oxygen so as to be completely depleted by the P-type doped region and the substrate, thereby improving the breakdown voltage of the NLDMOS structure.

Description

Semiconductor device, NLDMOS structure and manufacturing method thereof

Technical Field

The invention relates to the technical field of integrated circuit manufacturing, in particular to a semiconductor device, an NLDMOS structure and a manufacturing method thereof.

Background

The LDMOS has the advantages of high voltage resistance, high current driving capability, extremely low power consumption, integration with CMOS and the like, and is widely used in power management circuits at present. The breakdown voltage and on-resistance of the medium-high voltage LDMOS are important electrical indexes of the device.

Taking a medium-high voltage NLDMOS device as an example, in the related art as shown in fig. 1a, an N-type well region 21' is generally used as a drift region, and the drift region is depleted by using a substrate 10' and a P-type well region 22' to achieve a higher breakdown voltage, however, with the development of the market, the breakdown voltage of the NLDMOS structure is difficult to meet the requirement of increasing high breakdown voltage.

Disclosure of Invention

The invention aims to provide a semiconductor device, an NLDMOS structure and a manufacturing method thereof, which are used for improving breakdown voltage.

In order to solve the above technical problems, the NLDMOS structure provided by the present invention includes:

a substrate, the surface of which is provided with a first field oxygen;

the grid structure is arranged on the substrate and covers part of the first field oxygen;

the first N-type doped region is arranged in the substrate below the grid structure and coats the first field oxide;

the P-type doped region is arranged in the substrate at one side of the first N-type doped region, which is far away from the first field oxide, and extends to the lower part of the grid structure;

the first N-type heavily doped region is arranged in the substrate of the first field oxide far away from the grid structure;

the second N-type doped region is connected with the first N-type doped region and is positioned on one side of the substrate far away from the P-type doped region, wherein the doping depth of the second N-type doped region is smaller than that of the first N-type doped region, and at least partially coats the first N-type heavily doped region.

Optionally, a second field oxide is further formed on the surface of the substrate above the P-type doped region, a second N-type heavily doped region is disposed on a side, close to the first field oxide, of the second field oxide, a P-type heavily doped region is disposed on a side, away from the first field oxide, of the second field oxide, and the P-type heavily doped region covers the second N-type heavily doped region and the P-type heavily doped region.

Optionally, a third field oxide is further provided, the third field oxide is located on the surface of the substrate on one side of the first field oxide away from the second field oxide, and the first N-type heavily doped region is located in the substrate between the first field oxide and the third field oxide.

Optionally, an edge of the first N-type doped region far from one side of the gate structure is aligned with an edge corresponding to the second field oxide, and the second N-type doped region wraps the first N-type heavily doped region.

Optionally, the edge of the first N-type doped region far from one side of the gate structure exceeds the edge corresponding to the second field oxide, and the second N-type doped region and the first N-type doped region cover the first N-type heavily doped region.

Optionally, the P-type doped region and the first N-type doped region are connected or spaced apart.

Optionally, the doping depth of the first N-type doped region is greater than the doping depth of the P-type doped region.

Based on another aspect of the present invention, there is also provided a method for manufacturing an NLDMOS structure, including:

providing a substrate;

forming a first N-type doped region in the substrate, and forming first field oxygen on the surface of the substrate on the first N-type doped region;

forming a second N-type doped region and a P-type doped region in the substrate at two sides of the first N-type doped region respectively, wherein the second N-type doped region is connected with the first N-type doped region and is positioned at one side of the second N-type doped region close to the first field oxygen, and the doping depth of the second N-type doped region is smaller than that of the first N-type doped region;

forming a gate structure on the substrate, wherein the gate structure is positioned on the P-type doped region, the first N-type doped region and the first field oxide;

and forming a first N-type heavily doped region in the second N-type doped region.

Optionally, the first N-type doped region is formed by a deep well process.

According to another aspect of the present invention, there is also provided a semiconductor device including an NLDMOS structure including:

a substrate, the surface of which is provided with a first field oxygen;

the grid structure is arranged on the substrate and covers part of the first field oxygen;

the first N-type doped region is arranged in the substrate below the grid structure and coats the first field oxide;

the P-type doped region is arranged in the substrate at one side of the first N-type doped region, which is far away from the first field oxide, and extends to the lower part of the grid structure;

the first N-type heavily doped region is arranged in the substrate of the first field oxide far away from the grid structure;

the second N-type doped region is connected with the first N-type doped region and is positioned on one side of the substrate far away from the P-type doped region, wherein the doping depth of the second N-type doped region is smaller than that of the first N-type doped region, and at least partially coats the first N-type heavily doped region.

In summary, in the present invention, the second N-type doped region is disposed in the substrate below the first N-type heavily doped region, and the second N-type doped region is connected to the first N-type doped region, and the second N-type doped region and the first N-type doped region are used as the drift region of the NLDMOS structure to cover the gate structure and the substrate (conductive and drain) under the first field oxygen, wherein the doping depth of the second N-type doped region is smaller than that of the first N-type doped region, so that the drift region of the NLDMOS structure has a step structure below the drain, thereby enabling the second N-type doped region and the first N-type doped region to be completely depleted by the P-type doped region and the substrate, and further improving the breakdown voltage of the NLDMOS structure. In addition, compared with the prior art that an N-type doped region is used for cladding the channel and the drain end as the drift region, the drift region is formed by the second N-type doped region and the first N-type doped region, and the breakdown voltage and the on-resistance can be further optimized by adjusting the doping concentrations of the two N-type doped regions.

Drawings

It will be appreciated by those skilled in the art that the drawings are provided for a better understanding of the invention and do not constitute any limitation on the scope of the invention.

Fig. 1a is a schematic structural diagram of an NLDMOS of the related art;

fig. 1b is a depletion schematic diagram of a NLDMOS structure in the related art;

fig. 2a is a schematic diagram of an NLDMOS structure provided in the first embodiment;

fig. 2b is a schematic diagram of another NLDMOS structure provided in the first embodiment;

fig. 2c is a depletion schematic diagram of the NLDMOS structure provided in the first embodiment;

fig. 3 is a schematic diagram of an NLDMOS structure provided in embodiment two;

fig. 4 is a flowchart of a method for manufacturing an NLDMOS structure provided in embodiment three;

fig. 5a to 5g are schematic structural diagrams corresponding to corresponding steps of a method for manufacturing an NLDMOS structure according to a third embodiment.

In fig. 1a to 1 b:

a 10' -substrate; a 21' -N-type well region; 22' -P-type well region; a 24' -gate structure; 25' -depletion layer.

Fig. 2a to 5 g:

10-a substrate; 11-a first field oxygen; 12-second field oxygen; 13-third field oxygen; 21-a first N-type doped region; 22-a second N-type doped region; a 23-P type doped region; a 24-gate structure; 24 a-gate oxide; 24 b-a layer of gate material; 25-depletion layer; 31-a first N-type heavily doped region; 32-a second N-type heavily doped region; a 33-P type heavily doped region; 41-a metal plug; 42-metal electrode.

Detailed Description

The invention will be described in further detail with reference to the drawings and the specific embodiments thereof in order to make the objects, advantages and features of the invention more apparent. It should be noted that the drawings are in a very simplified form and are not drawn to scale, merely for convenience and clarity in aiding in the description of embodiments of the invention. Furthermore, the structures shown in the drawings are often part of actual structures. In particular, the drawings are shown with different emphasis instead being placed upon illustrating the various embodiments.

As used in this disclosure, the singular forms "a," "an," and "the" include plural referents, the term "or" are generally used in the sense of comprising "and/or" and the term "several" are generally used in the sense of comprising "at least one," the term "at least two" are generally used in the sense of comprising "two or more," and the term "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying any relative importance or number of features indicated. Thus, a feature defining "a first", "a second", and "a third" may include one or at least two of the feature, either explicitly or implicitly, unless the context clearly dictates otherwise.

Example 1

An embodiment one provides an NLDMOS structure.

Fig. 1 is a schematic diagram of an NLDMOS structure provided in an embodiment.

As shown in fig. 1, the NLDMOS structure provided in this embodiment includes a substrate 10, a gate structure 24, a P-type doped region 23, a first N-type doped region 21, a second N-type doped region 22, and a first N-type heavily doped region 31. A first field oxygen 11 is arranged on the surface of the substrate 10; the gate structure 24 is disposed on the surface of the substrate 10 and covers a portion of the first field oxide 11; the first N-type doped region 21 is disposed in the substrate 10 under the gate structure 24 and encapsulates the first field oxide 11; the P-type doped region 23 is disposed in the substrate 10 on the side of the first N-type doped region 21 away from the first field oxide 11 and extends to below the gate structure 24; the first N-type heavily doped region 31 is disposed in the substrate 10 of the first field oxide 11 far from the gate structure 24; the second N-type doped region 22 is connected to the first N-type doped region 21 and is located on a side of the substrate 10 away from the P-type doped region 23, wherein a doping depth of the second N-type doped region 22 is smaller than a doping depth of the first N-type doped region 21, and at least partially encapsulates the first N-type heavily doped region 31.

The substrate 10 may be P-type, and the substrate 10 may be made of any suitable base material, and in this embodiment, the substrate 10 is made of silicon. In an example, the NLDMOS structure may also be formed in a P-well of the N-type substrate 10. In other examples, P-type epitaxy is formed on substrate 10, and NLDMOS structures may also be formed in the P-type epitaxy of substrate 10.

Referring to fig. 1, in addition to the first field oxide 11, a second field oxide 12 and a third field oxide 13 are disposed on two sides of the first field oxide 11, and the second field oxide 12 and the third field oxide 13 are disposed at intervals from the first field oxide 11. The first field oxide 11, the second field oxide 12 and the third field oxide 13 protrude from the surface of the substrate 10, and the size (width) of the first field oxide 11 is larger than the sizes of the second field oxide 12 and the third field oxide 13. The gate structure 24 is disposed on the substrate 10 between the second field oxide 12 and the first field oxide 11 and extends to cover a portion of the first field oxide 11. Specifically, the gate structure 24 may include a gate oxide layer 24a covering the surface of the substrate 10 and a gate material layer 24b covering the gate oxide layer 24 a. In particular, the gate material layer 24b also extends anteriorly over a portion of the width of the first field oxide 11. A first N-type heavily doped region 31 is disposed in the substrate 10 between the first field oxide 11 and the third field oxide 13, and is used as a drain terminal of the NLDMOS structure, and a second N-type heavily doped region 32 is disposed in the substrate 10 between the gate structure 24 and the first field oxide 11, and is used as a source terminal of the NLDMOS structure.

With continued reference to fig. 1, a p-type doped region 23 is formed in the substrate 10 under the second field oxide 12 and extends below the gate structure 24. Specifically, the second N-type heavily doped region 32 and the P-type heavily doped region 33 are formed in the substrate 10 at two sides of the second field oxide 12, wherein the second N-type heavily doped region 32 is located at one side of the second field oxide 12 close to the first field oxide 11, and the P-type heavily doped region 33 is located at one side of the second field oxide 12 far from the first field oxide 11, for electrically leading out the P-type doped region 23 and the substrate 10 (body region). The P-type doped region 23 wraps around the P-type heavily doped region 33, the second field oxide 12 and the second N-type heavily doped region 32 and extends below the gate oxide layer 24 a. The P-type doped region 23 may be formed by a plurality of P-type ion implantations to have different concentration levels and different shapes (cross-sectional shape in cross-section). In the example of the present embodiment, the P-type doped region 23 may have a rectangular cross-sectional shape. In other examples, the P-doped region 23 may also have a shape with two sides protruding and a concave middle, and the shape of the P-doped region 23 is not limited in this embodiment.

With continued reference to fig. 1, the first N-doped region 21 is located in the substrate 10 under the gate structure 24 and the first field oxide 11, and may be formed by a deep N-well process, so as to have a deep junction depth (deep doping depth), and the doping depth of the first N-doped region 21 may be preferably greater than that of the P-doped region 23, so as to prolong the path lengths of the source and drain ends of the NLDMOS structure in the substrate 10. And has a doping concentration less than that of the substrate 10 and the P-type doped region 23. The first N-doped region 21 may be connected to the P-doped region 23 under the gate structure 24, so that the first N-doped region 21 is depleted by using the P-doped region 23 and the substrate 10, so as to form a depletion region as deep as possible under the gate structure 24 and the first field oxide 11, thereby realizing a higher breakdown voltage. In one example, as shown in fig. 1, the edge of the first N-type doped region 21 away from the second field oxide 12 may be aligned with the corresponding edge of the first field oxide 11 as much as possible. In other examples, as shown in fig. 2, the edge of the first N-type doped region 21 away from the second field oxide 12 may extend beyond the edge of the first field oxide 11, i.e., the first N-type doped region 21 extends into the substrate 10 of the first field oxide 11 and the third field oxide 13.

With continued reference to fig. 1, in this embodiment, a second N-type doped region 22 is further disposed in the substrate 10 below the first N-type heavily doped region 31, one side of the second N-type doped region 22 is connected to the first N-type doped region 21, and the other side extends below the third field oxide 13, so that the second N-type doped region 22 covers the first N-type heavily doped region 31, i.e. covers the drain end of the NLDMOS structure, and the second N-type doped region 22 and the first N-type doped region 21 are used as the drift region of the NLDMOS structure to cover the gate structure and the channel under the first field oxide 11. Specifically, as shown in fig. 2c, the doping depth of the second N-type doped region 22 is smaller than that of the first N-type doped region 21, so that the drift region of the NLDMOS structure has a step structure below the drain, and the second N-type doped region 22 and the first N-type doped region 21 can be completely depleted by the P-type doped region 23 and the substrate 10, thereby improving the breakdown voltage of the NLDMOS structure. In addition, compared to the related art in which an N-type well region is used to cover the channel and the drain as the drift region (as shown in the depletion layer 25' of fig. 1b, the portion of the N-type well region under the drain is not fully depleted), the second N-type doped region 22 and the first N-type doped region 21 are used to form the drift region in this embodiment, so that the breakdown voltage and the on-resistance can be further optimized by adjusting the doping concentrations of the two N-type doped regions.

Example two

The second embodiment provides an NLDMOS structure.

Fig. 3 is a schematic diagram of an NLDMOS structure provided in embodiment two.

As shown in fig. 3, the NLDMOS structure provided in this embodiment is substantially the same as that of the first embodiment, and includes a substrate 10, a gate structure 24, a P-type doped region 23, a first N-type doped region 21, a second N-type doped region 22, and a first N-type heavily doped region 31. A first field oxygen 11 is arranged on the surface of the substrate 10; the gate structure 24 is disposed on the surface of the substrate 10 and covers a portion of the first field oxide 11; the first N-type doped region 21 is disposed in the substrate 10 under the gate structure 24 and encapsulates the first field oxide 11; the P-type doped region 23 is disposed in the substrate 10 on the side of the first N-type doped region 21 away from the first field oxide 11 and extends to below the gate structure 24; the first N-type heavily doped region 31 is disposed in the substrate 10 of the first field oxide 11 far from the gate structure 24; the second N-type doped region 22 is connected to the first N-type doped region 21 and is located on a side of the substrate 10 away from the P-type doped region 23, wherein a doping depth of the second N-type doped region 22 is smaller than a doping depth of the first N-type doped region 21, and at least partially encapsulates the first N-type heavily doped region 31.

The main difference between the NLDMOS structure provided in this embodiment and the structure provided in the first embodiment is that the P-type doped region 23 and the first N-type doped region 21 are not connected, but are spaced apart from each other by a predetermined distance under the gate oxide layer 24a in the second embodiment.

Example III

An embodiment three provides a manufacturing method of the NLDMOS structure.

Fig. 4 is a flowchart of a method for manufacturing an NLDMOS structure provided in the third embodiment.

As shown in fig. 4, the manufacturing method of the NLDMOS structure provided in this embodiment includes:

s01: providing a substrate;

s02: forming a first N-type doped region in the substrate, and forming first field oxygen on the surface of the substrate on the first N-type doped region;

s03: forming a second N-type doped region and a P-type doped region in the substrate at two sides of the first N-type doped region respectively, wherein the second N-type doped region is connected with the first N-type doped region and is positioned at one side of the second N-type doped region close to the first field oxygen, and the doping depth of the second N-type doped region is smaller than that of the first N-type doped region;

s04: forming a gate structure on the substrate, wherein the gate structure is positioned on the P-type doped region, the first N-type doped region and the first field oxide;

s05: and forming a first N-type heavily doped region in the second N-type doped region.

Fig. 5a to 5g are schematic structural views corresponding to the corresponding steps of forming the NLDMOS structure according to the third embodiment, and a method for manufacturing the NLDMOS structure will be described in detail with reference to fig. 5a to 5 g.

First, step S01 is performed, please refer to fig. 5a, to provide a substrate.

Next, step S02 is performed to form a first N-type doped region 21 in the substrate 10, and a first field oxide 11 is formed on the surface of the substrate 10 on the first N-type doped region 21.

Specifically, referring to fig. 5b, a deep N-well process may be used to form the first N-doped region 21 in the substrate 10. The process can comprise the following steps: an ion implantation process is used to implant N-type ions on the substrate 10, and a reheat drive process is used to form an N-type deep well as the first N-type doped region 21.

Referring to fig. 5c, a first field oxide 11, a second field oxide 12 and a third field oxide 13 are formed on the surface of the substrate 10 on the first N-type doped region 21, wherein the first field oxide 11 is disposed on the first N-type doped region 21 and exposes at least a portion of the surface of the first N-type doped region 21, and the second field oxide 12 and the third field oxide 13 are respectively disposed at two sides of the first field oxide 11 at intervals and keep intervals with the first N-type doped region 21. In this example, the edge of the first field oxide 11 may be aligned with one side edge of the first N-type doped region 21 as much as possible; in other examples, the edges of the first field oxide 11 may be located within the first N-type doped region 21, i.e., the edges of the first N-type doped region 21 extend beyond the first field oxide 11.

Next, step S03 is performed, in which a second N-type doped region 22 and a P-type doped region 23 are formed in the substrate 10 at both sides of the first N-type doped region 21, the second N-type doped region 22 is connected to the first N-type doped region 21 and is located at a side of the second N-type doped region 22 close to the first field oxide 11, and the doping depth of the second N-type doped region 22 is smaller than that of the first N-type doped region 21.

Specifically, referring to fig. 5d, a first patterned mask (not shown) is formed to expose the surface of the substrate 10 between the third field oxide 13 and the first N-type doped region 21, and an ion implantation process is performed to implant N-type ions to form a second N-type doped region 22. In this embodiment, since one side edge of the first N-type doped region 21 is aligned with the first field oxide 11, the first patterned mask may expose the surface of the substrate 10 between the first field oxide 11 and the third field oxide 13. The ion implantation depth (junction depth, doping depth) of the second N-type doped region 22 is smaller than that of the first N-type doped region 21, and the edge of the second N-type doped region 22 is located below the third field oxide 13 by adjusting the ion implantation angle (tilt), and the other edge of the second N-type doped region 22 is connected with the first N-type doped region 21.

Referring to fig. 5e, a second patterned mask (not shown) is formed to expose the surface of the substrate 10 on both sides of the second field oxide 12, and an ion implantation process is performed to implant P-type ions to form P-type doped regions 23. In this example, the edge of the second patterned mask near the opening of the first field oxide 11 may be aligned with the edge of the first N-type doped region 21 as much as possible so that the P-type doped region 23 meets the first N-type doped region 21. In other examples, the edge of the second patterned mask near the opening of the first field oxide 11 may exceed the edge of the first N-type doped region 21, i.e., the second patterned mask completely covers the first N-type doped region 21, such that the P-type doped region 23 is spaced apart from the first N-type doped region 21 by a predetermined distance. The P-type doped region 23 may be formed by multiple ion implantations, including multi-angle angled ion implantations, such that doped regions under both sides of the second field oxide 12 communicate with doped regions under the second field oxide 12.

It should be noted that, in other examples of the present embodiment, the P-type doped region 23 may be formed in the substrate 10 first, and then the second N-type doped region 22 may be formed, which is not limited by the forming sequence and the forming method of the two.

Next, step S04 is performed, referring to fig. 5f, a gate structure 24 is formed on the substrate 10, which is located on the P-type doped region 23, the first N-type doped region 21 and the first field oxide 11.

A gate oxide layer 24a may be formed to cover a portion of the substrate 10 between the second field oxide 12 and the first field oxide 11 and extend to cover a portion of the first field oxide 11, i.e., to cover a portion of the P-type doped region 23, a portion of the first N-type doped region 21, and a portion of the surface of the first field oxide 11, and then a gate material layer 24b (e.g., polysilicon material) may be formed on the gate oxide layer 24 a. Of course, the material of the gate oxide layer 24a is similar to that of the first field oxide 11, and it is also possible to not provide the gate oxide layer 24a on the first field oxide 11.

Next, step S05 is performed, referring to fig. 5g, a first heavily N-doped region 31 is formed in the second heavily N-doped region 22.

The first N-type heavily doped region 31 and the second N-type heavily doped region 32 can be formed simultaneously between the substrate 10 of the second N-type doped region 22 and the substrate 10 between the first field oxide 11 and the gate structure 24 by source-drain ion implantation (N-type ion heavy doping) to serve as a drain and a source.

In addition, a P-type heavily doped region 33 is formed in the P-type doped region 23 at a side of the second field oxide 12 far from the second N-type heavily doped region 32 for electrically leading out the P-type doped region 23 and the substrate 10 as a body terminal, then an interlayer dielectric layer is formed to cover the surface of the substrate 10, a plurality of contact holes are formed in the interlayer dielectric layer to expose the first N-type heavily doped region 31, the second N-type heavily doped region 32 and the P-type heavily doped region 33, plugs are formed in the contact holes, and metal electrodes 42 are formed on the plugs for electrically leading out the NLDMOS structure.

Example IV

The fourth embodiment provides a semiconductor device.

The semiconductor device provided in the fourth embodiment may be a composite device including a device structure having a plurality of functions, for example, a logic device structure, a power device structure, a memory device structure, and the like. The semiconductor device provided in this embodiment may include the NLDMOS structure described above as a power device structure or one of the power device structures therein. Specifically, referring to fig. 1, the NLDMOS structure may include a substrate 10, a gate structure 24, a P-type doped region 23, a first N-type doped region 21, a second N-type doped region 22, and a first N-type heavily doped region 31. A first field oxygen 11 is arranged on the surface of the substrate 10; the gate structure 24 is disposed on the surface of the substrate 10 and covers a portion of the first field oxide 11; the first N-type doped region 21 is disposed in the substrate 10 under the gate structure 24 and encapsulates the first field oxide 11; the P-type doped region 23 is disposed in the substrate 10 on the side of the first N-type doped region 21 away from the first field oxide 11 and extends to below the gate structure 24; the first N-type heavily doped region 31 is disposed in the substrate 10 of the first field oxide 11 far from the gate structure 24; the second N-type doped region 22 is connected to the first N-type doped region 21 and is located on a side of the substrate 10 away from the P-type doped region 23, wherein a doping depth of the second N-type doped region 22 is smaller than a doping depth of the first N-type doped region 21, and at least partially encapsulates the first N-type heavily doped region 31.

In summary, in the present invention, the second N-type doped region is disposed in the substrate below the first N-type heavily doped region, and the second N-type doped region is connected to the first N-type doped region, and the second N-type doped region and the first N-type doped region are used as the drift region of the NLDMOS structure to cover the gate structure and the substrate (conductive and drain) under the first field oxygen, wherein the doping depth of the second N-type doped region is smaller than that of the first N-type doped region, so that the drift region of the NLDMOS structure has a step structure below the drain, thereby enabling the second N-type doped region and the first N-type doped region to be completely depleted by the P-type doped region and the substrate, and further improving the breakdown voltage of the NLDMOS structure. In addition, compared with the prior art that an N-type doped region is used for cladding the channel and the drain end as the drift region, the drift region is formed by the second N-type doped region and the first N-type doped region, and the breakdown voltage and the on-resistance can be further optimized by adjusting the doping concentrations of the two N-type doped regions.

The above description is only illustrative of the preferred embodiments of the present invention and is not intended to limit the scope of the present invention, and any alterations and modifications made by those skilled in the art based on the above disclosure shall fall within the scope of the appended claims.

Claims (10)

1. An NLDMOS structure, comprising:

a substrate, the surface of which is provided with a first field oxygen;

the grid structure is arranged on the substrate and covers part of the first field oxygen;

the first N-type doped region is arranged in the substrate below the grid structure and coats the first field oxide;

the P-type doped region is arranged in the substrate at one side of the first N-type doped region, which is far away from the first field oxide, and extends to the lower part of the grid structure;

the first N-type heavily doped region is arranged in the substrate of the first field oxide far away from the grid structure;

the second N-type doped region is connected with the first N-type doped region and is positioned on one side of the substrate far away from the P-type doped region, wherein the doping depth of the second N-type doped region is smaller than that of the first N-type doped region, and at least partially coats the first N-type heavily doped region.

2. The NLDMOS structure of claim 1, wherein a second field oxide is further formed on a surface of the substrate above the P-type doped region, a second N-type heavily doped region is disposed on a side of the second field oxide adjacent to the first field oxide, a P-type heavily doped region is disposed on a side of the second field oxide away from the first field oxide, and the P-type heavily doped region encapsulates the second N-type heavily doped region and the P-type heavily doped region.

3. The NLDMOS structure of claim 1 or 2, further comprising a third field oxide, wherein the first N-type heavily doped region is disposed in the substrate between the first field oxide and the third field oxide, on a surface of the substrate on a side of the first field oxide remote from the second field oxide.

4. The NLDMOS structure of claim 1, wherein a side edge of the first N-type doped region remote from the gate structure is aligned with a corresponding edge of the second field oxide, the second N-type doped region surrounding the first N-type heavily doped region.

5. The NLDMOS structure of claim 1, wherein a side edge of the first N-type doped region remote from the gate structure exceeds a corresponding edge of the second field oxide, the second N-type doped region and the first N-type doped region surrounding the first N-type heavily doped region.

6. The NLDMOS structure of claim 1, wherein the P-type doped region and the first N-type doped region are disposed in abutment or in spaced relation.

7. The NLDMOS structure of claim 1, wherein a doping depth of the first N-type doped region is greater than a doping depth of the P-type doped region.

8. A method of manufacturing an NLDMOS structure, comprising:

providing a substrate;

forming a first N-type doped region in the substrate, and forming first field oxygen on the surface of the substrate on the first N-type doped region;

forming a second N-type doped region and a P-type doped region in the substrate at two sides of the first N-type doped region respectively, wherein the second N-type doped region is connected with the first N-type doped region and is positioned at one side of the second N-type doped region close to the first field oxygen, and the doping depth of the second N-type doped region is smaller than that of the first N-type doped region;

forming a gate structure on the substrate, wherein the gate structure is positioned on the P-type doped region, the first N-type doped region and the first field oxide;

and forming a first N-type heavily doped region in the second N-type doped region.

9. The method of manufacturing the NLDMOS structure of claim 8, wherein the first N-type doped region is formed using a deep well process.

10. A semiconductor device comprising an NLDMOS structure, the NLDMOS structure comprising:

a substrate, the surface of which is provided with a first field oxygen;

the grid structure is arranged on the substrate and covers part of the first field oxygen;

the first N-type doped region is arranged in the substrate below the grid structure and coats the first field oxide;

the P-type doped region is arranged in the substrate at one side of the first N-type doped region, which is far away from the first field oxide, and extends to the lower part of the grid structure;

the first N-type heavily doped region is arranged in the substrate of the first field oxide far away from the grid structure;

the second N-type doped region is connected with the first N-type doped region and is positioned on one side of the substrate far away from the P-type doped region, wherein the doping depth of the second N-type doped region is smaller than that of the first N-type doped region, and at least partially coats the first N-type heavily doped region.