CN117198350A

CN117198350A - Control circuit, control method and related equipment of memory chip

Info

Publication number: CN117198350A
Application number: CN202210615322.1A
Authority: CN
Inventors: 拜福君
Original assignee: Xian Unilc Semiconductors Co Ltd
Current assignee: Xian Unilc Semiconductors Co Ltd
Priority date: 2022-05-31
Filing date: 2022-05-31
Publication date: 2023-12-08

Abstract

The invention discloses a control circuit, a control method and equipment of a memory chip. The control circuit includes: at least two array selection modules and at least two decoders; each array selection module is connected with the corresponding decoder, and the array selection module is connected with the adjacent array selection module on at least one side of the decoder; the array selection module is used for generating an enabling signal for activating the decoder according to the array selection signal and the storage mode selection signal; the decoder is used for receiving the enabling signal and the row address signal and decoding the row address signal under the control of the enabling signal so as to determine a target word line. The common storage mode can fully utilize the storage unit to increase the capacity, and the differential storage mode has higher storage speed, so that the storage mode of the storage space of the storage chip can be flexibly switched based on the requirement of a user, and the requirement of the user on the storage space and the storage speed is met.

Description

Control circuit, control method and related equipment of memory chip

Technical Field

The present disclosure relates to the field of chip technologies, and in particular, to a control circuit, a control method, and related devices for a memory chip.

Background

Not only is a significant computational requirement required to achieve high performance computing, but also a significant data storage and throughput requirement is required. However, the gap between processor performance and memory access bandwidth and latency is increasing, and is one of the main factors limiting computational performance. This imbalance of memory's ability to provide data and processor computing power is also referred to as a "memory wall".

Currently, eliminating "memory walls" is mainly used to increase the data-providing capacity of the entire memory by increasing the data bandwidth of each memory chip or reducing the data delay of the memory cells in the memory chip. The method of increasing the bandwidth has the disadvantage that only data access to consecutive addresses is effective. The method for reducing the data delay is to search the low-delay storage space in the memory or improve the structure of the chip, and the method for searching the low-delay storage space in the memory is greatly influenced by environment and is complex to control; the way to improve the chip structure increases the process difficulty and reduces the memory capacity.

Disclosure of Invention

In the summary, a series of concepts in a simplified form are introduced, which will be further described in detail in the detailed description. The summary of the invention is not intended to define the key features and essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.

In order to find a reasonable and simple way to effectively eliminate the "memory wall", the first aspect of the present invention proposes a control circuit of a memory chip, which comprises:

at least two array selection modules and at least two decoders;

each array selection module is connected with the corresponding decoder, and the array selection module is connected with the adjacent array selection module on at least one side of the decoder;

the array selection module is used for generating an enabling signal for activating the decoder according to the array selection signal and the storage mode selection signal;

the decoder is used for receiving the enabling signal and the row address signal, and decoding the row address signal under the control of the enabling signal so as to determine a target word line.

Optionally, the decoder includes: first decoders, each of which shares the same address signal;

the row address signal includes a row address first signal;

the first decoder is configured to receive an enable signal and a row address first signal to generate a target word line first address, and the target word line first address is used to determine the target word line.

Optionally, the decoder further includes: at least one word line driving module and a second decoder;

The word line driving module is connected with the first decoder corresponding to the word line driving module; the row address signals further include a row address second signal;

the second decoder is configured to generate a target word line second address according to a row address second signal, where the target word line second address is used to determine the target word line;

the second address of the target word line is shared among the word line driving modules;

the word line driving module is used for determining and activating the target word line according to the target word line first address and the target word line second address.

Optionally, the storage mode selection signal includes: the indication storage mode is a differential storage mode or an indication storage mode is a common storage mode, and the differential storage mode is used for simultaneously starting a plurality of decoders.

In a second aspect, the present invention further proposes a control method of a memory chip, for a control circuit according to any one of the first aspect, including:

an array selection module is adopted to generate an enabling signal for activating a decoder according to an array selection signal and a storage mode selection signal;

the decoder receives the enable signal and the row address signal and decodes the row address signal according to the enable signal to determine a target word line.

Optionally, the storage mode selection signal includes a signal indicating that the storage mode is a differential storage mode;

the method comprises the following steps:

the array selection module sends the array selection signal to other array selection modules, and the array selection module and the other array selection modules are a group of array selection modules for differentially storing data;

each of the decoders receives an enable signal and a row address signal to determine a target word line, the enable signal including a signal for activating the decoder transmitted by the array selection module corresponding to each of the decoders.

Optionally, the method further comprises:

determining a word line corresponding to the row address signal and N adjacent word lines as a second target word line;

activating the second target word line;

and controlling N second sense amplifier arrays between the storage units connected with the second target word line and the second target word line to process data in a differential storage mode.

In a third aspect, the present invention also proposes a three-dimensional chip comprising: a control circuit as claimed in any one of the preceding aspects.

In a fourth aspect, the present invention also proposes an electronic device, including: the three-dimensional chip as recited in the third aspect.

In a fifth aspect, an electronic system includes: a memory, a processor and a computer program stored in the memory and executable on the processor, wherein the processor is configured to implement the steps of the control method of the memory chip according to any one of the second aspects when executing the computer program stored in the memory.

In summary, the control circuit of the memory chip provided by the embodiment of the application comprises at least two array selection modules and at least two decoders, wherein each array selection module is connected with a decoder corresponding to the corresponding array selection module, the array selection module is connected with an array selection module adjacent to at least one side of the array selection module, the array selection module generates an enabling signal for activating the decoder according to an array selection signal and a storage mode selection signal, the decoder receives the enabling signal and an address signal, decodes a row address signal according to the enabling signal to determine a target word line, activates a corresponding target word line, and controls the memory chip to store data in a storage mode corresponding to the storage mode selection signal. The common storage mode can fully utilize the storage unit to increase the capacity, and the differential storage mode has higher storage speed, so that the storage mode of the storage space of the storage chip can be flexibly switched based on the requirement of a user, and the requirement of the user on the storage space and the storage speed is met.

Additional advantages, objects, and features of the application will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the application.

Drawings

Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the specification. Also, like reference numerals are used to designate like parts throughout the figures. In the drawings:

FIG. 1 is a schematic diagram of a control circuit structure of a memory chip according to an embodiment of the present application;

FIG. 2 is a schematic diagram of a control principle of a memory chip according to an embodiment of the present application;

FIG. 3 is a schematic diagram of a partition mode of a memory chip according to an embodiment of the present application;

fig. 4 is a schematic diagram of a first signal sharing principle of a row address according to an embodiment of the present application;

FIG. 5 is a schematic diagram of another first signal sharing principle of a row address according to an embodiment of the present application;

FIG. 6 is a schematic diagram of a control circuit of another memory chip according to an embodiment of the present application;

FIG. 7 is a schematic diagram of a memory chip according to an embodiment of the present application;

FIG. 8 is a schematic flow chart of a control method of a memory chip according to an embodiment of the present application;

FIG. 9 is a schematic diagram of a three-dimensional chip structure according to an embodiment of the present application;

fig. 10 is a schematic structural diagram of an electronic device according to an embodiment of the present application;

fig. 11 is a schematic structural diagram of an electronic system according to an embodiment of the present application.

Detailed Description

The control circuit of the memory chip comprises at least two array selection modules and at least two decoders, wherein each array selection module is connected with the corresponding decoder, the array selection module is connected with the adjacent array selection module on at least one side of the array selection module, the array selection module generates an enabling signal for activating the decoder according to the array selection signal and the storage mode selection signal, the decoder receives the enabling signal and the address signal, decodes the row address signal according to the enabling signal to determine a target word line, activates the corresponding target word line, and controls the memory chip to store data in the storage mode corresponding to the storage mode selection signal. The common storage mode can fully utilize the storage unit to increase the capacity, and the differential storage mode has higher storage speed, so that the storage mode of the storage space of the storage chip can be flexibly switched based on the requirement of a user, and the requirement of the user on the storage space and the storage speed is met.

The terms "first," "second," "third," "fourth" and the like in the description and in the claims and in the above drawings, if any, are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments described herein may be implemented in other sequences than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus. The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments.

In a first aspect, referring to fig. 1, a schematic diagram of a control circuit of a memory chip according to an embodiment of the present application is provided, which specifically may include:

At least two array selection modules and at least two decoders;

the decoder is used for receiving the enabling signal and the address signal, and decoding the row address signal under the control of the enabling signal so as to determine a target word line.

In some examples, not only is significant computational demand required to achieve high performance computing, but also significant data storage and throughput requirements are required. However, the gap between processor performance and memory access bandwidth and latency is increasing, and is one of the main factors limiting computational performance. This imbalance of memory's ability to provide data and processor computing power is also referred to as a "memory wall".

It is understood that the CPU (Central Processing Unit ) communicates with the memory through a Controller. Multiple memory channels are generally provided for the CPU to access simultaneously, so that the data access efficiency is improved at the system layer. Each Channel further includes a plurality of ranks (memory banks), each Rank is composed of a plurality of memory chips (chips), each Chip includes a plurality of memory Array (Array) and SA (Sense Amplifier) Array, each memory Array includes a plurality of memory cells (cells), the memory cells are determined by WL (Word Line) and BL (Base Line) in the memory Array, one memory Cell is located at an intersection of each WL and BL, and each memory Cell is connected to one SA (Sense Amplifier) by BL.

To eliminate "memory walls," the data-providing capability of the overall memory can be improved by increasing the data bandwidth per Chip or reducing the data delay. In some cases, the gap between the two is mainly made up by increasing the data bandwidth of the memory interface, which has the disadvantage that only data access to consecutive addresses is effective. In contrast, the data access bottleneck of the random address is mainly the delay of the memory, and for the random address access situation, the existing high-speed interface technology cannot obtain obvious improvement of data throughput efficiency.

In other cases, the low-latency memory space in the existing memory is searched through a special test step, and the low-latency memory space is utilized to realize quick reading. There are still some problems with this approach: first, the testing of the memory takes additional test time. Secondly, the test result is affected by factors such as temperature, voltage, data topology and the like, the found low-delay storage space cannot completely guarantee reliability, and compatibility problems exist between partitions and repair (repair) and Address (Address) and Data mapping (Data mapping) of the memory. Finally, the low-latency memory space and other spaces require different access latencies, which results in different access latencies being required for memory access according to the location of the accessed data, which increases the design difficulty and cost of the controller.

In still other cases, memory latency is reduced by improving the memory Array structure at the cost of increased memory process difficulty, area, power consumption, and the like. The storage Array is the most sensitive part of the memory to the process and the area, and the modification of the storage Array can increase the process difficulty and the chip area. In order to match the modified storage Array, the peripheral circuit needs to be correspondingly modified, so that the chip area and the power consumption are increased. In short, modifying the array structure increases the area of the memory and the difficulty of the array process, correspondingly reduces the capacity of the memory, and increases the cost of the memory. And all changes to the modified memory are cured without flexibility.

In order to solve the possible problems in the foregoing, an embodiment of the present application proposes a control circuit of a memory chip, as shown in fig. 1, including at least two array selection modules and at least two decoders, where each array selection module is connected to its own corresponding decoder, the array selection module is connected to its at least one side adjacent array selection module, the array selection module generates an enable signal for activating the decoder according to the array selection signal and the storage mode selection signal, the decoder receives the enable signal and the address signal, decodes the row address signal according to the enable signal to determine a target word line, activates the corresponding target word line, and controls the memory chip to store data in a storage mode corresponding to the storage mode selection signal. The storage mode selection signal is a storage mode for switching the storage unit corresponding to the target word line, and the storage mode may include a differential storage mode and a normal storage mode. The enabling signals formed by the different storage mode selection signals after passing through the array selection module are different, and the decoder can distinguish the storage modes corresponding to the different storage mode selection signals, so that the row address signals are decoded according to the enabling signals, and the target word line in the corresponding storage mode is determined.

In some examples, as shown in fig. 2, a schematic structure of a memory chip is illustrated, where a plurality of memory cells are included in a memory Array1, a memory Array2 and a memory Array3, for illustrating that only memory cells with reference numbers of C10, C11, C20, C21, C30 and C31 are listed, each memory Array further includes a plurality of WLs, for illustrating that only three WLs of WL0, WL1 and WL2 are listed, and also includes a plurality of SAs in SA0, SA1, SA2 and SA3, the number of SAs in each SA Array (any one of SA0, SA1, SA2 and SA3 can be regarded as an Array made up of a plurality of SAs) is one half of the number of the memory cells on each word Line, and the SAs in the SA arrays adjacent to each other are sequentially connected at intervals through BL, and the structure of the memory chip is also referred to as an Open-BL (Open bit Line) structure.

In some examples, as shown in fig. 2, only one WL is the target word line in performing the normal memory mode, if the target word line determined by the decoder is WL1, WL1 is the word line in the memory Array2, the WL1 word line is activated, and two SA arrays (SA 1 and SA 2) adjacent to WL1 are activated. When the reading operation is performed, SA2 reads data in C20 through BL and transmits the data to a peripheral circuit through a data transmission line to realize the data reading in C20; in performing the write operation, SA2 reads the external data transferred by the data transfer line, and writes the external data in C20 through BL to complete the write operation. Similarly, the C21 completes the writing and reading of data together with the SA1 connected thereto. When WL0 or WL2 is selected as the target word line, the operations of storing data and reading are similar to the above method and will not be described herein. Each memory Cell can independently store 1bit of data through a common memory mode, 6 bits of data can be stored by taking the example shown in fig. 2 as an example, and the memory space of the memory Cell can be fully utilized through the common memory mode, but the read-write speed is poor.

In some examples, as shown in fig. 2, when the differential storage mode is performed, a plurality of word lines are selected by the target word line selection unit to be activated according to the word line selection information and the storage mode configuration information, the corresponding word line is determined to be WL1 according to the word line selection information, and the storage mode is acquired according to the storage mode configuration information, so that WL0 and WL1 can be determined to be the target word lines, or WL1 and WL2 can be determined to be the target word lines, and WL0 and WL1 are taken as target word lines as an example, when the differential storage mode is performed, information is stored by using two storage cells in complementary states (C10 is state 1, C21 is state 0). The redundant storage mode has various advantages, high storage reliability and high information access performance. In the normal storage mode, since only a single storage Cell stores information, the voltage (Vbl) of the BL needs to be compared with the reference voltage (Vblh/2) in data reading, if Vbl is higher than the reference voltage, the data 1 is represented, otherwise the data 0 is represented; in the differential memory mode, no additional reference voltage is needed in data reading, and only the BL1 voltage of C10 and the BL2 voltage of C21 respectively connected to two complementary state memory cells are required to be compared. If the BL1 voltage is higher than the BL2 voltage, it represents data 1, otherwise it represents data 0. In contrast, during SA operation, the differential storage mode can provide a larger initial voltage difference, that is, a shorter time is required for the differential structure when the same initial voltage difference is obtained, so that a faster data storage speed can be obtained. Although the differential memory method uses the differential between the C10 and C21 with inconsistent states to perform data writing and reading, the speed of writing and reading is increased, but since the two memory cells store 1bit of data, the memory capacity is reduced, and at the same time, the memory cells at both ends have wasteful phenomena, such as (C20 and C11). Of course, a plurality of target word lines may be activated, and differential storage is adopted, for example, WL0, WL1 and WL2 may be activated simultaneously in fig. 2, C10 and C21 store 1bit of data in a differential manner, and C20 and C31 store 1bit of data in a differential manner. According to the embodiment, when two target WLs are selected, 4 storage cells can store 1bit of data, 2 storage Cell spaces are wasted, and when 3 target WLs are selected, 6 cells can store 2 bits of data, and 2 storage Cell spaces are wasted, so that the more WLs are activated simultaneously, the more data are stored simultaneously, the less space waste is caused, but when N WLs are activated simultaneously, N-1 SA arrays in the middle of the N WLs need to be simultaneously operated, and the maximum number of simultaneous operation of the SA arrays is limited by a chip structure. Therefore, users and developers can reasonably select the N value according to the chip structure, and the requirements of meeting the storage requirement and wasting the storage space as little as possible are met.

According to the control circuit based on the memory chip, the memory mode for storing the Array can be flexibly switched according to the Array selection signal, the memory mode selection signal and the address signal, namely, the duty ratio of the differential memory mode and the common memory mode can be dynamically adjusted, so that the memory space can be flexibly configured according to the use requirement of a user. Taking fig. 3 as an example, a memory chip with 9 memory arrays is shown, the memory arrays can be divided into a differential memory Array, a normal memory Array and an edge memory Array, the differential memory Array, that is, internal memory cells, all store data in a differential manner and have no memory Cell waste, the normal memory Array, that is, internal memory cells, all store data in a normal manner and have no memory Cell waste, and the edge memory Array refers to the phenomenon that internal memory cells store data in a normal manner or in a differential manner and have memory Cell waste. The memory chip can adopt three partition modes (namely a partition mode A, a partition mode B and a partition mode C, which can also adopt other modes, and the partition mode A is just for illustration, wherein the partition mode A adopts a common memory mode for the memory chip, two edge arrays can be equivalent to a common memory module, each other common memory Array and two SA arrays adjacent to the other common memory arrays form a common memory module, the partition mode A totally has 0-7 total 8 memory modules, because of the common memory mode, each memory Cell can store 1bit of data, and the capacity corresponding to the memory mode A is the largest. In order to reduce delay and improve storage speed, the above chip control circuit can be used to partition the storage chip again in partition mode a, and can be switched to partition mode B or partition mode C, where the partition modes of the differential storage modules in partition modes B and C are used to select three target WLs as the basis of the partition of the differential storage modules, that is, two edge arrays, one differential storage Array and two SA arrays in the middle form one differential storage module. The partition mode B is seen to include 2 differential memory modules (0 and 1) and 2 normal memory modules (2 and 3), and the partition mode C includes 3 differential memory modules (0, 1 and 2). Therefore, a user can flexibly adjust the storage mode of the internal storage space of the storage chip through the control circuit of the storage chip according to the use requirement, so that the storage mode meets the requirement of the storage capacity and the storage speed of the user.

In summary, the control circuit of the memory chip provided by the application comprises at least two array selection modules and at least two decoders, wherein each array selection module is connected with a decoder corresponding to the corresponding array selection module, the array selection module is connected with an array selection module adjacent to at least one side of the array selection module, the array selection module generates an enabling signal for activating the decoder according to an array selection signal and a storage mode selection signal, the decoder receives the enabling signal and an address signal, decodes a row address signal according to the enabling signal to determine a target word line, activates a corresponding target word line, and controls the memory chip to store data in a storage mode corresponding to the storage mode selection signal. The common storage mode can fully utilize the storage unit to increase the capacity, and the differential storage mode has higher storage speed, so that the storage mode of the storage space of the storage chip can be flexibly switched based on the requirement of a user, and the requirement of the user on the storage space and the storage speed is met.

In some examples, the decoder includes: first decoders, each of which shares the same address signal;

the row address signal includes a row address first signal;

The decoder includes a first decoder, and the plurality of decoders corresponds to the plurality of first decoders, and the first decoder is configured to receive the enable signal and the row address first signal to generate a target word line first address, and the target word line first address is configured to determine a target word line. The decoder is a multiple-input multiple-output (mimo) combinational logic circuit device, and the decoding is the inverse of the encoding, and each binary code is "translated" by row address selection information corresponding to a target word line address through a specific meaning of the decoder code state during encoding, which is called decoding. The decoder can calculate the target word line addresses according to the decoding rules by using the row address selection information, so that the purpose that fewer row address selection information is changed into more target word line addresses is achieved. It should be noted that, each first decoder shares the same address signal, the manner of sharing the address signal may be that the row address signal is input to any one first decoder (without limiting the input to the first decoder a), each decoder is connected by a line, and the row address first signal is shared by the line; the manner of sharing the address signal may be such that the plurality of first decoders share the input terminal of the row address first signal, as shown in fig. 5.

In some examples, the decoder further includes: at least one word line driving module and a second decoder;

By way of example, the operation of changing less row address selection information to more target word line addresses can be achieved by a combination of at least two decoders (a first decoder and a second decoder), thereby simplifying the complexity of the control method by means of a simple hardware combination. The second decoder is used for generating a target word line second address according to the row address second signal, the decoder further comprises at least one word line driving module, the word line driving module is connected with all WLs in the same storage Array, the word line driving module determines a target word line according to the target word line first address and the target word line second address, and the target WL is activated, so that a storage Cell connected to the target WL can execute read-write operation.

In some examples, the storage mode selection signal includes: the indication storage mode is a differential storage mode or an indication storage mode is a common storage mode, and the differential storage mode is used for simultaneously starting a plurality of decoders.

The memory mode selection signal includes a signal indicating that the memory mode is a differential memory mode or a signal indicating that the memory mode is a normal memory mode, the enable signals formed by the different memory mode selection signals after passing through the array selection module are different, and the decoder can distinguish the memory modes corresponding to the different memory mode selection signals, so that the row address signal is decoded according to the enable signals, and a target word line in the corresponding memory mode is determined.

In some examples, as shown in fig. 6, when selecting the Array storage mode stored in the memory chip, the Array selection module determines which arrays are target arrays according to the Array selection signal, and the Array selection module also selects according to the storage modeThe decoder of the embodiment includes a first decoder, a second decoder and a word line driving module, where the first decoder corresponding to the target array generates a first address of a target word line according to the enable signal and a first signal of a row address, the second decoder generates a second address of the target word line according to a second signal of the row address, and the word line driving module determines and activates the target word line according to the first address of the target word line and the second address of the target word line to complete an operation of selecting data of the storage mode corresponding to the signal of the storage mode. The decoding process of the row address is divided into two steps, the first step is binary decoding of the first decoder and the second decoder, namely: the first decoder decodes the RA1 6-bit address into 2 for a binary decoder ⁶ The target word line first address of=64 bits, the second decoder decodes the three-bit address of RA2 to 2 ³ A target word line second address of 8 bits; the second step is the multiplication decoding of the word line driving module, and the received 64-bit target word line first address and the 8-bit target word line second address are decoded into 64×8=512-bit addresses, so that the purpose that less row address selection information is changed into more target word line addresses can be achieved.

By the memory chip control circuit shown in fig. 6, the memory mode of the memory space of the chip can be flexibly switched based on the user demand, so as to meet the user demand on the memory space and the memory speed. And can be changed to a more target word line address by less row address selection information.

The storage mode selection information described in the present application can be set by the user through a specific memory command. As shown in fig. 7, taking a DRAM memory chip as an example, this is a schematic diagram of a DRAM memory chip structure in which storage mode selection information is set by a memory command. The memory chip receives a specific Command (CMD) and stores the received storage mode selection signal in the register module through the IO module. In this example there are 8 independent storage arrays, all of which can configure independent storage mode selection information from the register module. This can be achieved in two ways:

In one aspect, a DRAM memory has a dedicated mode register configuration command (MRS) to configure a particular register. In addition to registers that are already occupied by the interface protocol, the present application uses unoccupied registers as inputs to the configuration signals. The advantage of this approach is that the MRS command itself is a legal command.

In the second method, the data writing of the memory chip needs to provide an address, and generally does not respond to the access of the illegal address to the memory chip. The present application can use one or a plurality of illegal addresses which are prescribed in advance as input addresses of a storage mode selection signal. When the storage mode selection signal is required to be changed, the data writing is performed on the address. The access to the illegal address does not affect the normal data access, and only the internal storage mode selection signal of the memory chip is changed. The advantage of this approach is that more configuration information can be supported.

In a second aspect, the present application further proposes a control method of a memory chip, as shown in fig. 8, for a control circuit according to any one of the above-mentioned first aspect, including:

s810, generating an enabling signal for activating a decoder by adopting an array selection module according to an array selection signal and a storage mode selection signal;

The storage mode selection signal is issued by a user, and may include a signal indicating that the storage mode is a differential storage mode and a signal indicating that the storage mode is a normal storage mode, and the Array selection unit generates an enable signal after receiving the Array selection signal and the storage mode selection signal, where the enable signal can be used to activate a decoder corresponding to the target Array;

s820, a decoder receives the enable signal and the row address signal and decodes the row address signal according to the enable signal to determine a target word line

In an exemplary embodiment, the plurality of decoders receives an enable signal and a row address signal, each decoder shares a same row address signal, the decoders receive the enable signal and the address signal, and decode the row address signal according to the enable signal to determine a target word line, and after the target word line is determined, the corresponding target word line may be activated, and the memory chip is controlled to store data in a memory manner corresponding to the memory manner selection signal.

In summary, by using the method provided by the embodiment of the application, the storage mode of the storage space of the storage chip can be flexibly switched based on the user requirement by the control circuit, the advantages of improving the capacity of the storage unit and the advantage of higher storage speed of the differential storage mode can be fully utilized by fully playing the common storage mode according to the configuration of the user, and the requirements of the user on the storage space and the storage speed are met.

In some examples, the storage mode selection signal includes a signal indicating that the storage mode is a differential storage mode;

the method comprises the following steps:

In some examples, when one array selection module receives an array selection signal and the signal in the differential storage mode, the array selection module that receives the array selection signal shares the array selection signal with other array selection modules in the same group for differentially storing data. The array selection module generates an enabling signal after receiving the array selection signal, and sends the enabling signal to a decoder corresponding to the array selection module, and the decoder is started based on the enabling signal and determines a target word line according to the row address signal.

If the storage system signal is the signal indicating that the storage system is the differential storage system, as shown in fig. 2, for example: when the differential memory method is executed, the target word line selection unit uses the word lines corresponding to the word line selection information as WL1 and the word lines adjacent to WL1 as WLO and WL2, so that WL0 and WL1 can be determined as the first target word line or WL1 and WL2 can be determined as the first target word line, and when the differential memory method is adopted, the data writing and reading are performed by using the differences of C10 and C21 with inconsistent states, and the reading and writing speed is increased.

In summary, when the storage mode signal indicates that the storage mode is the differential storage mode, the control circuit may determine the first target word lines according to the array selection signal, the storage mode selection signal, and the row address, and control the first sense amplifier arrays between the first target word lines to store data in the differential storage mode, so that the memory Cell may rapidly read the data based on the control of the user.

In some examples, the above method further comprises:

Activating the second target word line;

In some examples, according to the above embodiment, when two target WLs are selected, 4 storage cells can store 1bit of data, 2 storage Cell spaces are wasted, and when 3 target WLs are selected, 6 cells can store 2 bits of data, and 2 storage Cell spaces are wasted, so that the more WLs are activated simultaneously, the more data are stored simultaneously, the less space waste is caused, but when n+1 WLs are activated simultaneously, N SA arrays in the middle of n+1 WLs need to be simultaneously operated, and the maximum number of SA arrays to be simultaneously operated is limited by the chip structure. Therefore, users and developers can reasonably select the N value according to the chip structure, so that the requirements of meeting the storage requirement and wasting the storage space as little as possible can be met.

In summary, the user and the developer can reasonably select the N value according to the chip structure, determine the word line corresponding to the word line selection information and the adjacent N word lines thereof as the second target word line by adopting the target word line selection unit, activate the second target word line, and control the N second sense amplifier arrays between the memory cell connected with the second target word line and the second target word line to store data in a differential memory mode by using the memory mode selection unit, so that the memory requirement can be met, and the requirement of wasting the memory space as little as possible can be realized.

In some examples, the storage mode selection signal further includes an indication that the storage mode is a normal storage mode;

the method further comprises the following steps:

determining a word line corresponding to the row address signal as the third target word line;

activating the third target word line;

and controlling the memory cells connected with the third target word line and the two third sense amplifier arrays adjacent to the third target word line to store data in the common memory mode.

In some examples, in the case where the storage mode selection signal indicates that the storage mode is the normal storage mode, as shown in fig. 2, only one WL is the target word line, that is, the word line corresponding to the word line selection information is the third target word line when the normal storage mode is performed. If the third target word line after the enable signal and the row address signal are decoded is WL1, WL1 is the word line in the memory Array2, the WL1 word line is activated, and two SA arrays (SA 1 and SA 2) adjacent to WL1 are activated. When the reading operation is performed, SA2 reads data in C20 through BL and transmits the data to a peripheral circuit through a data transmission line to realize the data reading in C20; at the time of the write operation, SA2 reads the external data transferred by the data transfer line, and writes in C20 through BL to complete the write operation. Similarly, the C21 completes the writing and reading of data together with the SA1 connected thereto. When the common storage mode is adopted, each storage Cell can store 1bit of data respectively, and the storage space of the storage Cell can be fully utilized.

In summary, when the storage mode selection signal indicates that the storage mode is the normal storage mode, the control circuit may determine the third target word line according to the array selection signal, the storage mode selection signal, and the row address, and control two third sense amplifier arrays adjacent to the third target word line to store data in the normal storage mode, and based on the control of the user, make full use of the storage space of the storage Cell.

In a third aspect, the present invention further provides a three-dimensional chip, as shown in fig. 9, including: a control circuit as claimed in any one of the first aspects.

Such a three-dimensional chip comprises the control circuit of any one of the first aspects, the control circuit comprising at least two array selection modules and at least two decoders; each array selection module is connected with a decoder corresponding to the array selection module, and the array selection module is connected with an adjacent array selection module on at least one side of the array selection module; the array selection module is used for generating an enabling signal for activating the decoder according to the array selection signal and the storage mode selection signal; and a decoder for receiving the enable signal and the address signal and decoding the row address signal according to the enable signal to determine the target word line. The common storage mode can fully utilize the storage unit to increase the capacity, the differential storage mode has higher storage speed, and the storage mode of the storage space of the storage chip can be flexibly switched based on the user demand by the control circuit, so that the demands of the user on the storage space and the storage speed are met, and the transmission of the data DQ is completed.

In a fourth aspect, the present application further provides an electronic device, referring to fig. 10, including: the three-dimensional chip 1000 as described in the third aspect.

As shown in fig. 11, an electronic system 700 is further provided according to an embodiment of the present application, including a memory 710, a processor 720, and a computer program 711 stored in the memory 710 and executable on the processor, where the processor 720 executes any one of the steps of the method for controlling the memory chip.

Since the electronic system described in this embodiment is a device used for implementing the control device of the memory chip in this embodiment of the present application, based on the method described in this embodiment of the present application, those skilled in the art can understand the specific implementation of the electronic system in this embodiment and various modifications thereof, so how the electronic system implements the method in this embodiment of the present application will not be described in detail herein, and as long as those skilled in the art use the device for implementing the method in this embodiment of the present application are all within the scope of the application to be protected.

In a specific implementation, the computer program 711, when executed by a processor, may implement any of the embodiments corresponding to fig. 8.

In the foregoing embodiments, the descriptions of the embodiments are focused on, and for those portions of one embodiment that are not described in detail, reference may be made to the related descriptions of other embodiments.

It will be appreciated by those skilled in the art that embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.

The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

Embodiments of the present application also provide a computer program product comprising computer software instructions which, when run on a processing device, cause the processing device to perform a flow of control of a memory chip as in the corresponding embodiment of fig. 8.

The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the processes or functions in accordance with embodiments of the present application are produced in whole or in part. The computer may be a general purpose computer, a special purpose computer, a computer network, or other programmable apparatus. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by a wired (e.g., coaxial cable, fiber optic, digital subscriber line (digital subscriber line, DSL)) or wireless (e.g., infrared, wireless, microwave, etc.). Computer readable storage media can be any available media that can be stored by a computer or data storage devices such as servers, data centers, etc. that contain an integration of one or more available media. Usable media may be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., DVDs), or semiconductor media (e.g., solid State Disks (SSDs)), among others.

It will be clear to those skilled in the art that, for convenience and brevity of description, specific working procedures of the above-described systems, apparatuses and units may refer to corresponding procedures in the foregoing method embodiments, which are not repeated herein.

In the several embodiments provided in the present application, it should be understood that the disclosed systems, devices, and methods may be implemented in other manners. For example, the apparatus embodiments described above are merely illustrative, e.g., the division of elements is merely a logical functional division, and there may be additional divisions of actual implementation, e.g., multiple elements or components may be combined or integrated into another system, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, which may be in electrical, mechanical or other form.

The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed over a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional unit in the embodiments of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in software functional units.

The integrated units, if implemented in the form of software functional units and sold or used as stand-alone products, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present application may be embodied in essence or a part contributing to the prior art or all or part of the technical solution in the form of a software product stored in a storage medium, including several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods of the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (Random Access Memory, RAM), a magnetic disk, or an optical disk, or other various media capable of storing program codes.

The above embodiments are only for illustrating the technical solution of the present application, and are not limiting; although the application has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A control circuit of a memory chip, comprising: at least two array selection modules and at least two decoders;

2. The control circuit of claim 1, wherein the decoder comprises: first decoders, each of which shares the same row address signal;

The row address signals include a row address first signal;

the first decoder is to receive an enable signal and a row address first signal to generate a target word line first address, the target word line first address to determine the target word line.

3. The control circuit of claim 2, wherein the decoder further comprises: at least one word line driving module and a second decoder;

the second decoder is used for generating a target word line second address according to a row address second signal, and the target word line second address is used for determining the target word line;

the word line driving modules share the target word line second address;

4. The control circuit of claim 1, wherein the storage mode selection signal comprises: the indication storage mode is a differential storage mode or an indication storage mode is a common storage mode, and the differential storage mode is used for simultaneously starting a plurality of decoders.

5. A control method of a memory chip, comprising:

the array selection module generates an enabling signal for activating the decoder according to the array selection signal and the storage mode selection signal;

a decoder receives an enable signal and a row address signal and decodes the row address signal under control of the enable signal to determine a target word line.

6. The control method according to claim 5, wherein the storage mode selection signal includes a signal indicating that the storage mode is a differential storage mode;

the method further comprises the steps of:

the array selection module sends the array selection signals to other array selection modules, and the array selection modules and the other array selection modules are a group of array selection modules for differentially storing data;

7. The method as recited in claim 6, further comprising:

Activating the second target word line;

8. A three-dimensional chip, comprising: a control circuit as claimed in any one of claims 1 to 4.

9. An electronic device, comprising: the three-dimensional chip of claim 9.

10. An electronic system, comprising: memory, a processor and a computer program stored in the memory and executable on the processor, characterized in that the processor is adapted to carry out the steps of the control method of the memory chip according to any one of claims 5 to 7 when the computer program stored in the memory is executed.