CN117194288A - Three-dimensional chip, access control method and electronic equipment - Google Patents
Three-dimensional chip, access control method and electronic equipment Download PDFInfo
- Publication number
- CN117194288A CN117194288A CN202210615016.8A CN202210615016A CN117194288A CN 117194288 A CN117194288 A CN 117194288A CN 202210615016 A CN202210615016 A CN 202210615016A CN 117194288 A CN117194288 A CN 117194288A
- Authority
- CN
- China
- Prior art keywords
- chip
- memory
- logic
- dimensional
- access
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 48
- 238000012545 processing Methods 0.000 claims abstract description 108
- 230000010354 integration Effects 0.000 claims abstract description 30
- 238000006243 chemical reaction Methods 0.000 claims description 6
- 238000004458 analytical method Methods 0.000 claims description 5
- 238000004364 calculation method Methods 0.000 description 33
- 230000008569 process Effects 0.000 description 20
- 238000010586 diagram Methods 0.000 description 16
- 238000004590 computer program Methods 0.000 description 10
- 230000006870 function Effects 0.000 description 10
- 239000000243 solution Substances 0.000 description 9
- 235000012431 wafers Nutrition 0.000 description 7
- 238000012986 modification Methods 0.000 description 6
- 230000004048 modification Effects 0.000 description 6
- 230000008901 benefit Effects 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 5
- 239000007853 buffer solution Substances 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 230000004044 response Effects 0.000 description 4
- 230000009471 action Effects 0.000 description 3
- 230000008878 coupling Effects 0.000 description 3
- 238000010168 coupling process Methods 0.000 description 3
- 238000005859 coupling reaction Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 230000003287 optical effect Effects 0.000 description 3
- 101100498818 Arabidopsis thaliana DDR4 gene Proteins 0.000 description 2
- 102100036725 Epithelial discoidin domain-containing receptor 1 Human genes 0.000 description 2
- 101710131668 Epithelial discoidin domain-containing receptor 1 Proteins 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
- 238000000605 extraction Methods 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- 238000012546 transfer Methods 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 230000006399 behavior Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000000284 extract Substances 0.000 description 1
- 239000000835 fiber Substances 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000010801 machine learning Methods 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Dram (AREA)
Abstract
The application discloses a three-dimensional chip, an access control method and electronic equipment, relates to the technical field of chips, and can improve storage access efficiency and data processing efficiency. A three-dimensional chip, comprising: a logic chip; a memory chip; a memory interface chip; the logic chip, the memory chip and the memory interface chip are arranged in a stacked manner, and any two adjacent logic chips, the memory chip and the memory interface chip are connected through three-dimensional heterogeneous integration; the memory interface chip provides a memory protocol for global access of the logic chip to the memory chip, and the memory interface chip provides a memory protocol for global access of a host system to the three-dimensional chip.
Description
Technical Field
The present application relates to the field of chip technologies, and in particular, to a three-dimensional chip, an access control method, and an electronic device.
Background
The conventional DRAM (Dynamic Random Access Memory ) architecture is internal memory access to DRAM through a standard DRAM interface. When the upper system performs operation, data is read out from the DRAM interface in series, and after the operation is finished, a result is written back into the DRAM, so that the access efficiency is low, and system operation resources and a system bus are occupied. In particular, in the data processing process, the next calculation step depends on the calculation process of part or all of the last calculation result as input, and each storage access needs to traverse a storage wall formed by a DRAM interface, a CPU (central processing unit) cache system and the like.
Therefore, the memory access of the existing upper system needs to repeatedly traverse the memory wall formed by the DRAM interface, the CPU cache system and the like, which causes the spending of time and power consumption to be greatly increased, and the memory access efficiency of the upper system is low and the data processing efficiency is low.
Disclosure of Invention
The embodiment of the application provides a three-dimensional chip, an access control method and electronic equipment, which can improve storage access efficiency and data processing efficiency.
In a first aspect of an embodiment of the present application, there is provided a three-dimensional chip including:
a logic chip;
a memory chip;
a memory interface chip;
the logic chip, the memory chip and the memory interface chip are arranged in a stacked manner, and any two adjacent logic chips, the memory chip and the memory interface chip are connected through three-dimensional heterogeneous integration;
the memory interface chip provides a memory protocol for global access of the logic chip to the memory chip, and the memory interface chip provides a memory protocol for global access of a host system to the three-dimensional chip.
In some embodiments, the three-dimensional chip comprises:
the global memory access module is arranged on the logic chip or the memory interface chip;
The global memory access module is used for controlling the memory chip to be in a computing state or an idle state.
In some embodiments, the memory interface chip includes:
the global access bus is connected with the logic chip and is used for outputting a multi-path control signal so as to provide a storage protocol for the logic chip to perform global access to the storage chip and a storage protocol for the upper system to perform global access to the three-dimensional chip;
the multi-path control signal is used for controlling the logic chip to access the memory chip in a memory mode.
In some embodiments, the logic chip comprises a plurality of logic processing units, the memory chip comprises a plurality of memory modules, the memory modules comprise at least one memory unit;
in some embodiments, the global access of the logic chip to the memory chip includes a memory access of each of the logic processing units to all of the memory modules;
and the global access of the upper system to the three-dimensional chip comprises the storage access of the upper system to all the logic processing units and the storage access of the upper system to all the storage modules.
The logic processing units are interconnected one-to-one with the memory modules and/or the logic processing units are interconnected one-to-many with the memory modules.
In some embodiments, the logic chip further comprises a storage routing unit, the storage routing unit being interconnected one-to-one with the storage module, and/or the storage routing unit being interconnected one-to-many with the storage module;
the storage routing unit is used for determining the storage module corresponding to the address information as a target storage module according to the multipath control signals, so that the target storage module performs data writing and data reading based on the multipath control signals and the address information.
In some embodiments, the three-dimensional chip further comprises:
a memory controller disposed within one of the logic chip, the memory chip, and the memory interface chip;
the memory controller is used for controlling global access to the logic chip, global memory access to the memory chip and connection state of a standard memory interface.
In some embodiments, the memory controller is configured to control two or more of the logic processing units within the logic chip to access two or more of the memory modules in parallel.
In some embodiments, the memory chip further includes a rank decoding module, where the rank decoding module is connected to the memory module in a one-to-one correspondence.
In some embodiments, the memory interface chip includes:
the instruction analysis module is connected with the global access bus and is used for analyzing the control instruction to obtain the multi-path control signal;
the address decoding module is connected with the global access bus and is used for decoding the control instruction to obtain an address signal;
and the data serial-parallel conversion module is connected with the global access bus.
In some embodiments, the logic processing unit comprises a programmable logic array.
In some embodiments, the memory interface chip is interconnected with the logic chip by a three-dimensional heterogeneous integration, and the logic chip is interconnected with the memory chip by a three-dimensional heterogeneous integration; or alternatively, the first and second heat exchangers may be,
the logic chip is interconnected with the memory chip through three-dimensional heterogeneous integration, and the memory chip is interconnected with the memory interface chip through three-dimensional heterogeneous integration; or alternatively, the first and second heat exchangers may be,
The logic chip is interconnected with the memory interface chip through three-dimensional heterogeneous integration, and the memory interface chip is interconnected with the memory chip through three-dimensional heterogeneous integration.
In a second aspect of the embodiment of the present application, there is provided an access control method for a three-dimensional chip, including:
sending a control instruction to the three-dimensional chip;
according to the control instruction, the control logic chip performs global access to the memory chip based on a memory protocol of the memory interface chip; and/or the number of the groups of groups,
and according to the control instruction, performing global access on the three-dimensional chip based on a storage protocol of the storage interface chip.
In some embodiments, the logic chip includes a plurality of logic processing units, and the memory chip includes a plurality of memory modules;
the controlling the logic chip to globally access the memory chip based on the memory protocol of the memory interface chip according to the control instruction includes:
according to the control instruction, controlling a target logic processing unit to perform storage access on a target storage module, wherein the target logic processing unit comprises any logic processing unit of the logic chip, and the target storage module comprises any storage module of the storage chip;
The global access to the three-dimensional chip based on the memory protocol of the memory interface chip according to the control instruction comprises:
and according to the control instruction, controlling the upper system to perform storage access on the target logic processing unit of the three-dimensional chip, and/or controlling the upper system to perform storage access on the target storage module.
In a third aspect of an embodiment of the present application, there is provided an electronic device including:
the three-dimensional chip of the first aspect.
According to the three-dimensional chip, the access control method and the electronic device provided by the embodiment of the application, the logic chip, the memory chip and the memory interface chip are integrated into the three-dimensional chip, so that the access link can be greatly shortened, and the calculation and processing load of a CPU or an upper system can be fully released. The near-memory architecture of the three-dimensional chip directly establishes cross-region interconnection of the metal layers between the logic chip and the memory chip through three-dimensional heterogeneous integration, physical and electrical parameters follow the technological characteristics of a semiconductor manufacturing process, compared with the prior art through input and output and a memory wall, delay of memory access exceeding two orders of magnitude is greatly reduced, power consumption overhead exceeding two orders of magnitude is reduced, meanwhile, the high-order width interconnection of the logic chip and the memory chip is remarkably increased compared with the CPU access bit width, and the memory access bit width can be increased to more than two to three orders of magnitude.
Drawings
FIG. 1 is a schematic block diagram of a three-dimensional chip provided in an embodiment of the present application;
FIG. 2 is a schematic partial block diagram of a three-dimensional chip according to an embodiment of the present application;
FIG. 3 is a schematic block diagram of a memory chip according to an embodiment of the present application;
FIG. 4 is a schematic block diagram of a memory interface chip according to an embodiment of the present application;
FIG. 5 is a schematic flow chart of a method for controlling access to a three-dimensional chip according to an embodiment of the present application;
fig. 6 is a schematic block diagram of an electronic device according to an embodiment of the present application.
Detailed Description
In order to better understand the technical solutions provided by the embodiments of the present specification, the following detailed description of the technical solutions of the embodiments of the present specification is made through the accompanying drawings and the specific embodiments, and it should be understood that the specific features of the embodiments of the present specification are detailed descriptions of the technical solutions of the embodiments of the present specification, and not limit the technical solutions of the present specification, and the technical features of the embodiments of the present specification may be combined with each other without conflict.
In this document, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element. The term "two or more" includes two or more cases.
The conventional DRAM architecture is to access internal memory of the DRAM through a standard DRAM interface. When the upper system performs operation, data is read out from the DRAM interface in series, and after the operation is finished, a result is written back into the DRAM, so that the access efficiency is low, and system operation resources and a system bus are occupied. In particular, in the data processing process, the next calculation step depends on the calculation process of taking part or all of the last calculation result as input, and each storage access needs to pass through a storage wall formed by a DRAM interface, a CPU cache system and the like. Therefore, the memory access of the existing upper system needs to repeatedly traverse the memory wall formed by the DRAM interface, the CPU cache system and the like, which causes the spending of time and power consumption to be greatly increased, and the memory access efficiency of the upper system is low and the data processing efficiency is low.
In view of the above, the embodiments of the present application provide a three-dimensional chip and an electronic device, which can improve the storage access efficiency and the data processing efficiency.
In a first aspect of the embodiment of the present application, a three-dimensional chip is provided, and fig. 1 is a schematic structural diagram of the three-dimensional chip provided in the embodiment of the present application. As shown in fig. 1, the three-dimensional chip provided by the embodiment of the application includes: the memory chip 200, the memory interface chip 300, and the logic chip 100 may include an operation processing array, and a logic processing unit in the operation processing array may be used to process data, where the processing data may include operation processing on the data, and the like; the memory chip 200 may include a memory unit or a memory module, and a plurality of memory modules or a plurality of memory units may form a memory array, the memory unit may store data, the data processed by the logic processing unit may be stored in the memory unit, and the logic processing unit may call the data in the memory unit to process. The logic chip 100, the memory chip 200 and the memory interface chip 300 are arranged in a stacked manner, and any two adjacent chips are interconnected through three-dimensional heterogeneous integration; the memory interface chip 300 provides a memory protocol for globally accessing the memory chip 200 by the logic chip 100, and the memory interface chip 300 provides a memory protocol for globally accessing the three-dimensional chip by the upper system.
It should be noted that, the conventional DRAM internal array may be divided into multiple BANKs (memory modules or memory units), and because of the limitation of the interface bit width and the interface speed, all BANKs time-division multiplex interface buses, the system can only access one BANK of the DRAM at a time, and the system may be an upper system or a master control system outside the three-dimensional chip, and the embodiment of the present application is not limited specifically. When the system operates, data is read out from the DRAM interface in series, and after the operation is finished, the result is written back to the DRAM, so that the access efficiency is low, and the system operation resources and the system bus are occupied. In the prior art (taking the X86 architecture as an example), for the computational objective: inputting data A1I for A1 calculation and outputting data A1O; performing A2 calculation on the data A1O and outputting the data A2O; performing A3 calculation on the data A2O and outputting the data A3O; .. An is calculated for data AnO (n is a natural number greater than 0) and data AnO is output, and the implementation method is as follows:
the CPU controls the input data A1I to be loaded into the DRAM from a hard disk or a network interface and the like;
the CPU reads out Data A1I in the DRAM module or chip successively through a DRAM interface, a DDR (Double Data Rate) controller and a CPU cache system, calculates and generates a part of output Data A1O, writes the part into the DRAM through the CPU cache system, the DDR controller and the DRAM interface, and successively spells and constructs complete output Data A1O;
The CPU reads out data A1O in the DRAM successively through a DRAM interface, a DDR controller and a CPU cache system, calculates and generates a part of output data A2O, writes the part of output data A2O into the DRAM through the CPU cache system, the DDR controller and the DRAM interface, and successively splices the whole output data A2O;
the CPU reads out the data A2O in the DRAM successively through the DRAM interface, the DDR controller and the CPU buffer system, calculates and generates a part of the output data A3O, writes the part into the DRAM through the CPU buffer system, the DDR controller and the DRAM interface, and successively spells the whole output data A3O.
The CPU reads out the data An0 in the DRAM successively through the DRAM interface, the DDR controller and the CPU buffer system, calculates and generates a part of the output data An0, writes the part into the DRAM through the CPU buffer system, the DDR controller and the DRAM interface, and successively spells out the complete output data AnO.
In particular, for a calculation process in which the next calculation step depends on part or all of the last calculation result as input, intermediate calculation data cannot be completely retained in the CPU cache system, resulting in a large number of memory access behaviors between the CPU-CPU cache system-DDR controller-DRAM.
By way of example, the three-dimensional chip provided in the embodiment of the present application provides a storage protocol for globally accessing the logic chip 100 to the memory chip 200 by using the memory interface chip 300 by providing the memory interface chip 300, and provides a storage protocol for globally accessing the three-dimensional chip by using the memory interface chip 300 by using an upper system. The completion process for the computational goal may be:
The CPU controls loading of input data A1I from a hard disk or a network interface or the like into the memory chip 200 supporting in-memory computation using a memory protocol for global access of the memory interface chip 300 to the three-dimensional chip; it should be noted that, the CPU may be disposed outside the three-dimensional chip, or may be disposed inside the three-dimensional chip, and the embodiment of the present application is not limited specifically.
The logic chip 100 supporting in-memory calculation gradually calls corresponding input and output data through the global access protocol of the logic chip 100 provided by the memory interface chip 300 to the memory chip 200, so as to complete the whole calculation process; the whole calculation process can go through the global access of the logic chip 100 to the memory chip 200, and the global access can be understood as that the logic chip 100 can access each BANK in the memory chip 200 in parallel, that is, the logic chip 100 can access a plurality of BANKs simultaneously.
The CPU reads out output data AnO from the memory chip 200.
Illustratively, a certain data processing instruction includes 3 calculation steps, namely, a first step calculation S1, a second step calculation S2, and a third step calculation S3, where the first step calculation S1 is correspondingly performed by the first logic processing unit 111 in the logic chip 100, the second step calculation S2 is correspondingly performed by the second logic processing unit 121 in the logic chip 100, and the third step calculation S3 is correspondingly performed by the third logic processing unit 131 in the logic chip 100.
The original data0 is sent to a target storage module for storage by an upper system;
the first logic processing unit 111 retrieves the original data0 from the target storage module, and then performs a first step of computation S1, and the first logic processing unit 111 obtains the first processing data1 based on the original data 0; the first processing data1 is used as the input data of the second calculation step, and the first processing data1 may be directly transmitted to the second logic processing unit 121 by the first logic processing unit 111.
The second logic processing unit 121 performs a second step of calculation S2 based on the first processing data1, resulting in second processing data2; the second processing data2 is transmitted by the second logic processing unit 121 to the third logic processing unit 131 as input data of the third step calculation S3.
The third logic processing unit 131 performs a third step of computation S3 based on the second processing data2, resulting in the result data3.
And storing the result data3 into a target storage module for storage.
In the process of obtaining the result data3 from the original data0, the first processing data1 and the second processing data2 serving as intermediate data do not need to be stored and read by a storage module, the intermediate data do not need to be uploaded to an upper system and then read from the upper system, so that a large amount of intermediate data in the calculation process do not need to repeatedly pass through a storage wall formed by a DRAM interface, a DDR controller and a CPU cache system.
It should be noted that, in the process of issuing a control instruction to control the three-dimensional chip to execute S1 to S3 and obtaining the result data3 from the original data0, other control instructions may be issued at the same time to control other logic processing units and memory modules of the three-dimensional chip to execute other computing tasks, so as to implement parallel memory access, that is, a global access mode.
Compared with the prior art, the three-dimensional chip provided by the embodiment of the application has the advantages that a large amount of intermediate data in the calculation process does not need to repeatedly pass through a storage wall formed by a DRAM interface, a DDR controller and a CPU cache system.
The three-dimensional chip provided by the embodiment of the application can greatly shorten the memory link and fully release the calculation and processing load of the CPU or the upper system by integrating the logic chip 100, the memory chip 200 and the memory interface chip 300 into the three-dimensional chip. The near memory architecture of the three-dimensional chip directly establishes cross-regional interconnection of metal layers between the logic chip 100 and the memory chip 200 through three-dimensional heterogeneous integration, physical and electrical parameters follow the technological characteristics of a semiconductor manufacturing process, compared with the prior art of input/output (I/O) and a memory wall, delay of memory access exceeding two orders of magnitude is greatly reduced, power consumption overhead exceeding two orders of magnitude is reduced, meanwhile, high-bit-width interconnection of the logic chip 100 and the memory chip 200 is obviously increased compared with CPU memory access bit width (for example, 8-64 bit) and can be increased to more than two to three orders of magnitude.
The three-dimensional chip provided by the embodiment of the application interconnects the logic chip 100 and the memory chip in a Hybrid bonding (TSV) mode by using a multi-layer wafer (chip), so that a three-dimensional heterogeneous integrated near-memory architecture of the memory chip 200 and the logic chip 100 is realized, and the data of the memory chip 200 can be operated in the following three-dimensional chip. Meanwhile, the memory interface chip 300 is added, so that the standard DRAM interface protocol can be compatible, the standard DRAM interface protocol can be not limited to DDR1, DDR2, DDR3, DDR4, DDR5, LPDDR2, LPDDR3, LPDDR4, LPDDR5, GDDR3, GDDR5 and the like, an in-memory computing architecture facing to a standard computer system (CPU/GPU) is realized, and the system operation efficiency is greatly improved. In addition, the global memory access interconnection resources of the memory interface chip 300 are multiplexed, so that the global memory access of the logic chip 100 to the memory chip 200 can be realized in the three-dimensional chip, the global memory access of the three-dimensional chip can be prevented from passing through a memory wall and being transferred by a CPU, and the CPU resources can be released; layout constraints on the logic chip 100 can also be simplified and improved, and the implementation density of the logic chip 100 can be greatly increased, and especially, the improvement effect is more obvious when the granularity of the logic chip 100 is different.
In some implementations, fig. 2 is a schematic partial block diagram of a three-dimensional chip according to an embodiment of the present disclosure. As illustrated in fig. 2, the logic chip 100 includes a plurality of logic processing units 110, the memory chip 200 includes a plurality of memory modules bank including at least one memory unit; the plurality of memory modules bank may form a memory array. The logic processing units 110 are interconnected one-to-one with the memory module bank and/or the logic processing units 110 are interconnected one-to-many with the memory module bank. The logic processing unit 110 shown in fig. 2 is illustratively interconnected with the memory modules bank one-to-one, and the memory modules bank shown in fig. 2 are, for example, the first memory module bank0, the second memory module bank1, the third memory module bank2, and the fourth memory module bank3, respectively, which are not intended to be specific limitations of the embodiments of the present application. The logic chip 100 further includes a storage routing unit 120, where the storage routing unit 120 is one-to-one interconnected with the storage module bank, and/or the storage routing unit 120 is one-to-many interconnected with the storage module bank; the storage routing unit 120 is configured to determine, according to the multiple control signals, a storage module bank corresponding to the address information as a target storage module, so that the target storage module performs data writing and data reading based on the multiple control signals and the address signals. The target storage module is a storage module where the data written or read is controlled by the multipath control signals and the address signals, wherein the multipath control signals and the address signals can come from control instructions, and the control instructions can be sent by an upper system or can be sent by the inside of a three-dimensional chip.
For example, the logic chip 100 may include a two-part function, and the memory routing unit 120 may implement an access routing function of the memory module bank, and write data into or read data from the corresponding bank mainly according to the address signal and the multi-path control signal. The logic processing unit 110 may implement decoding of the operation command, control the operation processing unit to read data from the designated memory module bank and perform corresponding operation, and store the operation result back to the memory module bank or temporarily store the operation result in an internal register.
It should be noted that, the global access may be that the global access of the logic chip to the memory chip includes the memory access of each logic processing unit to all the memory modules. The global access may also be that the global access of the upper system to the three-dimensional chip includes a memory access of the upper system to all the logic processing units and a memory access of the upper system to all the memory modules.
In some implementations, the logic processing unit 110 may include a programmable logic array.
By way of example, the logical operations may refer to a PE (Processing Element, hard-core operation/processing unit) that may include one or more of any combination of a multiply-add computation array, a multiply computation array, a systolic processor array, a hash computation array, a variety of encoder arrays, a specialized layer array for machine learning, a search function array, an image/video processing array, and hard-core operation/logic processing units such as CPU, MCU, and DSP; reconfigurable units of the programmable logic array may also be included in the PE to establish the reconfigurable capability of the PE.
In some embodiments, the three-dimensional chip provided by the embodiment of the present application further includes: a memory controller disposed within one of the logic chip 100, the memory chip 200, and the memory interface chip 300; the memory controller is used to control global access to the logic chip 100, global memory access to the memory chip 200, and connection status of the standard memory interface.
The memory controller may also be used to control two or more logic processing units 110 within the logic chip 100 to access two or more memory modules bank in parallel.
In some embodiments, the memory interface chip 300 includes:
the global access bus is connected with the logic chip 100 and is used for outputting a multi-path control signal so as to provide a storage protocol for the logic chip 100 to globally access the memory chip 200 and a storage protocol for the upper system to globally access the three-dimensional chip; the multi-path control signal is used for controlling the logic chip to store and access the memory chip. The global access bus may include an external global access bus for providing a storage protocol for global access of the upper system to the three-dimensional chip and an internal global access bus for outputting a multi-path control signal to provide a storage protocol for global access of the logic chip to the memory chip.
In some embodiments, the memory interface chip 300 and the logic chip 100 are interconnected by three-dimensional heterogeneous integration, and the logic chip 100 and the memory chip 200 are interconnected by three-dimensional heterogeneous integration, i.e., the logic chip 100 is disposed between the memory chip 200 and the memory interface chip 300. Or, the logic chip 100 and the memory chip 200 are interconnected by three-dimensional heterogeneous integration, and the memory chip 200 and the memory interface chip 300 are interconnected by three-dimensional heterogeneous integration, i.e., the memory chip 200 is disposed between the logic chip 100 and the memory interface chip 300. Or, the logic chip 100 and the memory interface chip 300 are interconnected by three-dimensional heterogeneous integration, and the memory interface chip 300 and the memory chip 200 are interconnected by three-dimensional heterogeneous integration, i.e., the memory interface chip 300 is disposed between the logic chip 100 and the memory chip 200.
In the three-dimensional chip, the memory interface chip 300, the logic chip 100 and the memory chip 200 are arranged in sequence from top to bottom, the relative structural advantage of the chip stacking mode is that the access distance of the logic chip 100 to the memory module in the memory chip 200 is shortest, the memory access advantage is fully calculated in the memory, and the memory interface chip 300 is closely adjacent to the signal extraction layer of the three-dimensional chip, namely the RDL (outermost extraction interface, binding boundary surface), so that the standard memory interface can be conveniently extracted.
In the three-dimensional chip, the logic chip 100, the memory interface chip 300 and the memory chip 200 are arranged in sequence from top to bottom, and the advantage is that the memory interface chip 300 is close to the memory chip 200, the global memory access network path is shorter, and the method is applicable to engineering targets with shorter DDR interface delay and more frequent memory global memory access.
In the three-dimensional chip, the memory interface chip 300, the memory chip 200 and the logic chip 100 are arranged in sequence from top to bottom, and the advantage is that the memory chip 200 is closest to the logic chip 100 and the memory interface chip at the same time, the performance of the external standard DDR interface is optimal, and the performance of in-memory computing memory access is optimal.
Illustratively, the logic chip 100 includes an operation array composed of a plurality of logic processing units 110. Each logic processing unit 110 is interconnected with the memory module bank through three-dimensional heterogeneous integration, which may be a one-to-one interconnection or a one-to-many interconnection. The logic processing unit 110 may further include a memory controller, which is configured to implement a read, write, and refresh instruction for the memory module bank, that is, implement memory access of the logic processing unit 110 to the memory module bank. The memory controller of the logic processing unit 110 may also be separately designed on the memory interface chip 300 or the memory chip 200.
The memory interface chip 300 may be interconnected with the logic chip 100 through three-dimensional heterogeneous integration, and provides global memory access logic interconnection for the logic processing units 110 in the logic chip 100, so that data memory access between the cross-region (crossing different logic processing units 110) and the corresponding memory modules bank thereof is performed without passing through a memory wall.
The memory interface chip 300 can be based on three-dimensional heterogeneous integration and is interconnected with the memory chip 200 through the logic chip 100, and partial or global logic interconnection on the memory chip 200 is established on the memory interface chip 300, so that external standard memory interface memory access of the three-dimensional chip is realized.
The memory interface chip 300 may also include a memory controller for implementing read, write, refresh instructions to the memory module bank, and memory access to the memory module bank via a standard memory interface and/or an internal global access bus. The memory controller on the memory interface chip 300 may also be separately designed on the logic chip 100 or the memory chip 200. The memory controller on the memory interface chip 300 may also be provided on any chip in a multiplexed manner with the memory controller on the logic chip 100.
In some embodiments, the three-dimensional chip provided by the embodiment of the present application includes: the global memory access module is arranged on the logic chip 100 or the memory interface chip 200; the global memory access module is configured to control the memory chip 200 to be in a computing state or an idle state, when the upper system accesses a certain memory unit, the accessed memory unit is in the computing state, and the global memory access module is required to switch the state of the memory unit to the idle state, so that the upper system can access the memory unit, and when the upper system successfully accesses the memory unit, the state of the memory unit is in the access state.
The global memory access module can realize in-memory computing access and standard memory interface access states among all or part of memory modules bank. That is, the standard computer system (the upper system may be a CPU/GPU) controls part or all of the storage units in the three-dimensional chip to be in a computing state or a standard storage interface access state, so as to avoid that when the standard computer system initiates a standard storage interface storage access to the three-dimensional chip, a timeout response occurs if the corresponding storage unit in the three-dimensional chip is in the computing state or the access state, which leads to breakdown or error of the standard computer system. The state switching of all the memory cells is simpler to realize; the state switching of the partial storage units can enable the standard computer system to access the partial storage units of the three-dimensional chip, namely, the partial storage units load or read the calculation data, and meanwhile, other storage units of the three-dimensional chip can still perform in-memory calculation work, so that the system efficiency is improved.
For example, the state-switching input signal sources obtained by the three-dimensional chip from a standard computer system may include:
independent external signals, such as SPD (Serial Presence Detect, standard memory interface signal), SPD can be used for configuration information of memory module, and standard computer system can control state switching of memory unit of three-dimensional chip by means of independent external signals.
Control instructions or expansion instructions of the standard storage interface, wherein the control instructions can comprise a plurality of paths of control signals and address signals; the standard computer system can control the state switching of the memory unit of the three-dimensional chip through a control instruction or an expansion instruction.
The memory space expansion of the standard memory interface, namely, defining a section of memory space (physically, registers formed by a dual-port RAM, a DFF array and the like) in a three-dimensional chip; the standard computer system can write the switching instruction into the extended storage space, the global storage access module extracts the information for setting the state switching of the storage unit of the three-dimensional chip, and the global storage access module feeds back the output signal after receiving the state switching instruction of the storage unit of the standard computer system.
After the global storage access module receives and implements the state switching instruction of the storage unit of the standard computer system, and/or after receiving the state query instruction of the storage unit of the standard computer system, the storage unit can be automatically switched to the access state of the standard storage interface, and the response result of the standard computer system is realized through an output link corresponding to the source of the input signal.
Another implementation manner of cross-region, i.e. cross-logic processing unit storage access may be to set a storage controller on any chip, and automatically complete transfer of storage data between the cross-logic processing units and corresponding storage modules in response to a data transfer instruction of some or all logic processing units. The global memory access logic interconnect of the memory interface chip may be multiplexed above.
In order to realize capacity expansion, the memory chips may also be stacked in multiple layers, and embodiments of the present application are not particularly limited.
In some implementations, fig. 3 is a schematic block diagram of a memory chip according to an embodiment of the present application. As shown in fig. 3, the memory chip 200 further includes a row-column decoding module 210, where the row-column decoding module 210 is connected to the memory module bank in a one-to-one correspondence manner. The memory modules shown in fig. 3 are a first memory module bank0, a second memory module bank1, a third memory module bank2, a fourth memory module bank3, a fifth memory module bank4, a sixth memory module bank5, and a seventh memory module bank6.
For example, the memory chip 200 may include a memory module bank and a corresponding rank decode module 210 without setting memory interface protocol parsing and data serial-parallel conversion logic, so that access to the memory module bank is more efficient and direct. Because the Hybrid bonding mode is adopted to interconnect with the logic chip 100, the size and the space of the bonding structure are reduced by hundreds of times compared with the common inter-chip interconnecting connection structure, and the occupied area is reduced by nearly tens of thousands times, so that the read-write buses of all the memory modules bank of the memory chip 200 can be led out through the bonding structure, and compared with the prior art, the read-write buses are increased by more than nearly three orders of magnitude, so that the logic chip 100 can access all the memory modules bank of the memory chip 200 in parallel.
In some implementations, fig. 4 is a schematic block diagram of a memory interface chip according to an embodiment of the present application. As shown in fig. 4, the memory interface chip 300 may include: the instruction analysis module 310, the instruction analysis module 310 is connected with the global access bus, and the instruction analysis module 310 is used for analyzing the control instruction to obtain a multi-path control signal; the address decoding module 320, the address decoding module 320 is connected with the global access bus, and the address decoding module 320 is used for decoding the control instruction to obtain an address signal; the data serial-parallel conversion module 330 is connected to the global access bus, and the data serial-parallel conversion module 330 can output a data serial-parallel signal. The memory interface chip 300 may also include a control module 340 that may be used for refresh control, calibration control, mode control, or test control, among others.
The logic chip 100 is an independent chip, and can have more general computing versatility, more powerful computing power and more powerful bandwidth, and can implement any computing or data processing as needed.
The memory interface chip 300 may implement standard memory protocol conversion including command decoding, address resolution, refresh control, data serial-to-parallel processing, ZQ calibration, mode control, test control, etc. Among them, the storage interface protocols include, but are not limited to, DDR1, DDR2, DDR3, DDR4, DDR5, LPDDR2, LPDDR3, LPDDR4, LPDDR5, GDDR3, GDDR5, etc. The logic chip 100 may select the logic processing unit 110 for memory access or the memory interface chip 300 for memory access. The storage routing unit 120 may also be disposed on the storage interface chip 300, which is not particularly limited in the embodiment of the present application.
For example, the memory interface chip 300 may perform data movement in response to a logic processing unit request.
The 3DIC (three-dimensional chip) process is a mature technology suitable for multi-chip stacked interconnection, where two memory wafers and two logic wafers are interconnected by small-sized Hybrid bonding and tsv technology. Two storage wafers and two logic wafers can be connected in the same direction through Hybrid bonding and tsv, and then the connected storage wafers and the logic wafers are connected face to face through Hybrid bonding.
The three-dimensional chip provided by the embodiment of the application interconnects a plurality of chips, realizes the standard storage function, is embedded with the logic chip, can realize the access operation on data in the chip, and greatly improves the system performance. The internal computing architecture is realized through the near memory access of the 3DIC, so that the memory link is greatly shortened, and the computing and processing load of the CPU is fully released. The 3DIC near memory architecture directly establishes metal layer cross-region interconnection between a logic chip and a memory chip through three-dimensional heterogeneous integration, and physical and electrical parameters follow the technological characteristics of a semiconductor manufacturing process, compared with the prior art through input and output and a memory wall: the delay and the power consumption expenditure of the memory access are greatly reduced, and meanwhile, the high bit width interconnection of the logic chip to the near memory access is obviously increased compared with the memory access bit width of the CPU.
In a second aspect of the embodiment of the present application, a method for controlling access to a three-dimensional chip is provided, and fig. 5 is a schematic flowchart of the method for controlling access to a three-dimensional chip provided in the embodiment of the present application, as shown in fig. 5, where the method for controlling access to a three-dimensional chip provided in the embodiment of the present application includes:
s101: sending a control instruction to the three-dimensional chip; the control instruction may be issued by a host system.
S201: according to the control instruction, the control logic chip performs global access to the memory chip based on a memory protocol of the memory interface chip; the global access of the logic chip to the memory chip belongs to the global access inside the three-dimensional chip.
S301: and according to the control instruction, performing global access on the three-dimensional chip based on a storage protocol of the storage interface chip. Global access to the three-dimensional chip belongs to external full access to the three-dimensional chip by the upper system through the memory interface chip.
It should be noted that, the access control method for a three-dimensional chip provided by the embodiment of the present application may include only step S101 and step S201, only step S101 and step S301, and simultaneously include step S101, step S201 and step S301.
According to the access control method for the three-dimensional chip, the logic chip 100, the memory chip 200 and the memory interface chip 300 are integrated into the three-dimensional chip, so that the access link can be greatly shortened, and the calculation and processing load of a CPU or an upper system can be fully released. The near-memory architecture of the three-dimensional chip directly establishes the cross-module interconnection of the metal layers between the logic chip 100 and the memory chip 200 through three-dimensional heterogeneous integration, physical and electrical parameters follow the technological characteristics of a semiconductor manufacturing process, compared with the prior art through input and output and a memory wall, the delay of memory access exceeding two orders of magnitude and the power consumption overhead exceeding two orders of magnitude are greatly reduced, meanwhile, the high-order width interconnection of the logic chip 100 and the memory chip 200 is obviously increased compared with the CPU memory access bit width, and the memory access bit width can be increased to more than two to three orders of magnitude.
In some embodiments, the logic chip includes a plurality of logic processing units, and the memory chip includes a plurality of memory modules. Step S201 may include:
and controlling the target logic processing unit to perform storage access on the target storage module according to the control instruction, wherein the target logic processing unit comprises any logic processing unit of the logic chip, and the target storage module comprises any storage module of the storage chip. The target logic processing unit is a corresponding logic processing unit in the instruction sequence of the control instruction, and the target storage module is a corresponding storage module in the instruction sequence of the control instruction. Generally recorded in the instruction sequence of the control instruction are the address of the target logical processing unit and the address of the target memory module.
Step S301 may include:
and according to the control instruction, controlling the upper system to carry out storage access on the target logic processing unit of the three-dimensional chip, and/or controlling the upper system to carry out storage access on the target storage module.
In a third aspect of the embodiment of the present application, an electronic device is provided, and fig. 6 is a schematic block diagram of an electronic device provided in the embodiment of the present application, as shown in fig. 6, where the electronic device provided in the embodiment of the present application includes: the three-dimensional chip 1000 as described in the first aspect.
It should be noted that, the electronic device provided in the embodiment of the present application may be an integrated electronic device, an integrated electronic apparatus, a computer, a device including a computer function, or the like.
In the foregoing embodiments, the descriptions of the embodiments are focused on, and for those portions of one embodiment that are not described in detail, reference may be made to the related descriptions of other embodiments.
It will be appreciated by those skilled in the art that embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-readable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-readable program code embodied therein.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
Embodiments of the present application also provide a computer program product comprising computer software instructions that, when run on a processing device, cause the processing device to perform the flow of the method of access control of a three-dimensional chip.
The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the processes or functions in accordance with embodiments of the present application are produced in whole or in part. The computer may be a general purpose computer, a special purpose computer, a computer network, or other programmable apparatus. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by a wired (e.g., coaxial cable, fiber optic, digital Subscriber Line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.). Computer readable storage media can be any available media that can be stored by a computer or data storage devices such as servers, data centers, etc. that contain an integration of one or more available media. Usable media may be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., DVDs), or semiconductor media (e.g., solid State Disks (SSDs)), among others.
It will be clear to those skilled in the art that, for convenience and brevity of description, specific working procedures of the above-described systems, apparatuses and units may refer to corresponding procedures in the foregoing method embodiments, which are not repeated herein.
In the several embodiments provided in the present application, it should be understood that the disclosed apparatus, device and method may be implemented in other manners. For example, the apparatus embodiments described above are merely illustrative, e.g., the division of elements is merely a logical functional division, and there may be additional divisions of actual implementation, e.g., multiple elements or components may be combined or integrated into another system, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, which may be in electrical, mechanical or other form.
The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed over a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
In addition, each functional unit in the embodiments of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in software functional units.
The integrated units, if implemented in the form of software functional units and sold or used as stand-alone products, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present application may be embodied in essence or a part contributing to the prior art or all or part of the technical solution in the form of a software product stored in a storage medium, including several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods of the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (Random Access Memory, RAM), a magnetic disk, or an optical disk, or other various media capable of storing program codes.
The above embodiments are only for illustrating the technical solution of the present application, and not for limiting the same; although the application has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present application.
While preferred embodiments of the present description have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiments and all such alterations and modifications as fall within the scope of the disclosure.
It will be apparent to those skilled in the art that various modifications and variations can be made in the present specification without departing from the spirit or scope of the specification. Thus, if such modifications and variations of the present specification fall within the scope of the claims and the equivalents thereof, the present specification is also intended to include such modifications and variations.
Claims (15)
1. A three-dimensional chip, comprising:
a logic chip;
a memory chip;
a memory interface chip;
the logic chip, the memory chip and the memory interface chip are arranged in a stacked manner, and any two adjacent logic chips, the memory chip and the memory interface chip are connected through three-dimensional heterogeneous integration;
the memory interface chip provides a memory protocol for global access of the logic chip to the memory chip, and the memory interface chip provides a memory protocol for global access of a host system to the three-dimensional chip.
2. The three-dimensional chip according to claim 1, wherein the three-dimensional chip comprises:
the global memory access module is arranged on the logic chip or the memory interface chip;
the global memory access module is used for controlling the memory chip to be in a computing state or an idle state.
3. The three-dimensional chip of claim 2, wherein the memory interface chip comprises:
the global access bus is connected with the logic chip and is used for outputting a multi-path control signal so as to provide a storage protocol for the logic chip to perform global access to the storage chip and a storage protocol for the upper system to perform global access to the three-dimensional chip;
The multi-path control signal is used for controlling the logic chip to access the memory chip in a memory mode.
4. The three-dimensional chip according to any one of claims 1-3, wherein the logic chip comprises a plurality of logic processing units, the memory chip comprises a plurality of memory modules, the memory modules comprise at least one memory unit;
the logic processing units are interconnected one-to-one with the memory modules and/or the logic processing units are interconnected one-to-many with the memory modules.
5. The three-dimensional chip of claim 4, wherein the global access of the logic chip to the memory chip comprises a memory access of each of the logic processing units to all of the memory modules;
and the global access of the upper system to the three-dimensional chip comprises the storage access of the upper system to all the logic processing units and the storage access of the upper system to all the storage modules.
6. The three-dimensional chip according to claim 4, wherein the logic chip further comprises a storage routing unit, the storage routing unit being interconnected one-to-one with the storage module and/or the storage routing unit being interconnected one-to-many with the storage module;
The storage routing unit is used for determining the storage module corresponding to the address information as a target storage module according to the multipath control signals, so that the target storage module performs data writing and data reading based on the multipath control signals and the address information.
7. The three-dimensional chip of claim 4, further comprising:
a memory controller disposed within one of the logic chip, the memory chip, and the memory interface chip;
the memory controller is used for controlling global access to the logic chip, global memory access to the memory chip and connection state of a standard memory interface.
8. The three-dimensional chip of claim 7, wherein the memory controller is configured to control two or more of the logic processing units within the logic chip to access two or more of the memory modules in parallel.
9. The three-dimensional chip according to claim 4, wherein the memory chip further comprises a row-column decoding module, and the row-column decoding module is connected to the memory module in a one-to-one correspondence.
10. The three-dimensional chip according to claim 6, wherein the memory interface chip comprises:
the instruction analysis module is connected with the global access bus and is used for analyzing the control instruction to obtain a multi-path control signal;
the address decoding module is connected with the global access bus and is used for decoding the control instruction to obtain an address signal;
and the data serial-parallel conversion module is connected with the global access bus.
11. The three-dimensional chip of claim 1, wherein the logic processing unit comprises a programmable logic array.
12. The three-dimensional chip according to claim 1, wherein the memory interface chip and the logic chip are interconnected by three-dimensional heterogeneous integration, and wherein the logic chip and the memory chip are interconnected by three-dimensional heterogeneous integration; or alternatively, the first and second heat exchangers may be,
the logic chip is interconnected with the memory chip through three-dimensional heterogeneous integration, and the memory chip is interconnected with the memory interface chip through three-dimensional heterogeneous integration; or alternatively, the first and second heat exchangers may be,
The logic chip is interconnected with the memory interface chip through three-dimensional heterogeneous integration, and the memory interface chip is interconnected with the memory chip through three-dimensional heterogeneous integration.
13. An access control method for a three-dimensional chip, comprising:
sending a control instruction to the three-dimensional chip;
according to the control instruction, the control logic chip performs global access to the memory chip based on a memory protocol of the memory interface chip; and/or the number of the groups of groups,
and according to the control instruction, performing global access on the three-dimensional chip based on a storage protocol of the storage interface chip.
14. The access control method of the three-dimensional chip according to claim 13, wherein the logic chip includes a plurality of logic processing units, and the memory chip includes a plurality of memory modules;
the controlling the logic chip to globally access the memory chip based on the memory protocol of the memory interface chip according to the control instruction includes:
according to the control instruction, controlling a target logic processing unit to perform storage access on a target storage module, wherein the target logic processing unit comprises any logic processing unit of the logic chip, and the target storage module comprises any storage module of the storage chip;
The global access to the three-dimensional chip based on the memory protocol of the memory interface chip according to the control instruction comprises:
and according to the control instruction, controlling the upper system to perform storage access on the target logic processing unit of the three-dimensional chip, and/or controlling the upper system to perform storage access on the target storage module.
15. An electronic device, comprising:
the three-dimensional chip of any one of claims 1-12.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN202210615016.8A CN117194288A (en) | 2022-05-31 | 2022-05-31 | Three-dimensional chip, access control method and electronic equipment |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN202210615016.8A CN117194288A (en) | 2022-05-31 | 2022-05-31 | Three-dimensional chip, access control method and electronic equipment |
Publications (1)
Publication Number | Publication Date |
---|---|
CN117194288A true CN117194288A (en) | 2023-12-08 |
Family
ID=89004023
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN202210615016.8A Pending CN117194288A (en) | 2022-05-31 | 2022-05-31 | Three-dimensional chip, access control method and electronic equipment |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN117194288A (en) |
-
2022
- 2022-05-31 CN CN202210615016.8A patent/CN117194288A/en active Pending
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US11094371B2 (en) | Memory device for processing operation and method of operating the same | |
JP5231642B2 (en) | Independently controlled virtual memory device in memory module | |
KR101600447B1 (en) | Configurable bandwidth memory devices and methods | |
KR101525282B1 (en) | Switched interface stacked-die memory architecture | |
CN113126898A (en) | Memory device, operating method thereof, and operating method of memory controller | |
KR20200108768A (en) | Memory Device performing calculation process and Operation Method thereof | |
US20090097348A1 (en) | Integrated circuit including a memory module having a plurality of memory banks | |
CN114709205B (en) | Three-dimensional stacked chip and data processing method thereof | |
US20240099034A1 (en) | Llc chip, cache system and method for reading and writing llc chip | |
US20230051126A1 (en) | Signal routing between memory die and logic die for performing operations | |
US11869626B2 (en) | Internal and external data transfer for stacked memory dies | |
US11355181B2 (en) | High bandwidth memory and system having the same | |
KR101183739B1 (en) | Integrated circuit with multiported memory supercell and data path switching circuitry | |
US20160358671A1 (en) | Memory chip and stack type semiconductor apparatus including the same | |
US11861369B2 (en) | Processing-in-memory (PIM) device | |
JPH08297966A (en) | Memory cell array of multibank structure | |
US11385837B2 (en) | Memory system | |
CN103823773A (en) | Memory system and operating method thereof | |
CN110046111B (en) | Fusion memory device and method thereof | |
CN117194288A (en) | Three-dimensional chip, access control method and electronic equipment | |
CN216119560U (en) | LLC chip and cache system | |
JPWO2008038647A1 (en) | RAID system and data transfer method in RAID system | |
US20230033179A1 (en) | Accumulator and processing-in-memory (pim) device including the accumulator | |
CN117198350A (en) | Control circuit, control method and related equipment of memory chip | |
CN112835513A (en) | Control data read-write device and method |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
CB02 | Change of applicant information | ||
CB02 | Change of applicant information |
Country or region after: China Address after: 710075 4th floor, block a, No.38, Gaoxin 6th Road, Zhangba Street office, Gaoxin District, Xi'an City, Shaanxi Province Applicant after: Xi'an Ziguang Guoxin Semiconductor Co.,Ltd. Address before: 710075 4th floor, block a, No.38, Gaoxin 6th Road, Zhangba Street office, Gaoxin District, Xi'an City, Shaanxi Province Applicant before: XI''AN UNIIC SEMICONDUCTORS Co.,Ltd. Country or region before: China |