CN117198210A - Display panel and driving method thereof - Google Patents

Abstract

The invention discloses a display panel and a driving method thereof, wherein the display panel comprises a plurality of pixel circuits which are arranged in an array mode, and a first scanning line and a second scanning line which are connected with the pixel circuits, the pixel circuits comprise a driving module, a biasing module, a first initializing module and a light emitting module, and the biasing module is used for responding to a first scanning signal to be conducted in a voltage biasing stage so as to transmit biasing voltage to a first end or a second end of the driving module; the first initialization module is used for responding to the second scanning signal to be conducted in a first initialization stage so as to transmit a first initialization voltage to a first end of the light emitting module; the frequency of the second scanning signal is adjustable. According to the scheme, the split screen phenomenon caused by different initialization degrees of the first poles of the light emitting modules in different areas can be improved.

Description

Display panel and driving method thereof

Technical Field

The present invention relates to the field of display technologies, and in particular, to a display panel and a driving method thereof.

Background

With the development of display technology, the requirements of display quality of display panels are increasing.

At present, the existing display panel has the phenomenon of uneven display brightness, presents a visual effect of split screen, and seriously reduces the display quality.

Disclosure of Invention

The invention provides a display panel and a driving method thereof, which are used for improving the split screen phenomenon in the display process and improving the display quality.

According to an aspect of the present invention, there is provided a display panel including a plurality of pixel circuits arranged in an array manner, and first and second scan lines connected to the pixel circuits, the pixel circuits including: the device comprises a driving module, a biasing module, a first initializing module and a light emitting module;

the driving module is connected between the first power line and the first end of the light emitting module, the second end of the light emitting module is connected with the second power line, and the driving module is used for driving the light emitting module to emit light in a display period;

the bias module is connected with the driving module and is used for responding to a first scanning signal transmitted on a first scanning line connected with the control end of the bias module in a voltage bias stage to transmit bias voltage to a first end or a second end of the driving module;

the first initialization module is connected with the first end of the light-emitting module and is used for responding to a second scanning signal transmitted on a second scanning line connected with the control end of the first initialization module in a first initialization stage to transmit a first initialization voltage to the first end of the light-emitting module;

The frequency of the second scanning signal is adjustable to eliminate the load change caused by the first scanning signal.

Optionally, in a display period, a pulse width of the second scan signal is smaller than or equal to a pulse width of the first scan signal, and the pulse width of the second scan signal corresponds to a total time of the plurality of rows of pixel circuits in the first initialization stage.

Optionally, in a display period, the number of pulses of the second scan signal is greater than or equal to the number of pulses of the first scan signal.

Optionally, in a display period, the first scan signal includes a plurality of first pulse signals, the second scan signal includes a plurality of second pulse signals, a start time of the second pulse signals is after a start time of the first pulse signals, or the start time of the second pulse signals is the same as the start time of the first pulse signals, and an end time of the second pulse signals is before an end time of the first pulse signals, or the end time of the second pulse signals is the same as the end time of the first pulse signals.

Optionally, the second pulse signal includes a plurality of sub pulse signals, the start time of the first sub pulse signal is after the start time of the first pulse signal, or the start time of the first sub pulse signal is the same as the start time of the first pulse signal, and the end time of the last sub pulse signal is before the end time of the first pulse signal, or the end time of the last sub pulse signal is the same as the end time of the first pulse signal.

Optionally, the frequency of the second scan signal is greater than the refresh frequency of the display panel.

Optionally, the frequency of the first scan signal is greater than the refresh frequency of the display panel.

Optionally, the voltage bias phase coincides with the first initialization phase during a display period.

Optionally, the first initialization module includes a first transistor, a gate of the first transistor is connected to the second scan line, a first pole of the first transistor is connected to the first initialization signal line, a second pole of the first transistor is connected to the first end of the light emitting module, and the first transistor is used for transmitting a first initialization voltage on the first initialization signal line to the first end of the light emitting module in the first initialization stage;

the bias module comprises a second transistor, a grid electrode of the second transistor is connected with the first scanning line, a first pole of the second transistor is connected with the bias voltage signal line, a second pole of the second transistor is connected with the first end or the second end of the driving module, and the second transistor is used for transmitting bias voltage on the bias voltage signal line to the first end or the second end of the driving module in a voltage bias stage;

optionally, the channel type of the second transistor is different from the channel type of the first transistor;

Optionally, the first transistor is a metal oxide transistor.

Optionally, the pixel circuit further includes:

the data writing module is connected with the first end of the driving module and is used for transmitting data voltage to the driving module in a data writing stage;

the compensation module is connected between the second end and the control end of the driving module and is used for compensating the threshold voltage of the driving module;

the second initialization module is connected between the second initialization signal line and the second end of the driving module and is used for transmitting a second initialization voltage on the second initialization signal line to the control end of the driving module in a second initialization stage;

the first light-emitting control module is connected between the first power line and the first end of the driving module, and the second light-emitting control module is connected between the second end of the driving module and the first end of the light-emitting module;

the storage module is connected with the control end of the driving module and is used for storing the voltage of the control end of the driving module;

optionally, the driving module includes a third transistor, the data writing module includes a fourth transistor, the compensation module includes a fifth transistor, the second initialization module includes a sixth transistor, the first light emitting control module includes a seventh transistor, the second light emitting control module includes an eighth transistor, the light emitting module includes a light emitting diode, and the storage module includes a capacitor;

The grid electrode of the fourth transistor is connected with the third scanning line, the first electrode of the fourth transistor is connected with the data line, the second electrode of the fourth transistor is connected with the first electrode of the third transistor, the grid electrode of the fifth transistor is connected with the fourth scanning line, the first electrode of the fifth transistor is connected with the second electrode of the third transistor, and the second electrode of the fifth transistor is connected with the grid electrode of the third transistor;

a gate of the sixth transistor is connected to the fifth scan line, a first pole of the sixth transistor is connected to the second initialization signal line, and a second pole of the sixth transistor is connected to the first pole of the fifth transistor;

the grid electrode of the seventh transistor and the grid electrode of the eighth transistor are both connected with a light-emitting control signal line, the first electrode of the seventh transistor is connected with the first power line, the second electrode of the seventh transistor is connected with the first electrode of the third transistor, the first electrode of the eighth transistor is connected with the second electrode of the third transistor, the second electrode of the eighth transistor is connected with the first electrode of the light-emitting diode, and the second electrode of the light-emitting diode is connected with the second power line;

the first pole of the capacitor is connected with the first power line, and the second pole of the capacitor is connected with the grid electrode of the third transistor.

According to another aspect of the present invention, there is provided a driving method of a display panel including a plurality of pixel circuits arranged in an array manner, and first and second scan lines connected to the pixel circuits; the pixel circuit includes: the device comprises a driving module, a biasing module, a first initializing module and a light emitting module, wherein the driving module is connected between a first power line and a first end of the light emitting module, a second end of the light emitting module is connected with a second power line, the biasing module is connected with the driving module, and the first initializing module is connected with the first end of the light emitting module;

The driving method of the display panel comprises the following steps:

in a voltage bias stage in a display period, controlling bias modules in a plurality of rows of pixel circuits to be simultaneously turned on in response to a first scanning signal transmitted on a first scanning line, and transmitting bias voltages to a first end or a second end of a corresponding driving module;

in a first initialization stage in a display period, controlling a first initialization module in a plurality of rows of pixel circuits to simultaneously respond to a second scanning signal transmitted on a second scanning line to be conducted, and transmitting a first initialization voltage to a first end of a corresponding light emitting module;

in a lighting stage in a display period, controlling the driving module to generate driving current so as to drive the lighting module to emit light;

the frequency of the second scanning signal is adjustable to eliminate the load change caused by the first scanning signal.

Optionally, in a display period, the pulse width of the second scan signal is smaller than or equal to the pulse width of the first scan signal.

Optionally, the frequency of the second scanning signal is greater than the frequency of the first scanning signal.

According to the technical scheme provided by the embodiment of the invention, the initialization of the first end of the light emitting module is independently controlled through the second scanning signal, and the initialization of the first end or the second end of the driving module is independently controlled through the first scanning signal, so that the frequency of the second scanning signal is set to be adjustable. Compared with the scheme in the related art, even if the pulse of the second scanning signal enters the blank phase, the initialization frequency and degree of the voltage of the first end of the light emitting module are reduced by adjusting the frequency of the second scanning signal, so that the voltage difference of the first ends of the light emitting modules corresponding to different pixel rows in the display panel can be reduced in different display phases in a display period, the light emitting brightness difference of each row of pixels in the plane in the condition that the pulse of the second scanning signal enters the blank phase and the pulse of the pixels in the pixel of the light emitting module do not enter the blank phase is smaller, the uniformity of the display brightness is improved, and the split screen phenomenon caused by different initialization degrees of the first poles of the light emitting modules in different areas is improved.

It should be understood that the description in this section is not intended to identify key or critical features of the embodiments of the invention or to delineate the scope of the invention. Other features of the present invention will become apparent from the description that follows.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic diagram of a pixel circuit in the related art;

FIG. 2 is a schematic diagram of a display result of a display panel in the related art at a certain moment;

FIG. 3 is a schematic diagram of a display result of the display panel shown in FIG. 2 at another time;

fig. 4 is a schematic structural diagram of a display panel according to an embodiment of the present invention;

fig. 5 is a schematic structural diagram of a pixel circuit according to an embodiment of the present invention;

FIG. 6 is a timing diagram of a first scan signal and a second scan signal according to an embodiment of the present invention;

Fig. 7 is a schematic diagram of a display result of a display panel at a certain moment according to an embodiment of the present invention;

fig. 8 is a schematic diagram of a display result of a display panel at another moment according to an embodiment of the present invention;

fig. 9 is a schematic diagram of a display result of another display panel provided in an embodiment of the present invention at a certain moment;

FIG. 10 is a timing diagram of another first scan signal and a second scan signal according to an embodiment of the present invention;

fig. 11 is a schematic structural diagram of another pixel circuit according to an embodiment of the present invention;

fig. 12 is a schematic diagram of a driving timing diagram of a pixel circuit according to an embodiment of the present invention;

FIG. 13 is a schematic diagram of a driving timing diagram of another pixel circuit according to an embodiment of the present invention;

fig. 14 is a flowchart of a driving method of a display panel according to an embodiment of the present invention.

Detailed Description

In order that those skilled in the art will better understand the present invention, a technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, shall fall within the scope of the present invention.

It should be noted that the terms "first," "second," and the like in the description and the claims of the present invention and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the invention described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

As described in the background art, the existing display panel has a phenomenon of split display, and the display quality is reduced. The inventors found that the above problems occur for the following reasons:

the corresponding refresh frequencies of the display panel in different modes of operation are different. Currently, the low refresh rate is achieved by frame skipping on the basis of the high refresh rate, one display period includes a write frame and a hold frame, and the refresh rate can be changed by inserting the hold frame after the write frame and by adjusting the duration of the hold frame. A display panel generally includes a pixel circuit for driving a light emitting device to emit light, and in low frequency display, a first electrode or a second electrode of a driving transistor in the pixel circuit is in a biased state for a long time, resulting in a shift in characteristics of the driving transistor, such that the driving transistor has a difference in display luminance between a sustain frame and a write frame, thereby causing a flicker phenomenon. In order to solve the above-mentioned problems in the related art, it is common to voltage bias the first pole or the second pole of the driving transistor to improve the threshold characteristics of the driving transistor.

Fig. 1 is a schematic structural diagram of a pixel circuit in the related art, referring to fig. 1, the pixel circuit includes a first transistor M1, a second transistor M2, a third transistor M3, a seventh transistor M7, and an eighth transistor M8, wherein the third transistor M3 is a driving transistor. In the initialization stage, the first transistor M1 is turned on in response to the scan signal SP, and transmits an initialization voltage Vref to the first pole of the light emitting diode D1 to initialize the anode of the light emitting diode D1, and at the same time, the second transistor M2 is turned on in response to the scan signal SP, and transmits a bias voltage Vcom to the first pole of the third transistor M3, and resets the voltage of the first pole of the third transistor M3 to change the bias state of the third transistor M3, thereby improving the threshold characteristic of the third transistor M3, reducing the difference between the brightness in the holding frame and the writing frame, and improving the uniformity of the display brightness.

In the practical application process, the scan signal SP simultaneously controls the anode initialization of the light emitting diode D1 and the voltage bias of the third transistor M3, and the scan signal SP is a high-frequency signal, and the scan signal SP includes a plurality of pulse signals. For ease of understanding, specific examples are described. Fig. 2 is a schematic diagram of a display result of a display panel in the related art at a certain time, fig. 3 is a schematic diagram of a display result of the display panel in fig. 2 at another time, referring to fig. 1-3, a plurality of rows of pixel circuits are disposed in a display area a of the display panel, a scan signal SP includes a plurality of pulses in a display period, and in an active level of the scan signal SP, a first transistor M1 and a second transistor M2 are respectively turned on in response to pulse signals of the scan signal, and a first pole of a light emitting diode D1 and a first pole of a third transistor M3 are initialized. Taking the example that the scan signal SP includes 3 pulses, the pulse width is associated with the scan time of the pixel rows, where the pulse width of the scan signal SP may correspond to a plurality of rows (e.g., the scan time of 20 rows of pixel circuits), after the pixel circuits are stable in operation, the pixel circuits having three regions in the display area a perform the initialization of the first pole of the light emitting diode D1 and the first pole of the third transistor M3 in the same stage of a display period, that is, the 20 rows of pixel circuits in the first region 11, the 20 rows of pixel circuits in the second region 12, and the 20 rows of pixel circuits in the third region 13 respectively respond to the three pulses of the scan signal SP to initialize the respective corresponding light emitting diodes D1, and at this time, the load in the display area a is the load corresponding to the 60 rows of pixel circuits.

As shown in fig. 3, as time goes by, a pulse sequence of the scan signal SP enters a Blank phase, where the display panel is in a Blank scanning state, and may specifically correspond to a Blank area B, where the Blank area B does not actually exist on the display panel, and is only represented in a time dimension. That is, when one pulse timing of the scan signal SP enters the blank phase, only the fourth area 21 and the fifth area 22 are being scanned in the display area a, and the load in the display area a is the load corresponding to the 40 rows of pixel circuits. Therefore, a phenomenon that the pixel circuits of two areas in the display panel are initialized at one stage in a display period and the pixel circuits of three areas are initialized at other stages occurs, which results in different numbers of lines of the scanning circuits corresponding to the pixel rows and the pixel circuits driven by the initialization signal lines providing the initialization voltage Vref in different display stages, and different loads exist in the plane. When one pulse timing of the scan signal SP enters the blank phase, the in-plane load is smaller, so that the initialization degree of the pixel circuits in the fourth area 21 and the fifth area 22 corresponding to the first pole of the light emitting diode D1 is more sufficient, the voltage difference between the first pole and the second pole of the light emitting diode D1 in the fourth area 21 and the fifth area 22 is different from the voltage difference between the light emitting diodes D1 in other areas, and the display brightness in the fourth area 21 and the fifth area 22 is different from the display brightness in other areas, thereby dividing the display area a into three parts at the fourth area 21 and the fifth area 22 and visually presenting the effect of three split screens.

In view of the foregoing, embodiments of the present invention provide a display panel. Fig. 4 is a schematic structural diagram of a display panel according to an embodiment of the present invention, and fig. 5 is a schematic structural diagram of a pixel circuit according to an embodiment of the present invention, referring to fig. 4 and 5, the display panel 100 includes a plurality of pixel circuits PX arranged in an array manner, and a first scan line G1 and a second scan line G2 connected to the pixel circuits PX. The first scan line G1 is used for transmitting the first scan signal S1, and the second scan line G2 is used for transmitting the second scan signal S2. The first scanning line G1 (1) is connected to the pixel circuit PX in the first pixel row, the second first scanning line G1 (2) is connected to the pixel circuit PX in the second pixel row, the third first scanning line G1 (3) is connected to the pixel circuit PX in the third pixel row … …, and the nth first scanning line G1 (n) is connected to the pixel circuit PX in the nth pixel row; the first second scanning line G2 (1) is connected to the pixel circuit PX in the first pixel row, the second scanning line G2 (2) is connected to the pixel circuit PX in the second pixel row, the third second scanning line G2 (3) is connected … … nth second scanning line G2 (n) is connected to the pixel circuit PX in the nth pixel row.

Wherein, the first scan line G1 and the second scan line G2 both extend along the X direction. The display panel 100 further includes a data line DL extending along the Y direction, and the data line DL is used for transmitting the data voltage Vdata to realize different gray scale display of the display panel 100.

The pixel circuit includes: a driving module 110, a biasing module 120, a first initializing module 130, and a light emitting module 140; the driving module 110 is connected between the first power line L1 and the first end of the light emitting module 140, the second end of the light emitting module 140 is connected with the second power line L2, and the driving module 110 is used for driving the light emitting module 140 to emit light in a display period; the bias module 120 is connected to the driving module 110, and the bias module 120 is configured to be turned on in response to a first scan signal S1 transmitted on a first scan line G1 connected to a control terminal thereof in a voltage bias stage, so as to transmit a bias voltage Vcom to a first terminal D or a second terminal S of the driving module 110; the first initialization module 130 is connected to the first end of the light emitting module 140, and the first initialization module 130 is configured to be turned on in response to the second scan signal S2 transmitted on the second scan line G2 connected to the control end thereof in the first initialization stage, so as to transmit the first initialization voltage Vref1 to the first end of the light emitting module 140. The frequency of the second scan signal S2 is adjustable to eliminate the load variation caused by the first scan signal.

Optionally, in a display period, the pulse width of the second scan signal S2 is smaller than or equal to the pulse width of the first scan signal S1, and the pulse width of the second scan signal S2 corresponds to the total time of the plurality of rows of pixel circuits in the first initialization stage.

Specifically, the first power line L1 is configured to transmit the first power voltage VDD, the second power line L2 is configured to transmit the second power voltage VSS, the first power voltage VDD may be greater than the second power voltage VSS, and the driving module 110 drives the light emitting module 140 to emit light when the connection path between the first power line L1 and the second power line L2 is turned on. The operation of the pixel circuit at least comprises a first initialization phase, a voltage bias phase and a light emitting phase. In the first initialization stage, the first initialization module 130 is turned on in response to the second scan signal S2, and transmits the first initialization voltage Vref1 to the first terminal of the light emitting module 140 to initialize the potential of the first terminal of the light emitting module 140. In the voltage bias phase, the bias module 120 is turned on in response to the first scan signal S1, and transmits the bias voltage Vcom to the first terminal D of the driving module 110, and resets the potential of the first terminal D of the driving module 110 to adjust the threshold characteristic of the driving module 110. In the light emitting stage, the connection path between the first and second power lines L1 and L2 is controlled to be conductive so that the driving module 110 can drive the light emitting module 120 to emit light.

In the related art, the first initialization module 130 and the bias module 120 share one scan signal, and in the present embodiment, the first initialization module 130 and the bias module 120 are connected to different scan lines, respectively, to control the two separately. And the pulse width of the second scan signal S2 is set smaller than the pulse width of the first scan signal S1, so as to reduce the number of rows of the pixel circuit PX corresponding to the pulse width of the second scan signal S2. Fig. 6 is a timing diagram of a first scan signal and a second scan signal according to an embodiment of the present invention, referring to fig. 6, in a display period, the first scan signal S1 includes a plurality of first pulse signals, the second scan signal S2 includes a plurality of second pulse signals, a start time of the second pulse signals is after a start time of the first pulse signals, or a start time of the second pulse signals is the same as the start time of the first pulse signals, and an end time of the second pulse signals is before an end time of the first pulse signals, or an end time of the second pulse signals is the same as the end time of the first pulse signals. Taking the first scan signal S1 and the second scan signal S2 as 3 pulse signals as an example, in a display period, the pulse width of the second scan signal S2 is W1, the pulse width of the first scan signal S1 is W2, and W1 is less than W2, that is, the duration of one pulse of the second scan signal S2 corresponds to the total duration of the initialization of the light emitting modules 140 of fewer pixel rows.

Fig. 7 is a schematic diagram of a display result of a display panel provided by an embodiment of the present invention at a certain time, fig. 8 is a schematic diagram of a display result of a display panel provided by an embodiment of the present invention at another time, and referring to fig. 6 to 8, by way of example, by adjusting the pulse width of the second scan signal S2, the pulse width of the second scan signal S2 corresponds to the scan time of the 5 rows of pixel circuits PX, that is, the first area 11 includes the 5 rows of pixel circuits PX, the second area 12 includes the 5 rows of pixel circuits PX, and the third area 13 also includes the 5 rows of pixel circuits PX. Thus, in a display period of a display period, the in-plane load is normally the load corresponding to the 15 rows of pixel circuits. When one pulse of the second scan signal S2 scans to the blank phase, the fourth area 21 and the fifth area 22 within the display area a respectively include 5 lines of pixel circuits PX, that is, an in-plane load is a load corresponding to 10 lines of pixel circuits. Compared with the difference of loads corresponding to 60 rows and 40 rows of pixel circuits PX, the difference of loads corresponding to 15 rows and 10 rows of pixel circuits PX is smaller, and the initialization degree of the first end of the light emitting module 140 can be reduced, so that the voltage difference between the first end and the second end of the light emitting module 140 in different areas of the display panel 100 in different display stages in a display period is reduced, and the phenomenon of uneven display caused by different initialization degrees of the light emitting module 140 in different display areas is facilitated to be relieved.

In this embodiment, the pulse width of the second scan signal S2 may be equal to the pulse width of the first scan signal S1. Since the second scan signal S2 and the first scan signal S1 are not associated, the pulse widths of the first scan signal S1 and the second scan signal S2 can be reduced at the same time, and the above effects can be achieved as well, and the description is omitted.

According to the technical scheme provided by the embodiment of the invention, the initialization of the first end of the light emitting module is independently controlled through the second scanning signal, and the initialization of the first end or the second end of the driving module is independently controlled through the first scanning signal, and the pulse width of the second scanning signal is set to be smaller than or equal to the pulse width of the first scanning signal in a display period. Compared with the scheme in the related art, even if the pulse of the second scanning signal enters the blank phase, the initialization degree of the voltage of the first end of the light emitting module can be reduced by adjusting the frequency of the second scanning signal, so that the voltage difference of the first ends of the light emitting modules corresponding to different pixel rows in the display panel can be reduced in different display phases in a display period, the light emitting brightness difference of each row of pixels in the plane in the condition that the pulse of the second scanning signal enters the blank phase and the pulse of the pixels in the condition that the pixels do not enter the blank phase is smaller, the uniformity of the display brightness is improved, and the split screen phenomenon caused by the different initialization degrees of the first poles of the light emitting modules in different areas is improved.

Alternatively, in another embodiment provided by the present invention, the frequency of the second signal S2 may be changed more to improve the split screen phenomenon. Fig. 9 is a schematic diagram of a display result of another display panel provided by the embodiment of the invention at a certain moment, and in combination with fig. 9, in the embodiment, the number of pulses of the second scan signal S2 is greater than or equal to the number of pulses of the first scan signal S1 in a display period. By increasing the number of pulses of the second scan signal S2, the display area a can be initialized by controlling the light emitting modules 140 of the corresponding pixel rows by the pulse signals with a fixed number at any stage or time in the display period, so that the load in the plane will not change in a display period, the voltage initialization degree of the first ends of the light emitting modules 140 corresponding to the pixel rows is the same, and the split screen phenomenon can be eliminated.

According to the technical scheme provided by the embodiment, the frequency of the second scanning signal S2 is increased by increasing the pulse number of the second scanning signal S2, and the first end of the light emitting module 140 is reset at high frequency, so that the brightness uniformity in the display area A is improved.

Alternatively, fig. 10 is a timing diagram of another first scan signal and a second scan signal according to an embodiment of the present invention, and referring to fig. 9 and 10, the frequency of the second scan signal S2 may be increased by splitting one pulse of the second scan signal S2 into two pulses. For example, when the number of pulses of the first scan signal S1 is the same as that of the second scan signal S2 and the pulse width is 4H, in order to increase the frequency of the second scan signal S2, one pulse signal of the second scan signal S2 may be split into two sub-pulse signals, wherein the pulse width of one sub-pulse signal is 1H and the pulse width of the other sub-pulse signal is 2H. And the start time of the first sub-pulse signal is the same as the start time of the first pulse signal of the first scan signal S1, and the end time of the second sub-pulse signal is the same as the end time of the first pulse signal.

Of course, in other embodiments, the start time of the first sub-pulse signal may be after the start time of the first pulse signal of the first scan signal S1, and the end time of the second sub-pulse signal may be before the end time of the first pulse signal, so as to further reduce the pulse width of the second scan signal S2, which is beneficial to better improve the uniformity of the display brightness.

Optionally, one pulse signal of the second scan signal S2 may be split into more sub-pulse signals, so as to flexibly adjust the frequency of the second scan signal S2 to better satisfy the visual effect. At this time, the start time of the first sub-pulse signal of the second scan signal S2 is after the start time of the first pulse signal, or the start time of the first sub-pulse signal is the same as the start time of the first pulse signal, and the end time of the last sub-pulse signal is before the end time of the first pulse signal, or the end time of the last sub-pulse signal is the same as the end time of the first pulse signal.

With continued reference to fig. 5, the pixel circuit further includes:

the data writing module 150 is connected to the first end D of the driving module 110, and the data writing module 150 is configured to transmit the data voltage Vdata to the driving module 110 during the data writing stage, so that the data voltage Vdata is written to the control end G of the driving module 110.

The compensation module 160 is connected between the second terminal S and the control terminal G of the driving module 110, and the compensation module 160 is used for compensating the threshold voltage of the driving module 110.

The storage module 170 is connected to the control terminal G of the driving module 110, and the storage module 170 is used for storing the voltage of the control terminal G of the driving module 110.

The light emitting control module 180 is connected in series with the driving module 110 between the first power line L1 and the second power line L2.

Fig. 11 is a schematic structural diagram of another pixel circuit according to an embodiment of the present invention, referring to fig. 5 and 11, the pixel circuit further includes a second initialization module 190 connected between the second initialization signal line and the second terminal D of the driving module 110, where the second initialization module 190 is configured to transmit the second initialization voltage Vref2 on the second initialization signal line to the control terminal G of the driving module 110 in the second initialization stage.

Alternatively, the light emitting control module 180 includes a first light emitting control module 181 and a second light emitting control module 182, the first light emitting control module 181 is connected between the first power line L1 and the first end S of the driving module 110, and the second light emitting control module 182 is connected between the second end D of the driving module 110 and the first end of the light emitting module 140.

The first initialization module 130 includes a first transistor M1, a gate of the first transistor M1 is connected to the second scan line, a first pole of the first transistor M1 is connected to the first initialization signal line, a second pole of the first transistor M1 is connected to the first end of the light emitting module 140, and the first transistor M1 is configured to transmit a first initialization voltage Vref1 on the first initialization signal line to the first end of the light emitting module 140 in a first initialization stage; the bias module 120 includes a second transistor M2, a gate of the second transistor M2 is connected to the first scan line, a first pole of the second transistor M2 is connected to the bias voltage signal line, a second pole of the second transistor M2 is connected to the first terminal S or the second terminal D of the driving module 110, and the second transistor M2 is configured to transmit the bias voltage Vcom on the bias voltage signal line to the first terminal S or the second terminal D of the driving module 110 in the voltage bias stage.

The driving module 110 includes a third transistor M3, the data writing module 150 includes a fourth transistor M4, the compensation module 160 includes a fifth transistor M5, the second initialization module 190 includes a sixth transistor M6, the first light emitting control module 181 includes a seventh transistor M7, the second light emitting control module 182 includes an eighth transistor M8, the light emitting module 140 includes a light emitting diode D1, and the storage module 170 includes a capacitor C. The gate of the fourth transistor M4 is connected to the third scan line, the first pole of the fourth transistor M4 is connected to the data line, the second pole of the fourth transistor M4 is connected to the first pole of the third transistor M3, the gate of the fifth transistor M5 is connected to the fourth scan line, the first pole of the fifth transistor M5 is connected to the second pole of the third transistor M3, and the second pole of the fifth transistor M5 is connected to the gate of the third transistor M3; a gate of the sixth transistor M6 is connected to the fifth scan line, a first pole of the sixth transistor M6 is connected to the second initialization signal line, and a second pole of the sixth transistor M6 is connected to a first pole of the fifth transistor M5; the grid electrode of the seventh transistor M7 and the grid electrode of the eighth transistor M8 are both connected with a light-emitting control signal line, the first pole of the seventh transistor M7 is connected with the first power line L1, the second pole of the seventh transistor M7 is connected with the first pole of the third transistor M3, the first pole of the eighth transistor M8 is connected with the second pole of the third transistor M3, the second pole of the eighth transistor M8 is connected with the first pole of the light-emitting diode D1, and the second pole of the light-emitting diode D1 is connected with the second power line L2; a first pole of the capacitor C is connected to the first power line L1, and a second pole of the capacitor C is connected to the gate of the third transistor M3. Here, the first pole of the light emitting diode D1 may be an anode and the second pole may be a cathode. The first transistor M1, the fifth transistor M5 and the sixth transistor M6 may be N-type transistors or P-type transistors, and the remaining transistors are P-type transistors. Fig. 11 only shows the case where the first transistor M1, the fifth transistor M5 and the sixth transistor M6 are N-type transistors, for example, the first transistor M1, the fifth transistor M5 and the sixth transistor M6 are all metal oxide transistors, which has the advantage that the leakage problem of the third transistor M3 can be reduced, which is beneficial to maintaining the stability of the gate voltage of the third transistor M3.

Fig. 12 is a schematic diagram of a driving timing diagram of a pixel circuit according to an embodiment of the present invention, which is applicable to the pixel circuit shown in fig. 11. Referring to fig. 11 and 12, the working process of the pixel circuit provided in this embodiment at least includes a second initialization stage t1, a data writing stage t2, a first initialization stage t3 (coinciding with the voltage bias stage) and a light emitting stage t4.

In the second initialization stage t1, the first scan signal S1 is at a high level, the second scan signal S2 is at a low level, the third scan signal S3 is at a high level, the fourth scan signal S4 is at a high level, the fifth scan signal S5 is at a high level, and the emission control signal EM is at a high level. Accordingly, the fifth transistor M5 and the sixth transistor M6 are turned on, the second initialization voltage Vref2 on the second initialization signal line is transmitted to the gate of the third transistor M3 via the sixth transistor M6 and the fifth transistor M5, the gate voltage of the third transistor M3 is initialized, and the third transistor M3 is turned on. The second initialization voltage Vref2 is also transmitted to the second and first poles D and S of the third transistor M3 via the sixth transistor M6, and initializes the second and first poles D and S of the third transistor M3.

In the data writing stage t2, the first scan signal S1 is at a high level, the second scan signal S2 is at a low level, the third scan signal S3 is at a low level, the fourth scan signal S4 is at a high level, the fifth scan signal S5 is at a low level, and the emission control signal EM is at a high level. Therefore, the fourth transistor M4 and the fifth transistor M5 are turned on, the data voltage Vdata is written to the gate of the third transistor M3 through the fourth transistor M4, the third transistor M3 and the fifth transistor M5, the gate voltage of the third transistor M3 is associated with the data voltage Vdata and the threshold voltage of the third transistor M3, and the threshold compensation of the third transistor M3 is realized. The capacitor C stores the gate voltage of the third transistor M3.

In the first initialization stage t3, the first scan signal S1 is low, the second scan signal S2 is high, the third scan signal S3 is high, the fourth scan signal S4 is low, the fifth scan signal S5 is low, and the emission control signal EM is high. Therefore, the first transistor M1 and the second transistor M2 are turned on, and the first initialization voltage Vref1 on the first initialization signal line is transmitted to the first pole of the light emitting diode D1 via the first transistor M1, and initializes the first pole of the light emitting diode D1. Meanwhile, the reference voltage Vcom on the reference voltage signal line is transmitted to the first pole of the third transistor M3 through the second transistor M2, and the voltage of the first pole of the third transistor M3 is reset to change the bias state of the third transistor M3, so that the threshold characteristics of the third transistor M3 can be kept stable under different gray scales, and uniformity of the driving current generated by the third transistor M3 is improved.

In the light emitting stage t4, the first scan signal S1 is at a high level, the second scan signal S2 is at a low level, the third scan signal S3 is at a high level, the fourth scan signal S4 is at a low level, the fifth scan signal S5 is at a low level, and the light emission control signal EM is at a low level. Accordingly, the seventh transistor M7 and the eighth transistor M8 are turned on, the connection path between the first power line L1 and the second power line L2 is turned on, and the third transistor M3 generates a driving current to drive the light emitting diode D1 to emit light.

It should be understood that the driving timing shown in fig. 12 is the driving timing of one row of pixel circuits, and in this embodiment, the pulse width of the second scanning signal S2 corresponds to the total time for initializing the first poles of the light emitting diodes D1 by the plurality of rows of pixel circuits. By adjusting the pulse width of the second scanning signal S2, the load corresponding to the first initializing voltage Vref1 can be smaller, and even if a certain pulse of the second scanning signal S2 just scans to a blank stage, the first pole initializing degree of the light emitting diode D1 corresponding to the pixel row can be ensured to be close due to smaller in-plane load variation, so that the problem of uneven display brightness caused by larger initializing degree difference of the first pole of the light emitting diode D1 in different display stages can be solved, and the split screen phenomenon can be reduced.

On the basis of the above technical solutions, optionally, the frequency of the second scan signal S2 is greater than the refresh frequency of the display panel, and the frequency of the second scan signal S2 is greater than the frequency of the first scan signal S1. Fig. 13 is a schematic diagram of a driving timing diagram of another pixel circuit according to an embodiment of the invention, which is applicable to the pixel circuit shown in fig. 11. Wherein a display period includes a write frame and a hold frame.

In the writing frame, the second initialization phase t1, the data writing phase t2, the first initialization phase t3 (coinciding with the voltage bias phase) and the light emitting phase t4 are identical to the driving timing shown in fig. 12, and will not be described again.

In the hold frame, in the period t5 (corresponding to the first initialization period t3 in the write frame), the first scan signal S1 is at a high level, the second scan signal S2 is at a high level, the third scan signal S3 is at a high level, the fourth scan signal S4 is at a low level, the fifth scan signal S5 is at a low level, and the emission control signal EM is at a high level. Therefore, the first transistor M1 is turned on, and the first initialization voltage Vref1 on the first initialization signal line is transmitted to the first pole of the light emitting diode D1 via the first transistor M1, and initializes the first pole of the light emitting diode D1.

In the period t6 (corresponding to the light emission period t4 in the writing frame), the first scan signal S1 is at a high level, the second scan signal S2 is at a low level, the third scan signal S3 is at a high level, the fourth scan signal S4 is at a low level, the fifth scan signal S5 is at a low level, and the light emission control signal EM is at a low level. Accordingly, the seventh transistor M7 and the eighth transistor M8 are turned on, the connection path between the first power line L1 and the second power line L2 is turned on, and the third transistor M3 generates a driving current to drive the light emitting diode D1 to emit light.

the t7 stage and the t8 stage are the same as the working processes of the t5 stage and the t6 stage.

In this scheme, by setting the frequency of the second scan signal S2, the first electrode of the light emitting diode D1 can be initialized in both the write frame and the hold frame, which is advantageous for improving the display effect. Since the frequency of the second scan signal S2 is increased, and accordingly, the number of pulses of the second scan signal S2 is increased, the first electrodes of the light emitting diodes D1 in more regions are initialized in the first initialization stage in a display period, so that the regions in the display panel surface where the first electrodes of the light emitting diodes D1 are initialized can be distributed more uniformly. Under normal conditions, in the same display stage, since the number of lines of the pixel circuit initializing the first pole of the light emitting diode D1 in the display panel is large, in another display stage, even when the pulse of the second scanning signal S2 scans to the blank stage, the difference of the number of lines of the pixel circuit initializing the first pole of the light emitting diode D1 in the display panel is small, that is, in different display stages, the difference of the in-plane loads of the first initializing signal line corresponding to the display panel is small, the difference of the initialization degrees of the first poles of the light emitting diodes D1 in different areas can be reduced, and the split screen phenomenon is favorable to be improved. Further, by reducing the pulse width of the second scan signal S2, the width of the region where the difference in brightness occurs becomes narrower in the pixel row where the difference in brightness occurs, that is, the region where the difference in brightness occurs, thereby reducing mura effect perceived by human eyes.

It should be noted that, with reference to fig. 9, when the frequency of the second scan signal S2 increases, by properly adjusting the number of pulses of the second scan signal S2, the number of pulses of the second scan signal S2 corresponding to the display area a is constant in any display stage, so that the load in the display area a is not different, which is beneficial to eliminating the split screen phenomenon caused by the load difference in the display area a in different display stages.

Optionally, the frequency of the first scan signal S1 may be greater than the refresh frequency of the display panel, that is, the first end or the second end of the driving module 110 is also biased in the holding frame, which is beneficial to improving the uneven display phenomenon caused by the difference of the threshold characteristics of the driving module 110 in the holding frame and the writing frame, and improving the display effect.

The embodiment of the invention also provides a driving method of the display panel, which can be used for driving the display panel provided by any embodiment of the invention. Fig. 14 is a flowchart of a driving method of a display panel according to an embodiment of the present invention, and in combination with fig. 4 to 14, the driving method of a display panel according to the embodiment includes:

s110, in a voltage bias stage in a display period, controlling bias modules in the pixel circuits in a plurality of rows to simultaneously respond to the first scanning signal transmitted on the first scanning line and transmit bias voltages to the first end or the second end of the corresponding driving module.

S120, in a first initialization stage in a display period, a first initialization module in the multi-row pixel circuit is controlled to be simultaneously turned on in response to a second scanning signal transmitted on a second scanning line, and a first initialization voltage is transmitted to a first end of a corresponding light emitting module.

The frequency of the second scanning signal is adjustable to eliminate the load change caused by the first scanning signal. In a display period, the pulse width of the second scanning signal is smaller than or equal to the pulse width of the first scanning signal.

S130, controlling the driving module to generate driving current in a light-emitting stage in a display period so as to drive the light-emitting module to emit light.

The driving method of the display panel provided in this embodiment is used to drive the display panel provided in any of the foregoing embodiments, so the driving method of the display panel provided in this embodiment also has the beneficial effects described in any of the foregoing embodiments, and is not described herein again.

It should be appreciated that various forms of the flows shown above may be used to reorder, add, or delete steps. For example, the steps described in the present invention may be performed in parallel, sequentially, or in a different order, so long as the desired results of the technical solution of the present invention are achieved, and the present invention is not limited herein.

The above embodiments do not limit the scope of the present invention. It will be apparent to those skilled in the art that various modifications, combinations, sub-combinations and alternatives are possible, depending on design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the scope of the present invention.

Claims (10)

1. A display panel comprising a plurality of pixel circuits arranged in an array, and a first scan line and a second scan line connected to the pixel circuits, the pixel circuits comprising: the device comprises a driving module, a biasing module, a first initializing module and a light emitting module;

the driving module is connected between the first power line and the first end of the light emitting module, the second end of the light emitting module is connected with the second power line, and the driving module is used for driving the light emitting module to emit light in a display period;

the bias module is connected with the driving module and is used for responding to a first scanning signal transmitted on the first scanning line connected with the control end of the bias module in a voltage bias stage to transmit bias voltage to the first end or the second end of the driving module;

The first initialization module is connected with the first end of the light-emitting module, and is used for responding to a second scanning signal transmitted on the second scanning line connected with the control end of the first initialization module in a first initialization stage to transmit a first initialization voltage to the first end of the light-emitting module;

the frequency of the second scanning signal is adjustable to eliminate the load change caused by the first scanning signal.

2. The display panel according to claim 1, wherein in one of the display periods, a pulse width of the second scan signal is smaller than or equal to a pulse width of the first scan signal, and the pulse width of the second scan signal corresponds to a total time of a plurality of rows of the pixel circuits in the first initialization stage;

preferably, in one of the display periods, the number of pulses of the second scan signal is greater than or equal to the number of pulses of the first scan signal.

3. The display panel according to claim 2, wherein in one of the display periods, the first scan signal includes a plurality of first pulse signals, the second scan signal includes a plurality of second pulse signals, a start time of the second pulse signals is after a start time of the first pulse signals, or the start time of the second pulse signals is the same as the start time of the first pulse signals, and an end time of the second pulse signals is before an end time of the first pulse signals, or the end time of the second pulse signals is the same as the end time of the first pulse signals.

4. A display panel according to claim 3, wherein the second pulse signal comprises a plurality of sub pulse signals, a start time of a first sub pulse signal is after a start time of the first pulse signal or the start time of the first sub pulse signal is the same as the start time of the first pulse signal, and an end time of a last sub pulse signal is before an end time of the first pulse signal or the end time of the last sub pulse signal is the same as the end time of the first pulse signal.

5. The display panel of claim 1, wherein a frequency of the second scan signal is greater than a refresh frequency of the display panel;

preferably, the frequency of the first scan signal is greater than the refresh frequency of the display panel.

6. The display panel of claim 1, wherein the voltage bias phase coincides with the first initialization phase during one of the display periods.

7. The display panel according to claim 1, wherein the first initialization module includes a first transistor having a gate connected to the second scan line, a first electrode connected to a first initialization signal line, a second electrode connected to a first terminal of the light emitting module, the first transistor for transmitting the first initialization voltage on the first initialization signal line to the first terminal of the light emitting module in the first initialization stage;

The bias module comprises a second transistor, a grid electrode of the second transistor is connected with the first scanning line, a first pole of the second transistor is connected with a bias voltage signal line, a second pole of the second transistor is connected with a first end or a second end of the driving module, and the second transistor is used for transmitting the bias voltage on the bias voltage signal line to the first end or the second end of the driving module in the voltage bias stage;

preferably, the channel type of the second transistor is different from the channel type of the first transistor;

preferably, the first transistor is a metal oxide transistor.

8. The display panel according to any one of claims 1 to 7, wherein the pixel circuit further comprises:

the data writing module is connected with the first end of the driving module and is used for transmitting data voltage to the driving module in a data writing stage;

the compensation module is connected between the second end and the control end of the driving module and is used for compensating the threshold voltage of the driving module;

the second initialization module is connected between a second initialization signal line and a second end of the driving module, and is used for transmitting a second initialization voltage on the second initialization signal line to a control end of the driving module in a second initialization stage;

The first light-emitting control module is connected between the first power line and the first end of the driving module, and the second light-emitting control module is connected between the second end of the driving module and the first end of the light-emitting module;

the storage module is connected with the control end of the driving module and is used for storing the voltage of the control end of the driving module;

preferably, the driving module includes a third transistor, the data writing module includes a fourth transistor, the compensation module includes a fifth transistor, the second initializing module includes a sixth transistor, the first light emitting control module includes a seventh transistor, the second light emitting control module includes an eighth transistor, the light emitting module includes a light emitting diode, and the storage module includes a capacitor;

the grid electrode of the fourth transistor is connected with a third scanning line, the first electrode of the fourth transistor is connected with a data line, the second electrode of the fourth transistor is connected with the first electrode of the third transistor, the grid electrode of the fifth transistor is connected with the fourth scanning line, the first electrode of the fifth transistor is connected with the second electrode of the third transistor, and the second electrode of the fifth transistor is connected with the grid electrode of the third transistor;

A gate of the sixth transistor is connected to a fifth scan line, a first pole of the sixth transistor is connected to the second initialization signal line, and a second pole of the sixth transistor is connected to a first pole of the fifth transistor;

the grid electrode of the seventh transistor and the grid electrode of the eighth transistor are both connected with a light-emitting control signal line, the first pole of the seventh transistor is connected with the first power line, the second pole of the seventh transistor is connected with the first pole of the third transistor, the first pole of the eighth transistor is connected with the second pole of the third transistor, the second pole of the eighth transistor is connected with the first pole of the light-emitting diode, and the second pole of the light-emitting diode is connected with the second power line;

a first pole of the capacitor is connected to the first power line, and a second pole of the capacitor is connected to the gate of the third transistor.

9. The driving method of the display panel is characterized in that the display panel comprises a plurality of pixel circuits which are arranged in an array mode, and a first scanning line and a second scanning line which are connected with the pixel circuits; the pixel circuit includes: the device comprises a driving module, a biasing module, a first initializing module and a light emitting module, wherein the driving module is connected between a first power line and a first end of the light emitting module, a second end of the light emitting module is connected with a second power line, the biasing module is connected with the driving module, and the first initializing module is connected with the first end of the light emitting module;

The driving method of the display panel comprises the following steps:

in a voltage bias stage in a display period, controlling the bias modules in a plurality of rows of pixel circuits to be simultaneously turned on in response to a first scanning signal transmitted on the first scanning line, and transmitting bias voltages to a first end or a second end of the corresponding driving module;

in a first initialization stage in a display period, controlling the first initialization modules in a plurality of rows of pixel circuits to simultaneously respond to the conduction of a second scanning signal transmitted on the second scanning line and transmit a first initialization voltage to a first end of a corresponding light emitting module;

in a light-emitting stage in the display period, controlling the driving module to generate driving current so as to drive the light-emitting module to emit light;

the frequency of the second scanning signal is adjustable to eliminate the load change caused by the first scanning signal.

10. The driving method of a display panel according to claim 9, wherein a frequency of the second scan signal is greater than a frequency of the first scan signal;

preferably, in the display period, the pulse width of the second scan signal is smaller than or equal to the pulse width of the first scan signal.