CN117195786A

CN117195786A - Simulation method and device for test comparison, computer equipment and storage medium

Info

Publication number: CN117195786A
Application number: CN202311229207.1A
Authority: CN
Inventors: 胡道雪; 饶荣武
Original assignee: Dongguan Yiyun Information System Co ltd
Current assignee: Dongguan Yiyun Information System Co ltd
Priority date: 2023-09-21
Filing date: 2023-09-21
Publication date: 2023-12-08

Abstract

The invention relates to the field of PCB design, and discloses a simulation method, a simulation device, computer equipment and a storage medium for test comparison. The method comprises the following steps: obtaining a PCB schematic diagram, adding test points on a network to be tested of the PCB schematic diagram, and obtaining a schematic diagram netlist containing the network of the test points; importing a schematic diagram netlist containing a test point network into a PCB Layout file and editing the schematic diagram netlist to obtain a target PCB Layout file; extracting a PCB link model of a network to be tested of a schematic diagram netlist containing a test point network from a target PCB Layout file; adding the PCB link model into a preset simulation engineering file for simulation to obtain a PCB link simulation result; and obtaining a test result of the through hole on the PCB, and comparing the test result with a PCB link simulation result to adjust simulation parameters of the PCB link model. The embodiment of the invention can improve the coincidence degree of the simulation result and the test result.

Description

Simulation method and device for test comparison, computer equipment and storage medium

Technical Field

The embodiment of the invention relates to the field of PCB design, in particular to a simulation method, a simulation device, computer equipment and a storage medium for test comparison.

Background

In the development process of PCB single board hardware, simulation software is needed to be used for circuit simulation of some parallel buses, and the signal quality is prejudged according to simulation results; in the test and verification stage of the PCB single board, signal test is required to be carried out on the single board so as to carry out regression verification on the signal quality of the designed single board.

Current simulation methods can only observe waveforms on the Pin pins (e.g., BGA ball) of the device and on the inside of the chip (Die); the signal waveform can be observed only at the Via hole (Via) on the PCB surface by using the oscilloscope in the PCB single board test, so that the observation point in the simulation is inconsistent with the observation point in the test, and a lot of uncertainty is brought to the comparison of the results of the observation point and the observation point in the test. Moreover, since the via on the PCB surface is in the middle of the link, the measured waveform is superimposed by the reflected waveform generated from the via to the end of the link, including reflections caused by nodes such as solder balls (Ball), traces in the substrate (submount), and end chips (Die). The superposition of these reflected waveforms may generate steps in the jump edges of the test waveforms, resulting in distortion of the tested eye pattern waveform, such as a small eye width, a high eye height, etc., which is easy to misjudge the simulation result, as shown in fig. 1, the left graph in fig. 1 is the test eye pattern at the Via hole (Via), and the right graph is the simulation eye pattern at the chip (Die), and it can be seen from fig. 1 that the difference of the eye pattern waveforms in the two graphs is large. Therefore, how to improve the consistency of the simulation result and the test result is a difficult problem.

Disclosure of Invention

The embodiment of the invention provides a simulation method, a simulation device, computer equipment and a storage medium for test comparison, and aims to solve the problem that the simulation result and the test result of the existing PCB simulation method are low in matching degree.

In a first aspect, an embodiment of the present invention provides a simulation method for test comparison, including:

obtaining a PCB schematic diagram, adding test points on a network to be tested of the PCB schematic diagram, and obtaining a schematic diagram netlist containing the network of the test points;

importing the schematic diagram netlist containing the test point network into a PCB Layout file and editing the schematic diagram netlist to obtain a target PCB Layout file;

extracting a PCB link model of the network to be tested of the schematic diagram netlist containing the test point network from the target PCB Layout file;

adding the PCB link model into a preset simulation engineering file for simulation to obtain a PCB link simulation result;

and obtaining a test result of the through hole on the PCB, and comparing the test result with the PCB link simulation result to adjust simulation parameters of the PCB link model.

In a second aspect, an embodiment of the present invention further provides a simulation apparatus for test comparison, including:

an adding unit, configured to obtain a schematic diagram of a PCB, and add test points on a network to be tested of the schematic diagram of the PCB, to obtain a schematic diagram netlist including the network of test points;

the importing unit is used for importing the schematic diagram netlist containing the test point network into a PCB Layout file and editing the schematic diagram netlist to obtain a target PCB Layout file;

the extraction unit is used for extracting the PCB link model of the network to be tested of the schematic diagram netlist containing the test point network from the target PCB Layout file;

the simulation unit is used for adding the PCB link model into a preset simulation engineering file to simulate so as to obtain a PCB link simulation result;

and the comparison and adjustment unit is used for acquiring a test result of the through hole on the PCB and comparing the test result with the PCB link simulation result so as to adjust simulation parameters of the PCB link model.

In a third aspect, an embodiment of the present invention further provides a computer device, which includes a memory and a processor, where the memory stores a computer program, and the processor implements the method when executing the computer program.

In a fourth aspect, embodiments of the present invention also provide a computer readable storage medium storing a computer program which, when executed by a processor, implements the above method.

The embodiment of the invention provides a simulation method, a simulation device, computer equipment and a storage medium for test comparison. Wherein the method comprises the following steps: obtaining a PCB schematic diagram, adding test points on a network to be tested of the PCB schematic diagram, and obtaining a schematic diagram netlist containing the network of the test points; importing the schematic diagram netlist containing the test point network into a PCB Layout file and editing the schematic diagram netlist to obtain a target PCB Layout file; extracting a PCB link model of the network to be tested of the schematic diagram netlist containing the test point network from the target PCB Layout file; adding the PCB link model into a preset simulation engineering file for simulation to obtain a PCB link simulation result; and obtaining a test result of the through hole on the PCB, and comparing the test result with the PCB link simulation result to adjust simulation parameters of the PCB link model. According to the technical scheme, the test points are added on the network to be tested in the PCB schematic diagram and are led into the PCB Layout file, the PCB link model of the network to be tested containing the test points is extracted from the PCB Layout file for simulation, the simulation result is compared with the test result of the PCB to adjust the simulation parameters of the PCB link model, the coincidence degree of the simulation result and the test result can be improved, and therefore the signal quality of the PCB can be accurately judged.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a diagram of a prior art PCB test eye diagram and a PCB simulated eye diagram according to the present invention;

FIG. 2 is a schematic flow chart of a simulation method for test comparison according to an embodiment of the present invention;

FIG. 3 is a schematic sub-flowchart of a simulation method for test comparison according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of a PCB link model provided by a simulation method for test comparison according to an embodiment of the present invention;

FIG. 5 is a schematic sub-flowchart of a simulation method for test comparison according to an embodiment of the present invention;

FIG. 6 is a schematic sub-flowchart of a simulation method for test comparison according to an embodiment of the present invention;

FIG. 7 is a schematic diagram of a simulation waveform and a schematic diagram of a test waveform of a simulation method for test comparison according to an embodiment of the present invention;

FIG. 8 is a schematic block diagram of a simulation apparatus for test comparison according to an embodiment of the present invention;

fig. 9 is a schematic block diagram of a computer device according to an embodiment of the present invention.

Detailed Description

The following description of the embodiments of the present invention will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are some, but not all embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

It should be understood that the terms "comprises" and "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

It is also to be understood that the terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in this specification and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

It should be further understood that the term "and/or" as used in the present specification and the appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes such combinations.

As used in this specification and the appended claims, the term "if" may be interpreted as "when..once" or "in response to a determination" or "in response to detection" depending on the context. Similarly, the phrase "if a determination" or "if a [ described condition or event ] is detected" may be interpreted in the context of meaning "upon determination" or "in response to determination" or "upon detection of a [ described condition or event ]" or "in response to detection of a [ described condition or event ]".

Referring to fig. 2, fig. 2 is a flow chart of a simulation method for test comparison according to an embodiment of the invention. The simulation method for test comparison is described in detail below. As shown in fig. 1, the method includes the following steps S100 to S140.

S100, obtaining a PCB schematic diagram, and adding test points on a network to be tested of the PCB schematic diagram to obtain a schematic diagram netlist containing the network of the test points.

In the embodiment of the invention, the PCB simulation only can observe waveforms on the Pin pins (such as BGAball) and the chip (Die) of the device; the signal waveform can only be observed by an oscilloscope at a Via hole (Via) on the surface of the PCB, so that the observation point in simulation is inconsistent with the observation point in test, the simulation result is greatly different from the test result, and the signal quality of the PCB is difficult to determine according to the simulation result. Specifically, a PCB schematic diagram is obtained, test points are added on a network to be tested of the PCB schematic diagram, a schematic diagram netlist containing a network of the test points is obtained, the test points can be mapped to via test points on a PCB single board, namely, the added test points correspond to the via test points on the PCB single board. The schematic netlist containing a network of test points is understandably a schematic of a PCB containing test points. It should be noted that, in this embodiment, the test point is typically in the form of an SMD package; the network to be tested is a network selected for simulation test in the PCB schematic diagram.

S110, importing the schematic diagram netlist containing the test point network into a PCB Layout file and editing the schematic diagram netlist to obtain a target PCB Layout file.

In the embodiment of the invention, after a schematic diagram netlist containing a test point network is obtained, the schematic diagram netlist containing the test point network is imported into a PCB Layout file, and editing is performed in the PCB Layout file to obtain a target PCB Layout file. Wherein, PCB Layout file is the design file of PCB. And importing the schematic diagram netlist containing the test point network into a PCB Layout file, and editing, optimizing and the like the schematic diagram netlist containing the test point network.

Referring to fig. 3, in an embodiment, for example, in the embodiment of the present invention, the step S110 includes the following steps S111-S112.

S111, importing the schematic diagram netlist containing the test point network into a PCB Layout file to obtain an initial PCB Layout file;

and S112, optimizing the Layout positions and the bonding pads of the test points in the initial PCB Layout file to obtain the target PCB Layout file.

In the embodiment of the invention, the schematic diagram netlist containing the test point network is imported into a PCB Layout file to obtain an initial PCB Layout file, and in order to avoid the degradation of the performance of the original network to be tested caused by the existence of stub (invalid via length) and too large Pad (bonding Pad) in the initial PCB Layout file, the test points need to be edited and optimized: and optimizing the Layout positions and the bonding pads of the test points in the initial PCB Layout file to obtain the target PCB Layout file.

S120, extracting the PCB link model of the network to be tested of the schematic diagram netlist containing the test point network from the target PCB Layout file.

In the embodiment of the invention, the PCB link model of the network to be tested of the schematic diagram netlist containing the test point network is extracted from the target PCB Layout file, the PCB link model can be used for PCB simulation, and the extracted PCB link model can be used for standardizing the characteristics of the PCB link. It will be appreciated that the network to be tested of the extracted PCB link model contains added test points. As shown in fig. 4, if the original network to be measured is an S-Parameter model in S2P format, after the test points are added, the original network to be measured becomes an S-Parameter model in S3P format. Curve 1 in fig. 3 is the S-Parameter model in S2P format; curve 3 is an S-Parameter model in S3P format, and as can be seen from fig. 3, the curves of the two S-Parameter models substantially coincide, which indicates that the test point introduced in the original network under test has little effect on the performance of the network under test.

S130, adding the PCB link model into a preset simulation engineering file for simulation, and obtaining a PCB link simulation result.

In the embodiment of the invention, after the PCB link model is obtained, the PCB link model can be added into a preset simulation engineering file for simulation so as to obtain a PCB link simulation result. The preset simulation file is a simulation engineering file built in advance by a user, and when a PCB link model for simulation is carried in the simulation engineering file, the simulation can be started. Further, simulation waveforms at the 3 positions of the test point, the device pin (Ball) node and the chip (Die) node can be observed at the same time in the simulation result of the PCB link simulation. It is understood that the test points are test points added on the network to be tested of the PCB schematic.

Referring to fig. 5, in an embodiment, for example, in the embodiment of the present invention, the step S130 includes the following steps S131-S132.

S131, adding the PCB link model into a simulation engineering file to obtain a to-be-simulated engineering file;

s132, simulating the test point, the device pin node and the chip node in the engineering file to be simulated to obtain the PCB link simulation result.

In the embodiment of the invention, the PCB link model is added into a simulation engineering file to obtain the to-be-simulated engineering file, and the nodes needing to be simulated, such as added test points, device pin (Ball) nodes and chip (Die) nodes, are selected from the to-be-simulated engineering file; and then simulating the test point, the device pin node and the chip node to obtain the PCB link simulation result, wherein the PCB link simulation result comprises simulation waveforms of the test point, the device pin (Ball) node and the chip (Die) node at 3 positions.

Referring to fig. 6, in an embodiment, for example, the step S132 includes the following steps S1321-S1324 in an embodiment of the present invention.

S1321, simulating the test points in the PCB link model to obtain simulation waveforms of the test points;

s1322, simulating the device pin node in the PCB link model to obtain a simulation waveform of the device pin node;

s1323, simulating the chip node in the PCB link model to obtain a simulation waveform of the chip node;

s1324, taking the simulation waveform of the test point, the simulation waveform of the device pin and the simulation waveform of the chip node as the simulation result of the PCB link.

In the embodiment of the invention, the 3 nodes of the test point, the device pin node and the chip node in the simulation engineering file to be tested are respectively simulated: simulating the test points in the PCB link model to obtain simulation waveforms of the test points; simulating the device pin node in the PCB link model to obtain a simulation waveform of the device pin node; simulating the chip node in the PCB link model to obtain a simulation waveform of the chip node; and taking the simulation waveforms of the test points, the simulation waveforms of the device pins and the simulation waveforms of the chip nodes as the simulation results of the PCB links.

S140, obtaining a test result of the through hole on the PCB, and comparing the test result with the PCB link simulation result to adjust simulation parameters of the PCB link model.

In the embodiment of the invention, the test result of the PCB can be obtained from the oscilloscope test, and the test waveform of the Via hole (Via) on the PCB is specifically obtained. The PCB is processed according to the PCB schematic diagram, and can be used for testing a single board. Comparing the test waveform of the via hole with the simulation waveform of the test point, and adjusting the simulation parameters of the PCB link model according to the comparison result. Specifically, adjusting the simulation parameters of the PCB link model according to the comparison result includes: judging whether the comparison result meets a preset specification or not; and if the comparison result does not meet the preset specification, adjusting simulation parameters of the PCB link model, returning to execute the step of acquiring a test result of the via hole on the PCB, comparing the test result of the via hole with the PCB link simulation result, and adjusting the simulation parameters of the PCB link model according to the comparison result until the comparison result meets the preset specification, and continuously adjusting and optimizing the simulation parameters of the PCB link model to enable the simulation result to meet simulation requirements. As shown in fig. 7, the left graph of fig. 7 is a test waveform at the via hole of the PCB board, and the right graph is a simulation waveform of the test point in the PCB link model, and from the comparison of the test waveform of the left graph and the test waveform of the right graph, it can be seen that the test waveform and the simulation waveform are more consistent, and conform to the preset specification.

In the embodiment of the invention, if the comparison result of the test result of the via hole on the PCB and the simulation result of the test point meets the preset specification, namely that the error of the test waveform of the via hole and the simulation waveform of the test point is within the acceptable error range, the adjustment of the simulation parameters of the PCB link model can be stopped, and the simulation is ended. At the moment, the simulation waveform of the chip node in the PCB link model can be used as the real signal working waveform of the PCB, so that the signal quality of the PCB can be accurately judged according to the signal working waveform of the PCB.

Fig. 8 is a schematic block diagram of a simulation apparatus 200 for test comparison according to an embodiment of the present invention. As shown in fig. 8, the present invention further provides a simulation apparatus 200 for test comparison, corresponding to the above simulation method for test comparison. The simulation apparatus 200 for test comparison, which includes means for performing the simulation method for test comparison described above, may be configured in a computer device. Specifically, referring to fig. 8, the simulation apparatus 200 for test comparison includes an adding unit 201, an importing unit 202, an extracting unit 203, a simulation unit 204, and a comparison adjusting unit 205.

The adding unit 201 is configured to obtain a schematic diagram of a PCB, and add test points on a network to be tested of the schematic diagram of the PCB to obtain a schematic diagram netlist including the network of test points; the importing unit 202 is configured to import the schematic netlist including the test point network into a PCB Layout file and edit the schematic netlist to obtain a target PCB Layout file; the extracting unit 203 is configured to extract, from the target PCB Layout file, a PCB link model of the network to be tested of the schematic diagram netlist including the test point network; the simulation unit 204 is configured to add the PCB link model to a preset simulation engineering file for simulation, so as to obtain a PCB link simulation result; the comparison and adjustment unit 205 is configured to obtain a test result of a via hole on a PCB, and compare the test result with the PCB link simulation result to adjust simulation parameters of the PCB link model.

In some embodiments, for example, the import unit 202 includes an import subunit and an optimization subunit.

The importing subunit is used for importing the schematic diagram netlist containing the test point network into a PCB Layout file to obtain an initial PCB Layout file; and the optimizing subunit is used for optimizing the Layout positions and the bonding pads of the test points in the initial PCB Layout file to obtain the target PCB Layout file.

In some embodiments, such as the present embodiment, the simulation unit 204 includes an add subunit and a first simulation subunit.

The adding subunit is used for adding the PCB link model into a simulation engineering file to obtain the engineering file to be simulated; and the first simulation subunit is used for simulating the test point, the device pin node and the chip node in the engineering file to be simulated to obtain the PCB link simulation result.

In some embodiments, for example, the first simulation subunit includes a second simulation subunit, a third simulation subunit, a fourth simulation subunit, and a first as subunit.

The second simulation subunit is used for simulating the test points in the PCB link model to obtain simulation waveforms of the test points; the third simulation subunit is used for simulating the device pin node in the PCB link model to obtain a simulation waveform of the device pin node; the fourth simulation subunit is used for simulating the chip node in the PCB link model to obtain a simulation waveform of the chip node; the first sub-unit is used for taking the simulation waveform of the test point, the simulation waveform of the device pin and the simulation waveform of the chip node as the simulation result of the PCB link.

In some embodiments, for example, the contrast adjustment unit 205 includes a first acquisition subunit and a contrast adjustment subunit.

The first acquisition subunit is used for acquiring test waveforms of the through holes on the PCB, wherein the PCB is processed according to the PCB schematic diagram; the comparison and adjustment subunit is used for comparing the test waveform of the via hole with the simulation waveform of the test point and adjusting the simulation parameters of the PCB link model according to the comparison result.

In some embodiments, for example, the contrast adjustment subunit includes a determination subunit and an adjustment subunit.

The judging subunit is used for judging whether the comparison result meets a preset specification or not; and the adjustment subunit is used for adjusting the simulation parameters of the PCB link model if the comparison result does not meet the preset specification, returning to execute the steps of acquiring the test result of the through hole on the PCB, comparing the test result of the through hole with the PCB link simulation result, and adjusting the simulation parameters of the PCB link model according to the comparison result until the comparison result meets the preset specification.

In some embodiments, for example, in this embodiment, the simulation device 200 for testing comparison further includes a second obtaining subunit and a second serving subunit.

The second obtaining subunit is configured to obtain a simulation waveform of the chip node if the comparison result meets a preset specification; and the second sub-unit is used for taking the simulation waveform of the chip node as the actual signal working waveform of the PCB.

The simulation apparatus for test comparison described above may be implemented in the form of a computer program which can be run on a computer device as shown in fig. 9.

Referring to fig. 9, fig. 9 is a schematic block diagram of a computer device according to an embodiment of the present invention. The computer device 300 is a simulated computer device for testing contrast.

With reference to FIG. 9, the computer device 300 includes a processor 302, a memory, and a network interface 305, which are connected by a system bus 301, wherein the memory may include a non-volatile storage medium 303 and an internal memory 304.

The non-volatile storage medium 303 may store an operating system 3031 and a computer program 3032. The computer program 3032, when executed, may cause the processor 302 to perform a simulation method for test comparison.

The processor 302 is used to provide computing and control capabilities to support the operation of the overall computer device 300.

The internal memory 304 provides an environment for the execution of a computer program 3032 in the non-volatile storage medium 303, which computer program 3032, when executed by the processor 302, causes the processor 302 to perform a simulation method for test comparison.

The network interface 305 is used for network communication with other devices. It will be appreciated by those skilled in the art that the structure shown in FIG. 9 is merely a block diagram of some of the structures associated with the present inventive arrangements and does not constitute a limitation of the computer device 300 to which the present inventive arrangements may be applied, and that a particular computer device 300 may include more or fewer components than shown, or may combine certain components, or may have a different arrangement of components.

It should be appreciated that in embodiments of the present invention, the processor 302 may be a central processing unit (Central Processing Unit, CPU), the processor 302 may also be other general purpose processors, digital signal processors (Digital Signal Processor, DSPs), application specific integrated circuits (Application Specific Integrated Circuit, ASICs), field programmable gate arrays (Field-Programmable Gate Array, FPGAs) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, or the like. Wherein the general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.

Those skilled in the art will appreciate that all or part of the flow in a method embodying the above described embodiments may be accomplished by computer programs instructing the relevant hardware. The computer program may be stored in a storage medium that is a computer readable storage medium. The computer program is executed by at least one processor in the computer system to implement the flow steps of the embodiments of the method described above.

Accordingly, the present invention also provides a storage medium. The storage medium may be a computer readable storage medium. The storage medium stores a computer program. The computer program, when executed by a processor, causes the processor to perform any of the embodiments of the simulation method for test comparison described above.

The storage medium may be a U-disk, a removable hard disk, a Read-Only Memory (ROM), a magnetic disk, or an optical disk, or other various computer-readable storage media that can store program codes.

Those of ordinary skill in the art will appreciate that the elements and algorithm steps described in connection with the embodiments disclosed herein may be embodied in electronic hardware, in computer software, or in a combination of the two, and that the elements and steps of the examples have been generally described in terms of function in the foregoing description to clearly illustrate the interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.

In the several embodiments provided by the present invention, it should be understood that the disclosed apparatus and method may be implemented in other manners. For example, the device embodiments described above are merely illustrative. For example, the division of each unit is only one logic function division, and there may be another division manner in actual implementation. For example, multiple units or components may be combined or may be integrated into another system, or some features may be omitted, or not performed.

The steps in the method of the embodiment of the invention can be sequentially adjusted, combined and deleted according to actual needs. The units in the device of the embodiment of the invention can be combined, divided and deleted according to actual needs. In addition, each functional unit in the embodiments of the present invention may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit.

The integrated unit may be stored in a storage medium if implemented in the form of a software functional unit and sold or used as a stand-alone product. Based on such understanding, the technical solution of the present invention is essentially or a part contributing to the prior art, or all or part of the technical solution may be embodied in the form of a software product stored in a storage medium, comprising several instructions for causing a computer device (which may be a personal computer, a terminal, a network device, etc.) to perform all or part of the steps of the method according to the embodiments of the present invention.

In the foregoing embodiments, the descriptions of the embodiments are focused on, and for those portions of one embodiment that are not described in detail, reference may be made to the related descriptions of other embodiments.

It will be apparent to those skilled in the art that various modifications and variations can be made to the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.

While the invention has been described with reference to certain preferred embodiments, it will be understood by those skilled in the art that various changes and substitutions of equivalents may be made and equivalents will be apparent to those skilled in the art without departing from the scope of the invention. Therefore, the protection scope of the invention is subject to the protection scope of the claims.

Claims

1. A simulation method for test comparison, comprising:

2. The simulation method for test comparison according to claim 1, wherein the importing the schematic netlist including the test point network into the PCB Layout file and editing the schematic netlist to obtain the target PCB Layout file includes:

importing the schematic diagram netlist containing the test point network into a PCB Layout file to obtain an initial PCB Layout file;

and optimizing the Layout positions and the bonding pads of the test points in the initial PCB Layout file to obtain the target PCB Layout file.

3. The simulation method for test comparison according to claim 1, wherein the step of adding the PCB link model to a preset simulation engineering file for simulation to obtain a PCB link simulation result includes:

adding the PCB link model into a simulation engineering file to obtain a to-be-simulated engineering file;

and simulating the test point, the device pin node and the chip node in the engineering file to be simulated to obtain the PCB link simulation result.

4. The simulation method for test comparison according to claim 3, wherein the simulating the test point, the device pin node and the chip node in the to-be-simulated engineering file to obtain the PCB link simulation result comprises:

simulating the test points in the PCB link model to obtain simulation waveforms of the test points;

simulating the device pin node in the PCB link model to obtain a simulation waveform of the device pin node;

simulating the chip node in the PCB link model to obtain a simulation waveform of the chip node;

and taking the simulation waveforms of the test points, the simulation waveforms of the device pins and the simulation waveforms of the chip nodes as the simulation results of the PCB links.

5. The simulation method for testing comparison according to claim 4, wherein the obtaining a test result of a via hole on a PCB board, comparing the test result with the PCB link simulation result to adjust simulation parameters of the PCB link model, comprises:

obtaining test waveforms of the through holes on the PCB, wherein the PCB is processed according to the PCB schematic diagram;

comparing the test waveform of the via hole with the simulation waveform of the test point, and adjusting the simulation parameters of the PCB link model according to the comparison result.

6. The simulation method for test comparison according to claim 5, wherein the adjusting the simulation parameters of the PCB link model according to the comparison result comprises:

judging whether the comparison result meets a preset specification or not;

and if the comparison result does not meet the preset specification, adjusting simulation parameters of the PCB link model, returning to the step of executing and obtaining the test result of the through hole on the PCB, comparing the test result of the through hole with the PCB link simulation result, and adjusting the simulation parameters of the PCB link model according to the comparison result until the comparison result meets the preset specification.

7. The simulation method for test comparison according to claim 6, further comprising:

if the comparison result meets a preset specification, acquiring a simulation waveform of the chip node;

and taking the simulation waveform of the chip node as the actual working signal waveform of the PCB.

8. A simulation device for test comparison, comprising:

9. A computer device, characterized in that it comprises a memory on which a computer program is stored and a processor which, when executing the computer program, implements the method according to any of claims 1-7.

10. A computer readable storage medium, characterized in that the storage medium stores a computer program which, when executed by a processor, implements the method according to any of claims 1-7.