CN117194137A - Memory stripe testing method, device and jig based on FPGA - Google Patents
Memory stripe testing method, device and jig based on FPGA Download PDFInfo
- Publication number
- CN117194137A CN117194137A CN202311143536.4A CN202311143536A CN117194137A CN 117194137 A CN117194137 A CN 117194137A CN 202311143536 A CN202311143536 A CN 202311143536A CN 117194137 A CN117194137 A CN 117194137A
- Authority
- CN
- China
- Prior art keywords
- memory
- test
- signal
- fpga module
- fpga
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000015654 memory Effects 0.000 title claims abstract description 331
- 238000012360 testing method Methods 0.000 title claims abstract description 223
- 238000012545 processing Methods 0.000 claims abstract description 29
- 238000000034 method Methods 0.000 claims abstract description 27
- 238000012546 transfer Methods 0.000 claims abstract description 18
- 238000001514 detection method Methods 0.000 claims description 12
- 238000010998 test method Methods 0.000 claims description 8
- 238000004891 communication Methods 0.000 claims description 4
- 238000013102 re-test Methods 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 12
- 230000008569 process Effects 0.000 description 6
- 230000009471 action Effects 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000006978 adaptation Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000002238 attenuated effect Effects 0.000 description 1
- 238000012790 confirmation Methods 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000013100 final test Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 238000011144 upstream manufacturing Methods 0.000 description 1
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
The application discloses a memory stripe testing method, a device and a jig based on an FPGA, wherein the method comprises the following steps: transmitting a memory signal to the FPGA module, and carrying out transfer processing on the memory signal through the FPGA module; connecting the memory signals subjected to the transfer processing to a first memory slot of a test platform by using an FPGA module so as to test a first memory bar in the first memory slot; after the first memory bank is tested, a channel switching instruction is sent to the FPGA module so that the FPGA module is connected with a second memory slot of the test platform, and the second memory bank in the second memory slot is tested; and the same is repeated until the test is completed on the memory strips in all the memory slots of the test platform. According to the embodiment of the application, the memory signals are transferred to the test platform through the FPGA module, so that each memory strip in the test platform can be tested one by one, the test quantity of the memory strips is improved, the labor cost is reduced, and the test efficiency is improved.
Description
Technical Field
The application relates to the technical field of memory strip testing, in particular to a memory strip testing method, device and jig based on an FPGA.
Background
With the development of computer technology, the role of memory banks in computers is becoming more and more important, and testing of memory banks is becoming more critical. The current memory strip test environment is that only one memory strip can be tested in a single memory slot under a single test platform, and after the test is completed, the memory strip needs to be manually plugged and replaced, and then the next memory strip is tested. Moreover, the existing test platform only has two memory slots, that is to say, only two memory strips can be tested at a time, so that when a plurality of memory strips are required to be tested, a plurality of test platforms are required to be purchased and built, and as a single test platform only can test two memory strips (two memory slots) on average, the cost and time cost of a plurality of test platforms are high if the test of a whole batch of memory strip products is required to be completed, the time cost and labor cost are greatly increased, the test efficiency of testing the memory strips of the single test platform is low, the test period is long, and thus the intelligent requirement of the current production cannot be met.
Disclosure of Invention
The embodiment of the application provides a memory strip testing method, device and jig based on an FPGA, aiming at improving the testing efficiency of a memory strip so as to meet the production requirement.
In a first aspect, an embodiment of the present application provides a method for testing a memory stripe based on an FPGA, which is applicable to a test platform including a plurality of memory slots, including:
transmitting a memory signal to an FPGA module, and carrying out switching processing on the memory signal through the FPGA module;
connecting the memory signals subjected to transfer processing to a first memory slot of a test platform by using the FPGA module so as to test a first memory strip in the first memory slot;
after the first memory bank is tested, a channel switching instruction is sent to the FPGA module so that the FPGA module is connected with a second memory slot of the test platform, and a second memory bank in the second memory slot is tested; and the same is repeated until the test is completed on the memory strips in all the memory slots of the test platform.
In a second aspect, an embodiment of the present application provides an FPGA-based memory stripe testing apparatus, which is applicable to a testing platform including a plurality of memory slots, and includes:
the signal sending unit is used for sending a memory signal to the FPGA module and carrying out switching processing on the memory signal through the FPGA module;
the memory test unit is used for connecting the memory signals after the transfer processing to a first memory slot of the test platform by utilizing the FPGA module so as to test a first memory strip in the first memory slot;
the channel switching unit is used for sending a channel switching instruction to the FPGA module after the first memory bank is tested, so that the FPGA module is connected with the second memory slot of the test platform, and the second memory bank in the second memory slot is tested; and the same is repeated until the test is completed on the memory strips in all the memory slots of the test platform.
In a third aspect, an embodiment of the present application provides a memory stripe test fixture based on FPGA, including: the device comprises a CPU detection unit, an FPGA module and a test platform, wherein the FPGA module is respectively connected with the CPU detection unit and the test platform, and the test platform comprises a plurality of memory slots for placing memory strips;
the CPU detection unit adopts the memory strip test method based on the FPGA in the first aspect to test the memory strips in the test platform.
The embodiment of the application provides a method, a device and a jig for testing a memory bank based on an FPGA, which are suitable for a test platform comprising a plurality of memory slots, and the method comprises the following steps: transmitting a memory signal to an FPGA module, and carrying out switching processing on the memory signal through the FPGA module; connecting the memory signals subjected to transfer processing to a first memory slot of a test platform by using the FPGA module so as to test a first memory strip in the first memory slot; after the first memory bank is tested, a channel switching instruction is sent to the FPGA module so that the FPGA module is connected with a second memory slot of the test platform, and a second memory bank in the second memory slot is tested; and the same is repeated until the test is completed on the memory strips in all the memory slots of the test platform. According to the embodiment of the application, the memory signals are transferred to the test platform through the FPGA module, so that each memory strip in the test platform can be tested one by one, the test quantity of the memory strips is improved under the condition that more test platforms are not required to be added, meanwhile, the signal transfer is carried out through the FPGA module, so that the operation of manual replacement is saved, the labor cost is reduced, the test efficiency is improved, and the requirement of a larger test environment is met.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for the description of the embodiments will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flow chart of a memory stripe test method based on an FPGA according to an embodiment of the present application;
FIG. 2 is a schematic block diagram of a memory strip test device based on an FPGA according to an embodiment of the present application;
fig. 3 is a schematic structural diagram of a memory stripe test fixture based on FPGA according to an embodiment of the present application;
fig. 4 is a test schematic diagram of a memory stripe test fixture based on FPGA according to an embodiment of the present application;
FIG. 5 is a schematic diagram of a test display of a memory stripe test method based on an FPGA according to an embodiment of the present application;
FIG. 6 is a schematic diagram of another embodiment of a method for testing memory banks based on an FPGA;
FIG. 7 is a signal conversion logic block diagram of an FPGA module in an FPGA-based memory bank test method according to an embodiment of the present application;
fig. 8 is a schematic diagram of a first signal switching of a method for testing a memory stripe based on an FPGA according to an embodiment of the present application;
fig. 9 is a schematic diagram of a second signal transfer of a method for testing a memory stripe based on an FPGA according to an embodiment of the present application;
fig. 10 is a third signal switching schematic diagram of a memory stripe testing method based on FPGA according to an embodiment of the present application;
fig. 11 is a fourth signal switching schematic diagram of a memory stripe testing method based on FPGA according to an embodiment of the present application.
Detailed Description
The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are some, but not all embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
It should be understood that the terms "comprises" and "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It is also to be understood that the terminology used in the description of the application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this specification and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
It should be further understood that the term "and/or" as used in the present specification and the appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes such combinations.
Referring to fig. 1, fig. 1 is a flow chart of a method for testing a memory stripe based on an FPGA according to an embodiment of the present application, where the method is applicable to a test platform including a plurality of memory slots, and specifically includes: steps S101 to S103.
S101, sending a memory signal to an FPGA module, and carrying out transfer processing on the memory signal through the FPGA module;
s102, connecting the memory signals subjected to transfer processing to a first memory slot of a test platform by utilizing the FPGA module so as to test a first memory strip in the first memory slot;
s103, after the first memory bank is tested, a channel switching instruction is sent to the FPGA module so that the FPGA module is connected with a second memory slot of the test platform, and a second memory bank in the second memory slot is tested; and the same is repeated until the test is completed on the memory strips in all the memory slots of the test platform.
In this embodiment, first, a memory signal is sent to the FPGA module, and then the FPGA module switches the memory signal to a memory slot of the test platform. Because the test platform comprises a plurality of memory slots, one of the memory slots can be connected in sequence, and the memory bars in the memory slots can be tested after the connection is successful. After the test is completed, a channel switching instruction is sent to the FPGA module to connect the memory signal to the next memory slot, and the test of the memory strips is started, and the like until all the memory strips are tested.
According to the embodiment, the memory signals are transferred to the test platform through the FPGA module, so that each memory strip in the test platform can be tested one by one, the test quantity of the memory strips is improved under the condition that more test platforms are not required to be added, meanwhile, the signal transfer is carried out through the FPGA module, so that the operation of manual replacement is saved, the labor cost is reduced, the test efficiency is improved, and the requirement of a larger test environment is met. Specifically, the FPGA module can adopt the siren Virtex 7FPGA series, and the FPGA has the characteristics of flexible architecture and logic unit, low signal delay, high integration level, wide application range, and the like. The FPGA is very suitable for converting the memory signals by utilizing the characteristic of the FPGA, and the FPGA can be provided with enhanced driving capability when converting the signals, so that the problem of signal attenuation caused by overlong memory wiring can be solved, and the DDR memory signal transferred and output by the FPGA can be ensured to meet JEDEC specification requirements.
Particularly, the implementation main body of the memory stripe test method based on the FPGA is a CPU. Referring to fig. 3 and fig. 4, the embodiment of the present application further provides a memory stripe test fixture based on FPGA, including: the device comprises a CPU detection unit, an FPGA module and a test platform, wherein the FPGA module is respectively connected with the CPU detection unit and the test platform, and the test platform comprises a plurality of memory slots for placing memory strips;
the CPU detection unit adopts the memory strip test method based on the FPGA to test the memory strips in the test platform.
In a specific scenario, as shown in fig. 3, the test platform includes 4 memory slots, i.e., UDIMM0, UDIMM1, UDIMM2, and UDIMM3. The FPGA module consists of an FPGA chip, processes the memory signals of a single memory bank and simultaneously transfers the processed memory signals to 4 memory slot interfaces, and each memory slot interface is used for placing the memory bank to be tested. The FPGA module sequentially connects the memory signals sent by the uplink CPU end to the memory slots UDIMM0, UDIMM1, UDIMM2 and UDIMM3, wherein the memory test mode is a polling test, namely the first test starts from the memory bank in the memory slot UDIMM0, and when the memory bank of the memory slot UDIMM0 is tested, the memory signals are switched to the memory bank to be tested in the memory slot UDIMM1 and sequentially performed until the memory bank in the memory slot UDIMM3 is tested. The test fixture is fully loaded and can be inserted into 4 memory strips, namely, the test work of the 4 memory strips is completed under the condition that manual replacement operation is not needed, the 4 memory strips are tested continuously and sequentially, the single memory test quantity of a single test platform matched with the test fixture is increased by 4 times compared with that of the prior art, the test efficiency is greatly improved, and the production cost is reduced. Of course, in other embodiments, more or fewer memory slots may be provided on the test platform to meet different test scenario requirements. The test fixture of the embodiment supports the test of the memory strips with different memory capacities, and greatly enriches the types of the testable memories. The test fixture omits the process of manually and frequently replacing the memory strips, can support the memory strips of different manufacturers, and the number of the memory strips which can be tested by a single test platform is improved by 4 times (or n times) compared with the original number, so that the test efficiency is greatly improved, and the test cost is reduced. For the final test result, if the memory test fails, the corresponding ERROR information code can be prompted to display, and common fault types such as address decoding fault (AF), fixed fault (SAF), jump fault (TF), coupling Fault (CF) and the like are shown.
In a specific embodiment, the CPU detection unit of the test fixture is a communication channel between the FPGA module and the CPU, the signal is a serial port, and the serial port of the test fixture needs to be connected to the serial port of the test platform motherboard before testing. The communication between the FPGA module and the CPU is transmitted through the serial port, and the FPGA module can report the number of memory strips of the current jig, the current test progress, the test pass/fail information, parameters set by the management network port and the like to the CPU through the serial port. In addition, the CPU detection unit can also provide a management network port, and the remote management function of the jig can be realized through the external management network port. The management network port can also set the test times of the memory strip, specify the repeated test requirement of the memory strip, and can also set the memory strip for retesting the FAIL.
In addition, the test fixture may further include an indication unit for displaying a test condition and controlling a test process, where the indication unit indicates a current test condition for the FPGA module, and optionally, the indication unit is a liquid crystal screen capable of displaying test information, through which the test condition of all memory banks of the current side fixture may be obtained in real time, for example, as shown in fig. 5 and 6, the memory slots not inserted into the memory banks are displayed in a first color (e.g., white), the memory slots inserted into the memory banks are displayed in a second color (e.g., yellow), when the current memory slots are tested, the current slot indication frame indicates a current status with a third color (e.g., green) and displays a progress percentage, when the third color (e.g., green) progress fills up 100% of the memory bank time table, and the current memory banks are tested pass, and the memory banks are indicated in a third color (e.g., green). When an error test fail occurs, a fourth color (e.g., red) may be used for fill indication.
In one embodiment, the step S101 includes:
and switching the memory signal to a test platform through the FPGA module based on a bypass mode.
In another embodiment, the step S101 further includes:
setting a signal enhancement mode for the FPGA module;
and based on the signal enhancement mode, performing signal enhancement processing on the memory signal through the FPGA module, and transferring the memory signal subjected to the signal enhancement processing to a test platform.
From the above, the two switching processing modes of the FPGA module for the memory signal are two, namely, bypass mode (Bypass mode) and driving compensation mode (signal enhancement mode). In the Bypass mode, the memory signal is directly connected to the memory slot by the golden finger, no processing is needed, and the internal signal of the FPGA module is in a direct mode. The memory signal of the golden finger end is directly connected to any memory slot through Bypass, and the memory signal is not subjected to any compensation processing in the mode.
The compensation driving mode is to take a signal enhancement of 6dB (or other value) for the memory signal, so that the compensation effect can be achieved when the memory signal is attenuated. When the internal of the FPGA module is set to be in a signal enhancement mode, the FPGA module can enhance the internal memory signal by 6dB, and then the enhanced internal memory signal is transferred to the internal memory slot, so that the attenuation caused by wiring can be compensated by the signal compensation.
It should be noted that, the Bypass mode and the compensation driving mode of the FPGA module may be set by a dial switch on the fixture, and the user may determine whether compensation is required according to the main frequency of the memory bank to be tested.
In an embodiment, the step S101 includes:
detecting the number of memory slots of the test platform and the number of memory stripes to be tested through the FPGA module;
reading and judging whether the memory bank to be tested is successfully connected or not through the FPGA module;
when the connection of the memory strips to be tested is judged to be successful, carrying out test initialization;
based on the basic input/output system, the communication is carried out with the test platform so as to read the test information; the test information comprises the frequency of the memory bank to be tested and the number of the test slot;
and setting the memory test times and failure retest parameters according to the test information.
In this embodiment, before the memory signal is sent to the FPGA module, the FPGA module first reads the number of memory slots included in the test platform, and confirms the number of memory banks placed in the memory slots, and at the same time, confirms whether the hardware connection of the memory banks is successful through the FPGA module, and performs test initialization after the confirmation is successful, which may specifically include CPU detection unit initialization, display unit initialization, management portal initialization, and so on. And then, the BIOS is communicated with the test platform through the BIOS to acquire information such as the frequency of the memory bank in the test platform, the number of the test slot and the like, and corresponding parameters are configured according to the acquired information, such as setting the memory test times according to the number of the test slot, and if the test fails, how to perform failure retest and the like.
In one embodiment, the memory signals include data signals, address signals, and control signals.
Referring to fig. 7, the memory signals are composed of data signals, address signals and control signals, and the three signals are connected to the FPGA module, which is responsible for processing the memory signals and then connecting the processed memory signals to the slots of the UDIMM0, UDIMM1, UDIMM2, UDIMM3 and UDIMM 4. FIG. 7 is a logic block diagram of memory signal transfer, wherein DDR data transfer logic is configured to transfer data signals from an upstream golden finger CPU memory to one of UDIMM0, UDIMM1, UDIMM2 and UDIMM3 at will;
the DDR address conversion logic is used for converting an address signal of the uplink golden finger CPU memory into one of UDIMM0, UDIMM1, UDIMM2 and UDIMM3 at will;
the DDR control conversion logic is used for arbitrarily converting a control signal of the uplink golden finger CPU memory into one of UDIMM0, UDIMM1, UDIMM2 and UDIMM 3;
it should be noted that, in the driving compensation mode, the data signal, the address signal and the control signal in the memory signal are all compensated.
In one embodiment, the step S102 includes:
the data signals, the address signals and the control signals are respectively connected to the first memory slot by the FPGA module;
and testing the first memory bank based on the data signals, the address signals and the control signals.
Referring to fig. 8 to 11, in fig. 8, the uplink signal DDR memory signal is transferred to the UDIMM0 memory slot by the golden finger, that is, the CPU data signal is connected to UDIMM0, the CPU address signal is connected to UDIMM0, and the CPU control signal is connected to UDIMM0. The logic can realize the memory bank to be tested on the memory slot UDIMM0 on the test fixture.
As shown in fig. 9, the uplink signal DDR memory signal is transferred to the UDIMM1 memory slot by a golden finger, i.e., the CPU data signal is connected to UDIMM1, the CPU address signal is connected to UDIMM1, and the CPU control signal is connected to UDIMM1. The logic can realize the memory bank to be tested on the memory slot UDIMM1 on the test fixture.
As shown in fig. 10, the uplink signal DDR memory signal is transferred to the UDIMM1 memory slot by a golden finger, i.e., the CPU data signal is connected to UDIMM1, the CPU address signal is connected to UDIMM1, and the CPU control signal is connected to UDIMM1. The logic can realize the memory bank to be tested on the memory slot UDIMM1 on the test fixture.
As shown in fig. 11, the uplink signal DDR memory signal is transferred to the UDIMM3 memory slot by a golden finger, i.e., the CPU data signal is connected to UDIMM3, the CPU address signal is connected to UDIMM3, and the CPU control signal is connected to UDIMM3. The logic can realize the memory bank to be tested on the memory slot UDIMM3 on the test fixture.
When the jig is fully inserted with 4 memory strips to be tested, the test platform can test the memory strips to be tested on the memory slots UDIMM0, UDIMM1, UDIMM2 and UDIMM3 on the jig without manual replacement operation.
Fig. 2 is a schematic block diagram of an FPGA-based memory bank testing apparatus 200 according to an embodiment of the present application, where the apparatus 200 is suitable for a testing platform including a plurality of memory slots, and includes:
the signal sending unit 201 is configured to send a memory signal to an FPGA module, and perform switching processing on the memory signal through the FPGA module;
the memory test unit 202 is configured to connect the converted memory signal to a first memory slot of a test platform by using the FPGA module, so as to test a first memory bank in the first memory slot;
the channel switching unit 203 is configured to send a channel switching instruction to the FPGA module after the first memory bank is tested, so that the FPGA module is connected with the second memory slot of the test platform, and test the second memory bank in the second memory slot; and the same is repeated until the test is completed on the memory strips in all the memory slots of the test platform.
In an embodiment, the signal transmitting unit 201 includes:
and the first switching unit is used for switching the memory signal to the test platform through the FPGA module based on a bypass mode.
In an embodiment, the signal transmitting unit 201 further includes:
the mode setting unit is used for setting a signal enhancement mode for the FPGA module;
and the second switching unit is used for carrying out signal enhancement processing on the memory signal through the FPGA module based on the signal enhancement mode and switching the memory signal subjected to the signal enhancement processing to the test platform.
In one embodiment, the FPGA-based memory strip test apparatus 200 further includes:
the quantity detection unit is used for detecting the quantity of the memory slots of the test platform and the quantity of the memory strips to be tested through the FPGA module;
the connection judging unit is used for reading and judging whether the memory bank to be tested is successfully connected or not through the FPGA module;
the test initialization unit is used for performing test initialization when judging that the memory bank to be tested is successfully connected;
the information reading unit is used for communicating with the test platform based on the basic input and output system so as to read test information; the test information comprises the frequency of the memory bank to be tested and the number of the test slot;
and setting the memory test times and failure retest parameters according to the test information.
In one embodiment, the memory signals include data signals, address signals, and control signals.
In one embodiment, the memory test unit 202 includes:
the signal connection unit is used for respectively connecting the data signals, the address signals and the control signals to the first memory slot by utilizing the FPGA module;
and the first test unit is used for testing the first memory bank based on the data signals, the address signals and the control signals.
Since the embodiments of the apparatus portion and the embodiments of the method portion correspond to each other, the embodiments of the apparatus portion are referred to the description of the embodiments of the method portion, and are not repeated herein.
In the description, each embodiment is described in a progressive manner, and each embodiment is mainly described by the differences from other embodiments, so that the same similar parts among the embodiments are mutually referred. For the system disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant points refer to the description of the method section. It should be noted that it will be apparent to those skilled in the art that various modifications and adaptations of the application can be made without departing from the principles of the application and these modifications and adaptations are intended to be within the scope of the application as defined in the following claims.
It should also be noted that in this specification, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
Claims (10)
1. The method for testing the memory stripe based on the FPGA is suitable for a test platform comprising a plurality of memory slots and is characterized by comprising the following steps:
transmitting a memory signal to an FPGA module, and carrying out switching processing on the memory signal through the FPGA module;
connecting the memory signals subjected to transfer processing to a first memory slot of a test platform by using the FPGA module so as to test a first memory strip in the first memory slot;
after the first memory bank is tested, a channel switching instruction is sent to the FPGA module so that the FPGA module is connected with a second memory slot of the test platform, and a second memory bank in the second memory slot is tested; and the same is repeated until the test is completed on the memory strips in all the memory slots of the test platform.
2. The method for testing the memory stripe based on the FPGA of claim 1, wherein the sending the memory signal to the FPGA module and performing the transfer processing on the memory signal by the FPGA module comprise:
and switching the memory signal to a test platform through the FPGA module based on a bypass mode.
3. The method for testing the memory stripe based on the FPGA of claim 1, wherein the sending the memory signal to the FPGA module and performing the transfer processing on the memory signal by the FPGA module further comprises:
setting a signal enhancement mode for the FPGA module;
and based on the signal enhancement mode, performing signal enhancement processing on the memory signal through the FPGA module, and transferring the memory signal subjected to the signal enhancement processing to a test platform.
4. The method for testing the memory bank based on the FPGA of claim 1, wherein before the step of sending the memory signal to the FPGA module, the method comprises:
detecting the number of memory slots of the test platform and the number of memory stripes to be tested through the FPGA module;
reading and judging whether the memory bank to be tested is successfully connected or not through the FPGA module;
when the connection of the memory strips to be tested is judged to be successful, carrying out test initialization;
based on the basic input/output system, the communication is carried out with the test platform so as to read the test information; the test information comprises the frequency of the memory bank to be tested and the number of the test slot;
and setting the memory test times and failure retest parameters according to the test information.
5. The FPGA-based memory stick test method of claim 1, wherein the memory signals include data signals, address signals, control signals.
6. The FPGA-based memory stick testing method according to claim 5, wherein the connecting the transferred memory signal to the first memory socket of the testing platform by using the FPGA module to test the first memory stick in the first memory socket includes:
the data signals, the address signals and the control signals are respectively connected to the first memory slot by the FPGA module;
and testing the first memory bank based on the data signals, the address signals and the control signals.
7. The utility model provides a memory strip testing arrangement based on FPGA, is applicable to the test platform that includes a plurality of memory slots, its characterized in that includes:
the signal sending unit is used for sending a memory signal to the FPGA module and carrying out switching processing on the memory signal through the FPGA module;
the memory test unit is used for connecting the memory signals after the transfer processing to a first memory slot of the test platform by utilizing the FPGA module so as to test a first memory strip in the first memory slot;
the channel switching unit is used for sending a channel switching instruction to the FPGA module after the first memory bank is tested, so that the FPGA module is connected with the second memory slot of the test platform, and the second memory bank in the second memory slot is tested; and the same is repeated until the test is completed on the memory strips in all the memory slots of the test platform.
8. The FPGA-based memory stick testing apparatus of claim 7, wherein the signal sending unit:
and the first switching unit is used for switching the memory signal to the test platform through the FPGA module based on a bypass mode.
9. The FPGA-based memory stick testing apparatus of claim 7, wherein the signal transmitting unit further comprises:
the mode setting unit is used for setting a signal enhancement mode for the FPGA module;
and the second switching unit is used for carrying out signal enhancement processing on the memory signal through the FPGA module based on the signal enhancement mode and switching the memory signal subjected to the signal enhancement processing to the test platform.
10. Memory strip test fixture based on FPGA, its characterized in that includes: the device comprises a CPU detection unit, an FPGA module and a test platform, wherein the FPGA module is respectively connected with the CPU detection unit and the test platform, and the test platform comprises a plurality of memory slots for placing memory strips;
the CPU test unit tests the memory bank in the test platform by using the FPGA-based memory bank test method according to any one of claims 1 to 6.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311143536.4A CN117194137A (en) | 2023-09-06 | 2023-09-06 | Memory stripe testing method, device and jig based on FPGA |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311143536.4A CN117194137A (en) | 2023-09-06 | 2023-09-06 | Memory stripe testing method, device and jig based on FPGA |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN117194137A true CN117194137A (en) | 2023-12-08 |
Family
ID=88993581
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202311143536.4A Pending CN117194137A (en) | 2023-09-06 | 2023-09-06 | Memory stripe testing method, device and jig based on FPGA |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN117194137A (en) |
-
2023
- 2023-09-06 CN CN202311143536.4A patent/CN117194137A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101325625B (en) | System, apparatus and method for testing remote handset | |
| CN104483959A (en) | Fault simulation and test system | |
| CN110646674B (en) | Radio frequency chip pin impedance test method | |
| CN111063386A (en) | DDR chip testing method and device | |
| CN112463243B (en) | Online cascade loading firmware system based on boundary scanning and method thereof | |
| EP1939748A1 (en) | Circuit state scan-chain, data collection system and emulation method | |
| CN101102566B (en) | A design method and debugging method for mobile phone JTAG debugging interface signals | |
| CN110058147A (en) | Chip test system and method based on fpga | |
| CN101713812A (en) | Test system, test method and test interface board of IC design circuit board | |
| CN101593903B (en) | Test backboard, backboard-based loading method and backboard-based testing method | |
| CN103077114A (en) | Automatic testing method based on communication protocol of temperature measuring device | |
| CN103376340A (en) | Adapter plate, a multi-platform serial test system and method | |
| CN101751313B (en) | Measuring device of input/output end port and measuring method thereof | |
| CN111381150B (en) | Chip automatic verification system and method thereof | |
| CN102053898A (en) | Method for testing bus interface on PCIE (Peripheral Component Interface Express) slot of host and read-write test method thereof | |
| CN1987509A (en) | Power detecting system and method | |
| CN117194137A (en) | Memory stripe testing method, device and jig based on FPGA | |
| CN110412496B (en) | Test function quick self-checking circuit and method for integrated circuit multi-parameter tester | |
| CN105676024A (en) | Aging test method and device for electronic product | |
| CN106059723B (en) | Signal generating device and method, error code tester and method | |
| US11953550B2 (en) | Server JTAG component adaptive interconnection system and method | |
| US8346498B2 (en) | Programmable device testing | |
| CN113254290A (en) | Memory particle multidimensional test method, device and system and readable storage medium | |
| CN200996981Y (en) | Terminal-module tester | |
| CN217766718U (en) | Chip testing system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |