CN117193706A - Data transmission module, on-chip information output device and method, and chip - Google Patents

Abstract

The application discloses a data transmission module, an on-chip information output device, a method and a chip, wherein the data transmission module comprises: the device comprises a receiving unit, a FIFO buffer memory and a packaging unit; the receiving unit is used for receiving a data stream and sending the data stream into the FIFO buffer; and the packaging unit is used for extracting the data in the FIFO buffer after the data in the FIFO buffer reach the set length, and packaging the data to obtain a data packet with a set format. By using the scheme of the application, high-speed signal data in the SoC can be stably transmitted to the outside of the chip.

Description

Data transmission module, on-chip information output device and method, and chip

Technical Field

The application relates to the technical field of hardware, in particular to a data transmission module, an on-chip information output device, a method and a chip.

Background

When software debugging is performed on a chip, some debugging (debug) tools are usually needed, and these debug tools are limited, so that a large amount of program flow/data is difficult to store, and even if the program flow/data can be stored on the chip, the program flow/data is limited by the on-chip storage space, so that some software or chip problems are difficult to solve. For example, for DDR (Double Data Rate) bandwidth test, CPU link Data (i.e., trace Data) capture, and communication digital end Data verification, these program flows or Data flows have some common characteristics, that is, the Data size is large, the Rate is high, and it is difficult to solve by means of conventional debug means.

Disclosure of Invention

The embodiment of the application provides a data transmission module, an on-Chip information output device and method and a Chip, which can stably transmit high-speed signal data inside a System on Chip (SoC) to the outside of the Chip.

In one aspect, an embodiment of the present application provides a data transmission module, including: the device comprises a receiving unit, a FIFO buffer memory and a packaging unit;

the receiving unit is used for receiving a data stream and sending the data stream into the FIFO buffer;

and the packaging unit is used for extracting the data in the FIFO buffer after the data in the FIFO buffer reach the set length, and packaging the extracted data to obtain a data packet with a set format.

Optionally, the data stream received by the receiving unit is from a plurality of different data sources, and the data buffered within the set length corresponds to the same data source.

Optionally, the data formats of the different data sources are the same or different.

Optionally, the data format includes any one or more of: handshake mode data, source synchronization mode data, logic analysis mode data.

Optionally, the format of the data packet includes the following fields: synchronization identification, frame header, data, check bit.

Optionally, the packaging unit encodes the extracted data and packages the encoded data to obtain a data packet with a set format.

On the other hand, the embodiment of the application also provides an on-chip information output device, which comprises: a multiplexer, a data transmitter, and a serial physical interface; the data transmitter comprises the data transmission module;

the multiplexer is used for receiving the data streams from a plurality of hosts and selecting one of the data streams of the hosts to output to the data transmitter;

the data transmission circuit is used for carrying out encapsulation processing on the data stream received by the data transmitter according to a set length and outputting encapsulated data packets;

the serial physical interface is used for outputting the data packet to the outside of the chip.

Optionally, the apparatus further comprises: and the overflow state register is used for indicating whether overflow occurs in the data transmission process.

Optionally, the serial physical interface includes one or more DSI interfaces, and/or one or more CSI interfaces.

Optionally, the DSI interface and the CSI interface are single-wire, or two-wire, or four-wire interfaces.

Optionally, the apparatus further comprises: a channel enable register, a test module;

the test module is used for generating one or more test data streams with set formats and inputting the test data streams into the data transmitter through a test channel;

the channel enabling register is used for controlling the test channel to be opened or closed.

Optionally, the apparatus further comprises: and the controller is used for controlling the transmission rate of the test data stream entering the data transmitter.

Optionally, the controller is further configured to output a selection signal; the multiplexer selects one of the hosts to output the data to the data transmitter according to the selection signal.

On the other hand, the embodiment of the application also provides an on-chip information output method, which comprises the following steps:

the method for outputting the on-chip data to the outside of the chip by utilizing the on-chip data transmission link specifically comprises the following steps:

outputting data from a plurality of hosts to the FIFO buffer in a multiplexing mode;

after the data in the FIFO buffer reaches a set length, extracting the data of the FIFO buffer and packaging the data into a data packet with a set format;

and outputting the data packet to the outside of the chip through a serial physical interface.

Optionally, the method further comprises:

before working, the data transmission link is tested, which specifically comprises:

generating one or more test data streams in a set format;

outputting the test data stream to the outside of the chip by utilizing the data transmission link;

and determining whether the data transmission link is normal according to the test data flow output to the outside of the chip.

On the other hand, the embodiment of the application also provides a chip, which comprises the on-chip information output device.

In another aspect, embodiments of the present application also provide a computer-readable storage medium, on which a computer program is stored, which when being executed by a processor performs the steps of the above-described method.

The data transmission module, the on-chip information output device and the method provided by the embodiment of the application input the high-speed signal data in the chip into the FIFO buffer, extract the data in the FIFO buffer after the data in the FIFO buffer reach the set length, package the data into the data packet with the set format, and provide the transfer routing function for the on-chip data. Accordingly, the on-chip information output device and method provided by the embodiment of the application use the transfer routing function of the data transmission module to package the high-speed signal data from a plurality of different hosts in the chip into the data packet with the set format, and then output the data packet to the outside of the chip through the serial physical interface, so that the on-chip high-speed signal data can be simply and conveniently stably transmitted to the outside of the chip, and further the outside of the chip can be used for carrying out corresponding analysis processing on the data.

Furthermore, the scheme of the application can be compatible with data in different formats of various data sources, and has strong adaptability.

Further, when the data in the extracted FIFO is packaged, the corresponding data is encoded and then packaged, so that the chip external receiving equipment can be ensured to correctly analyze the original data, and the correctness of the data is ensured.

Further, the serial physical interface may include multiple types of interfaces, meeting the requirements of multiple off-chip device transmission interfaces.

Further, through the designed test channel, the data transmission channel provided by the data transmission module is tested by using the test data stream before working, and on-chip data is output to the outside of the chip under the condition that the data transmission channel is normal, so that the correctness of data transmission is fully ensured.

Furthermore, the transmission rate of the test data stream is designed to be adjustable, so that the test can be performed aiming at the test data streams with different transmission rates, and the output requirements of the on-chip data with different transmission rates can be better met.

Drawings

Fig. 1 is a schematic structural diagram of a data transmission module according to an embodiment of the present application;

FIG. 2 is an example of a packet structure after encapsulation in an embodiment of the present application;

FIG. 3 is a schematic diagram of an on-chip information output device according to an embodiment of the present application;

fig. 4 is a schematic diagram of another structure of an on-chip information output device according to an embodiment of the present application;

fig. 5 is a schematic diagram of another structure of an on-chip information output device according to an embodiment of the present application;

FIG. 6 is a flowchart of a method for outputting on-chip information according to an embodiment of the present application;

fig. 7 is another flowchart of an on-chip information output method according to an embodiment of the present application.

Detailed Description

In order to make the above objects, features and advantages of the present application more comprehensible, embodiments accompanied with figures are described in detail below.

Fig. 1 is a schematic structural diagram of a data transmission module according to an embodiment of the present application.

The data transmission module 10 includes: a receiving unit 11, a FIFO buffer 12, an encapsulating unit 13.

Wherein:

the receiving unit 11 is configured to receive a data stream and send the data stream to the FIFO buffer 12;

the encapsulation unit 13 is configured to extract the data in the FIFO buffer 12 after the data in the FIFO buffer 12 reaches the set length, and encapsulate the data to obtain a data packet with a set format.

It should be noted that, in practical applications, the size of the FIFO buffer 12 may be configured according to needs, which is not limited to this embodiment of the present application.

The data stream received by the receiving unit 11 may be from a plurality of different data sources and the data buffered within the set length corresponds to the same data source. That is, only data streams from the same data source are received at a certain time.

In addition, it should be noted that the data formats of different data sources may be the same or different, which is not limited to the embodiment of the present application. For example, the data format may include, but is not limited to, any one or more of the following: handshake mode data, source synchronization mode data, logic analysis mode data.

The data formats of different data sources are the same or not, and the structure of the packaged data packet adopts a unified format, for example, one structure example of the data packet is shown in fig. 2, and includes the following fields: synchronization (SYNC) identification, frame HEADER (HEADER), DATA (DATAn … DATA 0), check bits.

Wherein:

the synchronous identification field is used for identifying a packet of data, so that the off-chip equipment can conveniently analyze the data from the corresponding position;

the frame header field is used for inserting some transmission configuration information, such as a source of corresponding transmission data and the like; the data field is used for bearing the extracted data in the FIFO buffer;

the check bit field is used for checking the data carried in the data packet so as to ensure the correctness of the data.

In order to further improve the accuracy and the data transmission efficiency of the data, the data extracted from the FIFO buffer 12 may be encoded and encapsulated, that is, the encoded data may be placed in the data field, for example, but not limited to, 8b10b encoding.

Correspondingly, based on the data transmission module, the embodiment of the application also provides an on-chip information output device.

Fig. 3 is a schematic structural diagram of an on-chip information output device according to an embodiment of the present application.

In this embodiment, the on-chip information output apparatus 300 includes: a multiplexer 301, a data transmitter 302, and a serial physical interface 303. Wherein the data transmitter 302 includes the data transmission module 10 described above.

The multiplexer 301 is configured to receive data streams from a plurality of hosts, and select one of the data streams for outputting to the data transmitter; m0 to m2 in fig. 3 represent different hosts;

the data transmission module 10 is configured to perform encapsulation processing on the data stream received by the data transmitter 302 according to a set length, and output an encapsulated data packet;

the serial physical interface 303 is configured to output the data packet to an off-chip device, for example, to a corresponding device outside the chip.

It should be noted that the data streams from different hosts may have the same or different rates. Considering that in some cases, such as when the rate of the data stream output by the host is greater than the rate of the data packet output by the serial physical interface 303, the FIFO may overflow, for this purpose, in a non-limiting embodiment, the on-chip information output device 300 may further include: an overflow status register (not shown) for indicating whether or not overflow has occurred during data transfer.

By monitoring the overflow state register, whether the current data transmission is abnormal or not can be conveniently determined in real time, so that the correct output of the on-chip data is ensured.

In specific applications, the serial physical interface 303 may employ a mobile industry processor interface (Mobile Industry Processor Interface, MIPI), for example, may include one or more display serial interfaces (Display Serial Interface, DSI), and/or one or more camera serial interfaces (Camera Serial Interface, CSI), although other serial interfaces may be included, and embodiments of the present application are not limited in this respect. In addition, the DSI interface and the CSI interface may be a single-wire, or a two-wire, or a four-wire interface, etc.

The CSI protocol is a communication protocol used between a camera, an image sensor and a processor, defines a high-speed serial interface, supports various data formats and transmission modes, and can realize the transmission of high-definition video and images. The DSI protocol is a communication protocol used between a display and a processor, defines a high-speed serial interface, supports various data formats and transmission modes, and can realize the transmission of high-definition video and images.

The on-chip information output device provided by the embodiment of the application utilizes the transfer routing function of the data transmission module to package the high-speed signal data from a plurality of different hosts in the chip into the data packet with the set format, and then outputs the data packet to the outside of the chip through the serial physical interface, so that the on-chip high-speed signal data can be simply and conveniently stably transmitted to the outside of the chip, and further the outside of the chip can be utilized to perform corresponding analysis processing on the data, such as DDR bandwidth test, CPU link data capture, communication digital end data verification and the like.

Fig. 4 is a schematic diagram of another on-chip information output device according to an embodiment of the present application.

The difference from the embodiment shown in fig. 3 is that in this embodiment, the on-chip information output apparatus 300 further includes: a channel enable register 304 and a test module 305. Wherein:

the test module 305 is configured to generate one or more test data streams in a set format, and input the test data streams to the data transmitter 302 through a test channel;

the channel enable register 304 is used to control the test channel to be opened or closed.

In this embodiment, before the on-chip information output apparatus 300 works, the channel enable register 304 is used to open a test channel, the data transmission module 10 packages the test data stream generated by the test module 305, outputs the test data stream to the outside of the chip through the serial physical interface 303, and detects the test data output to the outside of the chip, so as to determine whether the data transmission path is normal. For example, whether the data accords with a certain format is checked through a binary tool, if so, the data transmission path is normal, otherwise, the data transmission path is abnormal.

It should be noted that the test channels may have one or more test channels for the purpose of testing the correctness of the transmission link. Such as in use, select a test channel, tracking 1 or tracking in2.

Wherein, the tracking 1 data format is as follows (for example, 33 bits per packet of data):

hexadecimal format representation:

01FFFF FF F0- - -1 packet data

0000000000- - -1 packet data

01FF FF FE-1 packet data

0000000002- - -1 packet data

01FF FF FC- - -1 packet data

00 00000004- - -1 packet data

……

The data shows the change rule, and after the data is output to the outside of the chip, whether the output data format is consistent with the change rule can be directly observed, so that whether the data transmission channel is normal is further determined.

Wherein, the data format of each packet of the tracking 2 is as follows (for example, 33 bits of data per packet):

hexadecimal format representation:

004 a and 4 a-1 packet data

01 2 b-1 packet data

00a5 25 25- - -1 packet data

01ea 15 95- - -1 packet data

……

Each packet of data may be in any of the formats described above, and the rule of the data output to the outside of the chip cannot be directly observed, and the data may be checked by using an analysis script to determine whether the data transmission path is normal.

Accordingly, when there are multiple test channels, different test channels may be gated by different values in the channel enable register 304.

Further, as shown in fig. 5, in another non-limiting embodiment of the on-chip information output apparatus provided in the embodiment of the present application, the on-chip information output apparatus 300 may further include:

a controller 306 for controlling the transmission rate of the test data stream into the data transmitter 302.

Further, the controller 306 is also configured to output a selection signal.

Accordingly, the multiplexer 301 may select one of the hosts to output data to the data transmitter 302 according to the selection signal.

The data transmission process in the on-chip information output apparatus 300 of the present application is described in detail below with reference to fig. 1 and 5.

Before the on-chip information output device 300 works, firstly, corresponding control words are written in the channel enabling register 304, the test channel is opened, the test module 305 generates and outputs test data to the data transmission module 10, the controller 306 controls the output rate of the test data, the data transmission module 10 packages and packages the test data, then transmits the test data to the outside of the chip through the serial physical interface 303, and the data transmission path is determined to be normal by detecting the test data transmitted to the outside of the chip.

After determining that the data transmission path is normal, the data stream generated by each host in the chip can be output to the outside of the chip. Assuming that the data of the host m0 is required to be output to the outside of the chip currently, the controller 306 outputs a selection signal, outputs a data stream of the host m0 to the data transmitter 302 through the multiplexer 301, the receiving unit 11 synchronizes the data stream to the inside of the data transmission circuit 10, then the data enters the internal FIFO buffer 12, after the data in the FIFO buffer 12 reaches a set length, the data in the FIFO buffer 12 is sent to the packaging unit 13, the packaging unit 13 performs identification addition and check bit addition on the data to obtain a packaged data packet, and then sends the packaged data packet to the serial physical interface 303 to be output to the outside of the chip.

When the FIFO 12 is empty, the next batch of data is transferred into the FIFO 12, and so on, all data of the host m0 can be output from on-chip to off-chip.

When data of other hosts, such as host m2, needs to be output to the off-chip, the controller 306 outputs a corresponding selection signal, and outputs the data stream of host m2 to the data transmitter 302 through the multiplexer 301, and then, all data of host m2 is finally output from the on-chip to the off-chip, similar to the output process of the data stream of host m0 described above.

The data synchronization between the data source of each host and the data transmission module 10 depends on the designed bus clock signal, data signal, bus valid signal, bus ready signal, etc., and by the combination of these signals, synchronization of signal data in different modes can be achieved. Such as:

handshake mode (Handshake mode) signal: depending on the bus clock signal, the data signal, the bus valid signal, the bus ready signal;

source synchronization pattern (Source Synchronous mode) signal: depending on the bus clock signal, the data signal, the bus valid signal;

logic analysis mode (Logic analyzer mode) signal: depending on the data signal.

The specific mode to be selected is determined by the signals required for chip design, and the embodiment of the application is not limited.

Of course, the above-mentioned signals of each mode are only examples, and in specific applications, signals of other modes are also possible, and may be specifically determined according to actual needs.

Correspondingly, the embodiment of the application also provides an on-chip information output method, which outputs on-chip data to the outside of the chip by utilizing a data transmission link in the chip, and the specific flow is shown in fig. 6, and comprises the following steps:

in step 601, data from a plurality of hosts is output to the FIFO buffer by multiplexing.

Step 602, after the data in the FIFO buffer reaches the set length, extracting the data in the FIFO buffer and encapsulating the data into a data packet with a set format.

The specific format of the data packet is not limited in this embodiment, and for example, in a non-limiting embodiment, the data packet structure shown in fig. 2 may be used.

Step 603, outputting the data packet to the outside of the chip through the serial physical interface.

According to the on-chip information output method provided by the embodiment of the application, the transfer routing function of the data transmission module is utilized, after the high-speed signal data from a plurality of different hosts in the chip are packaged into the data packet with the set format, the data packet is output to the outside of the chip through the serial physical interface, so that the high-speed signal data in the chip can be simply and conveniently stably transmitted to the outside of the chip, and further, the data can be subjected to corresponding analysis processing such as DDR bandwidth test, CPU link data grabbing, communication digital end data verification and the like by utilizing the outside of the chip.

Fig. 7 is another flowchart of an on-chip information output method according to an embodiment of the present application.

In this embodiment, before the operation, the data transmission link is tested, and after it is determined that the on-chip data link is transmitting normally, the on-chip data to be exported is output to the outside of the chip. The embodiment shown in fig. 7 includes the following steps:

in step 701, a test data stream of one or more set formats is generated.

Step 702, outputting the test data stream to the off-chip by using the data transmission link.

Step 703, determining whether the data transmission link is normal according to the test data stream output to the off-chip. If so, step 704 is performed; otherwise, step 707 is performed.

In step 704, data from multiple hosts is output to the FIFO buffer by multiplexing.

Step 705, after the data in the FIFO buffer reaches the set length, extracting the data in the FIFO buffer and encapsulating the data into a data packet with a set format.

Step 706, outputting the data packet to the outside of the chip through the serial physical interface.

Step 707, error prompt is performed.

Through the test of the data transmission path before work, the on-chip data can be output to the outside of the chip under the condition that the data transmission path is normal, and the correctness of the data transmission is further ensured.

Correspondingly, the application further provides a chip, which comprises the on-chip information output device 300 of any embodiment.

In a specific implementation, the above-mentioned apparatus may correspond to a Chip of a corresponding function in the network device and/or the user device, such as an SOC (System-On-a-Chip), a baseband Chip, a Chip module, etc.

In a specific implementation, regarding each apparatus and each module/unit included in each product described in the above embodiments, it may be a software module/unit, or a hardware module/unit, or may be a software module/unit partially, or a hardware module/unit partially. For example, for each device or product applied to or integrated on a chip, each module/unit included in the device or product may be implemented in hardware such as a circuit, or at least part of the modules/units may be implemented in software program, where the software program runs on a processor integrated inside the chip, and the rest (if any) of the modules/units may be implemented in hardware such as a circuit; for each device and product applied to or integrated in the chip module, each module/unit contained in the device and product can be realized in a hardware manner such as a circuit, different modules/units can be located in the same component (such as a chip, a circuit module and the like) or different components of the chip module, or at least part of the modules/units can be realized in a software program, the software program runs on a processor integrated in the chip module, and the rest (if any) of the modules/units can be realized in a hardware manner such as a circuit; for each device, product, or application to or integrated with the terminal, each module/unit included in the device, product, or application may be implemented by using hardware such as a circuit, different modules/units may be located in the same component (for example, a chip, a circuit module, or the like) or different components in the terminal, or at least part of the modules/units may be implemented by using a software program, where the software program runs on a processor integrated inside the terminal, and the remaining (if any) part of the modules/units may be implemented by using hardware such as a circuit.

The embodiment of the application also discloses a storage medium which is a computer readable storage medium and is stored with a computer program, and the computer program can execute part or all of the steps of the method shown in fig. 6 or fig. 7 when running. The storage medium may include Read-Only Memory (ROM), random access Memory (Random Access Memory, RAM), magnetic or optical disks, and the like. The storage medium may also include non-volatile memory (non-volatile) or non-transitory memory (non-transitory) or the like.

It should be understood that the term "and/or" is merely an association relationship describing the associated object, and means that three relationships may exist, for example, a and/or B may mean: a exists alone, A and B exist together, and B exists alone. In this context, the character "/" indicates that the front and rear associated objects are an "or" relationship.

The term "plurality" as used in the embodiments of the present application means two or more.

The first, second, etc. descriptions in the embodiments of the present application are only used for illustrating and distinguishing the description objects, and no order is used, nor is the number of the devices in the embodiments of the present application limited, and no limitation on the embodiments of the present application should be construed.

It should be understood that, in various embodiments of the present application, the sequence numbers of the foregoing processes do not mean the order of execution, and the order of execution of the processes should be determined by the functions and internal logic thereof, and should not constitute any limitation on the implementation process of the embodiments of the present application.

The above embodiments may be implemented in whole or in part by software, hardware, firmware, or any other combination. When implemented in software, the above-described embodiments may be implemented in whole or in part in the form of a computer program product. The computer program product comprises one or more computer instructions or computer programs. When the computer instructions or computer program are loaded or executed on a computer, the processes or functions described in accordance with embodiments of the present application are produced in whole or in part. The computer may be a general purpose computer, a special purpose computer, a computer network, or other programmable apparatus. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from one website site, computer, server, or data center to another website site, computer, server, or data center by wired or wireless means.

It should be understood that, in various embodiments of the present application, the sequence numbers of the foregoing processes do not mean the order of execution, and the order of execution of the processes should be determined by the functions and internal logic thereof, and should not constitute any limitation on the implementation process of the embodiments of the present application.

In the several embodiments provided in the present application, it should be understood that the disclosed method, apparatus and system may be implemented in other manners. For example, the device embodiments described above are merely illustrative; for example, the division of the units is only one logic function division, and other division modes can be adopted in actual implementation; for example, multiple units or components may be combined or may be integrated into another system, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, which may be in electrical, mechanical or other form.

The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed over a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional unit in the embodiments of the present application may be integrated in one processing unit, or each unit may be physically disposed separately, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in hardware plus software functional units.

The integrated units implemented in the form of software functional units described above may be stored in a computer readable storage medium. The software functional unit is stored in a storage medium, and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to perform part of the steps of the method according to the embodiments of the present application.

Although the present application is disclosed above, the present application is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the application, and the scope of the application should be assessed accordingly to that of the appended claims.

Claims (17)

1. A data transmission module, the module comprising: the device comprises a receiving unit, a FIFO buffer memory and a packaging unit;

the receiving unit is used for receiving a data stream and sending the data stream into the FIFO buffer;

and the packaging unit is used for extracting the data in the FIFO buffer after the data in the FIFO buffer reach the set length, and packaging the extracted data to obtain a data packet with a set format.

2. The data transmission module of claim 1, wherein the data streams received by the receiving unit are from a plurality of different data sources, and the data buffered within the set length corresponds to the same data source.

3. The data transmission module of claim 2, wherein the data formats of different data sources are the same or different.

4. A data transmission module according to claim 3, wherein the data format comprises any one or more of: handshake mode data, source synchronization mode data, logic analysis mode data.

5. The data transmission module according to any one of claims 1 to 4, wherein the format of the data packet comprises the following fields: synchronization identification, frame header, data, check bit.

6. The data transmission module according to claim 5, wherein the encapsulation unit encodes the extracted data and encapsulates the encoded data to obtain the data packet in the set format.

7. An on-chip information output apparatus, the apparatus comprising: a multiplexer, a data transmitter, and a serial physical interface; the data transmitter comprises a data transmission module according to any one of claims 1 to 6;

the multiplexer is used for receiving the data streams from a plurality of hosts and selecting one of the data streams of the hosts to output to the data transmitter;

the data transmission circuit is used for carrying out encapsulation processing on the data stream received by the data transmitter according to a set length and outputting encapsulated data packets;

the serial physical interface is used for outputting the data packet to the outside of the chip.

8. The on-chip information output apparatus according to claim 7, wherein the apparatus further comprises:

and the overflow state register is used for indicating whether overflow occurs in the data transmission process.

9. The on-chip information output device according to claim 7, wherein the serial physical interface comprises one or more DSI interfaces, and/or one or more CSI interfaces.

10. The on-chip information output apparatus according to claim 9, wherein the DSI interface and the CSI interface are single-wire, or two-wire, or four-wire interfaces.

11. An on-chip information output apparatus according to any one of claims 7 to 10, wherein the apparatus further comprises: a channel enable register, a test module;

the test module is used for generating one or more test data streams with set formats and inputting the test data streams into the data transmitter through a test channel;

the channel enabling register is used for controlling the test channel to be opened or closed.

12. The on-chip information output apparatus according to claim 11, wherein the apparatus further comprises:

and the controller is used for controlling the transmission rate of the test data stream entering the data transmitter.

13. The on-chip information output apparatus according to claim 12, wherein,

the controller is also used for outputting a selection signal;

the multiplexer selects one of the hosts to output the data to the data transmitter according to the selection signal.

14. An on-chip information output method, the method comprising:

the method for outputting the on-chip data to the outside of the chip by utilizing the on-chip data transmission link specifically comprises the following steps:

outputting data from a plurality of hosts to the FIFO buffer in a multiplexing mode;

after the data in the FIFO buffer reaches a set length, extracting the data of the FIFO buffer and packaging the data into a data packet with a set format;

and outputting the data packet to the outside of the chip through a serial physical interface.

15. The on-chip information output method according to claim 14, characterized in that the method further comprises:

before working, the data transmission link is tested, which specifically comprises:

generating one or more test data streams in a set format;

outputting the test data stream to the outside of the chip by utilizing the data transmission link;

and determining whether the data transmission link is normal according to the test data flow output to the outside of the chip.

16. A chip comprising an on-chip information output device according to any one of claims 7 to 13.

17. A computer readable storage medium, on which a computer program is stored, characterized in that the computer program, when being executed by a processor, performs the steps of the method of claim 14 or 15.