CN117193510A

CN117193510A - Memory control method, memory, system on chip and terminal

Info

Publication number: CN117193510A
Application number: CN202210616146.3A
Authority: CN
Inventors: 刘卓睿
Original assignee: Zeku Technology Shanghai Corp Ltd
Current assignee: Zeku Technology Shanghai Corp Ltd
Priority date: 2022-05-31
Filing date: 2022-05-31
Publication date: 2023-12-08

Abstract

The embodiment of the application discloses a memory control method, a memory, a system-on-chip and a terminal, and belongs to the technical field of storage. The control method of the memory comprises the following steps: controlling the first storage element to switch to an idle power-down state under the condition that a first control signal is detected on a chip select bus of the first storage element; wherein the first storage element is a portion of the n storage elements. The embodiment of the application provides a control method of a memory, which is used for independently controlling a memory element to be switched into an idle power-down state through a chip selection bus on each memory element, so that the power-saving control of the granularity of the memory element is realized, the accurate control of finer granularity is realized under the condition of ensuring the normal operation of a system, and the effect of more excellent power consumption saving is achieved.

Description

Memory control method, memory, system on chip and terminal

Technical Field

The embodiment of the application relates to the technical field of storage, in particular to a control method of a memory, the memory, a system on chip and a terminal.

Background

The memory is an indispensable electronic component in the terminal. A common memory on a cell phone is currently low power double data rate memory (Low Power Double Data Rate SDRAM, LPDDR), such as 4-channel LPDDR.

In the related art, the memory includes x memory channels, where x is an even number. When the processor does not need to read and write the memory, all x storage elements corresponding to the x memory channels can be put into a dormant state, so as to achieve the effect of saving electricity.

However, as the number of memory channels in the memory increases, the above manner cannot meet the power saving requirement in some situations.

Disclosure of Invention

The embodiment of the application provides a memory control method, a memory, a system-on-chip and a terminal. The technical scheme is as follows:

in one aspect, an embodiment of the present application provides a method for controlling a memory, the method being performed by a memory, the memory including n storage elements, each storage element having an independent chip select bus, the memory including:

controlling the first storage element to switch to an idle power-down state under the condition that a first control signal is detected on a chip select bus of the first storage element;

wherein the first storage element is a part of the n storage elements, and n is a positive integer greater than 1.

In another aspect, an embodiment of the present application provides a method for controlling a memory, the method being performed by a master device, the master device being configured to control the memory, the memory including n storage elements, each of the storage elements having a separate chip select bus, the method including:

Outputting a first control signal to a chip selection bus of a first storage element, wherein the first control signal is used for controlling the first storage element to be switched to an idle power-down state;

On the other hand, the embodiment of the application provides a memory, which is used for realizing the control method of the memory.

In another aspect, an embodiment of the present application provides a system on a chip, including: a master device, a memory controller, and a memory;

the main equipment is connected with the storage controller through a main bus;

the storage controller is connected with the storage through a physical layer interface;

the memory is used for realizing the control method of the memory according to the aspect, and the master device is used for realizing the control method of the memory according to the aspect.

On the other hand, the embodiment of the application provides a terminal, which is used for realizing the control method of the memory in the aspect.

The embodiment of the application provides a control method of a memory, which is characterized in that a chip selection bus on each memory element is used for independently controlling the memory element to be switched into an idle power-down state, so that the power saving control of the granularity of the memory element is realized.

Drawings

FIG. 1 illustrates a schematic diagram of a system-on-chip provided in accordance with an exemplary embodiment of the present application;

FIG. 2 illustrates a schematic diagram of a memory provided by an exemplary embodiment of the present application;

FIG. 3 illustrates a schematic diagram of a memory provided by an exemplary embodiment of the present application;

FIG. 4 is a schematic diagram of an 8-memory channel storage according to an exemplary embodiment of the present application;

FIG. 5 illustrates a state-switching diagram of a memory provided by an exemplary embodiment of the present application;

FIG. 6 illustrates a schematic diagram of the partitioning of storage areas in a memory provided by an exemplary embodiment of the present application;

FIG. 7 illustrates a schematic diagram of the partitioning of storage areas in a memory according to an exemplary embodiment of the present application;

FIG. 8 is a flow chart illustrating a method of controlling a memory according to an exemplary embodiment of the present application;

FIG. 9 is a flow chart illustrating a method of controlling a memory according to an exemplary embodiment of the present application;

FIG. 10 is a diagram illustrating a state of a memory channel in a non-performance mode according to an exemplary embodiment of the present application;

FIG. 11 is a diagram illustrating a state of a memory channel in a performance mode according to an exemplary embodiment of the present application;

FIG. 12 is a diagram illustrating a state of a memory channel in an exit performance mode according to an exemplary embodiment of the present application;

FIG. 13 is a schematic diagram illustrating the state of an 8-memory channel storage according to an exemplary embodiment of the present application;

FIG. 14 is a diagram illustrating the partitioning of memory regions in a memory according to an exemplary embodiment of the present application;

fig. 15 shows a schematic structural diagram of a terminal according to an exemplary embodiment of the present application.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the present application more apparent, the embodiments of the present application will be described in further detail with reference to the accompanying drawings.

References herein to "a plurality" means two or more. "and/or", describes an association relationship of an association object, and indicates that there may be three relationships, for example, a and/or B, and may indicate: a exists alone, A and B exist together, and B exists alone. The character "/" generally indicates that the context-dependent object is an "or" relationship.

In the related art, a memory is designed to support several memory channels, and Chip Select (CS) technology is generally used to further increase the capacity (Density) of the memory.

For example, for a memory supporting 4 memory channels, 8 storage elements are provided in the memory, where the 8 storage elements correspond to the 4 memory channels, i.e., each memory channel corresponds to 2 storage elements. In the data reading and writing process, a target storage element is selected from 2 storage elements corresponding to the same memory channel based on a chip selection signal, and then the data reading and writing are carried out on the target storage element. When power consumption is required to be saved, all 8 storage elements of 4 memory channels are usually put into a dormant state or an idle state, which affects the performance of the memory.

In the embodiment of the application, a memory supporting n memory channels is designed, n storage elements in the memory respectively correspond to the n memory channels, each storage element is provided with an independent chip selection bus, the corresponding storage element is independently controlled to be switched to different states through each chip selection bus, and the requirements of memory requirement and power consumption saving are simultaneously met on the premise of not losing the performance of the memory.

The structure of the memory and the control method are described below by way of exemplary embodiments.

First, a brief description will be made of a state that may occur in the memory according to the present application:

Power-on/Power-up State): the voltage of the memory power supply rises to the normal working voltage and reaches a stable state.

Idle State: in this state, the memory does not provide data access service (or read/write service) to the host device, and although there is a small amount of voltage in the memory, the power consumption is very low.

Idle power down state (Idle Power Down State): also known as the Self-refresh (Self-refresh) state or Self-refresh state, which consumes less power than the idle state. In this state, the memory can generate refresh pulses by itself inside the device without an external refresh command to maintain the data retention.

Reset State (Reset State): refers to the memory being restored to a default value or factory data state.

Operational state (Work mode): refers to the state in which memory is providing data access services to the host device.

Fig. 1 illustrates a schematic diagram of a System on Chip (SoC) structure including a memory according to an exemplary embodiment of the present application. The system on a chip of the present application is described with reference to at least one of a mobile terminal, such as a smart phone, a smart watch, an electronic book reader, a tablet computer, a laptop computer, a desktop computer, a television, a game machine, an augmented Reality (Augmented Reality, AR) terminal, a Virtual Reality (VR) terminal, a Mixed Reality (MR) terminal, a wearable device, and the like. The system on chip 100 in the present embodiment includes: a master device 101, a master bus 103, a memory controller 105, and a memory 200.

The master device 101 is connected to a memory controller 105 via a master Bus 103 (Primary Bus), and the memory controller 105 is connected to a memory 200 via a Physical Layer (PHY) interface. In some embodiments, the memory 200 is a dynamic random access memory (Dynamic Random Access Memory, DRAM). Optionally, the dynamic random access memory is packaged using a stack (Packaging on Packaging, poP).

The host device 101 is a processor or a non-processor with data read-write requirements. The host device may include, but is not limited to, a central processing unit (Central Processing Unit, CPU), an Image processor (Graphics Processing Unit, GPU), a Neural-network processor (Neural-network Processing Unit, NPU), a digital signal processor (Digital Signal Processor, DSP), and the like, and a non-processor such as an Image Sensor (Image Sensor), an Image signal processing unit (Image Signal Processing Unit, ISP), a video processing unit (Video Processing Unit, VPU), and the like. The above-mentioned master devices all have memory data read and/or write requirements during operation. The example of a processor including a CPU, GPU and NPU, and a non-processor including an image sensor and a VPU are schematically illustrated in FIG. 1, but are not limited thereto.

Wherein the processor connects various parts within the overall terminal using various interfaces and lines, performs various functions of the terminal and processes data by running or executing instructions, programs, code sets, or instruction sets stored in the memory, and invoking data stored in the memory.

In some embodiments, the processor may be implemented in at least one hardware form of digital signal processing (Digital Signal Processing, DSP), field programmable gate array (Field-Programmable Gate Array, FPGA), programmable logic array (Programmable Logic Array, PLA).

The processor may integrate one or a combination of several of CPU, GPU, NPU and baseband chips, etc. The CPU mainly processes an operating system, a user interface, an application program and the like; the GPU is used for rendering and drawing the content required to be displayed by the display screen; the NPU is used for realizing the AI function; the baseband chip is used for processing wireless communication.

In some embodiments, m links using AXI protocol are established between master device 101 and master bus 103, and between master bus 103 and memory controller 105. As shown in fig. 1, for example, an AXI link with a bit Width (Width) of 256bits is established between each host device 101 and the host bus 103, and between the host bus 103 and the memory controller 105.

In some embodiments, the memory controller 105 includes a Secondary bus (Secondary Sus), k controllers (corresponding to k memory channels), and a physical layer interface corresponding to each controller.

In some embodiments, a link employing the AXI protocol is established between the slave bus and the controller, and a branching function is implemented at the slave bus. For example, after branching from the bus (k branches are n), 8 AXI links with a bit width of 128bits are established between the slave bus and the controller. Accordingly, 8 AXI links of 128bits wide are established between memory controller 105 and memory 200.

The memory 200 is a memory supporting n (n > k) memory channels, and n storage elements in the memory 200 are each provided with an operation bus, that is, the operation buses of the storage elements are connected to the memory controller 105 in a concurrent manner.

Fig. 1 illustrates an example of integrating a memory in a system-on-chip (i.e., the memory is disposed inside the system-on-chip), and in other possible designs, the memory may be disposed outside the system-on-chip, which is not limited by the embodiment of the present application.

Fig. 2 illustrates a schematic structure of a memory according to an exemplary embodiment of the present application.

The memory 200 includes n (a positive integer greater than 1) storage elements 201. In some embodiments, the memory 200 is a dynamic random access memory and the memory element 201 is a memory die. Alternatively, the dynamic random access memory employs a stack package (package stack technique). The embodiments of the present application are not limited to the specific type of memory 200 and storage element 201.

In some possible designs, the internal grains of the memory element 201 may be arranged in a 2D manner or a 3D manner.

In some embodiments, the element parameters (e.g., capacity) of each storage element are the same, e.g., each storage element 201 is a 16Gb by 16 Data bit width (Data width) specification. In other embodiments, the component parameters of some storage elements are the same, the component parameters of some storage elements are different, or the component parameters of different storage elements are different, and the embodiment of the present application is not limited to specific component parameters of each storage element.

n memory elements 201 are packaged as one memory particle, such as a dynamic random access memory device employing stacked packaging (package-on-package technology). In some possible designs, n storage elements 201 are packaged in 2D or 3D, and embodiments of the present application are not limited to specific packaging methods.

In the embodiment of the application, the memory 200 supports n memory channels, so the number of the storage elements 201 in the memory 200 is equal to n, and the different storage elements 201 respectively correspond to the respective memory channels, i.e. the n storage elements correspond to the n memory channels.

For example, for a memory supporting 8 memory channels, 8 storage elements are disposed in the memory; for a memory supporting 6 memory channels, 6 storage elements are provided in the memory. The embodiment of the present application does not limit the specific number of the memory elements (the positive integer may be even or odd).

To improve parallelism in data access through different memory channels, power consumption is reduced without compromising memory performance, and in some embodiments, memory element 201 is provided with a chip select bus, as shown in FIG. 2. The n memory elements 201 each include a chip select bus 202, that is, the chip select buses 202 of the memory elements 201 are not shared, and the memory elements 201 switch states by their corresponding chip select buses 202.

The chip select bus 202 is used for selecting a chip from the memory element 201, and selecting control of different operation states of the memory element 201. Illustratively, when the high-performance application program is running, the chip selection bus is used for controlling part or all of the storage elements to be switched to the working state, so that the high-performance running requirement is met; when the high-performance application program is exited, a part of storage elements are controlled to be switched to an idle power-down state (Idle Power Down State) through the chip selection bus, other storage elements in a working state are not affected, and power consumption is saved under the granularity of the storage elements under the condition that normal operation of the system is ensured.

The memory element 201 is provided with an operation bus in addition to the chip select bus 202. In an alternative design, as shown in fig. 2, n storage elements 201 are respectively provided with working buses, that is, the working buses of the storage elements 201 are not shared, and each storage element 201 provides data access service to the outside through its corresponding working bus; alternatively, some or all of the memory elements 201 share a working bus, as shown in fig. 3, the memory channels 1 and 3 share the same set of working buses, the memory channels 2 and 4 share the same set of working buses, and so on, the memory channels n-2 and n share the same set of working buses, and the memory elements 201 sharing the same set of working buses provide data access services to the outside through the shared working buses.

The working bus includes at least some of an address control bus and a data bus. Wherein the Address control bus is used for addressing and receiving control instructions of external devices, and the Address control bus can comprise at least one of a Command/Address (CA) bus, a ClocK bus (CK) bus, a ZQ Calibration (ZQ Calibration) bus and a Reset (Reset) bus; the Data bus is used for Data interaction (Data reading and writing) with the external device, and may include at least one of a Data Queue (DQ) bus, a Read Data Strobe (RDQS) bus, a direct media interface (Direct Media Interface, DMI) bus, and a Word ClocK (WCK) bus.

In the present application, for ease of understanding, each storage element in the memory is schematically illustrated with an independent chip select bus and working bus.

The operation bus and the chip select bus are not all buses corresponding to the memory elements, that is, each memory element may have a bus shared with or unique to other memory elements in addition to the operation bus and the individual chip select bus.

In one possible design, the working bus includes at least one of a data queue bus, a read data strobe bus, a direct media interface bus, a word clock bus, a command/address bus, and a clock bus.

Illustratively, as shown in fig. 4, 8 storage elements 201,8 storage elements 201 are provided in the memory 200 corresponding to the memory channels A, B, C, D, E, F, G and H, respectively. Each memory element 201 is provided with a chip select bus 202. The working buses provided for each memory element 201 include a data queue bus, a read data strobe bus, a direct media interface bus, a word clock bus, a command/address bus, and a clock bus.

The data queue bus may be DQ [15:0] bus, the read data strobe bus may include RDQS [1:0] T and RDQS [1:0] C buses, the direct media interface bus may include DMI [1:0] bus, the word clock bus may include WCK [1:0] T and WCK [1:0] C buses, the command/address bus may be CA [6:0] bus, and the clock bus may include CK_T and CK_C buses.

In addition, the memory element 200 includes one or at least two reset buses; the memory element 200 contains one or more ZQ calibration buses. The ZQ calibration bus is connected to an external 240 Ω resistor and automatically calibrates the termination resistors and output drivers in the memory to maintain signal integrity in the presence of temperature and voltage variations.

The memory provided by the embodiment of the application has the advantages of high parallelism, high capacity and effective power consumption saving on the premise of not influencing the memory performance, so that the memory can be applied to the mobile terminal to improve the performance of the mobile terminal. The mobile terminal may be a smart phone, a smart watch, an electronic book reader, a tablet computer, a laptop, a desktop computer, a television, a game console, an AR terminal, a VR terminal, an MR terminal, a wearable device, or the like.

Under a possible application scenario, after the memory provided by the embodiment of the application is applied to a mobile terminal with an image shooting function (a memory controller which supports the same memory channel number is required to be set), the data read-write bandwidth can meet the requirements of high-speed shooting, american Yan Suanfa and AI algorithms, when shooting operation is not required, part of memory elements can be quickly switched to an idle power-down state, the shooting quality, user experience and overall performance of the mobile terminal are improved, meanwhile, the power consumption is saved, and the long-time standby requirement is met.

Under another possible application scenario, after the memory provided by the embodiment of the application is applied to the folding screen terminal (the memory controller supporting the same memory channel number is required to be set), the data read-write bandwidth can meet the requirement of running a plurality of application programs at the same time in the foreground, and when the application programs are exited, part of memory elements can be quickly switched to an idle power-down state, so that the support of the folding screen terminal to the concurrent application scenario is facilitated to be improved.

In summary, the embodiment of the application provides a memory supporting flexible control of memory elements, which independently controls the switching state of the memory elements through the chip selection bus on each memory element, thereby realizing effective control of some or all memory channels in a power consumption saving dimension, and achieving more excellent power consumption saving effect under the condition of ensuring normal operation of a system.

Fig. 5 shows a state change flowchart of a memory provided by an exemplary embodiment of the present application.

Initialization phase (mode one)

During the system start-up phase, after each storage element is powered on (Power-on), the master device puts each storage element in a Reset State (Reset State) by setting the Reset port of the storage element low, and performs a Reset procedure (Reset will clear the data stored in the storage element). In the reset State, the master device sets the reset ports of the storage elements high to enable all the storage elements to be in an Idle State, and sets the reset ports of part of the storage elements low to enable the part of the storage elements to be in an Idle power-down State. In the initialization stage of the method, one part of memory cells are initialized to be in an idle state, and the other part of memory elements are initialized to be in an idle power-down state, so that preparation is made for subsequent data reading and writing. Furthermore, in a subsequent process, the storage element will re-enter the initialization phase when an initialization event is triggered.

The memory state after the initialization stage in the present embodiment may also be referred to as a power consumption mode, that is, in the initialization procedure provided in the first embodiment, the memory is directly in the power consumption mode after the initialization is completed.

Initialization phase (mode two)

In the system start-up phase, after each storage element is powered on, the main device enables each storage element to be in a reset state through a reset port of a low storage element, and executes a reset process (resetting can clear data stored in the storage element). In the reset state, the main device initializes all the storage elements to an idle state through the reset port of the high storage element, and prepares for subsequent data reading and writing. Furthermore, in a subsequent process, the storage element will re-enter the initialization phase when an initialization event is triggered.

The two initialization modes can be alternatively executed.

Enter into Power consumption mode

When a first control signal is detected on a chip select bus of a storage element, the storage element switches from an idle state or an active state to an idle power down state. The first control signal is sent by the master device to the memory for controlling the storage element to switch to an idle power down state. In the power consumption mode, a part of the storage elements are still in an idle state, and the other part of the storage elements are in an idle power-down state. But does not exclude the case that in some implementations all storage elements are in an idle power down state.

In some embodiments, the first control signal is sent by the master device to the memory upon entering the power consumption mode; alternatively, the first control signal is sent to the memory when the master device exits the performance mode; alternatively, the first control signal is sent by the master device to the memory during an initialization phase.

Enter performance mode

When the second control signal is detected on the chip select bus of the memory element, the memory element switches from an idle power down state or idle state to an active state. The second control signal is sent by the master device to the memory for controlling the switching of the memory element to the operating state. In the performance mode, the master device controls all or most of the storage elements in the memory to be in an operational state.

In some embodiments, the second control signal is sent by the master device to the memory in entering the performance mode.

Exit performance mode

When a first control signal is detected on a chip select bus of a storage element, the storage element switches from an active state to an idle power down state. In the non-performance mode, a portion of the storage elements are in an idle power-down state and another portion of the storage elements are still in an operational state.

In the related art, the capacity of the memory is limited, and each storage element in the memory enters an idle state after being powered on and enters a working state when being accessed by external equipment, so as to provide data access service for the external equipment. However, in the embodiment of the application, the memory capacity of the memory is large, so that the memory requirement of most scenes can be met through part of the storage elements. If all the storage elements are set in the idle state in a unified way, the power consumption is greatly affected. Therefore, by arranging an independent chip selection bus on each storage element, the storage elements are controlled to be switched to an idle power-down state through the chip selection bus under a specific scene, and other storage elements are kept to work normally or to be in the idle state, so that the power consumption of the memory is reduced on the premise of not influencing the performance of the memory.

In this embodiment, by setting an independent chip selection bus on each storage element in the memory, it is possible to control the switching state of a portion of the memory channels by the chip selection bus without affecting other memory channels; compared with the control of all memory channels through a single reset bus or a chip selection bus, the scheme provided by the embodiment of the application can realize finer-granularity memory channel control and is beneficial to reducing the power consumption of the multi-channel memory.

The performance mode is understood to be a mode in which all or a majority of the memory elements are in an operating state, the non-performance mode is a mode in which a portion or a small portion of the memory elements are in an operating state, and the power consumption mode is a mode in which all of the memory elements are in a non-operating state such as an idle state or an idle power-down state. In different embodiments, the names of the performance mode, the non-performance mode, and the power consumption mode may be referred to as other names.

In one possible design, n storage elements in a memory are divided into at least two storage areas (regions), with different storage areas not affecting each other.

Optionally, the different storage areas are for use by different objects, which may include at least one of an operating system, kernel Space (Kernel Space), reserved Space (Reserved Space), and application programs.

In an illustrative example, as shown in fig. 6, a plurality of storage elements in a memory are divided into a first storage area 51 and a second storage area 52, wherein the first storage area 51 is used by a high-performance application program, and the high-performance application program refers to an application program with high memory requirement, such as a game application program, an AI application program, and the like; the second storage area 52 is used for default Kernel (Kernel) control, reserved space, and common application (Normal Usage Application) which may be default setting or custom or determined based on frequency of use, such as desktop application, clock application, etc.

In one possible design, a second memory region of the at least two memory regions is configured to Boot (Boot Up) during a system Boot process and provide memory services for the system. The storage capacity of the storage element in the second storage area meets the memory requirement when the system operates. In addition, a first storage area in at least two storage areas is electrified in the system starting process, and an initialization control signal sent by the main equipment is detected on the chip selection bus, so that initialization is completed, namely, the system is switched to an idle state after entering a reset state, and therefore the system can quickly enter the idle power-down state to save power consumption or quickly enter a working state to meet the running requirement of an application program.

In an illustrative example, as shown in fig. 7, a plurality of storage elements in a memory are divided into a first storage area 51, a second storage area 52, and a third storage area 53, wherein the first storage area 51 and the third storage area 53 are used for high-performance application programs, which refer to application programs with high memory requirements, such as game application programs, AI application programs, and the like; the second storage area 52 is used for default kernel control, reserved space, and common applications, which may be default settings or custom or determined based on frequency of use, such as desktop applications, clock applications, etc.

In one possible design, a second memory region of the at least two memory regions is configured to Boot (Boot Up) during a system Boot process and provide memory services for the system. The storage capacity of the storage element in the second storage area meets the memory requirement when the system operates. In addition, for the storage areas except the second storage area in at least two storage areas, namely the first storage area and the third storage area, power is supplied in the system starting process, and an initialization control signal sent by the main equipment is detected on the chip selection bus, so that initialization is completed, namely the state is switched to an idle state after the state is reset, and the idle power-down state is quickly entered to save power consumption or the working state is quickly entered to meet the running requirement of an application program.

In one possible design, to meet memory requirements during operation of a high performance application without reducing power consumption, a first memory region of the at least two memory regions is configured to switch from an active state or an idle state to an idle power down state upon exiting the performance mode, and from the idle power down state to the active state upon entering the performance mode.

Alternatively, different memory regions are set to operate in different modes. Wherein the mode is determined by the system on chip based on the memory requirements of the currently running application.

In some embodiments, the mode includes at least one of a power consumption mode, a performance mode, and a non-performance mode. When the currently running application program does not belong to the high-performance application program, the system-on-chip is determined to be in a non-performance mode; when the currently running application belongs to the high-performance application, the system on a chip is determined to be in a performance mode; the system-on-chip determines to be in a power consumption mode when the application program is not currently required to be run. Wherein the high-performance application may be preconfigured and the system-on-chip may identify whether the application belongs to the high-performance application based on the application identification.

Illustratively, where the at least two memory regions include a first memory region and a second memory region, the first memory region is configured to operate in a performance mode and to remain in an idle power-down state in a non-performance mode. The second storage area is configured to be in an operational state in both the performance mode and the non-performance mode. In the power consumption mode, the first storage area and the second storage area are in an idle power-down state; or the first storage area is in an idle power-down state, and the second storage area is in an idle state; or the first storage area is in an idle state, and the second storage area is in an idle power-down state.

When a performance mode is entered (e.g., when a high performance application is started), the first storage area is started, and all storage elements in the first storage area are switched from an idle power-down state to an operating state. The storage elements in the first storage area that are active provide data access services for the high-performance application (the high-performance application does not occupy the second storage area).

When the performance mode is exited (such as when a high performance application enters the background or is turned off), the storage elements in the first storage area and the second storage area are re-switched from the active state or the idle state to the idle power-down state, thereby reducing power consumption.

Optionally, when the first storage area and the second storage area are switched from the working state or the idle state to the idle power-down state, in order to ensure normal operation when the subsequent high-performance application program is restarted, the first storage area and the second storage area store stored data, for example, in a Static Random-Access Memory (SRAM). The first storage area and the second storage area are set back to an operating state upon subsequent high performance application start-up, i.e. by retraining (Training) and recovering the stored data, e.g. reading from SRAM.

Fig. 8 is a schematic diagram illustrating a method for controlling a memory according to an exemplary embodiment of the present application. The present embodiment will be described taking a first memory element in a control memory as an example. The control method of the memory comprises at least part of the following steps:

step 810: the master device sends a first control signal to the first storage element;

the memory in this embodiment includes n storage elements in total, where the first storage element is a part of the n storage elements, and n is a positive integer greater than 1. Optionally, n is an even number, and the first storage element is n/2 storage elements of the n storage elements; alternatively, the first storage element is n-m storage elements of n storage elements, m being a positive integer not greater than n and not equal to n/2. The second memory element is a part of the n memory elements other than the first memory element.

In some embodiments, the first storage element belongs to a first storage region and the second storage element belongs to a second storage region. Optionally, the first storage area is at least one of the at least two storage areas, and the second storage area is at least one of the at least two storage areas other than the first storage area.

The first storage element is in an idle state or an operating state before the first storage element receives a first control signal, the first control signal being used to control the first storage element to switch to an idle power-down state. In some embodiments, the first control signal is sent by the master device to the memory in the exit performance mode; alternatively, the first control signal is sent to the memory by the master device upon entering the power consumption mode; alternatively, the first control signal is sent by the master device to the memory during the initialization phase.

The second storage element is in an idle state or an active state or an idle power-down state before the first storage element receives the first control signal. Because the control of the first storage element and the second storage element are independent of each other, the master device does not send the first control signal to the second storage element during the process of the master device sending the first control signal to the first storage element; alternatively, the master device may send other control signals or data access instructions to the second storage element, or the master device may also send the first control signal to the second storage element, and in different embodiments, different control scenarios are possible, which is not limited by the present application.

Step 820: detecting a first control signal on a chip select bus of a first memory element;

step 830: the first storage element is switched to an idle power-down state based on control of the first control signal;

the first storage element is switched from an operating state to an idle power-down state based on control of the first control signal, or the first storage element is switched from an idle state to an idle power-down state based on control of the first control signal.

Illustratively, no first control signal is detected on the chip select bus of the second storage element at this time, and no action to switch to the idle power-down state is performed.

Step 840: the master device sends a second control signal to the first storage element;

the second control signal is used for controlling the first storage element to be switched from the idle power-down state to the working state.

The second storage element is in an idle state or an active state or an idle power-down state before the first storage element receives the second control signal. Because the control of the first storage element and the second storage element are independent of each other, the master device does not send the second control signal to the second storage element during the process of the master device sending the second control signal to the first storage element; alternatively, the second storage element also receives a second control signal sent by the master device.

Step 850: detecting a second control signal on the chip select bus of the first memory element;

step 860: the first storage element is switched to an operating state based on control of the second control signal.

The first storage element is switched from the idle power-down state to the operating state based on control of the second control signal.

If the second control signal is not detected on the chip select bus of the second storage element at this time, the second storage element does not perform the action of switching to the idle power-down state.

The power consumption of the working state is larger than that of the idle state, and the power consumption of the idle state is larger than that of the idle power-down state.

Steps 840 to 860 are optional steps. The steps performed by the master device may be implemented separately as one embodiment on the master device side, and the steps performed by the memory may be implemented separately as one embodiment on the memory side.

In summary, in the control method of the memory provided in this embodiment, on the premise of ensuring normal operation of the memory, when the memory enters the performance mode, the storage elements in the first storage area are controlled to enter the working state through the independent chip selection bus, so that the storage elements in other storage areas are not affected, and the operation requirement of the high-performance application program is satisfied; when exiting the performance mode, the storage elements in the first storage area are controlled to enter an idle power-down state through the independent chip selection bus, so that the power consumption of the memory is reduced, and the storage elements in other storage areas are not affected.

Fig. 9 is a schematic diagram showing a control method of a memory according to an exemplary embodiment of the present application. The present embodiment is described by taking the memory including the first memory area and the second memory area as an example. The control method of the memory comprises at least part of the following steps:

an initialization stage:

step 910: the master device sends an initialization control signal to the storage elements in the first storage area and the second storage area;

after the system is started and each storage element is powered on, the main device enables each storage element in the first storage area and the second storage area to be in a reset state by setting the reset port of each storage element low, and executes a reset process (resetting can clear data stored in the storage element). In the reset state, the master device sets the reset ports of the high storage elements to enable all storage elements in the first storage area and the second storage area to be in an idle state.

The initialization control signal is a composite of a set of control signals.

Under the condition of adopting the first initialization mode, the initialization control signals corresponding to the first storage area comprise all control signals which sequentially enter a power-on state, a reset state, an idle state and an idle power-off state; the initialization control signals corresponding to the second storage area comprise control signals which sequentially enter a power-on state, a reset state and an idle state.

In the case of the second initialization method, the initialization control signals corresponding to the first storage area and the second storage area include respective control signals that sequentially enter the power-on state, the reset state, and the idle state.

In this embodiment, the storage elements in the first storage area are initialized to the idle power-down state, and the storage elements in the second storage area are initialized to the idle state.

Entering a non-performance mode:

step 920: the master device sends a second control signal to the storage elements in the second storage area;

when a common application program runs in the system, the main equipment sends a second control signal to the second storage area, and the second control signal is used for controlling the storage elements in the second storage area to be switched to the working state.

The second control signals are detected on chip selection buses of the storage elements in the second storage area, and the storage elements in the second storage area are switched from an idle state to a working state based on the control of the second control signals so as to meet the basic operation requirement of the system and ensure the normal operation of the system.

The storage elements in the first storage area are still in an idle power down state to save power consumption.

Entering a performance mode:

step 930: the master device sends a second control signal to the storage elements in the first storage area;

when a system runs high performance applications, the demand for memory increases.

In one possible design, when the system enters the performance mode from a state in which the common application is running, the master device sends a second control signal to the first storage area, the second control signal being used to control the storage elements in the first storage area to switch to an operating state.

The second control signals are detected on chip select buses of the storage elements in the first storage area, and the storage elements in the first storage area are switched from an idle power-down state to an operating state based on control of the second control signals.

In some embodiments, when the system initialization is completed and the performance mode may be directly entered, the master device sends a second control signal to the first storage area and the second storage area, where the second control signal is used to control the storage element to switch to an operating state, which is not limited.

The second control signals are detected on chip select buses of the storage elements in the second storage area, and the storage elements in the second storage area are switched from an idle state to an operating state based on control of the second control signals.

In the performance mode, the storage elements in the first storage area and the second storage area are in a working state so as to meet the running requirements of high-performance application programs.

Exiting performance mode:

step 940: the master device sends a first control signal to the storage elements in the first storage area;

the system exits the high performance application and memory requirements are reduced. The master device sends a first control signal to the first storage area, the first control signal being used to control the storage element to switch to an idle power-down state.

The first control signals are detected on chip select buses of storage elements in the first storage area, and the storage elements in the first storage area are switched from an operating state to an idle power-down state based on control of the first control signals.

In the non-performance mode, the storage elements in the first storage area are in idle power-down state so as to save power consumption, and the storage elements in the second storage area are still in working state so as to meet the basic operation requirement of the system.

Entering a power consumption mode:

step 950: the master device sends a first control signal to the storage elements in the second storage area.

In one possible design, when the system switches from the non-performance mode to the power consumption mode, the master device sends a first control signal to the second storage area, the first control signal being used to control the storage elements in the second storage area to switch to the idle power-down state.

The first control signals are detected on chip select buses of the storage elements in the second storage area, and the storage elements in the second storage area are switched from an operating state to an idle power-down state based on control of the first control signals.

In one possible design, when the system switches from the performance mode to the power consumption mode, the master device sends a first control signal to the first storage region and the second storage region, the first control signal being used to control the storage element to switch to the idle power down state.

The chip select buses of the storage elements in the first storage area and the second storage area detect first control signals, and the storage elements in the first storage area and the second storage area are switched to an idle power-down state based on control of the first control signals.

In the power consumption mode in this embodiment, the storage elements in the first storage area and the second storage area are in idle power-down states, so as to save power consumption. In some embodiments, but not exclusively, in the power consumption mode, the first storage area is in an idle power down state and the second storage area is in an idle state; or the first storage area is in an idle state, and the second storage area is in an idle power-down state.

In some embodiments, the order in which the various modes described above occur may be other, depending on the particular use scenario.

It should be understood that only some or all of the above steps may be performed in actual situations, and the order of execution of the above steps may be changed adaptively according to specific situations, which is not limited in this embodiment.

In summary, the control method of the memory provided in this embodiment controls the switching state of the storage elements in any storage area through the independent chip select bus without affecting the storage elements in other storage areas on the premise of ensuring the normal operation of the memory.

The application provides an exemplary embodiment of a memory control method. This embodiment is described by taking an example of including 8 memory channels.

In this embodiment, the memory supporting 8 memory channels is divided into a first memory area and a second memory area, wherein the first memory area includes the memory element 201 corresponding to the memory channel A, B, C, D, and the second memory area includes the memory element 201 corresponding to the memory channel E, F, G, H.

In the system start-up phase, the storage element 201 corresponding to the memory channel E, F, G, H in the second storage area is initialized to be in an idle state, the second storage area is used for providing data access services for the default kernel space, the reserved space and the common application program, and the storage element 201 corresponding to the memory channel A, B, C, D in the first storage area is initialized to be in an idle power-down state to prepare for subsequent data reading and writing.

When in the non-performance mode, the storage element 201 corresponding to the memory channel E, F, G, H detects the second control signal sent by the master device on the chip select bus, and switches from the idle state to the working state, and the storage element 201 corresponding to the memory channel A, B, C, D is still in the idle power-down state. In the non-performance mode, as shown in fig. 10, the storage elements 201 corresponding to the memory channels A, B, C, D are all in idle power-down state, so as to save power consumption, and the storage elements 201 corresponding to the memory channels E, F, G, H are all in working state, so as to meet the basic operation requirement of the system.

When the performance mode is entered, the storage element 201 corresponding to the memory channel A, B, C, D detects the second control signal sent by the master device on the chip select bus, and switches from the idle power-down state to the working state. In the performance mode, as shown in fig. 11, the storage elements 201 corresponding to the memory channels A, B, C, D and E, F, G, H are all in a working state, so as to ensure the normal operation of the high-performance application program in the performance mode.

When the high-performance application program exits, the main device sends a first control signal to the memory, and the storage element 201 corresponding to the memory channel A, B, C, D detects the first control signal sent by the main device on the chip select bus, so as to control the memory channel A, B, C, D to be switched to the idle power-down state again. As shown in fig. 12, the memory channel E, F, G, H is in an operating state, ensuring normal operation of the system and the common application program; the memory channel A, B, C, D is in an idle power down state, reducing the power consumption of the memory.

Analyzing from the power consumption angle, compared with the idle state, the power consumption saving amount of the first storage area in the idle power-down state is as follows:

N*(IDDstby*Utilizationstby+IDDsr*Utilizationsr+IDDref+IDDactive-IDDidlePowerDown*UtilizationPowerDown)

where N is the number of storage elements in the first storage area, IDDstby is the Standby memory current, utilizationtby is the Standby (Standby) memory usage, IDDsr is the self-Refresh (self-Refresh) current, utilizationsr is the self-Refresh usage, IDDref is the Refresh (Refresh) current, IDDactive is the active current, IDDidlePowerDown is the idle power down current, and Utilizationpowerdown is the idle power down usage.

In the above embodiments, the memory is schematically described as being divided into two memory areas. In other possible designs, the memory may be divided into three or more memory regions. Correspondingly, the different storage areas are configured to enter the working state from the idle power-down state when entering the corresponding target working modes, and to be restored to the idle power-down state from the working state or the idle state when exiting the target working modes, so that finer-granularity power consumption control is realized, and the target working modes comprise at least one of the performance modes and the non-performance modes. The embodiment of the application does not limit the division number of the storage areas and the specific working modes corresponding to the storage areas.

For example, a memory supporting 8 memory channels is divided into a first memory area, which includes memory elements corresponding to memory channels A, B, C, D, a second memory area, which includes memory elements corresponding to memory channels E, F, and a third memory area, which includes memory elements corresponding to memory channels G, H. The second storage area is configured to be started when the system is started and is used by the kernel space, the reserved space and the first type application programs; the first storage area is configured to enter an idle power-down state from a working state when the second type application program is closed, so that power consumption is saved; the third storage area is configured to enter an idle power-down state from the operating state and be used by the third class of application when the third class of application is closed. Wherein the performance of the second type of application is less than the performance of the first type of application is less than the performance of the third type of application.

In the embodiment, the memory is divided into the memory areas, and when the memory enters the target working mode, the specific memory areas are controlled to enter the working state through the chip selection bus, so that the normal operation of the application program in the target working mode is ensured; when the target working mode is exited, the specific storage area is controlled to be switched to the idle power-down state through the chip selection bus, so that the power consumption of the memory is reduced, and the influence on application programs running in other storage areas is avoided.

In one illustrative example, a memory 200 supporting 8 memory channels is provided with 8 chip select buses for controlling the corresponding storage element switching states.

Because the different storage elements are controlled by the corresponding chip selection buses, the different storage elements enter the idle power-down state and have no influence on other storage elements. Under the target application scene, the system on chip can control most of memory channels of the target to enter an idle power-down state through the chip selection bus, and only a small part of memory channels are kept in a working state, so that the power consumption is reduced.

In one possible application scenario, the number of storage areas is dynamically configured or changed in different time periods or in different scenarios. As shown in fig. 13, when data transmission is required in the background, or when music playing is performed in the background, the system on chip may control 7 memory channels to enter an idle power-down state through 7 chip select buses corresponding to the memory channel A, B, C, D, E, F, G, and only the memory channel H is kept in a working state.

In this embodiment, the chip select bus is used to control most memory channels to enter an idle power-down state, and only a small part of memory channels are kept in a working state, so that power consumption is reduced and higher fine granularity control of the multi-memory channel memory is realized on the premise of meeting storage requirements.

Fig. 14 illustrates a method of controlling a memory according to an exemplary embodiment of the present application. The memory 200 of the present embodiment includes 8 memory elements as an example for explanation:

the memory 200 in this embodiment supports 8 memory channels, and the 8 memory channels respectively correspond to 8 storage elements. The 8 storage elements are initially divided into two storage areas, each of which contains 4 storage elements. The second storage area contains storage elements E, F, G, H, which are started during the system startup process and initialized to an idle state; the first storage area includes storage elements A, B, C, D therein which are powered up at system start-up and initialized to an idle power-down state.

When the system runs the common APP, the storage element E, F, G, H in the second storage area is switched from the idle state to the working state so as to meet the running requirement of the system; the storage elements A, B, C, D in the first storage area remain in the idle powered-down state to save power consumption.

When the system runs a music application, the 8 storage elements are divided into three storage areas. The second storage area contains a storage element E, F, G, H which is still in a working state and is used for default kernel space, reserved space and common APP; the first storage area contains storage elements A, B, C, which are still in an idle power-down state; the third storage area contains a storage element D, and is switched from an idle power-down state to an operating state for the music application.

When the system runs the high-performance game application, in addition to the storage element E, F, G, H in the second storage area and the storage element D in the third storage area being in the operating state, the storage element A, B, C in the first storage area is also switched from the idle power-down state to the operating state to satisfy the running requirement of the high-performance game application.

When a high performance game application is run in the background, the 8 storage elements are divided into four storage areas. The second storage area contains a storage element E, F, G, H which is still in a working state and is used for default kernel space, reserved space and common APP; the first storage area contains a storage element A, B which is still in a working state and is used for running a high-performance game application program in the background; the third storage area contains a storage element D which is still in a working state and is used for a music application program; the fourth storage area contains a storage element C, and is switched from an operating state to an idle state, so that power consumption is saved.

When exiting the music application and the high performance game application, the 8 storage elements are divided into two storage areas. The second storage area contains a storage element E, F, G, H which is still in a working state and is used for default kernel space, reserved space and common APP; the memory element A, B, C, D in the first memory area is switched from an active state or an idle state to an idle power-down state to save power consumption.

When the terminal power is lower than 10%, 8 memory elements are divided into two memory areas. The second storage area contains a storage element G, H which is still in a working state and is used for default kernel space, reserved space and common APP; the storage elements A, B, C, D, E, F in the first storage area are all in an idle power-down state to save power consumption.

In summary, according to the control method of the memory provided by the embodiment, the storage areas of the memory are flexibly divided under different scenes, and the memory elements in the storage areas are individually controlled to switch states through the chip selection buses, so that the storage requirements under different scenes are met, the effect of saving power consumption is achieved under the condition that the normal operation of the system is ensured, and the control of the memory channels with higher granularity is realized.

Fig. 15 illustrates a terminal provided by an exemplary embodiment of the present application. The terminal 1400 in this embodiment is described by taking the example that it includes a main device and a memory:

terminal 1400 is provided with a host device 101 and a memory 200 as described in the above embodiments, where host device 101 and memory 200 are electrically connected. The memory 200 may be provided inside the system on chip or outside the system on chip. It should be noted that, in addition to the system on a chip, the terminal 1400 may further include other necessary components, such as a Read-Only Memory (ROM), a display component, an input unit, an audio circuit, a speaker, a microphone, a power supply, etc., which are not described herein.

The foregoing description of the preferred embodiments of the present application is not intended to limit the application, but rather, the application is to be construed as limited to the appended claims.

Claims

1. A method of controlling a memory, the method performed by a memory, the memory comprising n storage elements, each storage element having a separate chip select bus, the method comprising:

2. The method of claim 1, wherein the n storage elements are divided into at least two storage areas;

the controlling the first storage element in the idle power-down state under the condition that the first control signal is detected on the chip select bus of the first storage element comprises:

controlling a first storage element belonging to a first storage area to be in an idle power-down state under the condition that the first control signal is detected on a chip select bus of the first storage element;

wherein the first storage area is at least one of the at least two storage areas.

3. The method of claim 2, wherein the step of determining the position of the substrate comprises,

the first control signal is sent to the memory by the master device in the exit performance mode;

or, the first control signal is sent to the memory by the master device when entering a power consumption mode;

Or, the first control signal is sent to the memory by the master device in an initialization phase.

4. A method according to any one of claims 1 to 3, wherein the method further comprises:

controlling the first storage element to switch from the idle power-down state to an operating state under the condition that a second control signal is detected on a chip select bus of the first storage element belonging to the first storage area;

wherein the second control signal is sent by the master device to the memory upon entering the performance mode.

5. A method according to any one of claims 1 to 3, wherein the method further comprises:

initializing the storage elements belonging to the second storage area to an idle state during a system start-up phase;

wherein the second storage area is at least one of the at least two storage areas.

6. A method according to any one of claims 1 to 3, wherein,

the n storage elements are an even number of storage elements, and the first storage element is n/2 of the n storage elements;

or, the first storage element is n-m storage elements of the n storage elements, m is a positive integer not greater than n and not equal to n/2.

7. A method according to any one of claims 1 to 3, wherein,

the memory is used for the mobile terminal; or alternatively, the first and second heat exchangers may be,

the memory is a dynamic random access memory device employing a stack package.

8. A method of controlling a memory, the method performed by a master device for controlling a memory, the memory comprising n storage elements, each storage element having a separate chip select bus, the method comprising:

9. The method of claim 8, wherein the n storage elements are divided into at least two storage areas;

the outputting the first control signal to the chip select bus of the first memory element includes:

outputting the first control signal to a chip select bus of a first memory element belonging to a first memory region;

10. The method of claim 9, wherein outputting the first control signal onto the chip select bus of the first memory element belonging to the first memory region comprises:

outputting the first control signal onto a chip select bus of a first memory element belonging to the first memory region in the event of exiting a performance mode; or alternatively, the first and second heat exchangers may be,

outputting the first control signal onto a chip select bus of a first memory element belonging to the first memory region in the case of entering a power consumption mode; or alternatively, the first and second heat exchangers may be,

in an initialization phase, the first control signal is output onto a chip select bus of a first memory element belonging to the first memory region.

11. The method according to any one of claims 8 to 10, further comprising:

outputting a second control signal onto a chip select bus of a first memory element belonging to the first memory region upon entering the performance mode;

12. The method according to any one of claims 8 to 10, further comprising:

Outputting an initialization control signal to a storage element belonging to the second storage area at a system start-up stage;

wherein the initialization control signal is used for controlling the storage elements belonging to the second storage area to be initialized to an idle state, and the second storage area is at least one storage area in the at least two storage areas.

13. The method according to any one of claims 8 to 10, wherein,

14. The method according to any one of claims 8 to 10, wherein,

the memory is a dynamic random access memory device employing a stack package.

15. A memory for implementing the control method of the memory according to any one of claims 1 to 7.

16. The memory of claim 15, wherein the memory is configured to store, in the memory,

The memory is a dynamic random access memory device employing a stack package.

17. A system-on-chip, the system-on-chip comprising: a master device, a memory controller, and a memory;

the main equipment is connected with the storage controller through a main bus;

the memory is used for realizing the control method of the memory according to any one of claims 1 to 7, and the master device is used for realizing the control method of the memory according to any one of claims 8 to 14.

18. A terminal for implementing a method of controlling a memory according to any one of claims 1 to 14.

19. The terminal of claim 18, wherein a system on a chip is provided on the terminal, and wherein the memory is provided outside the system on a chip or wherein the memory is provided inside the system on a chip.