CN117176152A - Analog-to-digital converter based on voltage-controlled oscillator - Google Patents

Abstract

The application relates to the field of circuits, and discloses an analog-to-digital converter based on a voltage-controlled oscillator, which comprises: an oscillator module and a digital quantizer; the oscillator module generates two groups of phases according to the differential current; the digital quantizer comprises two phase decoding units, two period counting units and a digital decoding unit, wherein one phase decoding unit is connected with one period counting unit, and the digital decoding unit is connected with each period counting unit and each phase decoding unit; each phase decoding unit is used for determining the decimal of the period of the oscillator according to the current received phase; each period counting unit is used for determining the period number of the oscillator according to the decimal and the received multiple preset phases; and the digital decoding unit is used for determining digital output according to the decimal numbers and the oscillator cycle numbers. The application can reduce the number of digital samplers and simplify the arbiter, and simultaneously avoid quantization errors without affecting the performance of the analog-to-digital converter.

Description

Analog-to-digital converter based on voltage-controlled oscillator

Technical Field

The present application relates to the field of circuits, and in particular, to an analog-to-digital converter based on a voltage-controlled oscillator.

Background

Timing misalignment from clock jitter and/or different path delays can have a critical impact on the performance of the digital quantizer. If the Sampling Clock (SC) switches at a time near the edge of the period, a Cycle Counter (CC) error of ±1 period (quantization error) may occur. One prior art technique is to avoid this error by a triple sampling strategy, as shown in fig. 1, requiring 3 sets of sampling registers for one cycle counter. Assuming that one 16-bit digital cycle counter (Digital Cycle Counter, DCC) is used, the triple sampling strategy requires three sets of 16-bit sampling registers, thus requiring at least 48 digital samplers, which makes the existing triple sampling strategy redundant hardware.

In view of the foregoing, it is desirable to provide an analog-to-digital converter that reduces the overhead of the digital sampler.

Disclosure of Invention

In order to solve the above problems, the present application provides an analog-to-digital converter based on a voltage-controlled oscillator, comprising: an oscillator module and a digital quantizer; the oscillator module is connected with the digital quantizer module;

the oscillator module generates two groups of phases according to the differential current;

the digital quantizer comprises two phase decoding units, two period counting units and a digital decoding unit, wherein one phase decoding unit is connected with one period counting unit, and the digital decoding unit is connected with each period counting unit and each phase decoding unit;

each phase decoding unit is used for determining the decimal of the period of the oscillator according to the current received phase;

each period counting unit is used for determining the period number of the oscillator according to the decimal and the received multiple preset phases;

the digital decoding unit is used for determining digital output according to the decimal numbers and the oscillator cycle numbers.

Preferably, the oscillator module includes: the first ring oscillator is respectively connected with one phase decoding unit and one period counting unit, and the second ring oscillator is respectively connected with the other phase decoding unit and the other period counting unit.

Preferably, each of the cycle counting units includes: the system comprises a first period counter, a second period counter, a plurality of digital samplers and an arbiter, wherein the first period counter and the second period counter are connected with the arbiter, and the arbiter is respectively connected with a phase decoding unit and each digital sampler;

the first period counter is used for determining a first period result according to a first preset phase in the phases;

the second period counter is used for receiving the inverted signals of a second preset phase in the phases to determine a second period result;

the arbiter is configured to determine to reserve the first cycle result or the second cycle result according to the decimal, reserve the second cycle result if the decimal belongs to a first preset interval, and reserve the first cycle result if the decimal belongs to a second preset interval;

a plurality of the digital samplers are for sampling the first or second cycle result for which synchronization is preserved as the cycle number.

Preferably, the digital decoding unit includes: the subtracting subunit is respectively connected with the two phase decoding units and the two period counting units;

the subtracting subunit is configured to calculate a fractional difference value according to the fractional value currently determined by the same phase decoding unit and the fractional value determined by the last sampling, obtain two fractional difference values of the two phase decoding units, calculate a cycle number difference value according to the cycle number currently determined by the same cycle counting unit and the cycle number determined by the last sampling, obtain two cycle number difference values of the two cycle counting units, determine a digital cycle number according to the two cycle number difference values, and determine a digital phase number according to the two fractional difference values.

Preferably, the digital decoding unit further includes: a digital decoder connected to the subtracting subunit;

the digital decoder is used for determining a digital signal according to the digital cycle number and the digital phase number.

Preferably, the digital decoding unit further includes: a first chopper switch connected to the digital decoder;

the first chopping switch is used for carrying out chopping processing on the digital signal to obtain the digital output.

Preferably, the method further comprises: a transconductance amplifying module;

the transconductance amplification module includes: a first transconductance transistor and a second transconductance transistor;

the source electrode of the first transconductance transistor and the source electrode of the second transconductance transistor are sequentially connected in series with a current source and an input voltage end, and the drain electrode of the first transconductance transistor and the drain electrode of the second transconductance transistor are connected with the oscillator module.

Preferably, the method further comprises: a second chopper switch;

and the output end of the second chopper switch is respectively connected with the grid electrode of the first transconductance transistor and the grid electrode of the second transconductance transistor.

Preferably, the method further comprises: a high-pass filtering module;

the output end of the high-pass filtering module is connected with the input end of the second chopping switch, and the input end of the high-pass filtering module inputs differential voltage.

Preferably, the first ring oscillator and the second ring oscillator each generate a predetermined number of phases from the 0 th phase in one period.

The application has the advantages that: the period counting unit determines the number of periods of the oscillator according to the received decimal numbers determined by the plurality of preset phases and the phase decoding unit, so that the number of digital samplers can be reduced, quantization errors can be avoided, and the performance of the analog-to-digital converter is not affected.

Drawings

Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for the purpose of illustrating the preferred embodiments and are not to be construed as limiting the application. Also, like reference numerals are used to designate like parts throughout the figures. In the drawings:

FIG. 1 is a prior art cycle counter using a triple sampling strategy;

FIG. 2 is a schematic diagram of an analog front end based on a voltage controlled oscillator according to the present application;

fig. 3 is a schematic diagram of a digital quantizer of a voltage-controlled oscillator-based analog-to-digital converter according to the present application;

fig. 4 is a schematic diagram of a period counting unit and a digital decoding unit of an analog-to-digital converter based on a voltage-controlled oscillator according to the present application;

fig. 5 is a schematic diagram of a voltage-controlled oscillator-based analog-to-digital converter according to the present application;

FIG. 6 is a schematic diagram of differential voltage sampling for a voltage-controlled oscillator-based analog-to-digital converter according to the present application;

fig. 7 is a schematic diagram of a period counting unit sampling of an analog-to-digital converter based on a voltage-controlled oscillator according to the present application.

Detailed Description

Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

According to an embodiment of the present application, an analog-to-digital converter based on a voltage-controlled oscillator is provided, as shown in fig. 2, including: an oscillator module 101 and a digital quantizer 102; the oscillator module 101 is connected with the digital quantizer module 102;

the oscillator module 101 generates two groups of phases according to the differential current, wherein each group of phases comprises a plurality of phases; preferably, the number of phases of each group is the same;

the digital quantizer 102 includes two phase decoding units 201 (201N and 201P), two period counting units 202 (202N and 202P), and one digital decoding unit 203, wherein one phase decoding unit 201 is connected to one period counting unit 202, and the digital decoding unit 203 is connected to each cycle counting unit 202 and each phase decoding unit 201;

each phase decoding unit 201 is configured to determine a fraction of the period of the oscillator according to the current received phase;

each cycle counting unit 202 is configured to determine the number of oscillator cycles according to the decimal number and the received plurality of preset phases;

the digital decoding unit 203 is configured to determine a digital output according to the plurality of decimal places and the plurality of oscillator periods.

As shown in fig. 3, the oscillator module 101 includes: a first ring oscillator 111 and a second ring oscillator 112, wherein the first ring oscillator 111 is connected to one phase decoding unit 201N and one cycle counting unit 202N, respectively, and the second ring oscillator 112 is connected to the other phase decoding unit 201P and the other cycle counting unit 202P, respectively. The ring oscillator is one of voltage controlled oscillators (Voltage Controlled Oscillator, VCO).

As shown in fig. 4, each cycle counting unit 202 (202N and 202P) includes: a first period counter 221, a second period counter 222, a plurality of digital samplers 223 and an Arbiter (Arbiter) 224, wherein the first period counter 221 and the second period counter 222 are connected to the Arbiter 224, and the Arbiter 224 is connected to the phase decoding unit 201 (201N or 201P) and each digital sampler 223, respectively; a first period counter 221 (221N or 221P) for determining a first period result according to a first preset phase of the plurality of phases; a second period counter 222 (222N or 222P) for receiving an inverted signal of a second preset phase of the plurality of phases to determine a second period result; an arbiter 224 (224N or 224P) for determining to reserve the first cycle result or the second cycle result according to the decimal, if the decimal belongs to the first preset interval, the second cycle result is reserved, and if the decimal belongs to the second preset interval, the first cycle result is reserved; the plurality of digital samplers 223 (223N or 223P) are used to sample the first or second periodic result for which synchronization is preserved as a number of periods. The number of the digital samplers 223 is the same as the number of bits of the first period counter 221 or the second period counter 222, preferably, the first preset phase is the 14 th phase, the second preset phase is the 15 th phase, the first preset interval is 0 to 15, and the second preset interval is 15 to 28.

In general, a Flip-Flop (FF) can be used to implement a digital sampling function, and thus can be used as a basic unit of a digital sampler. It should be understood that the trigger does not limit the present embodiment, so long as the element and the device that can implement the digital sampling function can be used as the basic unit of the digital sampler. The digital sampler aligns the signal edges of the sampled result of the first cycle counter or the second cycle counter, so that the subtracting subunit can accurately complete subtracting processing.

As shown in fig. 4, the digital decoding unit 203 includes: subtracting subunit 301, subtracting subunit 301 is connected to two phase decoding units 201 and two period counting units 202, respectively; the subtracting subunit 301 is configured to calculate a fractional difference value according to the fractional value currently determined by the same phase decoding unit (201N or 201P) and the fractional value determined by the last sampling, obtain two fractional difference values of the two phase decoding units (201N and 201P), calculate a cycle number difference value according to the cycle number currently determined by the same cycle counting unit (202N or 202P) and the cycle number determined by the last sampling, obtain two cycle number difference values of the two cycle counting units (202 and 202B), determine a digital cycle number according to the two cycle number difference values, and determine a digital phase number according to the two fractional difference values. The subtraction subunit 301 may include 1 or more subtractors therein. The number of cycles is taken as an integer and the number of phases is taken as a decimal.

As shown in fig. 4, the digital decoding unit 203 further includes: a digital decoder 302, the digital decoder 302 being connected 301 to the subtracting subunit; the digital decoder 302 is configured to determine a digital signal according to the number of digital cycles and the number of digital phases.

As shown in fig. 4, the digital decoding unit 203 according to the embodiment of the present application further includes: a first Chopper Switch (Chopper Switch) 303, the first Chopper Switch 303 being connected to the digital decoder 302; the first chopper switch 303 is used for performing chopper processing on the digital signal to obtain a digital output.

As shown in fig. 5, the embodiment of the present application further includes: a transconductance amplification module 103; the transconductance amplification module 103 includes: first transconductance transistor M _N And a second transconductance transistor M _P The method comprises the steps of carrying out a first treatment on the surface of the First transconductance transistor M _N Source of (c) and second transconductance transistor M _P Source of (C) and current source I and input voltage terminal V _DD Sequentially connected in series with a first transconductance transistor M _N And a second transconductance transistor M _P Is connected to the oscillator module 101. The transconductance amplification block 103 is an amplifier for converting an input differential voltage into an output differential current.

As shown in fig. 5, the embodiment of the present application further includes: a second chopper switch 104; the output terminal of the second chopper switch 104 is connected to the gate of the first transconductance transistor MN and the gate of the second transconductance transistor MP, respectively. The chopping frequency of the first chopping switch 303 and the second chopping switch 304 is the same f _chop 。

As shown in fig. 5, the embodiment of the present application further includes: a high-pass filtering module 105; the output terminal of the high-pass filter module 105 is connected to the input terminal of the second chopper switch 104, and the input terminal of the high-pass filter module 105 inputs the differential voltage.

The high-pass filtering module 105 includes: a first high-pass filtering unit 501 and a second high-pass filtering unit 502. Each high pass filter unit comprises a capacitor and a resistor. One end of the capacitor is connected with the second chopper switch 104 and one end of the resistor, and the other end of the resistor inputs bias voltage V _bias The other end of the capacitor inputs differential voltage.

The first ring oscillator 111 and the second ring oscillator 112 each generate a predetermined number of phases from the 0 th phase in one period. The predetermined number of phases is determined according to a predetermined number of stages of the first ring oscillator 111 or the second ring oscillator 112. Preferably, the preset number of stages is 29, the preset number of phases is 2 times of the preset number of stages, namely 58, and the phases output by the first ring oscillator 111 and the second ring oscillator 112 start from the 0 th phase to the 57 th phase.

Each phase decoding unit 201 comprises a phase decoder 211 and a plurality of digital samplers 212, the phase decoder being connected to each digital sampler. The phase decoder is used for determining a currently received phase sequence number, and the plurality of digital samplers are used for sampling the synchronous phase sequence number as the decimal of the period of the oscillator. The number of digital samplers is generally determined based on a preset number of phases. I.e. if the preset number of phases is 58, half of which is 29, the number of digital samplers of the decoding unit is 5 since the 5 th power of 2 is 32 > 29.

The same enable signal EN is used to control the turning on and off of all the phase decoders, the first period counter and the second period counter in the digital quantizer 102, and the same sampling clock is used to control all the digital samplers in all the phase decoding units 201 and all the digital samplers in the period counting units 202 in the digital quantizer 102.

Next, an embodiment of the present application will be further described with reference to fig. 6 and 7.

As shown in fig. 6, a first differential voltage V _in And a second differential voltage V _ip And the signals are sequentially transmitted through a high-pass filter module 105 and a second chopper switch 104 and then are input to a transconductance amplifying module 103. First differential voltage V _in Through a first transconductance transistor M _N And then converted into a first differential current I _n Second differential voltage V _ip Through a second transconductance transistor M _P And then converted into a second differential current I _p . First differential current I _n Is input into the first ring oscillator 111, the second differential current I _p Is input into the second ring oscillator 112. The dynamic range of voltage controlled oscillator based Analog-to-Digital Converter (ADC) is independent of the supply voltage, its digital output allows more processing in the digital domain, which is suitable for process scaling. The first ring oscillator 111 and the second ring oscillator 112 are both a first differential current I according to a preset number of phases _n And a second differential current I _p A corresponding number of phases are generated and sent to the digital quantizer 102. Taking a preset number of 58 as an example, wherein the first ring oscillator 111 generates the 0 th phase to the 57 th phase (phi _n,0-57 ) Each of which is input to the phase decoder unit 201N, and the 14 th phase and the 15 th phase are input to the cycle counter unit 202N; phase 0 to phase 57 (phi) generated by the second ring oscillator 112 _p,0-57 ) Are input to the phase decoder unit 201P, and the 14 th phase and the 15 th phase are input to the cycle counter unit 202P. The calculation method for converting the differential voltage into the differential current by the transconductance transistor is shown in the formula (1):

wherein g _mn For the first transconductance transistor M _n G is the transconductance of (g) _mp Is a second transconductance transistor M _P Is a transconductance of the first pair. The relationship between the differential current and the period of the ring oscillator is shown in equation (2):

wherein, oc is a proportional symbol, T _ROp T is the period of the second ring oscillator 112 _ROn For the period of the first ring oscillator 111, N is a preset number of stages, which is the total number of stages of the first ring oscillator 111 or the second ring oscillator 112, N is set to 29 as a tradeoff between phase decoder complexity and phase noise, and a single ring oscillator generates 58 phases in one period.

As shown in fig. 7, to be input intoThe 14 th phase and the 15 th phase of the cycle counter unit 202N are exemplified. The cycle counting unit 202N and the phase decoding unit 201N sample the input phase at each rising edge of the sampling clock according to the same sampling clock. The phase decoder 211N and the plurality of digital samplers 212N in the phase decoding unit 201N determine the fraction D of the period of the oscillator of the first ring oscillator 111 based on the current sampling to phase _PD1,n Fractional number D of oscillator period _PD1,n To the arbiter 224N of the subtracting subunit 301 and the cycle counting unit 202N, respectively. Of the 58 phases generated by the first ring oscillator 111, the 14 th phase and the 15 th phase spaced by half a period are used to trigger two sets of period counters (the first period counter 221N and the second period counter 222N). The first period counter 221N receives the 14 th phase output from the first ring oscillator 111, and the second period counter 222N receives the 15 th phase inversion signal output from the first ring oscillator 111. The first period counter 221N is based on the 14 th phase (φ _n,14 ) Determining a first period result; the second period counter 222N is based on the 15 th phase inversion signalA second cycle result is determined. Arbiter 224N is based on decimal D _PD1,n And judging whether the first period result or the second period result is reserved. As shown in fig. 7, in the interval of about 0 to 14 in phase, there is no transition in the signal sampled by the second period counter 222N, and in the interval of about 15 to 28 in phase, there is no transition in the signal sampled by the first period counter 221N. Thus, if the decimal D _PD1,n Belonging to a first preset interval, namely decimal D _PD1,n A value of any one of 0 to 14, a second periodic result is retained, if the fraction belongs to a second preset interval, namely fraction D _PD1,n At any one of values 15 to 28, the first cycle result is retained. The arbiter 224N sends the reserved first cycle result or the second cycle result reserved to a plurality of the digital samplers 223N. The plurality of digital samplers 223N store the retained first or second period result as the number D of periods of the first differential voltage _CC1,n . The plurality of digital samplers 223N will beCycle number D of differential voltage _CC1,n To the subtracting subunit 301.

For period number D of the output of the period counter unit 202N _CC1,n And the fraction D output from the phase decoding unit 201N _PD1,n Subtracting subunit 301 first calculates the current number of cycles D _CC1,n With the cycle number D obtained by last sampling _CC0,n To obtain the cycle number difference D of the first differential voltage _CC,n And the current fraction D _PD1,n With the fraction D obtained from the last sampling _PD0,n To obtain the decimal difference D of the first differential voltage _PD,n 。

For the phase of the second differential current input to the cycle counting unit 202P and the phase decoding unit 201P, the processing flow and the cycle number difference D _CC,p Sum-fractional difference D _PD,p The calculation method of (2) is the same as that described above, and will not be described in detail here.

At the moment of obtaining the decimal difference D of the first differential voltage _PD,n Sum cycle number difference D _CC,n Decimal difference D of second differential voltage _PD,p Sum cycle number difference D _CC,p Then, the difference between the first differential voltage and the second differential voltage is calculated according to the formula (3), i.e. the number of digital cycles D is calculated _CC Number of digits D _PD ：

The subtraction subunit 301 will obtain the number of digital cycles D _CC Number of digits D _PD To decoder 302. The digital decoder 302 calculates the digital signal D according to equation (4) _p/n ：

D _p/n ＝N·D _cc +D _PD (4)

Wherein N is a preset level number, and the digital signal D _p/n Is a binary result. After the chopping process by the first chopping switch 303, the digital signal D _p/n Converted into digital output D _out 。

Embodiments of the application can also be applied to only oneIn the case of non-differential case of input voltage or input current, only one ring oscillator in the oscillator module 101, only one period counting unit, and only one phase decoding unit are used for the use of ring oscillators, period counting units, and phase decoding units. In the calculation, for equation (3), the value of the line that is not used is brought to 0. That is, assuming that only the second ring oscillator 112, the period counting unit 202P and the phase decoding unit 201P are used, D in the formula (3) can be obtained _cc,n And D _PD,n All brought into 0.

In the system of the application, the period counting unit determines the number of the periods of the oscillator according to the received decimal determined by the plurality of preset phases and the phase decoding units, so that the number of digital samplers can be reduced, quantization errors can be avoided, and the performance of the analog-to-digital converter is not affected. In addition, the existing triple sampling strategy also needs to use complex arbitration logic to realize comprehensive judgment of the counting results of the period and the phase of three samples, and the arbitration logic of the arbiter is simple, so that the complex arbiter is simplified. Compared with the traditional triple sampling strategy, the total number of the digital samplers is reduced by 25 percent for the 16-bit period counter, the digital sampler overhead caused by sampling is reduced to the greatest extent, and a complex arbiter is simplified.

The present application is not limited to the above-mentioned embodiments, and any changes or substitutions that can be easily understood by those skilled in the art within the technical scope of the present application are intended to be included in the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims (10)

1. An analog-to-digital converter based on a voltage controlled oscillator, comprising: an oscillator module and a digital quantizer; the oscillator module is connected with the digital quantizer module;

the oscillator module generates two groups of phases according to the differential current;

the digital quantizer comprises two phase decoding units, two period counting units and a digital decoding unit, wherein one phase decoding unit is connected with one period counting unit, and the digital decoding unit is connected with each period counting unit and each phase decoding unit;

each phase decoding unit is used for determining the decimal of the period of the oscillator according to the current received phase;

each period counting unit is used for determining the period number of the oscillator according to the decimal and the received multiple preset phases;

the digital decoding unit is used for determining digital output according to the decimal numbers and the oscillator cycle numbers.

2. The analog-to-digital converter of claim 1, wherein the oscillator module comprises: the first ring oscillator is respectively connected with one phase decoding unit and one period counting unit, and the second ring oscillator is respectively connected with the other phase decoding unit and the other period counting unit.

3. The analog-to-digital converter of claim 1, wherein each of said period counting units comprises: the system comprises a first period counter, a second period counter, a plurality of digital samplers and an arbiter, wherein the first period counter and the second period counter are connected with the arbiter, and the arbiter is respectively connected with a phase decoding unit and each digital sampler;

the first period counter is used for determining a first period result according to a first preset phase in the phases;

the second period counter is used for receiving the inverted signals of a second preset phase in the phases to determine a second period result;

the arbiter is configured to determine to reserve the first cycle result or the second cycle result according to the decimal, reserve the second cycle result if the decimal belongs to a first preset interval, and reserve the first cycle result if the decimal belongs to a second preset interval;

a plurality of the digital samplers are for sampling the first or second cycle result for which synchronization is preserved as the cycle number.

4. The analog-to-digital converter of claim 1, wherein the digital decoding unit comprises: the subtracting subunit is respectively connected with the two phase decoding units and the two period counting units;

the subtracting subunit is configured to calculate a fractional difference value according to the fractional value currently determined by the same phase decoding unit and the fractional value determined by the last sampling, obtain two fractional difference values of the two phase decoding units, calculate a cycle number difference value according to the cycle number currently determined by the same cycle counting unit and the cycle number determined by the last sampling, obtain two cycle number difference values of the two cycle counting units, determine a digital cycle number according to the two cycle number difference values, and determine a digital phase number according to the two fractional difference values.

5. The analog-to-digital converter of claim 4, wherein said digital decoding unit further comprises: a digital decoder connected to the subtracting subunit;

the digital decoder is used for determining a digital signal according to the digital cycle number and the digital phase number.

6. The analog-to-digital converter of claim 5, wherein said digital decoding unit further comprises: a first chopper switch connected to the digital decoder;

the first chopping switch is used for carrying out chopping processing on the digital signal to obtain the digital output.

7. The analog-to-digital converter of claim 1, further comprising: a transconductance amplifying module;

the transconductance amplification module includes: a first transconductance transistor and a second transconductance transistor;

the source electrode of the first transconductance transistor and the source electrode of the second transconductance transistor are sequentially connected in series with the current source I and the input voltage end, and the drain electrode of the first transconductance transistor and the drain electrode of the second transconductance transistor are connected with the oscillator module.

8. The analog-to-digital converter of claim 7, further comprising: a second chopper switch;

and the output end of the second chopper switch is respectively connected with the grid electrode of the first transconductance transistor and the grid electrode of the second transconductance transistor.

9. The analog-to-digital converter of claim 8, further comprising: a high-pass filtering module;

the output end of the high-pass filtering module is connected with the input end of the second chopping switch, and the input end of the high-pass filtering module inputs differential voltage.

10. The analog-to-digital converter of claim 2, wherein the first ring oscillator and the second ring oscillator each generate a predetermined number of phases starting from phase 0 in one period.