CN110069008B - Time-to-digital converter system and multiple delay phase-locked loop comprising same - Google Patents
Time-to-digital converter system and multiple delay phase-locked loop comprising same Download PDFInfo
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- CN110069008B CN110069008B CN201910355579.6A CN201910355579A CN110069008B CN 110069008 B CN110069008 B CN 110069008B CN 201910355579 A CN201910355579 A CN 201910355579A CN 110069008 B CN110069008 B CN 110069008B
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- G—PHYSICS
- G04—HOROLOGY
- G04F—TIME-INTERVAL MEASURING
- G04F10/00—Apparatus for measuring unknown time intervals by electric means
- G04F10/005—Time-to-digital converters [TDC]
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M3/00—Conversion of analogue values to or from differential modulation
- H03M3/30—Delta-sigma modulation
- H03M3/322—Continuously compensating for, or preventing, undesired influence of physical parameters
- H03M3/324—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by means or methods for compensating or preventing more than one type of error at a time, e.g. by synchronisation or using a ratiometric arrangement
- H03M3/344—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by means or methods for compensating or preventing more than one type of error at a time, e.g. by synchronisation or using a ratiometric arrangement by filtering other than the noise-shaping inherent to delta-sigma modulators, e.g. anti-aliasing
Abstract
The invention discloses a time-to-digital converter system and a multiple delay phase-locked loop comprising the same, wherein the system comprises: the time-to-digital converter comprises a first-stage time-to-digital converter, a first-stage digital-to-time converter, a first-stage time amplifier, a second-stage time-to-digital converter, a second-stage digital-to-time converter, a second-stage time amplifier, a third-stage successive approximation register type analog-to-digital converter and a digital-to-analog converter. The time-to-digital converter system and the multiple delay phase-locked loop with the function of reducing the in-band quantization noise effectively improve the precision of the time-to-digital converter applied to the multiple delay phase-locked loop by using the cascade algorithm similar to Delta-Sigma, thereby reducing the size of the quantization noise and improving the generation of the stray of the multiple delay phase-locked loop.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a time-to-digital converter system and a multiple delay phase-locked loop comprising the same.
Background
With the advance of technology, in the application of fully digital chips, the use of on-chip frequency doubling clocks has occupied a significant position in order to convert the off-chip oscillator input signal with lower frequency into the clock signal with higher frequency. In order to obtain a stable high frequency clock signal without being affected by phase noise, the multiple delay phase-locked loop must have the function of suppressing phase noise. Furthermore, the rise of the handheld device, low power consumption has become an indispensable condition for extending the battery life on the handheld device.
In the multiple delay phase locked loop, the vco is a loop, so the jitter generated by the vco accumulates along with the loop, and the multiple delay phase locked loop operates by re-inputting a new clock signal into the oscillator at intervals to reduce the jitter (jitter) of the oscillator, but generates spurs (spurs) accordingly. In addition, the multiple delay phase-locked loop is divided into digital and analog, and the analog multiple delay phase-locked loop and the phase-locked loop are similar in structure, but the nonlinearity caused by both the charge pump and the phase detector can affect the jitter of the output of the multiple delay phase-locked loop. Therefore, the digital multiple delay phase-locked loop uses the time-to-digital converter to replace the charge pump and the phase detector to improve the disadvantages of the analog multiple delay phase-locked loop.
Although a digital multiple delay locked loop may improve the disadvantages of an analog multiple delay locked loop. However, the use of a multiple-of-digital delay-locked loop suffers from the disadvantage that its in-band quantization noise is determined by the time-to-digital converter.
Disclosure of Invention
The invention aims to provide a time-to-digital converter system and a multiple delay phase-locked loop comprising the same, so as to reduce in-band quantization noise.
To achieve the above object, the present invention provides a time-to-digital converter system applied to a multiple delay phase-locked loop, the system comprising: a first stage time-to-digital converter, a first stage digital-to-time converter, a first stage time amplifier, a second stage time-to-digital converter, a second stage digital-to-time converter, a second stage time amplifier, a third stage successive approximation register type analog-to-digital converter and a digital-to-analog converter;
simultaneously inputting the reference clock signal and the output signal of the multiple delay phase-locked loop into a first-stage time-to-digital converter so as to convert the time difference between the reference clock signal and the output signal of the multiple delay phase-locked loop into a first-stage digital output signal; then, the first-stage digital time converter restores the first-stage digital output signal into a first-stage time domain signal; then, subtracting the reference clock signal from the first-stage time domain signal to obtain quantization noise of the first-stage time-to-digital converter, amplifying the quantization noise by using a first-stage time amplifier, and inputting the amplified quantization noise to a second-stage time-to-digital converter so as to convert the time difference between the signal amplified by the first-stage time amplifier and the output signal of the multiple delay phase-locked loop into a second-stage digital output signal; then, the second-stage digital time converter restores the second-stage digital output signal into a second-stage time domain signal; then, subtracting the signal amplified by the first-stage time amplifier from the second-stage time domain signal to obtain the quantization noise of a second-stage time-to-digital converter, and then inputting the signal amplified by the second-stage time amplifier to a successive approximation register type analog-to-digital converter so as to convert the time difference between the signal amplified by the second-stage time amplifier and the output signal of the multiple delay phase-locked loop into a third-stage digital output signal; and adding the first-stage digital output signal, the second-stage digital output signal and the third-stage digital output signal and inputting the added signals into a digital-to-analog converter to obtain an analog output signal, wherein the analog output signal is used for controlling the frequency of the output signal of the voltage-controlled oscillator so as to obtain the output signal of the multiple delay phase-locked loop.
The time-to-digital converter system described above, wherein the system further comprises a second stage shifter and a third stage shifter for reducing the magnification; firstly, inputting a second-stage digital output signal to the second-stage shifter to obtain a second-stage shifter digital output signal, and inputting a third-stage digital output signal to the third-stage shifter to obtain a third-stage shifter digital output signal; and then adding the first-stage digital output signal, the second-stage shifter digital output signal and the third-stage shifter digital output signal and inputting the sum to a digital-to-analog converter to obtain an analog output signal.
The invention also provides a multiple delay phase-locked loop, which comprises: the time-to-digital converter system comprises a voltage-controlled oscillator connected with the digital converter system and a digital control system connected with the voltage-controlled oscillator and used for eliminating the jitter of the voltage-controlled oscillator in a fixed period.
The multiple delay locked loop described above, wherein the digital control system comprises: the frequency divider, the digital control circuit and the data selector; the reference clock signal and the output signal of the voltage-controlled oscillator are simultaneously input to the data selector; the digital control circuit generates a control signal to determine whether the data selector selects to output a reference clock signal or a voltage-controlled oscillator output signal; when the output of the digital control circuit is 0, the data selector selects and outputs the output signal of the voltage-controlled oscillator to the voltage-controlled oscillator; when the output of the digital control circuit is 1, the data selector selects to output a reference clock signal to the voltage-controlled oscillator; the reference clock signal, the output signal of the voltage-controlled oscillator and the output signal of the voltage-controlled oscillator after the frequency reduction processing of the signal frequency by the frequency divider are input to the digital control circuit and used as a trigger signal of the digital control circuit to determine whether the output of the digital control circuit is 1.
Compared with the prior art, the invention has the following beneficial effects:
the invention provides a multiple delay phase-locked loop capable of reducing in-band quantization noise, which is characterized in that two branches for reducing in-band quantization noise are added on the basis of a digital multiple delay phase-locked loop, the purpose of the multiple delay phase-locked loop is mainly to extract the quantization noise on a time-to-digital converter, the quantization noise is fed back to a circuit after three times of sampling, the quantization noise of the time-to-digital converter is reduced, the output frequency of an oscillator is adjusted in a voltage mode, and the error between the output frequency of the oscillator and the input reference frequency is reduced.
The multiple delay phase-locked loop mainly comprises a first-stage time-to-digital converter, a digital-to-analog converter, a voltage-controlled oscillator and a digital control system, and branches for reducing in-band quantization noise are two other replication loops of the digital multiple delay phase-locked loop, and the multiple delay phase-locked loop mainly comprises a first-stage digital-to-digital converter, a first-stage time amplifier, a second-stage time-to-digital converter, a second-stage digital-to-time converter, a second-stage time amplifier, a second-stage shifter, a third-stage successive approximation register type analog-to-digital converter and a third-. The invention relates to a time-domain sampling method, which comprises the steps that a first-stage digital time converter restores a first-stage digital output signal output by a first-stage time-to-digital converter into a first-stage time-domain signal, the restored first-stage time-domain signal is subtracted from a reference clock signal to obtain a quantization error of the first-stage time-to-digital converter, the quantization error is amplified by a first-stage time amplifier and then sampled for the second time by a second-stage time-to-digital converter, and a third-stage successive approximation register type analog-to-digital converter samples the quantization error of the second-stage time-to-digital converter amplified by the second-stage time amplifier.
The time-to-digital converter system and the multiple delay phase-locked loop with the function of reducing the in-band quantization noise effectively improve the precision of the time-to-digital converter applied to the multiple delay phase-locked loop by using the cascade algorithm similar to Delta-Sigma, thereby reducing the size of the quantization noise and improving the generation of the stray of the multiple delay phase-locked loop.
The input range of the third-stage successive approximation register type analog-digital converter for reducing the in-band quantization noise branch is larger than that of the first-stage and second-stage time-digital converters, so that the amplification factor of the second-stage time amplifier can be increased, and the precision of the time-digital converter can be effectively improved.
In addition, the first-stage shifter and the second-stage shifter of the in-band quantization noise branch are reduced, the multiplication function is realized by using a digital shifting method, the number of digital-to-analog converters required to be used can be effectively reduced, the whole consumed power of the circuit is reduced, and errors caused by different magnification or reduction multiplying factors generated among all stages are reduced.
The invention adds two branches for reducing in-band quantization noise in the digital multiple delay phase-locked loop, which can reduce the quantization noise of the time-to-digital converter, thereby improving the stray generation of the multiple delay phase-locked loop. The use of the successive approximation register type analog-to-digital converter enables the amplification factor of the second stage time-to-digital amplifier to be more selected, so that the size of the second stage time-to-digital amplifier can be determined according to the power consumption of the multiple delay phase-locked loop and the required precision of the time-to-digital converter.
Drawings
FIG. 1 is a diagram of a multiple delay locked loop according to the present invention;
FIG. 2 is an architecture diagram of a time-to-digital converter system according to the present invention.
Detailed Description
The invention will be further described by the following specific examples in conjunction with the drawings, which are provided for illustration only and are not intended to limit the scope of the invention.
The invention relates to a time-to-digital conversion system applied to a multiple delay phase-locked loop, which mainly realizes innovation on the invention structure, and a time-to-digital converter, a digital-to-time converter, a time amplifier, a digital-to-analog converter, a successive approximation register type analog-to-digital converter and a shifter which are used by the invention are also common circuit structures, wherein two main circuits are the time-to-digital converter and the digital-to-time converter, the core structure of the time-to-digital converter is a common high-speed time-to-digital converter, and the digital-to-time converter mainly comprises a delay chain and a data selector.
As shown in fig. 1, the multiple delay locked loop provided by the present invention includes: the digital control system comprises a time-to-digital converter system, a voltage-controlled oscillator VCO (voltage controlled oscillator) connected with the digital converter system and a digital control system connected with the voltage-controlled oscillator VCO and used for eliminating the jitter of the voltage-controlled oscillator VCO in a fixed period.
The digital control system used in the invention is a common circuit architecture, comprising: divider, digital control circuit Selection logic, and data selector Mux. The operation principle is as follows: a reference clock signal REF and a voltage-controlled oscillator output signal OUT (namely, an output signal of a multiple delay phase-locked loop) are simultaneously input to a data selector Mux; the digital control circuit Selection logic generates a control signal sel to determine whether the data selector Mux selects the output reference clock signal REF or the voltage-controlled oscillator output signal OUT; when the output sel of the digital control circuit Selection logic is 0, the data selector Mux selects and outputs the voltage-controlled oscillator output signal OUT to the voltage-controlled oscillator VCO; when the output sel of the digital control circuit selectinglogic after a fixed time becomes 1, the data selector Mux selects the output reference clock signal REF to the voltage controlled oscillator VCO; the reference clock signal REF, the voltage-controlled oscillator output signal OUT and the voltage-controlled oscillator output signal OUT subjected to the signal frequency down-conversion processing by the Divider are input to the Selection logic of the digital control circuit, and are used as trigger signals of the Selection logic of the digital control circuit to determine whether the output of the Selection logic of the digital control circuit is 1. The multiple delay phase locked loop inputs a reference clock signal REF in a fixed period, so that the jitter generated by the voltage controlled oscillator VCO can be eliminated in the fixed period.
In the embodiment shown in fig. 1, the time-to-digital converter system applied to the multiple delay phase-locked loop provided by the invention comprises: a first stage time-to-digital converter TDC1, a first stage digital-to-time converter DTC1, a first stage time amplifier TA1, a second stage time-to-digital converter TDC2, a second stage Shifter Shifter1, a second stage digital-to-time converter DTC2, a second stage time amplifier TA2, a third stage successive approximation register type analog-to-digital converter SAR-ADC, a third stage Shifter Shifter2 and a digital-to-analog converter DAC;
the reference clock signal REF and the output signal OUT of the multiple delay phase-locked loop are simultaneously input into a first stage time-to-digital converter TDC1, so that the time difference between the reference clock signal REF and the output signal OUT of the multiple delay phase-locked loop is converted into a first stage digital output signal TDC1 OUT; then the first stage digital time converter DTC1 restores the first stage digital output signal TDC1out to a first stage time domain signal; then, subtracting the reference clock signal REF from the first-stage time domain signal to obtain quantization noise of the first-stage time-to-digital converter TDC1, further amplifying the quantization noise by using a first-stage time amplifier TA1, and inputting the amplified quantization noise to a second-stage time-to-digital converter TDC2, so as to convert the time difference between the signal amplified by the first-stage time amplifier TA1 (i.e. the amplified quantization noise of the first-stage time-to-digital converter TDC 1) and the output signal OUT of the multiple delay phase-locked loop into a second-stage digital output signal; the second stage digital-to-time converter DTC2 then restores the second stage digital output signal to a second stage time domain signal; then, subtracting the second-stage time domain signal from the signal amplified by the first-stage time amplifier TA1 to obtain the quantization noise of the second-stage time-to-digital converter TDC2, further amplifying the signal by using a second-stage time amplifier TA2, and inputting the amplified signal to a successive approximation register type analog-to-digital converter SAR-ADC, so as to convert the time difference between the signal amplified by the second-stage time amplifier TA2 (i.e. the amplified quantization noise of the second-stage time-to-digital converter TDC 2) and the output signal OUT of the multiple delay phase-locked loop into a third-stage digital output signal; inputting a second-stage digital output signal into the second-stage Shifter1 to obtain a second-stage Shifter digital output signal sh 1; inputting a third-stage digital output signal into the third-stage Shifter Shifter2 to obtain a third-stage Shifter digital output signal sh 2; the second-stage Shifter Shifter1 and the third-stage Shifter Shifter2 mainly achieve the function of reducing the multiplying power, and a first-stage digital output signal TDC1OUT, a second-stage Shifter digital output signal sh1 and a third-stage Shifter digital output signal sh2 are added and input to a digital-to-analog converter DAC to obtain an analog output signal DACsum which is used for controlling the frequency of an output signal OUT of a voltage-controlled oscillator, so that the output signal OUT of the multiplying delay phase-locked loop is obtained.
For example, fig. 2 is a system architecture diagram of the time-to-digital converter of the present invention, assuming that the difference between the two input signal reference clock signal REF and the output signal OUT of the multiple delay phase locked loop (Tin REF-OUT) is a sine wave, the outputs of the first stage time-to-digital converter TDC1 and the second stage time-to-digital converter TDC2 are 2 bits, the amplification factors of the first stage time amplifier TA1 and the second stage time amplifier TA2 are 4 times, the output of the third stage successive approximation register type analog-to-digital converter SAR-ADC is 4 bits, the output range obtained by three-stage addition is between 00000000 and 11111111, so the number of bits required by the digital-to-analog converter DAC is 8, the quantization noise at this time can be reduced to 16 times, and the analog output signal DACsum of the system is a sawtooth sine wave signal. If the amplification factor of the second-stage time amplifier TA2 is increased under the condition that the power consumption is allowed and the input of the successive approximation register type analog-to-digital converter SAR-ADC is not exceeded, assuming that the amplification factor is changed to 8 times, the quantization noise can be reduced to 32 times without increasing the number of DAC bits of the digital-to-analog converter, and the analog output signal DACsum output by the system will be closer to the sine wave signal of the original input end.
It can be known from the foregoing that the noise of the multiple delay phase locked loop mainly comes from the quantization noise of the time-to-digital converter, so the invention improves the quantization noise by sampling, extracting and amplifying the quantization noise, and then re-sampling to improve the accuracy of the time-to-digital converter, and meanwhile, the spurs generated by the multiple delay phase locked loop can be improved.
In summary, the multiple delay phase-locked loop with reduced in-band quantization noise provided by the present invention adds two branches for reducing in-band quantization noise on the basis of the multiple delay phase-locked loop, and mainly uses a cascade algorithm similar to Delta-Sigma to extract and amplify the quantization noise by sampling, and then re-sampling to improve the precision of the time-to-digital converter to improve the quantization noise, thereby improving the generation of the multiple delay phase-locked loop spurs. In addition, the successive approximation register type analog-digital converter is used, so that the amplification factor of the second-stage time amplifier is more selected, and the size of the second-stage time amplifier can be determined according to the power consumption of the multiple delay phase-locked loop and the required precision of the time-digital converter. The use of the shifter reduces the number of digital-to-analog converters and reduces the power consumption of the whole circuit.
While the present invention has been described in detail with reference to the preferred embodiments, it should be understood that the above description should not be taken as limiting the invention. Various modifications and alterations to this invention will become apparent to those skilled in the art upon reading the foregoing description. Accordingly, the scope of the invention should be determined from the following claims.
Claims (3)
1. A time-to-digital converter system for use in a multiple delay phase locked loop, the system comprising: a first stage time-to-digital converter, a first stage digital-to-time converter, a first stage time amplifier, a second stage time-to-digital converter, a second stage digital-to-time converter, a second stage time amplifier, a third stage successive approximation register type analog-to-digital converter, and a digital-to-analog converter;
simultaneously inputting the reference clock signal and the output signal of the multiple delay phase-locked loop into a first-stage time-to-digital converter so as to convert the time difference between the reference clock signal and the output signal of the multiple delay phase-locked loop into a first-stage digital output signal; then, the first-stage digital time converter restores the first-stage digital output signal into a first-stage time domain signal; then, subtracting the reference clock signal from the first-stage time domain signal to obtain quantization noise of the first-stage time-to-digital converter, amplifying the quantization noise by using a first-stage time amplifier, and inputting the amplified quantization noise to a second-stage time-to-digital converter so as to convert the time difference between the signal amplified by the first-stage time amplifier and the output signal of the multiple delay phase-locked loop into a second-stage digital output signal; then, the second-stage digital time converter restores the second-stage digital output signal into a second-stage time domain signal;
then, subtracting the signal amplified by the first-stage time amplifier from the second-stage time domain signal to obtain the quantization noise of a second-stage time-to-digital converter, and then inputting the signal amplified by the second-stage time amplifier to a successive approximation register type analog-to-digital converter so as to convert the time difference between the signal amplified by the second-stage time amplifier and the output signal of the multiple delay phase-locked loop into a third-stage digital output signal;
and adding the first-stage digital output signal, the second-stage digital output signal and the third-stage digital output signal and inputting the added signals into a digital-to-analog converter to obtain an analog output signal, wherein the analog output signal is used for controlling the frequency of the output signal of the voltage-controlled oscillator so as to obtain the output signal of the multiple delay phase-locked loop.
2. The time-to-digital converter system of claim 1, further comprising a second stage shifter and a third stage shifter for scaling down; firstly, inputting a second-stage digital output signal to the second-stage shifter to obtain a second-stage shifter digital output signal, and inputting a third-stage digital output signal to the third-stage shifter to obtain a third-stage shifter digital output signal; and then adding the first-stage digital output signal, the second-stage shifter digital output signal and the third-stage shifter digital output signal and inputting the sum to a digital-to-analog converter to obtain an analog output signal.
3. A multiple delay phase locked loop, comprising: a time to digital converter system as claimed in claim 1 or 2, a voltage controlled oscillator coupled to said digital converter system and a digital control system coupled to said voltage controlled oscillator for removing voltage controlled oscillator jitter during fixed periods; the digital control system includes: the frequency divider, the digital control circuit and the data selector; the reference clock signal and the output signal of the voltage-controlled oscillator are simultaneously input to the data selector; the digital control circuit generates a control signal to determine whether the data selector selects to output a reference clock signal or a voltage-controlled oscillator output signal; when the output of the digital control circuit is 0, the data selector selects and outputs the output signal of the voltage-controlled oscillator to the voltage-controlled oscillator; when the output of the digital control circuit is 1, the data selector selects to output a reference clock signal to the voltage-controlled oscillator; the reference clock signal, the output signal of the voltage-controlled oscillator and the output signal of the voltage-controlled oscillator after the frequency reduction processing of the signal frequency by the frequency divider are input to the digital control circuit and used as a trigger signal of the digital control circuit to determine whether the output of the digital control circuit is 1.
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