CN117174725A - Chip packaging structure - Google Patents
Chip packaging structure Download PDFInfo
- Publication number
- CN117174725A CN117174725A CN202311017159.XA CN202311017159A CN117174725A CN 117174725 A CN117174725 A CN 117174725A CN 202311017159 A CN202311017159 A CN 202311017159A CN 117174725 A CN117174725 A CN 117174725A
- Authority
- CN
- China
- Prior art keywords
- chip
- bonding
- melting point
- layer
- point metal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 25
- 229910052751 metal Inorganic materials 0.000 claims abstract description 55
- 239000002184 metal Substances 0.000 claims abstract description 55
- 229910000765 intermetallic Inorganic materials 0.000 claims abstract description 22
- 239000002131 composite material Substances 0.000 claims description 10
- 230000004888 barrier function Effects 0.000 claims description 8
- 238000005538 encapsulation Methods 0.000 claims 1
- 239000007769 metal material Substances 0.000 abstract description 63
- 238000002844 melting Methods 0.000 abstract description 60
- 239000004065 semiconductor Substances 0.000 abstract description 3
- 235000012431 wafers Nutrition 0.000 description 52
- 230000008018 melting Effects 0.000 description 27
- 238000000034 method Methods 0.000 description 15
- 239000000463 material Substances 0.000 description 8
- 230000003287 optical effect Effects 0.000 description 6
- 238000003384 imaging method Methods 0.000 description 5
- 230000007547 defect Effects 0.000 description 4
- 239000000428 dust Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 3
- 238000002834 transmittance Methods 0.000 description 3
- 239000000919 ceramic Substances 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 239000000155 melt Substances 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910052718 tin Inorganic materials 0.000 description 2
- ZSLUVFAKFWKJRC-IGMARMGPSA-N 232Th Chemical compound [232Th] ZSLUVFAKFWKJRC-IGMARMGPSA-N 0.000 description 1
- 229910052776 Thorium Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- QCWXUUIWCKQGHC-UHFFFAOYSA-N Zirconium Chemical compound [Zr] QCWXUUIWCKQGHC-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 238000005247 gettering Methods 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000003331 infrared imaging Methods 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229910052755 nonmetal Inorganic materials 0.000 description 1
- 238000012634 optical imaging Methods 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 230000002035 prolonged effect Effects 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 238000005086 pumping Methods 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 238000009461 vacuum packaging Methods 0.000 description 1
- 229910052720 vanadium Inorganic materials 0.000 description 1
- 229910052726 zirconium Inorganic materials 0.000 description 1
Abstract
The invention belongs to the technical field of semiconductor packaging, and particularly relates to a chip packaging structure which comprises a chip and a cover plate, wherein metal layers are arranged on the bonding surface of the chip and the bonding surface of the cover plate, and the metal layers are connected through intermetallic compound layers. The invention can respectively plate high-melting point metal materials on two bonding surfaces which are bonded with each other, and plate low-melting point metal materials on the high-melting point metal material of one bonding surface, the low-melting point metal materials are melted and then are diffused into the high-melting point metal materials on two sides to form intermetallic compound layers, the high-melting point metal materials remain with a certain thickness as the metal layers, and the metal layers on two sides are connected together through the intermetallic compound layers to realize the packaging of the chip.
Description
Technical Field
The invention belongs to the technical field of semiconductor packaging, and particularly relates to a chip packaging structure.
Background
Wafer level packaging is increasingly being used in semiconductor packaging due to its low cost, high yield, and the like. The chip package structure is mainly composed of a chip and a cap, and a package cavity is formed by etching a deep cavity on a cap wafer. Bonding of the chip and the cap is typically performed by sandwiching a thickness of solder between the chip and the cap, and then melting the solder at a high temperature in a bonding furnace to bond the chip and the cap together. And solder melting generally requires a higher problem, resulting in higher process costs. In addition, when the MEMS device on the chip is an optical device, the etching depth of the etching process is limited, which is generally only 0.1mm, so that the window area on the cap is very close to the imaging focal plane, which results in tiny defects on the window and tiny dust outside the window being very easy to cause imaging quality problems, and further results in narrow window processing process window, low yield, and meanwhile, the imaging is also affected by external dust, which results in poor user experience.
Disclosure of Invention
In order to overcome the defects in the prior art, the invention aims to provide a chip packaging structure which not only can be bonded at low temperature and has low process cost, but also has high melting point of a generated intermetallic compound layer, and the packaging structure can be used at high temperature and has wide application range.
In order to achieve the above purpose, the technical scheme of the invention is that the chip packaging structure comprises a chip and a cover plate, wherein the chip and the cover plate are bonded to form a packaging cavity, the opposite surfaces of the chip and the cover plate are two first bonding surfaces, a metal layer is arranged on the first bonding surface, and the two metal layers are connected through an intermetallic compound layer.
As one of the implementation manners, the cover plate and/or the chip are of a combined structure, the combined structure comprises a body and an intermediate structure which are bonded with each other, and the end face, facing away from the body, of the intermediate structure is the first bonding surface.
As one of the implementation manners, the opposite surfaces of the intermediate structure and the body are two second bonding surfaces, the metal layers are arranged on the two second bonding surfaces, and the metal layers of the two second bonding surfaces are connected through the intermetallic compound layer.
As one embodiment, the chip includes a readout circuit and a focal plane disposed on the readout circuit, the focal plane being located within the package cavity.
As one embodiment, the cover plate has a window area through which light of Rong Te fixed wavelength band can pass, the window area faces the focal plane, and the area of the window area is larger than the area of the focal plane.
As one embodiment, a getter is disposed in the enclosure.
As one embodiment, the thickness of the metal layer is not less than 0.1 μm.
As one embodiment, a composite metal base layer is disposed between the metal layer and the first bonding surface and/or the second bonding surface.
As one of the embodiments, the composite metal base includes an adhesion layer and a barrier layer sequentially disposed on the bonding surface, and the metal layer is disposed on the barrier layer.
As one embodiment, the composite metal base layer has a thickness of 0.1 to 5 μm.
Compared with the prior art, the invention has the beneficial effects that:
(1) According to the invention, the high-melting-point metal materials can be respectively plated on the two bonding surfaces which are bonded with each other, and the low-melting-point metal materials are plated on the high-melting-point metal materials of one bonding surface, so that the low-melting-point metal materials are melted and then diffused into the high-melting-point metal materials on two sides to form the intermetallic compound layer, the high-melting-point metal materials remain with a certain thickness as the metal layer, and the metal layers remained on two sides are connected together through the intermetallic compound layer, so that the chip package is realized, the bonding at low temperature is realized, the process cost is low, the intermetallic compound melting point is high, the package structure can be used at high temperature, and the application range is wider;
(2) According to the invention, the intermediate structure is added between the chip and the cover plate, so that the distance between the cover plate and the chip can be increased, the influence of tiny defects on a window of the cover plate and tiny dust outside on imaging quality is reduced, the yield of the window is improved, and the user experience is improved.
Drawings
In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic structural diagram of a chip package structure according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a cover wafer, an intermediate structure, and a chip wafer according to an embodiment of the present invention;
fig. 3 is a flowchart of a wafer level packaging method of a chip package structure according to an embodiment of the present invention;
FIG. 4 is another schematic diagram of a cover wafer, an intermediate structure, and a die wafer according to an embodiment of the present invention;
FIG. 5 is a flowchart of another wafer level packaging method of a chip package structure according to an embodiment of the present invention;
in the figure: 1. a cover plate; 2. an intermediate structure; 3. a chip; 31. a readout circuit; 32. a focal plane; 4. a composite metal base layer; 5. a metal layer; 6. an intermetallic compound layer; 7. a getter; 8. a cover plate wafer; 9. a wafer with an intermediate structure; 10. a chip wafer; 11. a high melting point metal material; 12. a low melting point metal material.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
In the description of the present invention, it should be understood that the terms "center," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like indicate orientations or positional relationships based on the orientation or positional relationships shown in the drawings, merely to facilitate describing the present invention and simplify the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present invention.
The terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first", "a second" may include one or more such features, either explicitly or implicitly; in the description of the present invention, unless otherwise indicated, the meaning of "a plurality" is two or more.
As shown in fig. 1, this embodiment provides a chip packaging structure, including a chip 3 and a cover plate 1, where the chip 3 and the cover plate 1 are bonded to form a packaging cavity, opposite surfaces of the chip 3 and the cover plate 1 are two first bonding surfaces, a metal layer 5 is disposed on the first bonding surface, and the two metal layers 5 are connected through an intermetallic compound layer 6. In this embodiment, a high-melting-point metal material (at least a certain thickness remains as the metal layer 5 after bonding) may be plated on the first bonding surface of the chip 3 and the first bonding surface of the cover plate 1, and a low-melting-point metal material may be plated on the metal layer 5 on one side of the first bonding surface and the first bonding surface of the cover plate 1, and by melting the low-melting-point metal material, the low-melting-point metal material is diffused into the high-melting-point metal materials on both sides to form the intermetallic compound layer 6, and the remaining metal layers 5 on both sides are connected together, so as to realize the package of the chip 3.
The package structure of the present embodiment can be used for packaging an absolute pressure sensor, an inertial sensor based on the resonance principle (such as an accelerometer, an angular velocity sensor, a gyroscope), a micro-vacuum electronic device, an optical device (an optical switch, an infrared imaging sensor, a digital micromirror device), and the like.
In some embodiments, the cover 1 and/or the chip 3 are/is a combined structure, the combined structure includes a body and an intermediate structure 2 bonded to each other, that is, the cover 1 includes a cover body and an intermediate structure 2 bonded to each other and/or the chip 3 includes a chip body and an intermediate structure 2 bonded to each other, and an end surface of the intermediate structure 2 facing away from the body is the first bonding surface. When the optical device is packaged, the intermediate structure 2 is added between the chip 3 and the cover plate 1, so that the distance between the cover plate 1 and the chip 3 can be increased, the influence of tiny defects on a window of the cover plate 1 and tiny dust outside on the imaging quality is reduced, the yield of the window is improved, and the user experience is improved.
Further, the opposite surfaces of the intermediate structure 2 and the body in the combined structure are two second bonding surfaces, the metal layers 5 are disposed on the two second bonding surfaces, and the metal layers 5 of the two second bonding surfaces are connected through the intermetallic compound layer 6. The material of the metal layer 5 on the second bonding surface and the material of the metal layer 5 on the first bonding surface may be the same or different, and the material of the metal layers 5 on the two first bonding surfaces or the material of the metal layers 5 on the two second bonding surfaces may be generally the same or different. In this embodiment, high-melting point metal materials (at least a certain thickness remains as the metal layer 5 after bonding) can be respectively plated on the two second bonding surfaces, and low-melting point metal materials are plated on the metal layer 5 on one side of the two second bonding surfaces, and the low-melting point metal materials are melted and then diffused into the high-melting point metal materials on the two sides to form the intermetallic compound layers 6, so that the metal layers 5 remained on the two sides are connected together, the bonding can be performed at a low temperature, the process cost is low, the melting point of the intermetallic compound is high, the packaging structure can be used at a high temperature, and the application range is wider.
Specifically, the intermediate structure 2 may be a cylindrical hollow structure or a cap-shaped hollow structure; the intermediate structure 2 may be a metal or non-metal part, preferably a material such as silicon, germanium, glass, ceramic, etc. The cover plate 1 and the intermediate structure 2 can be bonded to form a combined structure, and then the combined structure and the chip 3 can be bonded, or the intermediate structure 2 and the chip 3 can be bonded to form a combined structure, and then the combined structure and the cover plate 1 can be bonded.
As an embodiment, the chip 3 includes a readout circuit 31 and a focal plane 32 disposed on the readout circuit 31, and the focal plane 32 is located in the package cavity. The focal plane 32 receives an external optical signal and processes the external optical signal into an electrical signal by the readout circuit 31 to realize an optical imaging function.
Further, the cover plate 1 has a window area through which light with a fixed wavelength band of Rong Te passes, the window area faces the focal plane 32, and the area of the window area is larger than that of the focal plane 32, or all areas of the cover plate 1 may be window areas. The window region is transparent to light of a specific wavelength band and filters unwanted stray light. The window region can be made of silicon, germanium, sapphire, glass, ceramic and the like. According to the transmittance requirement, an antireflection film is plated on the surface of the window, so that the transmittance of light in a corresponding wave band is improved. For example, if the focal plane 32 is a focal plane of an infrared detector, an infrared antireflection film may be coated on the surface of the window, so as to improve the transmittance of infrared light.
The above embodiment is optimized, and the getter 7 is arranged in the package. For high vacuum packaging devices, the getter 7 may be disposed on the inner plate surface of the cover plate 1, on the inner wall of the intermediate structure 2 or on the non-focal plane 32 area of the readout circuit 31, for maintaining a high vacuum, and the getter 7 may be one or more of zirconium, titanium, cobalt, thorium, tantalum. During or after bonding, the getter 7 is heated and activated, so that the getter 7 has gettering capability, a long-term vacuum environment in the packaging cavity is maintained, the working stability and reliability of the device are improved, and the service life of the device is prolonged. As an embodiment, the getter 7 is deposited on the inner plate surface of the cover plate 1, and the getter 7 may be activated by heating during the bonding of the intermediate structure 2 and the chip 3 to the cover plate 1 or after the bonding of the intermediate structure 2 and the chip 3 and the cover plate 1 is completed.
Further, the thickness of the metal layer 5 is not less than 0.1 μm, that is, the high melting point metal material at least remains a certain thickness after the low melting point metal material is melted and diffused, and the remaining thickness is not less than 0.1 μm, so as to ensure that the low melting point metal material is reacted completely, and avoid the gas tightness failure caused by the melting of the remaining low melting point metal material at high temperature. The high-melting point metal material can be Cu, au and other high-melting point metal materials, the low-melting point metal material can be Sn, in and other low-melting point metal materials, and the high-melting point metal material and the low-melting point metal material can be prepared by adopting evaporation, sputtering or electroplating processes. The intermetallic compound formed by the low-melting point metal material and the high-melting point metal material may be AuSn, auIn, cuSn or the like.
The chip packaging structure can be packaged by adopting a wafer level packaging method, and specifically comprises the following steps:
s1, bonding a cover plate wafer 8 and a chip wafer 10: firstly, respectively plating high-melting-point metal materials 11 on two first bonding surfaces which are bonded with each other, plating low-melting-point metal materials 12 on the high-melting-point metal materials 11 on one side of the two first bonding surfaces, aligning the two first bonding surfaces, then melting the low-melting-point metal materials 12, diffusing the low-melting-point metal materials 12 to the high-melting-point metal materials 11 on two sides after melting to form intermetallic compound layers 6, taking the residual high-melting-point metal materials 11 on two sides as metal layers 5, and connecting the metal layers 5 on two sides through the intermetallic compound layers 6; in this embodiment, the chip wafer 10 is an infrared detector chip wafer 10;
s2, scribing, and removing an invalid region of the cover plate wafer 8;
s3, dicing, namely cutting the chip wafer 10 to form a single chip packaging structure.
When the cover wafer 8 and/or the chip wafer 10 are of a combined structure, that is, the cover wafer 8 includes a cover wafer body and an intermediate structure wafer 9 bonded to each other and/or the chip wafer 10 includes a chip wafer body and an intermediate structure wafer 9 bonded to each other, in the combined structure, an end surface of the intermediate structure wafer 9 facing away from the wafer body is the first bonding surface, an opposite surface of the intermediate structure wafer 9 and the wafer body is the second bonding surface, and a bonding method of the two second bonding surfaces is the same as that in the step S1.
Further, as shown in fig. 2-5, the assembly structure is manufactured in advance, and step S1 is performed. As an embodiment, the cover wafer 8 and the intermediate structure wafer 9 are bonded to form a combined structure at a certain temperature (higher than the melting point of the low-melting point metal material 12 and lower than the melting point of the high-melting point metal material 11) and under a certain pressure, and then the combined structure and the chip wafer 10 are bonded to each other at a certain temperature (higher than the melting point of the low-melting point metal material 12 and lower than the melting point of the high-melting point metal material 11) and under a certain pressure, and then step S1 is performed. As another embodiment, the intermediate structure wafer 9 is bonded to the chip wafer 10 under a certain temperature (higher than the melting point of the low-melting point metal material 12 and lower than the melting point of the high-melting point metal material 11) and pressure to form a combined structure, then the combined structure is bonded to the cover wafer 8 under a certain temperature (higher than the melting point of the low-melting point metal material 12 and lower than the melting point of the high-melting point metal material 11) and pressure, and then step S1 is performed. In both of the above embodiments, the ineffective area of the intermediate structure wafer 9 is simultaneously removed by dicing in step S2.
The above embodiment is optimized in that the temperature at which the low-melting-point metal material 12 is melted is higher than the melting point of the low-melting-point metal material 12 and lower than the melting point of the high-melting-point metal material 11. The present embodiment melts the low-melting point metal material 12 at a temperature lower than the melting point of the high-melting point metal material 11 and higher than the melting point of the low-melting point metal material 12, ensuring that the high-melting point metal material 11 does not melt when the low-melting point metal material 12 melts.
The bonding method is described below by way of a specific example.
In this embodiment, the bonding is performed on the separate cover wafer 8 and the chip wafer 10, and the specific bonding method is as follows:
1. sequentially depositing an Au material (high-melting-point metal material 11) and an Sn material (low-melting-point metal material 12) on the bonding surface of the cover wafer 8, and depositing an Au material (high-melting-point metal material 11) on the bonding surface of the chip wafer 10;
2. placing the cover plate wafer 8 and the chip wafer 10 in a cavity of bonding equipment and aligning bonding surfaces of the cover plate wafer 8 and the chip wafer 10;
3. vacuum-pumping in the cavity to 1×10 -2 Pa or less; or filling the cavity with a protective gas (such as N 2 )；
4. Heating the cover plate wafer 8 and the chip wafer 10 to 240-260 ℃, and preserving heat for 8-12 min to melt Sn;
5. applying pressure to the cover plate wafer 8 and the chip wafer 10 to be more than 100N for bonding, so that the two wafers are fully contacted;
6. preserving heat for more than 1min under the pressurized state, fully diffusing Sn, and forming an intermetallic compound AuSn between the Sn and Au;
7. and (5) cooling to room temperature, and finishing bonding.
When the cover wafer 8 and the chip wafer 10 are in a combined structure, or other high-melting metal materials and low-melting metal materials are used for bonding, the bonding method is similar to that of the above embodiment, and will not be repeated here.
In optimizing the above embodiment, a composite metal base layer 4 is disposed between the metal layer 5 and the first bonding surface and/or the second bonding surface. Further, the thickness of the composite metal base layer 4 is 0.1-5 μm. Still further, the composite metal base includes an adhesion layer and a barrier layer sequentially disposed on the bonding surface, and the metal layer 5 is disposed on the barrier layer. Wherein, the barrier layer can prevent the metal of the metal layer 5 and the intermetallic compound layer 6 from diffusing, ensure the bonding strength, and can adopt one of Ni, cu, pd, pt and other metals; the adhesion layer can improve the adhesion performance between the barrier layer and the cover plate 1/the intermediate structure 2/the chip 3, avoid falling off, and can adopt one of Cr, ti, V and other metals.
The foregoing description of the preferred embodiments of the invention is not intended to be limiting, but rather is intended to cover all modifications, equivalents, alternatives, and improvements that fall within the spirit and scope of the invention.
Claims (10)
1. The utility model provides a chip packaging structure, includes chip and apron, the chip with the apron bonding forms encapsulation chamber, its characterized in that: the chip and the opposite surface of the cover plate are two first bonding surfaces, a metal layer is arranged on the first bonding surfaces, and the two metal layers are connected through an intermetallic compound layer.
2. The chip package structure of claim 1, wherein: the cover plate and/or the chip are/is of a combined structure, the combined structure comprises a body and an intermediate structure which are mutually bonded, and the end face, deviating from the body, of the intermediate structure is the first bonding surface.
3. The chip package structure of claim 2, wherein: the opposite surfaces of the intermediate structure and the body are two second bonding surfaces, the metal layers are arranged on the two second bonding surfaces, and the metal layers of the two second bonding surfaces are connected through the intermetallic compound layer.
4. The chip package structure of claim 1, wherein: the chip comprises a reading circuit and a focal plane arranged on the reading circuit, wherein the focal plane is positioned in the packaging cavity.
5. The chip package structure of claim 4, wherein: the cover plate is provided with a window area which can transmit light with a Rong Te fixed wave band, the window area faces the focal plane, and the area of the window area is larger than that of the focal plane.
6. The chip package structure of claim 1, wherein: a getter is disposed in the enclosure.
7. A chip package structure according to claim 1 or 3, wherein: the thickness of the metal layer is not less than 0.1 μm.
8. A chip package structure according to claim 1 or 3, wherein: and a composite metal base layer is arranged between the metal layer and the first bonding surface and/or the second bonding surface.
9. The chip package structure of claim 8, wherein: the composite metal base comprises an adhesion layer and a barrier layer which are sequentially arranged on the bonding surface, and the metal layer is arranged on the barrier layer.
10. The chip package structure of claim 8, wherein: the thickness of the composite metal base layer is 0.1-5 mu m.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311017159.XA CN117174725A (en) | 2023-08-14 | 2023-08-14 | Chip packaging structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311017159.XA CN117174725A (en) | 2023-08-14 | 2023-08-14 | Chip packaging structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN117174725A true CN117174725A (en) | 2023-12-05 |
Family
ID=88943913
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202311017159.XA Pending CN117174725A (en) | 2023-08-14 | 2023-08-14 | Chip packaging structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN117174725A (en) |
-
2023
- 2023-08-14 CN CN202311017159.XA patent/CN117174725A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7164199B2 (en) | Device packages with low stress assembly process | |
| JP4665959B2 (en) | Vacuum package | |
| JP3864134B2 (en) | Low temperature antioxidant hermetic sealing method | |
| US6686653B2 (en) | Miniature microdevice package and process for making thereof | |
| US7667324B2 (en) | Systems, devices, components and methods for hermetically sealing electronic modules and packages | |
| US7077969B2 (en) | Miniature microdevice package and process for making thereof | |
| US6512219B1 (en) | Fabrication method for integrally connected image sensor packages having a window support in contact with the window and active area | |
| KR101307436B1 (en) | Mems sensor pakiging and the method | |
| CN101691200A (en) | Low temperature vacuum encapsulation structure of non-refrigeration infrared detector and manufacturing method thereof | |
| JP4475976B2 (en) | Airtight sealed package | |
| US6515269B1 (en) | Integrally connected image sensor packages having a window support in contact with a window and the active area | |
| JPH0481348B2 (en) | ||
| KR101068042B1 (en) | Micro infrared sensor for human detection and its manufacturing method | |
| CN103224218A (en) | Encapsulation method of MEMS device | |
| US20080110013A1 (en) | Method of sealing or welding two elements to one another | |
| CN114122036A (en) | Infrared microbolometer detector module and wafer-level packaging method thereof | |
| WO2007054819A2 (en) | Sealed package with glass window for optoelectronic components and assemblies incorporating the same | |
| CN117174725A (en) | Chip packaging structure | |
| CN116105856B (en) | Infrared detector and preparation method thereof | |
| CN117174724A (en) | Wafer level packaging method and packaging structure | |
| JP2005191313A (en) | Lid and package for optical semiconductor element housing using the same | |
| JP2011035436A (en) | Method of manufacturing vacuum package | |
| JP4429115B2 (en) | Lid and optical element storage package using the same | |
| TWI798286B (en) | Method for fabrication of a leak tight electrical connection in a ceramic package and image intensifying tube comprising such a package | |
| JP3635651B2 (en) | Window glass for optical semiconductor and optical semiconductor module |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |