CN117174692A - Radio frequency module chip and preparation method thereof - Google Patents

Abstract

The embodiment of the application belongs to the technical field of semiconductor manufacturing, and relates to a radio frequency module chip, which comprises a packaging substrate and a module chip; the packaging substrate comprises a metal layer and a dielectric layer, wherein the dielectric layer is arranged between two adjacent metal layers, and at least one packaging cavity is formed on the packaging substrate; the module chip is flip-chip mounted on two opposite sides of the package substrate and/or in the package cavity, and is connected with the metal layer. The application also relates to a preparation method of the radio frequency module chip. The technical scheme provided by the application can reduce the packaging height of the radio frequency module chip and realize the miniaturization design of the radio frequency module chip.

Description

Radio frequency module chip and preparation method thereof

Technical Field

The application relates to the technical field of semiconductor manufacturing, in particular to a radio frequency module chip and a preparation method of the radio frequency module chip.

Background

With the development of electronic technology, the integration level of the mobile communication radio frequency front end module is higher and higher. The radio frequency module is integrated with an active chip, a passive chip, components (capacitance, resistance, inductance) related to matching of internal circuits of the module, and the like. In the packaging process, the components are required to be integrated into a radio frequency front end module system, the integrated radio frequency module system is packaged into a module chip, and the module chip has the advantages of miniaturization and high integration compared with the radio frequency front end system formed by discrete components.

At present, the integrated package of the module usually adopts the design that devices such as an active/passive wafer, a matching circuit element and the like are uniformly integrated on the surface of one side of a package substrate, a bonding pad pin is integrated on the other side of the package substrate, the integrated package design can only be integrated on one side of the substrate, the integrated level of chip package is low, and the thickness of an active chip is larger than that of a passive chip, so that the chips on the same side of the package substrate have thickness difference, and the overall height of the radio frequency module chip is higher and the size is large.

Disclosure of Invention

The embodiment of the application aims to solve the technical problems that the chip package of the existing module integrated package has low integration level and the integrated module has large size.

In order to solve the above technical problems, the embodiment of the present application provides a radio frequency module chip, which adopts the following technical scheme:

a radio frequency module chip comprises a package substrate and a module chip;

the packaging substrate comprises a metal layer and a dielectric layer, wherein the dielectric layer is arranged between two adjacent metal layers, and at least one packaging cavity is formed on the packaging substrate;

the module chip is flip-chip mounted on two opposite sides of the packaging substrate and/or in the packaging cavity, and the module chip is connected with the metal layer.

Further, the heights of the top surfaces of the module chips positioned on the same side of the packaging substrate are the same;

the thickness of the module chip positioned in the packaging cavity is larger than that of the module chip positioned on the surface of the packaging substrate.

Further, the metal layer comprises a metal bonding pad and a metal terminal, and the metal bonding pad and the metal terminal are arranged on the dielectric layer at intervals;

the module chip is electrically connected with the metal bonding pad.

Further, the radio frequency module chip further comprises a solder mask layer, the solder mask layer is arranged on the metal layer, and an opening is formed at the position, corresponding to the metal bonding pad, of the solder mask layer.

Further, the packaging substrate further comprises a metallization hole, and the metallization hole penetrates through the dielectric layer;

adjacent two metal layers are connected through the metallized holes;

the metal bonding pad and the metal terminal are respectively connected with the metallized hole through wires.

Further, the package substrate further comprises a substrate pin, and the substrate pin is connected with the metal bonding pad.

Further, the module chip comprises a chip wafer and conductive bumps, and the chip wafer is flip-chip mounted on the metal layer through the conductive bumps; and/or

The radio frequency module chip further comprises a packaging layer, wherein the packaging layer is arranged on the metal layers on the two side surfaces of the packaging substrate, and the packaging layer completely covers the module chip.

In order to solve the above technical problems, the embodiment of the present application further provides a method for manufacturing a radio frequency module chip, which adopts the following technical scheme:

a preparation method of a radio frequency module chip is used for preparing the radio frequency module chip, and comprises the following steps:

providing a packaging substrate, wherein at least one packaging cavity is arranged on the surface of the packaging substrate, and the bottom surface of the packaging cavity is a metal layer;

etching the exposed metal layer on the surface of the packaging substrate to form metal pads and metal terminals which are arranged at intervals;

forming a solder mask layer on the metal layer, wherein an opening is formed in the solder mask layer corresponding to the metal bonding pad;

forming substrate pins on the metal pads on one side of the package substrate;

and mounting the module chip on the packaging substrate, wherein the module chip is positioned on the surface of the packaging substrate and in the packaging cavity, and the heights of the top surfaces of the module chips positioned on the same side surface of the packaging substrate are the same.

Further, the package substrate is prepared by the following steps:

providing a metal layer and a dielectric layer, and forming a packaging substrate in a pressing stacking mode, wherein the dielectric layer is arranged between two adjacent metal layers;

etching the surface of the packaging substrate to form a packaging cavity on the packaging substrate, wherein the bottom of the packaging cavity exposes the metal layer.

Further, the forming a solder mask layer on the metal layer includes the following steps:

forming an initial solder mask layer on the metal layer;

exposing the initial solder mask layer;

and developing and windowing the solder mask after exposure treatment to expose the metal bonding pad.

Compared with the prior art, the embodiment of the application has the following main beneficial effects:

according to the application, the package cavities are formed on the surfaces of the two opposite sides of the package substrate, the module chips are arranged in the package cavities, so that the height of the radio frequency module chips is effectively reduced, the miniaturized design of the radio frequency module chips is realized, and meanwhile, when the module chips with different thicknesses are arranged on the package substrate, the heights from the top surfaces of the module chips to the surfaces of the package substrate are consistent, so that the chip coverage of the package substrate is unified, and the package efficiency of the radio frequency module chips is improved; in addition, the module chip is arranged on the surfaces of two sides of the module packaging substrate or in the packaging cavities of two sides in a flip-chip mode, so that the overall size of the radio frequency packaging chip is effectively reduced, the integration level of the chip packaging is improved, and the design of miniaturized integration of the radio frequency module chip is realized.

Drawings

In order to more clearly illustrate the solution of the present application, a brief description will be given below of the drawings required for the description of the embodiments, it being apparent that the drawings in the following description are some embodiments of the present application and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic diagram of a RF module chip according to an embodiment of the present application;

FIG. 2 is a schematic diagram of a package substrate and a solder mask according to an embodiment of the application;

FIG. 3 is a flowchart of a method for manufacturing a radio frequency module chip according to an embodiment of the present application;

fig. 4a to 4d are schematic views of structural changes at various stages in the preparation process of the rf module chip according to the embodiment of the application.

Reference numerals:

1. packaging a substrate; 11. a metal layer; 111. a metal pad; 112. a metal terminal; 12. a dielectric layer; 13. packaging the cavity; 14. metallizing the holes; 15. a solder mask layer; 16. a substrate pin; 21. a first module chip; 211. a first chip wafer; 212. a first conductive bump; 22. a second module chip; 221. a second chip wafer; 222. a second conductive bump; 23. a third module chip; 231. a third chip wafer; 232. a third conductive bump; 3. and an encapsulation layer.

Detailed Description

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs; the terminology used in the description of the applications herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application; the terms "comprising" and "having" and any variations thereof in the description of the application and the claims and the description of the drawings above are intended to cover a non-exclusive inclusion. The terms first, second and the like in the description and in the claims or in the above-described figures, are used for distinguishing between different objects and not necessarily for describing a sequential or chronological order.

Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the application. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those of skill in the art will explicitly and implicitly appreciate that the embodiments described herein may be combined with other embodiments.

Referring to fig. 1, an embodiment of the present application provides a radio frequency module chip, including: the substrate 1 and the module chip are packaged.

The packaging substrate 1 comprises a metal layer 11 and a dielectric layer 12, wherein the dielectric layer 12 is arranged between two adjacent metal layers 11, and at least one packaging cavity 13 is formed on the packaging substrate 1; in this embodiment, two package cavities 13 are disposed on the package substrate 1, and in this embodiment, the height of the package cavities is equal to the sum of the etching depth of the dielectric layer and the etching depth of the metal layer. Two packaging cavities 13 are respectively formed on two opposite sides of the packaging substrate 1, and the bottom surface of the packaging cavity 13 exposes the metal layer 11.

The module chip is flip-chip mounted on two opposite sides of the package substrate 1 and/or in the package cavity 13, the module chip is connected with the metal layer 11,

according to the radio frequency module chip provided by the embodiment of the application, the packaging cavities 13 are formed on the surfaces of the two opposite sides of the packaging substrate 1, the module chip is arranged in the packaging cavities 13, so that the height of the radio frequency module chip is effectively reduced, the miniaturized design of the radio frequency module chip is realized, and meanwhile, when the module chips with different thicknesses are arranged on the packaging substrate 1 by controlling the depth of the packaging cavities 13, the heights from the top surface of the module chip to the surface of the packaging substrate 1 are consistent, so that the chip coverage arranged on the packaging substrate 1 is unified, and the packaging efficiency of the radio frequency module chip is improved; in addition, the module chip is arranged on the surfaces of the two sides of the module packaging substrate 1 or in the packaging cavities of the two sides in a flip-chip manner, so that the overall size of the radio frequency packaging chip is effectively reduced, the integration level of the chip packaging is improved, and the design of miniaturized integration of the radio frequency module chip is realized.

In this embodiment, the module chip includes at least two module chips respectively flipped onto two opposite sides of the package substrate 1, and hereinafter, for example, three module chips are included, as shown in fig. 1, the module chips include a first module chip 21, a second module chip 22, and a third module chip 23, where the first module chip 21 is flipped into the package cavity 13 on the top surface of the package substrate 1 and is connected to the exposed metal layer 11 on the bottom surface of the package cavity 13; the second module chip 22 is flip-chip mounted on the metal layer 11 on the top surface of the package substrate 1; the third module chip 23 is flip-chip mounted in the package cavity 13 on the bottom surface of the package substrate 1, and is connected to the exposed metal layer 11 on the bottom surface of the package cavity 13.

With continued reference to fig. 1, in some embodiments, the top surfaces of the die set chips on the same side of the package substrate 1 are the same, and the thickness of the die set chips in the package cavity 13 is greater than the thickness of the die set chips on the surface of the package substrate 1.

In this embodiment, the first module chip 21 is an active chip, and the first module chip 21 is flip-chip mounted in the package cavity 13 on the top surface of the package substrate 1 and is connected to the exposed metal layer 11 on the bottom surface of the package cavity 13; the second module chip 22 is a passive chip and is flip-chip mounted on the metal layer 11 on the top surface of the package substrate 1; because passive chip thickness is less than active chip thickness, when first module chip 21 install in encapsulation cavity 13, first module chip 21 is at least partly be located encapsulation cavity 13 to reduced the whole height of first module chip 21, shortened the interval between the top surface of first module chip 21 and the top surface of encapsulation base plate 1, thereby make the top surface height of first module chip 21 with the top surface height of second module chip 22 is the same, thereby control the height of radio frequency module chip is unanimous, so that follow-up encapsulation that unifies, simplify the encapsulation technology of follow-up radio frequency module chip.

Referring to fig. 1 and 2, in some embodiments, the metal layer 11 includes a metal pad 111 and a metal terminal 112, and the metal pad 111 and the metal terminal 112 are disposed on the dielectric layer 12 at intervals; the module chip is electrically connected to the metal pad 111.

In this embodiment, the metal layers 11 on two opposite side surfaces of the package substrate 1 form metal pads 111 and metal terminals 112 disposed at intervals by an etching process, where the metal pads 111 are used for electrically connecting with the module chip, and the metal terminals 112 serve as interconnection wires for each signal of the radio frequency module chip and as grounding signals.

Referring to fig. 2, in some embodiments, the rf module chip further includes a solder mask layer 15, the solder mask layer 15 is disposed on the metal layer 11, openings are formed at positions of the solder mask layer 15 corresponding to the metal pads 111, in this embodiment, the solder mask layer 15 is formed on the metal layer 11 on two opposite sides of the package substrate 1 by deposition, and a development windowing process is performed at positions corresponding to the metal pads 111, so as to form openings exposing the metal pads 111, so that the metal pads 111 can be electrically connected with the module chip, in this embodiment, the solder mask layer 15 after exposure and development processes is formed on the metal terminals 112, between two adjacent metal terminals 112, between the metal terminals 112 and the metal pads 111, and between two adjacent metal pads 111, so as to avoid a short circuit phenomenon when the module chip is attached to the metal layer 11, and protect the metal layer 11, thereby improving the service life of the rf module chip.

Referring to fig. 1 and 2, in some embodiments, the package substrate 1 further includes a metallization hole 14, and the metallization hole 14 penetrates through the dielectric layer 12; adjacent two metal layers 11 are connected by the metallized holes 14; the metal pads 111 and the metal terminals 112 are connected to the metallized holes 14 through wires (not shown in the figure), respectively, and in this embodiment, the metallized holes 14 are connected between the metal pads 111 of two adjacent metal layers 11 for signal interconnection between different metal layers 11.

Referring to fig. 1, in some embodiments, the package substrate 1 further includes substrate pins 16, the substrate pins 16 are connected to the metal pads 111, in this embodiment, two metal pads 111 are formed on opposite sides of the metal layer 11 on the bottom surface of the package substrate 1, the package substrate 1 includes two substrate pins 16, two substrate pins 16 are connected to two metal pads 111 on opposite sides of the metal layer 11 on the bottom surface of the package substrate 1, and a third module chip 23 is disposed between the two substrate pins 16.

In some embodiments, the die set chip includes a die wafer and conductive bumps, the die wafer is flip-chip mounted on the metal layer 11 through the conductive bumps, in this embodiment, the die set chip specifically includes a first die set chip 21, a second die set chip 22, and a third die set chip 23, the first die set chip 21 includes a first die wafer 211 and first conductive bumps 212, the first die wafer 211 is flip-chip mounted in the package cavity 13 on the top surface of the package substrate 1, and is connected with the exposed metal pads 111 on the bottom surface of the package cavity 13 through the first conductive bumps 212; the second module chip 22 includes a second chip wafer 221 and a second conductive bump 222, where the second chip wafer 221 is flip-chip mounted on the metal layer 11 on the top surface of the package substrate 1, and is connected to the exposed metal pad 111 on the top surface of the package substrate 1 through the second conductive bump 222; the third module chip 23 includes a third chip wafer 231 and third conductive bumps 232, and the third chip wafer 231 is flip-chip mounted in the package cavity 13 on the bottom surface of the package substrate 1, and is connected to the exposed metal pads 111 on the bottom surface of the package cavity 13 through the third conductive bumps 232.

According to the embodiment of the application, the module chip is arranged on the packaging substrate 1 in a flip-chip manner, so that the height of the module chip is reduced, and the space required by the chip on the packaging substrate 1 is reduced, thereby improving the utilization rate of the packaging substrate 1 and improving the integration degree of the chip on the packaging substrate 1.

Referring to fig. 1, in some embodiments, the rf module chip further includes a packaging layer 3, the packaging layer 3 is disposed on the metal layers 11 on two side surfaces of the packaging substrate 1, the packaging layer 3 completely covers the module chip, in this embodiment, the packaging layer 3 on the top surface of the packaging substrate 1 completely covers the exposed metal layers 11 on the top surface of the packaging substrate 1, the first module chip 21 and the second module chip 22, and the packaging layer 3 on the bottom surface of the packaging substrate 1 is disposed between the two substrate pins 16 and completely covers the third module chip 23.

According to the embodiment of the application, the packaging layers 3 are formed on the opposite side surfaces of the packaging substrate 1, so that the module chips are well packaged on the opposite side surfaces of the packaging substrate 1, the packaging layers 3 and the packaging substrate 1 form an integrated flat structure after the module chips are packaged, further the subsequent surface mounting processing of the radio frequency module chips is facilitated, and the packaging layers 3 are arranged, so that the module chips are isolated from the outside, and the effects of moisture prevention, insulation and module chip falling prevention are achieved.

Referring to fig. 1, in this embodiment, a solder mask layer 15 is further disposed on the package layer 3 on the bottom surface of the package substrate, so as to further improve the effects of moisture-proof, insulating and preventing the die set chip from falling off of the package layer 3.

Referring to fig. 3, the embodiment of the application also provides a method for preparing a radio frequency module chip, which is used for preparing the radio frequency module chip, and comprises the following steps:

step S100, providing a packaging substrate, wherein at least one packaging cavity is formed on the surface of the packaging substrate, and a metal layer is exposed at the bottom of the packaging cavity.

And step 200, etching the exposed metal layer on the surface of the packaging substrate to form metal pads and metal terminals which are arranged at intervals.

And step S300, forming a solder mask layer on the surface metal layer, wherein an opening is arranged at the position of the solder mask layer corresponding to the metal bonding pad.

And step S400, forming substrate pins on the metal pads on one side of the package substrate.

And S500, mounting a module chip on the packaging substrate, wherein the module chip is positioned on the surface of the packaging substrate and in the packaging cavity, and the heights of the top surfaces of the module chips positioned on the same side surface of the packaging substrate are the same.

According to the preparation method of the radio frequency module chip, the package cavity is formed on the surface of the package substrate, and the module chip is arranged in the package cavity, so that the height of the radio frequency module chip is effectively reduced, and the miniaturized design of the radio frequency module chip is realized; the surface of the opposite sides of the packaging substrate or the inside of the packaging cavity is provided with the module chip, so that the overall size of the radio frequency packaging chip is effectively reduced, the integration level of the chip packaging is improved, and the design of miniaturized integration of the radio frequency module chip is realized.

In this embodiment, the package substrate in the step S100 is prepared by the following steps:

providing a metal layer and a dielectric layer, and forming the packaging substrate in a pressing stacking mode.

In this embodiment, the package substrate includes a plurality of metal layers and a plurality of dielectric layers, and the metal layers and the dielectric layers are disposed at intervals and stacked by pressing, so that the package substrate is formed by the metal layers and the dielectric layers, where the dielectric layers are disposed between two adjacent metal layers, and the two adjacent metal layers are electrically connected through the metallized holes.

Etching the surface of the packaging substrate to form a packaging cavity on the packaging substrate, wherein the bottom of the packaging cavity exposes the metal layer.

In this embodiment, before etching the surface of the package substrate, the package substrate formed by lamination stacking is subjected to pre-treatment such as cutting, cleaning, dust removing, gluing, exposure, developing, etc. so as to form a cavity for later etching processing of the substrate.

And dry etching is performed on the top surface and the bottom surface of the packaging substrate, wherein the etching depth is at least one metal layer and at least one dielectric layer so as to form a packaging cavity, the metal layer is exposed at the bottom of the packaging cavity, and in other embodiments, the top surface and the bottom surface of the packaging substrate can be etched in a wet etching mode.

In other embodiments, the package substrate in the step S100 may be further prepared by the following steps:

providing a metal layer and a dielectric layer, and forming a single-layer substrate by pressing and stacking.

In this embodiment, the single-layer substrate includes two metal layers and a dielectric layer disposed between the two metal layers.

And etching the single-layer substrate to form a packaging cavity on the single-layer substrate.

In this embodiment, the single-layer substrate is subjected to dry etching to form a penetrating package cavity.

And laminating and stacking the single-layer substrate with the packaging cavity and the single-layer substrate without etching to form the packaging substrate.

In this embodiment, a single-layer substrate forming a package cavity is located on opposite sides of the package substrate to form a package substrate having at least one package cavity on a surface thereof.

In some embodiments, the step S200 of etching the exposed metal layer on the surface of the package substrate specifically includes the following steps:

and performing gluing treatment on the target area of the exposed metal layer on the surface of the packaging substrate.

And exposing and developing the metal layer subjected to the gluing treatment.

And etching the metal layer after exposure and development treatment.

The package substrate after the processing of step S200 is shown in fig. 4 a.

In some embodiments, the step S300 of forming a solder mask layer on the metal layer includes the steps of:

an initial solder mask layer is formed on the metal layer.

In this embodiment, the thickness of the initial solder mask layer is greater than that of the metal layer, so that the initial solder mask layer can completely cover the metal layer.

And performing exposure treatment on the initial solder mask layer to generate a chip solder mask layer windowing pattern required by the metal layer.

And developing and photoresist removing treatment is carried out on the solder mask after exposure treatment, so that the window of the solder mask is opened to expose the metal bonding pad.

According to the embodiment of the application, the solder mask layer is formed on the metal layer, and is subjected to exposure and development windowing treatment to expose the metal bonding pad, so that the short circuit phenomenon is avoided when the module chip is attached to the metal layer on the premise that the module chip can be stably attached to the packaging substrate and the chip wafer can be stably and electrically connected with the metal bonding pad, the service life of the radio frequency module chip is prolonged, and the packaging substrate processed in the step S300 is shown in fig. 2.

In some embodiments, the step S400 of forming substrate pins on metal pads on one side of the package substrate includes the steps of:

and carrying out metal coating or ball implantation treatment on the metal bonding pads on two opposite sides of the bottom surface of the packaging substrate to form substrate pins so as to prepare the packaging substrate capable of carrying out flip-chip bonding, wherein in the embodiment, the metal coating or ball implantation treatment is made of alloy materials of one or more of copper, silver, aluminum, tin, lead, nickel, titanium, platinum and gold.

In this embodiment, the package substrate processed in step S400 is shown in fig. 4b (the solder mask layer is omitted).

In some embodiments, the step S500 of attaching the module chip to the package substrate specifically includes the following steps:

and flip-chip mounting the first chip wafer in the packaging cavity on the top surface of the packaging substrate, and bonding and connecting the first chip wafer with the metal bonding pad in the packaging cavity through a first conductive bump, wherein in some embodiments, the material of the first conductive bump is selected from alloy materials of one or more of copper, silver, aluminum, tin, lead, nickel, titanium, platinum and gold, and in this embodiment, the material of the first conductive bump is consistent with the material of the base pin of the packaging substrate.

And the second chip wafer is inversely arranged on the top surface of the packaging substrate and is connected with the metal bonding pad on the top surface of the packaging substrate through a second conductive bump, the top surface of the second chip wafer is the same as the top surface of the first chip wafer, in some embodiments, the material of the second conductive bump is selected from alloy materials of one or more of copper, silver, aluminum, tin, lead, nickel, titanium, platinum and gold, and in this embodiment, the material of the second conductive bump is consistent with the material of the substrate pin to which the second conductive bump belongs.

And flip-chip mounting a third chip wafer in the packaging cavity on the bottom surface of the packaging substrate, and bonding and connecting the third chip wafer with the metal bonding pad in the packaging cavity through a third conductive bump, wherein the material of the third conductive bump is selected from alloy materials of one or more of copper, silver, aluminum, tin, lead, nickel, titanium, platinum and gold, and in the embodiment, the material of the third conductive bump is consistent with the material of the base pin of the packaging substrate.

The RF module chip after the module chip is mounted by the above steps is shown in FIG. 4 c.

According to the embodiment of the application, the module chip is arranged on the packaging substrate in a flip-chip manner, so that the height of the module chip is reduced, the space required by the chip on the packaging substrate is reduced, the utilization rate of the packaging substrate is improved, the integration degree of the chip on the packaging substrate is improved, and meanwhile, the substrate glue filling, the first conductive bump, the second conductive bump and the third conductive bump are prepared from the same material, so that the welding stability of the chip wafer and the packaging substrate is sequentially improved.

In some embodiments, after the step S500, the method further includes the following steps:

and forming a packaging layer on the exposed metal layer on the surface of the packaging substrate, wherein the packaging layer completely covers the module flip chip, and in the embodiment, the thickness of the packaging layer ranges from 100 mu m to 1500 mu m.

In this embodiment, the packaging layer is disposed on the metal layers on the two side surfaces of the packaging substrate, the packaging layer completely covers the module chip, in this embodiment, the packaging layer on the top surface of the packaging substrate completely covers the exposed metal layer on the top surface of the packaging substrate, the first module chip and the second module chip, and the packaging layer on the bottom surface of the packaging substrate is disposed between the two substrate pins and completely covers the third module chip.

The rf module chip after the package layer is prepared through the above steps is shown in fig. 4 d.

According to the embodiment of the application, the packaging layers are formed on the opposite side surfaces of the packaging substrate, so that the module chips are well packaged on the opposite side surfaces of the packaging substrate, the packaging layers and the packaging substrate form an integrated flat structure after the module chips are packaged, further the subsequent surface mounting processing of the radio frequency module chips is facilitated, and the module chips are isolated from the outside through the arrangement of the packaging layers, so that the effects of moisture prevention, insulation and chip falling prevention are achieved.

It is apparent that the above-described embodiments are only some embodiments of the present application, but not all embodiments, and the preferred embodiments of the present application are shown in the drawings, which do not limit the scope of the patent claims. This application may be embodied in many different forms, but rather, embodiments are provided in order to provide a thorough and complete understanding of the present disclosure. Although the application has been described in detail with reference to the foregoing embodiments, it will be apparent to those skilled in the art that modifications may be made to the embodiments described in the foregoing description, or equivalents may be substituted for elements thereof. All equivalent structures made by the content of the specification and the drawings of the application are directly or indirectly applied to other related technical fields, and are also within the scope of the application.

Claims (10)

1. The radio frequency module chip is characterized by comprising a packaging substrate and a module chip;

the packaging substrate comprises a metal layer and a dielectric layer, wherein the dielectric layer is arranged between two adjacent metal layers, and at least one packaging cavity is formed on the packaging substrate;

the module chip is flip-chip mounted on two opposite sides of the packaging substrate and/or in the packaging cavity, and the module chip is connected with the metal layer.

2. The rf module chip of claim 1, wherein the top surfaces of the module chips on the same side of the package substrate are the same height;

the thickness of the module chip positioned in the packaging cavity is larger than that of the module chip positioned on the surface of the packaging substrate.

3. The radio frequency module chip of claim 1, wherein the metal layer comprises a metal pad and a metal terminal, the metal pad and the metal terminal being disposed on the dielectric layer at a distance;

the module chip is electrically connected with the metal bonding pad.

4. The rf module chip of claim 3 further comprising a solder mask layer disposed on the metal layer, the solder mask layer forming an opening corresponding to the metal pad.

5. The rf module chip of claim 3 wherein the package substrate further comprises a metallized hole, the metallized hole being formed through the dielectric layer;

adjacent two metal layers are connected through the metallized holes;

the metal bonding pad and the metal terminal are respectively connected with the metallized hole through wires.

6. The radio frequency module chip of claim 3, wherein the package substrate further comprises substrate pins, the substrate pins being connected to the metal pads.

7. The rf module chip of any one of claims 1-6, wherein the module chip includes a chip wafer and conductive bumps, the chip wafer being flip-chip mounted on the metal layer by the conductive bumps; and/or

The radio frequency module chip further comprises a packaging layer, wherein the packaging layer is arranged on the metal layers on the two side surfaces of the packaging substrate, and the packaging layer completely covers the module chip.

8. A method for preparing a radio frequency module chip according to any one of claims 1 to 7, comprising the steps of:

providing a packaging substrate, wherein at least one packaging cavity is arranged on the surface of the packaging substrate, and the bottom surface of the packaging cavity is a metal layer;

etching the metal layer exposed by the packaging substrate to form metal pads and metal terminals which are arranged at intervals;

forming a solder mask layer on the metal layer, wherein an opening is formed in the solder mask layer corresponding to the metal bonding pad;

forming substrate pins on the metal pads on one side of the package substrate;

and mounting the module chip on the packaging substrate, wherein the module chip is positioned on the surface of the packaging substrate and in the packaging cavity, and the heights of the top surfaces of the module chips positioned on the same side surface of the packaging substrate are the same.

9. The method for manufacturing a radio frequency module chip according to claim 8, wherein the package substrate is manufactured by:

providing a metal layer and a dielectric layer, and forming a packaging substrate in a pressing stacking mode, wherein the dielectric layer is arranged between two adjacent metal layers;

etching the surface of the packaging substrate to form a packaging cavity on the packaging substrate, wherein the bottom of the packaging cavity exposes the metal layer.

10. The method for manufacturing a radio frequency module chip according to claim 8, wherein the forming a solder mask layer on the metal layer comprises the steps of:

forming an initial solder mask layer on the metal layer;

exposing the initial solder mask layer;

and developing and windowing the solder mask after exposure treatment to expose the metal bonding pad.