CN117174658A

CN117174658A - Semiconductor device including transistor cells and related methods of fabrication

Info

Publication number: CN117174658A
Application number: CN202311029066.9A
Authority: CN
Inventors: 维平达斯·帕拉; 索维克·乔杜里
Original assignee: Chengdu Monolithic Power Systems Co Ltd
Current assignee: Chengdu Monolithic Power Systems Co Ltd
Priority date: 2022-08-15
Filing date: 2023-08-15
Publication date: 2023-12-05
Also published as: CN118198143A

Abstract

A semiconductor device including a transistor cell and a related method of fabrication are disclosed. The semiconductor device includes a first source region, a first sidewall body region, a gate region, a second source region, and a connection region formed on a substrate having a first conductivity type. The first source region and the second source region are of a first conductivity type, while the first sidewall body region and the connection region are of a second conductivity type opposite the first conductivity type. The connection region and the gate region are disposed on a first side and a second side of the first source region, respectively. The first sidewall body region is disposed below the first source region. The semiconductor device disclosed by the invention has low on-resistance, high breakdown voltage and good high-voltage resistance.

Description

Semiconductor device including transistor cells and related methods of fabrication

Technical Field

Embodiments of the present invention relate to a semiconductor device, and more particularly, to a semiconductor device including a transistor cell and a related method of manufacturing the same.

Background

Power transistors, such as high voltage metal oxide semiconductor field effect transistors (Metal Oxide Semiconductor Field Effect Transistor, MOSFETs), are widely used in the power management field as power switching elements for power management devices in industrial and consumer electronic devices. In most high power applications, it is often desirable that the transistor have a high withstand voltage, low on-resistance, and high power handling capability.

Disclosure of Invention

In order to meet the high power application requirements of transistors, the present invention provides a semiconductor device comprising transistor cells, which can withstand high electric fields and has a high breakdown voltage and a low on-resistance, and a related manufacturing method.

According to an embodiment of the present invention, there is provided a method of manufacturing a semiconductor device, including: forming a substrate of a first conductivity type, the substrate comprising a drain region doped in a partial region of a first surface of an adjacent substrate; forming a first source region having a first conductivity type and a second source region having a first conductivity type in the substrate, wherein the first source region is formed in a partial region adjacent to a second surface of the substrate, wherein the second source region is formed below and spaced apart from the first source region, the second surface of the substrate being opposite to the first surface of the substrate; forming a gate groove of a gate region in the substrate so that the gate groove is adjacent to/close to the first source region; forming a first sidewall body region having a second conductivity type under the first source region to separate the first source region and the second source region; forming a connection region having a second conductivity type such that the connection region and the gate trench are disposed on a first side of the first source region and a second side of the first source region, respectively, wherein the first side of the first source region is opposite to the second side of the first source region; forming a gate insulating layer to cover the side wall and the bottom of the gate trench; and filling the gate trench with a gate conductive material.

In one embodiment, the step of forming a substrate in the method of manufacturing a semiconductor device includes: forming a semiconductor layer having a first conductivity type and forming an epitaxial layer having the first conductivity type over the semiconductor layer, the semiconductor layer including a drain region formed by doping a partial region of a first surface of an adjacent semiconductor layer.

According to an embodiment of the present invention, the foregoing method for manufacturing a semiconductor device further includes: an oxidation step to oxidize an uppermost portion of the gate conductive material in the gate trench to form a gate cap layer, wherein a preset gate cap thickness of the gate cap layer is thicker than a preset gate insulation thickness of the gate insulation layer; a post-etch treatment step to expose portions of the second surface of the substrate not covered by the gate cap layer; a deposition step to form a metal layer on the entire exposed top surface of the structure formed after the post-etch treatment step; a silicidation step of forming a silicide layer on a portion of the second surface of the substrate not covered by the gate capping layer; a deposition step to form an interlayer dielectric layer covering the silicide layer and the gate cover layer; an etching step to form a source contact trench and a gate contact trench, wherein the source contact trench is formed by etching the interlayer dielectric layer to expose at least a portion of the silicide layer located over the first source region, and the gate contact trench is formed by etching the interlayer dielectric layer to expose at least a portion of the gate conductive material in the gate trench; and a metal deposition step to fill the source contact trench and the gate contact trench to form a source metal contact and a gate metal contact, respectively.

These and other features of the present disclosure will be apparent to one of ordinary skill in the art upon review of all the disclosure, including the drawings and claims.

Drawings

For a better understanding of the present invention, the present invention will be described in detail with reference to the following drawings:

fig. 1 shows a schematic partial cross-sectional view of a semiconductor device 100 according to an embodiment of the invention;

fig. 2A shows a partial cross-sectional simulation of the resistance distribution between the MOSFET channel and the JFET when the semiconductor device 100 is in an on or conducting state;

fig. 2B shows a graph of a characteristic on-resistance (or specific on-resistance) versus distance from a second surface of the substrate (e.g., top surface S1 of epitaxial layer 102 shown in fig. 1) of semiconductor device 100 in an on or on state, wherein the given rated breakdown voltage is 750V;

fig. 3A shows a partial cross-sectional simulation of the equipotential line distribution for the semiconductor device 100 in an on or conducting state;

fig. 3B shows an electrical characteristic simulation curve 301 of the relationship between the drain-source current IDS flowing from the drain region 101 to the source region 103 and the gate-source voltage VG of the semiconductor device 100 in the on or off state;

fig. 4A shows a partial cross-sectional simulation of the equipotential lines and the depletion region boundary for the semiconductor device 100 in the off or off state;

Fig. 4B shows a JFET source voltage versus drain-source voltage VDS curve 401 at the second source region 108 and a drain-source current IDS versus drain-source voltage VDS curve 402 for the semiconductor device 100 when the semiconductor device 100 is in an off or off state;

FIGS. 5A-5T are schematic partial cross-sectional views illustrating a portion of a fabrication process in a method of fabricating a semiconductor device (e.g., semiconductor device 100 of FIG. 1) in accordance with one embodiment of the invention;

fig. 6 shows a schematic partial cross-sectional view of a semiconductor device 200 according to another embodiment of the invention;

fig. 7 illustrates a partial cross-sectional schematic view of a process for preparing a TBO layer implemented between the steps illustrated in fig. 5J and the steps illustrated in fig. 5K in a method for preparing a semiconductor device (e.g., semiconductor device 200 illustrated in fig. 6) in accordance with an embodiment of the present invention;

fig. 8 shows a schematic partial cross-sectional view of a semiconductor device 300 according to another embodiment of the invention;

fig. 9A and 9B are partial cross-sectional views illustrating a portion of a fabrication step in a method of fabricating a semiconductor device (e.g., semiconductor device 300 of fig. 8) according to an embodiment of the present invention, respectively, in place of the fabrication steps illustrated in fig. 5A and 5B, respectively;

Fig. 10 shows a schematic partial cross-sectional view of a semiconductor device 400 according to another embodiment of the invention;

fig. 11 shows a schematic partial cross-sectional view of a semiconductor device according to another embodiment of the present invention;

fig. 12 shows a schematic partial cross-sectional view of a semiconductor device according to another embodiment of the present invention;

fig. 13 shows a schematic partial cross-sectional view of a semiconductor device according to another embodiment of the present invention;

fig. 14 shows a schematic partial cross-sectional view of a semiconductor device according to yet another embodiment of the present invention.

Detailed Description

Specific embodiments of the invention will be described in detail below, it being noted that the embodiments described herein are for illustration only and are not intended to limit the invention. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be apparent to one of ordinary skill in the art that: no such specific details are necessary to practice the invention. In other instances, well-known circuits, materials, or methods have not been described in detail in order not to obscure the invention.

Throughout the specification and claims, "coupled" as used herein is defined as directly or indirectly connected in an electrical or non-electrical manner. When an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or one or more intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present. "a/an" is not intended to mean that the "one/the" is "but may be" plural, "and in the context of the present disclosure, when a layer/element is referred to as being" in "another layer/element, it includes when a layer/element is referred to as being" in "and" on "another layer/element, and the layer/element may be directly on/in the other layer/element, or intervening layers/elements may be present therebetween. The phrase "in one embodiment" as used herein does not necessarily refer to the same embodiment, although it may. The term "and/or" as disclosed in one or more embodiments of the present disclosure includes any and all combinations of one or more of the associated listed items, unless the context clearly indicates otherwise. The term "based on" is not exclusive and allows for being based on additional factors not described, unless the context clearly indicates otherwise. The term "circuit" means at least one component or a plurality of active and/or passive components coupled together to provide a desired function. The term "signal" may be at least one current, voltage, charge, temperature, data, or other signal. It should be understood by those skilled in the art that the meaning of the terms identified above is not necessarily limited to these terms, but merely provides illustrative examples of these terms.

As used herein, "comprising," "including," "having," and any variations thereof are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements is not necessarily limited to those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.

In the description and claims of the present disclosure, words such as "left, right, inner, outer, upper, lower" and the like are used merely for convenience of description and do not denote a necessary or permanent relative position of components/structures. Those skilled in the art will appreciate that such terms are interchangeable where appropriate, e.g., embodiments of the disclosure may still function in locations other than those depicted in the present specification.

For ease of description, the present disclosure is illustrated with an N-channel vertical device fabricated on a silicon carbide (SiC) substrate, but those skilled in the art will appreciate that the structures and principles disclosed herein are also applicable to P-channel vertical devices, as well as other types of semiconductor materials and devices, and the conductivity type of the various regions shown herein may be adjusted depending on the type of device desired. In embodiments of the present disclosure, the material filling the gate trench is preferably polysilicon, and conductors and other types of materials (e.g., combinations of metals, other semiconductors, semi-metals, and/or related materials) compatible with the device fabrication process may also be used. Thus, the terms "poly fill" and "poly fill" include filling other materials and combinations of materials in addition to polysilicon.

Fig. 1 illustrates a partial cross-sectional schematic view of a semiconductor device (e.g., vertical transistor 100) in accordance with an embodiment of the present invention. The cross-sectional view shown in fig. 1 may be illustrated using a three-dimensional coordinate system having x, y and z axes that are perpendicular to each other. It should be appreciated that the cross-section of the present disclosure may be a cross-section of the semiconductor device 100 obtained by cutting along a plane parallel to an x-y plane defined by the x-axis and the y-axis. In this disclosure, transverse may refer to a direction parallel to the x-axis and perpendicular may refer to a direction parallel to the y-axis. The semiconductor device 100 may be formed in/on a substrate having a first conductivity type (e.g., N-type) that includes a semiconductor layer 101. The semiconductor layer 101 may include one or more semiconductor materials, such as Si, ge, siC, siGe, gaN, gaAs or other suitable semiconductor materials. In one example, the semiconductor layer 101 is doped at least at a partial region near/near the first surface of the semiconductor layer 101 (e.g., the bottom surface of the semiconductor layer 101 shown in fig. 1) to have a first doping concentration (e.g., may also be referred to as a drain region doping concentration), thereby forming a drain region of the semiconductor device 100. The drain region may be referred to by those skilled in the art as a "highly doped region" or "heavily doped region" (e.g., with N in fig. 1) ⁺ Layer schematic). In one embodiment, the first doping concentration may range from 1e18 to 1e20 particles/cubeCm. In one example, a relatively thick epitaxial layer 102 having the first conductivity type (e.g., N-type) may be further formed on the semiconductor layer 101. In one embodiment, the epitaxial layer 102 may comprise one or more semiconductor materials, such as Si, ge, siC, siGe, gaN, gaAs or other suitable semiconductor materials. In an embodiment, the semiconductor material forming epitaxial layer 102 may be the same as the semiconductor material forming semiconductor layer 101. In one embodiment, the epitaxial layer 102 may be doped with a dopant having the first conductivity type to have a second doping concentration (as may also be referred to as an epitaxial doping concentration). The second doping concentration may be lower than the first doping concentration. For example, in FIG. 1, the reference number is represented by N ^- Epitaxial layer 102 is shown as a layer. For example, in one embodiment, the second doping concentration may range from 1e14 to 1e18 particles per cubic centimeter. In another embodiment, the second doping concentration may range from 1e14 to 1e16 particles per cubic centimeter. In an embodiment, the substrate of the semiconductor device 100 may include the semiconductor layer 101 and the epitaxial layer 102. However, it will be appreciated by those skilled in the art that the substrate structure of the semiconductor device 100 is not limited thereto, and in another embodiment, the substrate of the semiconductor device 100 may not include the epitaxial layer 102. In another embodiment, the substrate of semiconductor device 100 may include any selection or combination of non-epitaxial or epitaxial semiconductor layers having one or more layers of one or more semiconductor materials, including Si, ge, siC, siGe, gaN, gaAs or other suitable semiconductor materials. The drain region may be fabricated in at least a portion of the substrate of the semiconductor device 100 adjacent to/near the first surface of the substrate.

According to one embodiment of the present invention, the semiconductor device 100 may include a plurality of vertical transistor cells. The term "plurality" herein means one or more. In the example shown in fig. 1, a vertical chain line schematically indicates the approximate boundary of each vertical-type transistor cell. In each vertical transistor cell, a first source region (e.g., which may be a MOSFET source region) 103 may be formed in the substrate and disposed adjacent to a second surface of the substrate opposite the first surface of the substrateIs defined in the region of the base plate. In the example of fig. 1, the first source region 103 is formed in a partial region of the epitaxial layer 102 that is close to the top surface S1 of the epitaxial layer 102 (e.g., a broken line portion in the partial cross-sectional schematic view shown in fig. 1). The first source region 103 may be of a first conductivity type (e.g., N-type) and have a third doping concentration (e.g., may also be referred to as a first source region doping concentration) such that the first source region 103 may be used as a source region for the semiconductor device 100 and, therefore, may be referred to by those skilled in the art as a "highly doped region" or "heavily doped region" (e.g., N in fig. 1) ⁺ The region is indicated). In an embodiment, the third doping concentration may be higher than the second doping concentration. In an embodiment, the third doping concentration may be the same order of magnitude as the first doping concentration or the same as the first doping concentration. In an embodiment, the third doping concentration range may be 1e19 to 5e20 particles per cubic centimeter.

According to one embodiment of the invention, a first sidewall body region 105 of a second conductivity type (e.g., P-type) may be disposed under the first source region 103 of each vertical-type transistor cell in the epitaxial layer 102. The second conductivity type may be opposite to the first conductivity type. In the example of fig. 1, the first sidewall body region 105 is shown as a P region and may have a fourth doping concentration (as may also be referred to as a first body region doping concentration). In one embodiment, the fourth doping concentration may be in a concentration range of 5e16 to 1e18 particles per cubic centimeter.

In accordance with one embodiment of the present invention, in each vertical-type transistor cell, a body contact region 106 of a second conductivity type (e.g., P-type) may be further fabricated in the substrate, and the body contact region 106 of each transistor cell may be formed adjacent to and on a first side of the first source region 103 thereof. The body contact region 106 may be disposed adjacent/near the second surface of the substrate and in a region laterally adjacent to the first source region 103. In the example of fig. 1, a body contact region 106 in each vertical transistor cell is illustrated as being formed in the epitaxial layer 102 and adjacent to and on the first side of the first source region 103 in each vertical transistor cell. In the example of fig. 1, body contact region 106 is shown as a p+ region, formed to the right of first source region 103, and may have a fifth doping concentration (as may also be referred to as a body contact region doping concentration). The fifth doping concentration may be higher than the fourth doping concentration. In one embodiment, for example, the fifth doping concentration may range from 5e18 to 1e20 particles per cubic centimeter. According to an embodiment of the present invention, the body contact region 106 in each transistor cell may be in contact with its first source region 103 and its first sidewall body region 105 to be electrically connected to the first source region 103 and the first sidewall body region 105.

In accordance with one embodiment of the present invention, lightly doped regions 104 of the second conductivity type (e.g., P-type) may be formed under the first source regions 103 of each vertical-type transistor cell when the first sidewall body regions 105 are not in contact with the body contact regions 106. At this time, the first sidewall body region 105 may be formed in the lightly doped region 104, and the lightly doped region 104 may extend laterally beyond the first sidewall body region 105 to be in contact with the body contact region 106, so that the first sidewall body region 105 may be electrically connected to the body contact region 106 through the lightly doped region 104. In the example of fig. 1, lightly doped region 104 is shown as a P-region and may have a sixth doping concentration (as may also be referred to as a lightly doped region doping concentration). The sixth doping concentration may be lower than the fourth doping concentration. In an embodiment, the concentration of the sixth doping concentration may range from 5e16 to 1e18 particles per cubic centimeter.

In each vertical-type transistor cell, the gate region 107 located in the gate trench 1071 may be formed in the substrate and located in a partial region adjacent to/near the second side of the first source region 103 in its epitaxial layer 102, in accordance with one embodiment of the present invention. In each vertical-type transistor cell, the second side of its first source region 103 is opposite to the first side of its first source region 103. In the example of fig. 1, the gate region 107 is located to the left of the first source region 103 of each vertical-type transistor cell. The gate trenches 1071 may be notched (e.g., by etching) starting at the second surface of the substrate (e.g., from the top surface S1 of the epitaxial layer 102 as shown in fig. 1) and extending vertically into the substrate (e.g., the epitaxial layer 102 as shown in fig. 1) to obtain a predetermined gate trench depth d1 and gate trench width w1. In one embodiment, the predetermined gate groove depth d1 may range from 1.0 μm to 3.0 μm. In one embodiment, the predetermined gate groove width w1 may range from 0.25 μm to 2.0 μm.

In the example of fig. 1, in each vertical-type transistor cell, after forming a gate insulating layer 1072 (e.g., a gate oxide layer) on the sidewalls and bottom of the gate trench 1071 of each vertical-type transistor cell, a gate conductive material 1073 (e.g., heavily doped polysilicon) may be filled therewith. In one embodiment, the gate insulating layer 1072 may have a predetermined gate insulating layer thickness T1. In an embodiment, the predetermined gate insulation layer thickness T1 may range from 20nm to 100nm. In an embodiment, referring to the example in fig. 1, the gate conductive material 1073 in each gate trench 1071 may also be surrounded or covered by a gate cap layer 1074 formed of an insulating material (e.g., silicon dioxide). In each gate trench 1071, the gate cap 1074 may be placed on top of the gate conductive material 1073 and meet/bond with the gate insulating layer 1072 such that the gate cap 1074 forms a continuous "insulating cage" with the gate insulating layer 1072 to enclose the gate conductive material 1073. In one embodiment, the gate cap 1074 may have a predetermined cap thickness T2. In one embodiment, the predetermined thickness T2 of the capping layer may range from 50nm to 500nm.

According to one embodiment of the present invention, the semiconductor device 100 may have a MOSFET short channel (shown as a dashed box region in fig. 1). In each vertical-type transistor cell, the short channel may be formed in the first sidewall body region 105, allowing current to flow between the drain region 101 and the first source region 103 when a suitable voltage is applied to the drain region 101, the first source region 103, and the gate region 107, thereby turning on the semiconductor device 100 (i.e., operating the semiconductor device 100 in an on or conducting state). For example, in one embodiment, the short channel of the MOSFET may have a channel width of 0.1 μm to 0.8 μm. In another embodiment, the short channel of the MOSFET may have a channel width of 0.2 μm to 0.45 μm. In yet another embodiment, the short channel of the MOSFET may have a channel width of 0.25 μm to 0.3 μm.

In each vertical transistor cell in epitaxial layer 102, its second source region 108 is formed below its first sidewall body region 105, according to one embodiment of the present invention. The second source region 108 is of the first conductivity type (e.g., N-type) and may have a seventh doping concentration (e.g., may also be referred to as a second source region doping concentration) such that the second source region 108 may be used as one source region for a junction field effect transistor (Junction Field Electronic Transistor, JFET) integrated in each vertical transistor cell, which second source region 108 may be referred to by those skilled in the art as a "highly doped region" or "heavily doped region" (e.g., illustrated by another n+ region in fig. 1). In one embodiment, the second source region 108 may be used as a source region for a JFET. In an embodiment, the seventh doping concentration may be higher than the second doping concentration of the epitaxial layer 102. In an embodiment, the seventh doping concentration (e.g., the second source region doping concentration) may be on the same order of magnitude or equal to the first doping concentration (e.g., the drain region doping concentration) or the third doping concentration (e.g., the first source region doping concentration). In an embodiment, the seventh doping concentration range may be 1e16 to 1e18 particles per cubic centimeter. It will be appreciated by those skilled in the art that the semiconductor device 100 according to an embodiment of the present invention may include: a MOSFET having a plurality of vertical MOSFET cells and a JFET having a plurality of JFET cells. In each vertical transistor cell of the plurality of vertical transistors, the MOSFET cells and the JFET cells are in one-to-one correspondence.

In each vertical transistor cell of a substrate (e.g., epitaxial layer 102 shown in fig. 1), a second sidewall BODY region (BODY) 109 of a second conductivity type (e.g., P-type) may be selectively positioned under second source region 108, in accordance with one embodiment of the present invention. In the example of fig. 1, in each vertical transistor cell, the second sidewall body region 109 is shown as another P region than the first sidewall body region 105, and may have an eighth doping concentration (as may also be referred to as a second body region doping concentration). In an embodiment, the eighth doping concentration (e.g., the second body region doping concentration) of the second sidewall body region 109 may be lower than the fifth doping concentration (e.g., the body contact region doping concentration) of the body contact region 106. In an embodiment, the eighth doping concentration may be on the same order of magnitude or equal to the fourth doping concentration (e.g., the first body region doping concentration). In an embodiment, the eighth doping concentration of the second body region 109 (e.g., second body region doping concentration) may be lower than the seventh doping concentration of the second source region 108 (e.g., second source region doping concentration). However, it will be appreciated by those of ordinary skill in the art that the eighth doping concentration (e.g., second body region doping concentration) of the second sidewall body region 109 may be different from the fourth doping concentration (e.g., first body region doping concentration). In an embodiment, for example, the eighth doping concentration may range in concentration from 2e16 to 1e18 particles/cc.

In each vertical transistor cell, the first source region 103, the first lightly doped region 104 (if any), the first sidewall body region 105, the second source region 108, and the second sidewall body region 109 (if any) thereof may be disposed on a first sidewall (e.g., a right sidewall as shown in fig. 1) of the gate region 107 and may be in contact with the first sidewall of the gate region 107 while being vertically disposed along the first sidewall (e.g., the right sidewall as shown in fig. 1) of the gate region 107. In one embodiment, in each vertical transistor cell, its second sidewall body 109 (if any) may extend vertically downward from the bottom surface of its second source region 108 along the first sidewall (e.g., the right sidewall as shown in fig. 1) of its gate region 107 to wrap around the first bottom corner (e.g., the right bottom corner as shown in fig. 1) of its gate trench 1071.

According to one embodiment of the invention, a connection region (LINK) 110 having a second conductivity type (e.g., P-type) may be disposed on a first side (e.g., right side as shown in fig. 1) of the first source region 103 in each vertical-type transistor cell of the substrate (e.g., epitaxial layer 102 as shown in fig. 1). In other words, in each vertical transistor cell, the connection region 110 and the gate region 107 may be disposed at a first side and a second side of the first source region 103 opposite to each other, respectively. In each vertical-type transistor cell, a partial region of the connection region 110 may extend vertically downward into a substrate deeper than the second source region 103 (e.g., epitaxial layer 102 shown in fig. 1), in accordance with an embodiment of the present invention. In each vertical transistor cell of a substrate (e.g., epitaxial layer 102 shown in fig. 1), a majority of the area of connection region 110 may be deeper than the bottom surface of body contact region 105, in accordance with embodiments of the present invention. In each vertical transistor cell in a substrate (e.g., epitaxial layer 102 shown in fig. 1), a partial region of its connection region 110 may be disposed below body contact region 106, in accordance with embodiments of the present invention. In the embodiment shown in fig. 1, in each vertical transistor cell, the connection region 110 may be separated from the first source region 103, the first lightly doped region 104 (if any), the first sidewall body region 105, the second source region 108, and the second sidewall body region 109 (if any) by at least a portion of the substrate (e.g., a portion of the epitaxial layer 102 shown in fig. 1). It will be appreciated by those skilled in the art that embodiments of the present invention are not limited thereto, and that numerous variations derived from the structure of the semiconductor device 100 shown in fig. 1 are apparent and fall within the spirit and scope of the present disclosure. For example, as shown in the embodiment of fig. 11, in each vertical transistor cell, the connection region 110 may be separated from the first lightly doped region 104 (if any), the first sidewall body region 105, and the second sidewall body region 109 (if any) by at least a portion of the substrate (e.g., a portion of the epitaxial layer 102), while the second source region 108 may not be separated from the connection region 110. In another embodiment as provided in fig. 12, in each vertical transistor cell, the connection region 110 may be separated from the second source region 108 and the second sidewall body region 109 (if any) by at least a portion of the substrate (e.g., a portion of the epitaxial layer 102), while the first lightly doped region 104 (if any) and the first sidewall body region 105 may not be separated from the connection region 110. In another embodiment as provided in fig. 13, in each vertical transistor cell, the connection region 110 and the second sidewall body region 109 (if any) may be separated by at least a portion of the substrate (e.g., a portion of the epitaxial layer 102), while the first lightly doped region 104 (if any), the first sidewall body region 105, and the second source region 108 may not be separated from the connection region 110. In one embodiment, in each vertical transistor cell, its connection region 110 may be in contact with its body contact region 106. In the embodiment shown in fig. 1, in each vertical transistor cell, the top of its connection region 110 may be in contact with its body contact region 106. In the embodiment shown in fig. 11-13, in each vertical transistor cell, its connection region 110 may be in contact with its body contact region 106 on a side of the body contact region 106 (e.g., the right side of the body contact region 106 shown in fig. 11-13). In the embodiment shown in fig. 14, the body contact region 106 may not be formed, and thus its connection region 110 may be in physical contact with its first source region 103 and may be in electrical contact with that first source region 103. In one embodiment, in each vertical transistor cell, the connection region 110 may be disposed on a second side (e.g., left side as shown in fig. 1) of the gate region 107 of an adjacent vertical transistor cell. In one embodiment, in each vertical transistor cell, the connection region 110 may extend vertically downward from the bottom surface of the body contact region 106 or from the second surface of the substrate thereof along the second sidewall (e.g., the left sidewall as shown in fig. 1) of the gate region 107 of the adjacent vertical transistor cell to wrap around the second bottom corner (e.g., the left bottom corner as shown in fig. 1) of the gate trench 1071 of the adjacent vertical transistor cell. The connection region 110 may be in physical contact with the body contact region 106 while being in physical contact with the second sidewall of the gate region 107 of an adjacent vertical transistor cell. In an embodiment, the first side and first sidewall of the single gate region 107 (or single gate trench 1071) may be opposite the second side and second sidewall of the single gate region 107 (or single gate trench 1071). In the example of fig. 1, in each vertical transistor cell, its connection region 110 is shown as another p+ region that is different from its body contact region 106 and may have a ninth doping concentration (as may also be referred to as connection region doping concentration). In an embodiment, the ninth doping concentration (e.g., the connection region doping concentration of the connection region 110) may be higher than the first body region doping concentration (of the first sidewall body region 105) or the second body region doping concentration (of the second sidewall body region 109). In an embodiment, the ninth doping concentration may be on the same order of magnitude or the same as the fifth doping concentration (e.g., the body contact region doping concentration of the body contact region 106). However, it will be appreciated by those of ordinary skill in the art that the ninth doping concentration of the connection region 110 may be different from the fifth doping concentration (e.g., the body contact region doping concentration). In an embodiment, the ninth doping concentration of the connection region 110 (i.e., the connection region doping concentration) may be higher than the seventh doping concentration of the second source region 108 (i.e., the second source region doping concentration). In an embodiment, for example, the concentration of the ninth doping concentration may range from 1e18 to 5e19 particles per cubic centimeter.

Those skilled in the art will appreciate that when the vertical transistor 100 is turned off (i.e., in an off state or an off state), its connection region 110 helps to deplete a portion of the substrate (e.g., a portion of the epitaxial layer 102 shown in fig. 1) that separates the connection region 110 from its second sidewall body region 109 (if any). That is, the connection region 110 helps to deplete at least a portion of the region of the first conductivity type (e.g., N-type as shown in fig. 1) located between the gate region 107 and the connection region 110 and below the second source region 108. For ease of understanding, in the following description, in each vertical-type transistor cell, a "portion of the connection region 110 spaced apart from the second sidewall body region 109 (if any)" or a "portion of the region having the first conductivity type located between the gate region 107 and the connection region 110 and below the second source region 108" is referred to as a "JFET channel region". Once the drain-source voltage (i.e., the voltage difference applied between the drain region 101 and the first source region 103) VDS applied to the semiconductor device 100 increases, the JFET channel region is depleted and the JFET pinches off. That is, when the JFET pinches off, the source voltage of the JFET at its second source region 108 reaches the pinch-off threshold voltage Vp of the JFET. After the JFET is pinched off, even if the drain-source voltage VDS continues to rise, the JFET source voltage of the second source region 108 is no longer increased, and pinching off of the JFET can prevent the gate insulating layer 1072 (e.g., gate oxide layer) from being subjected to higher electric field stress and reduce the number of holes injected into the gate insulating layer 1072, thereby protecting the gate insulating layer 1072 from premature rupture and improving the breakdown voltage and high voltage resistance of the semiconductor device 100. In embodiments where both the second sidewall body region 109 and the connection region 110 are formed, both the second sidewall body region 109 and the connection region 110 help to deplete the channel region of the JFET (i.e., the portion of the epitaxial layer 102 located between the second sidewall body region 109 and the connection region 110) from both sides of the JFET channel region, and thus effectively reduce the pinch-off voltage Vp of the JFET while further preventing holes from being injected into the gate insulation layer 1072, thereby further improving the breakdown voltage and high voltage performance of the semiconductor device 100.

In each vertical transistor cell, a JFET channel implant region 111 of a first conductivity type (e.g., N-type) may be selectively formed in the JFET channel region adjacent or contiguous with the connection region 110, in accordance with one embodiment of the present invention. In the example of fig. 1, in each vertical transistor cell, its JFET channel implant region 111 is formed in the JFET channel region along and conformal with its connection region 110. In one embodiment, its JFET channel implant region 111 may be in contact with its body contact region 106 and adjacent to its connection region 110. In one embodiment, in each vertical transistor cell, the JFET channel implant region 111 and, if present, the second sidewall body region 109 may still be separated by at least a portion of the substrate (e.g., a portion of the epitaxial layer 102 shown in fig. 1). In one embodiment, in each vertical transistor cell, the connection region 110 and the second sidewall body region 109 (if any) may be separated by at least a JFET channel implant region 111. In one embodiment, in each vertical transistor cell, its JFET channel implant region 111 and its first lightly doped region 104 (if present), first sidewall body region 105, and second sidewall body region 109 (if present) may be separated by at least a portion of the substrate (e.g., epitaxial layer 102 shown in fig. 1). It will be appreciated by those skilled in the art that, taking as an example the JFET channel implant region 111 formed in each vertical transistor cell, "the portion of the first conductivity type located between the gate region 107 and the connection region 110 and below the second source region 108" or "JFET channel region" may include the portion of the substrate and JFET channel implant region located between the gate region 107 and the connection region 110 and below the second source region 108. The JFET channel implant region 111 may have a tenth doping concentration (e.g., JFET channel implant concentration). In an embodiment, the tenth doping concentration of the JFET channel implant region 111 (e.g., JFET channel implant concentration) may be higher than the epitaxial doping concentration of the epitaxial layer 102 and may be lower than the first source region doping concentration of the first source region 103. For example, in one embodiment, the tenth doping concentration may be in a concentration range of 5e16 to 5e17 particles/cc. The presence of the JFET channel implant region 111 facilitates simple and effective control of the threshold voltage Vp of the JFET compared to a JFET without the JFET channel implant region 111. It will be appreciated by those skilled in the art that if the JFET channel implant region 111 were not present, the pinch-off threshold voltage Vp of the JFET may be highly dependent on the pinch-off width L1 of each vertical transistor cell. Among the plurality of vertical type transistor cells, the pinch-off width L1 of a single vertical type transistor cell may refer to a lateral distance between the center lines of the gate trenches 1071 of every two adjacent vertical type transistor cells.

In accordance with one embodiment of the present invention, a protection region 112 having a second conductive type (e.g., P-type) may be selectively formed under each gate region 107 and may contact the bottom of each gate region 107. As shown in fig. 1, the guard region 112 (shown as a P region) may be disposed under the gate trench 1071 of each gate region 107. In one embodiment, the guard region 112 may be in physical contact with the second sidewall body regions 109 (if any) disposed on a first side (e.g., right side as shown in fig. 1) of each gate region 107/gate trench 1071 and/or the connection regions 110 disposed on a second side (e.g., left side as shown in fig. 1) of each gate region 107/gate trench 1071. When a higher drain-source voltage VDS is applied, the protection region 112 may protect the gate insulating layer 1072, and further improve the breakdown voltage and high voltage resistance of the semiconductor device 100 while avoiding the gate insulating layer 1072 from being subjected to a high electric field. The guard region 112 may have an eleventh doping concentration (e.g., guard region doping concentration). The eleventh doping concentration may be higher than the first body region doping concentration or the second body region doping concentration. In an embodiment, the eleventh doping concentration may be on the same order of magnitude as the fifth doping concentration (e.g., the body contact doping concentration).

Fig. 2A shows a partial cross-sectional simulation of the resistance distribution between the MOSFET channel and the JFET when the semiconductor device 100 is in an on or conducting state. In this example, simulations may be performed using the following exemplary parameters: pinch-off width l1=2.5μm, gate groove width w1=1.2μm, gate insulating layer thickness t1=65 nm, gate source voltage vg=15v, drain-source voltage vds=1v applied across semiconductor device 100. Simulation results show that the JFET can have a geometry of about 1mΩ×cm ² Characteristic on-resistance R of (2) _J *A _J While the MOSFET may have about 0.5mΩ cm ² Characteristic on-resistance R of (2) _M *A _M Thus, in this embodiment, the semiconductor device 100 may have a thickness of less than 2mΩ×cm ² Is used for the total on-resistance of the capacitor. It will be appreciated by those skilled in the art that embodiments of the present invention are not limited thereto. Characteristic on-resistance R of JFET _J *A _J Characteristic on-resistance R of MOSFET _M *A _M Total characteristic on-resistance R of semiconductor device 100 _on * A can be as wide as pinch-offThe values of parameters such as L1, the gate groove width w1, the gate insulating layer thickness T1, the gate-source voltage VG, and the drain-source voltage VDS are changed. For example, in another embodiment, the JFET can have a bulk density of about 0.1mΩ cm ² To 1mΩ cm ² Characteristic on-resistance R of (2) _J *A _J While the MOSFET may have about 0.3mΩ cm ² To 1.2mΩ cm ² Characteristic on-resistance R of (2) _M *A _M Thus, in this example, the semiconductor device 100 may have a thickness of less than 2.2mΩ cm ² Is the total characteristic on-resistance R of _on * A. In one embodiment, the semiconductor device 100 according to the embodiment of the invention may have a breakdown voltage of 750V rating of 1.5mΩ×cm ² To 1.8mΩ cm ² Is the total characteristic on-resistance R of _on * A. For example, fig. 2B shows a graph of a characteristic on-resistance versus distance from a second surface of a substrate (e.g., top surface S1 of epitaxial layer 102 shown in fig. 1) for semiconductor device 100 in an on or on state, where the given rated breakdown voltage is 750V. Referring to the graph of FIG. 2B, the characteristic on-resistance R of the JFET under test is readily obtained _J *A _J Characteristic on-resistance R of MOSFET _M *A _M Total characteristic on-resistance R of semiconductor device 100 _on * Distribution change relation of A.

Fig. 3A shows a partial cross-sectional simulation of the equipotential line distribution for the semiconductor device 100 in the on or off state, using the same simulation parameters as the exemplary parameters of fig. 2A described above.

Fig. 3B shows an electrical characteristic simulation curve 301 of the relationship between the drain-source current IDS flowing from the drain region 101 to the source region 103 and the gate-source voltage VG of the semiconductor device 100 in the on or off state, and the simulation parameters used are the same as the exemplary parameters of fig. 2 described above, except that the gate-source voltage VG is different. As can be seen from fig. 3B, in this example, the semiconductor device 100 may be turned on when the gate-source voltage VG reaches the turn-on threshold voltage Vth of about 6.4V.

Fig. 4A shows a partial cross-sectional simulation of the equipotential lines and the depletion region boundary for the semiconductor device 100 in the off or off state. Fig. 4A shows that the second source region 108 is not depleted in the off state during the continuous increase of the drain-source voltage VDS, and thus the gate insulating layer 1072 of the semiconductor device 100 may be protected from being damaged in a high electric field.

Fig. 4B shows a JFET source voltage versus drain-source voltage VDS curve 401 at the second source region 108 and a drain-source current IDS versus drain-source voltage VDS curve 402 for the semiconductor device 100 when the semiconductor device 100 is in an off or off state. In this example, simulations may be performed using the following exemplary parameters: pinch-off width l1=2.5μm, gate groove width w1=1.2μm, gate insulating layer thickness t1=65 nm; the drain-source voltage VDS applied to the semiconductor device 100 at the same time ranges from 0V to higher than 850V, and maintains the gate-source voltage VG < Vth. As can be seen from fig. 4B, as the drain-source voltage VDS continues to increase, the source voltage of the JFET of this example stops increasing after increasing to a maximum value of about 10V to 12V, which means that the JFET source voltage reaches the pinch-off threshold voltage Vp, i.e., the JFET is pinched off. Pinch-off of the JFET can prevent the gate insulating layer 1072 from withstanding a high electric field and improve breakdown voltage and high voltage resistance of the semiconductor device 100. As can be seen from curve 402, in this example, semiconductor device 100 breaks down when drain-source voltage VDS exceeds about 830V.

Fig. 5A-5T are schematic partial cross-sectional views illustrating a portion of a fabrication process in a method of a semiconductor device (e.g., semiconductor device 100 of fig. 1) according to an embodiment of the invention. The cross-sectional views shown in fig. 5A-5T may be illustrated using a three-dimensional coordinate system having mutually perpendicular x, y and z axes. It should be understood that the cross-sectional view shown is taken from a section parallel to the x-y plane formed by the x-axis and the y-axis. It should be appreciated that each cross-sectional view may be an exemplary cross-sectional image showing a portion of a single vertical-type transistor cell of the plurality of vertical-type transistor cells of semiconductor device 100 formed at a particular stage of the process. It will be appreciated by those skilled in the art that the semiconductor device 100 may include a plurality (i.e., one or more) of vertical-type transistor cells, each of which may be identical to a single vertical-type transistor cell illustrated herein. In one embodiment, each of a plurality of (i.e., one or more) vertical transistor cells of the semiconductor device 100 may have a preset cell pinch-off width L1. Although only a limited portion of a single vertical transistor cell of semiconductor device 100 is shown, it should be understood that the following steps are performed based on the entirety of a substrate (e.g., which may include semiconductor layer 101 and epitaxial layer 102 shown in fig. 1) to form a plurality of vertical transistor cells of semiconductor device 100.

As shown in fig. 5A, a substrate having a first conductivity type may be formed, which may include a drain region (e.g., an n+ layer shown in fig. 1 and 5A) doped at a partial region of a first surface (e.g., a bottom surface) of the substrate. In an embodiment, the substrate may include an epitaxial layer 102 having a first conductivity type (e.g., N-type) formed on a semiconductor layer (e.g., semiconductor layer 101 shown in fig. 1). In one example, the semiconductor layer 101 may be doped at adjacent partial regions of its first surface (e.g., the bottom surface of the semiconductor layer 101 shown in fig. 1) to have a first doping concentration (e.g., a drain region doping concentration) to form a drain region of the semiconductor device 100. The semiconductor material of the epitaxial layer 102 may be the same as the semiconductor layer 101, and a dopant of the first conductivity type may be doped in the epitaxial layer 102 to have a second doping concentration (e.g., epitaxial doping concentration). The second doping concentration may be lower than the first doping concentration (e.g., the doping concentration of the N-layer shown by fig. 1 and 5A). For example, in one embodiment, the concentration of the second doping concentration may range from 1e14 to 1e18 particles per cubic centimeter.

Subsequently, as shown in fig. 5B, under the protection of the patterned first implantation mask 501, a first source region (e.g., MOSFET source region 103), a lightly doped region (e.g., lightly doped region 104), and a second source region (e.g., JFET source region 108) may be formed in the substrate (e.g., epitaxial layer 102) by implanting each vertical transistor cell of the semiconductor device 100. A patterned first implantation mask 501 may be formed on the second surface of the substrate (e.g., the top surface S1 of the epitaxial layer 102 shown in fig. 5B) and patterned to expose predetermined regions on the second surface of the substrate (e.g., the top surface S1 of the epitaxial layer 102) that may be used to implant dopants to form the second source region 108, the lightly doped region 104, and the first source region 103 of each vertical transistor cell of the semiconductor device 100. After the implantation steps to form the second source regions 108, the lightly doped regions 104 and the first source regions 103 are completed, the patterned first implantation mask 501 may be removed. In each vertical-type transistor cell, a first source region 103 may be formed in an adjacent partial region of a second surface (e.g., a top surface) of the substrate opposite the first surface of the substrate, and the second source region 108 may be formed below the first source region 103 and spaced apart from the first source region 103. In each vertical-type transistor cell, lightly doped region 104 may be formed directly under its first source region 103 to separate the first source region 103 from the second source region 108. In one embodiment, the formation of the lightly doped region 104 of the plurality of vertical transistor cells is optional, i.e., the lightly doped region 104 may not be present, and thus the step of implanting to form the lightly doped region 104 may be omitted. The conductivity type (or doping type) and doping concentration of the second source region 108, the lightly doped region 104 (if any), and the first source region 103 are already described in detail in the example of fig. 1, and will not be described here again.

As shown in fig. 5C, a body contact region (e.g., body contact region 106) may be formed in the substrate (e.g., epitaxial layer 102) by implanting each vertical transistor cell of semiconductor device 100 under the protection of patterned second implantation mask 502. A second implantation mask 502 may be formed on a second surface of the substrate (e.g., the top surface S1 of the epitaxial layer 102 shown in fig. 5C) and patterned to expose predetermined regions on the second surface of the substrate (e.g., the top surface S1 of the epitaxial layer 102) that may be used to implant dopants to form the body contact regions 106 of each vertical transistor cell of the semiconductor device 100. In each vertical-type transistor cell, its body contact region 106 may be formed in a partial region adjacent to the second surface (e.g., top surface S1) of the substrate and adjacent to/near the first source region 103 on a first side (e.g., right side in the example of fig. 5C) of the first source region 103. After the step of implanting the body contact regions 106 forming the plurality of vertical transistor cells is completed, the patterned second implantation mask 502 may be removed. The conductivity type (or doping type) and doping concentration of the body contact region 106 are described in detail in the example of fig. 1, and will not be described here. In one embodiment, the body contact regions 106 of the plurality of vertical transistor cells may not be formed, and thus the step of preparing the body contact regions 106 as described in fig. 5C may be omitted.

As shown in fig. 5D, a gate trench 1071 for each vertical transistor cell of the semiconductor device 100 (e.g., gate region 107 shown in fig. 1) may be formed in a substrate (e.g., epitaxial layer 102 shown in fig. 5D) under the protection of the patterned trench formation mask 503. The trench forming mask 503 may be formed on a second surface of the substrate (e.g., the top surface S1 of the epitaxial layer 102 shown in fig. 5D) and patterned to expose a predetermined region on the second surface of the substrate (e.g., the top surface S1 of the epitaxial layer 102), which may be an opening of the gate trench 1071 of the gate region 107 of each vertical transistor cell of the semiconductor device 100. In the example of fig. 5D, gate trenches 1071 may be opened in the epitaxial layer 102 such that each gate trench 1071 is adjacent to a corresponding first source region 103 and on a second side (e.g., left side as shown in fig. 5D) of the corresponding first source region 103. Under the protection of the patterned trench formation mask 503, the trenches of each gate trench 1071 may be opened (e.g., by etching) from the second surface of the substrate (e.g., the top surface S1 of the epitaxial layer 102) and vertically extend into the epitaxial layer 102 by a predetermined depth d1 and width w 1. The location of the gate 107 or gate trench 1071 of the gate 107 of a plurality of vertical transistor cells may be better understood in conjunction with fig. 1. It will be appreciated by those skilled in the art that each two adjacent vertical transistor cells of the plurality of vertical transistor cells may share a gate region 107 (e.g., disposed in a single trench 1071). In the example of fig. 5D, a portion of a semiconductor device including a single vertical transistor cell of a plurality of vertical transistor cells is shown. The single vertical-type transistor cell shown in fig. 5D may share the gate trench 1071 of its gate region 107 with the vertical-type transistor cell adjacent to the left (half gate trench 1071 shown on the left) and may share the gate trench 1071 of its gate region 107 with the vertical-type transistor cell adjacent to the right (half gate trench 1071 shown on the right).

As shown in fig. 5E, the first sidewall body regions 105 may be formed in each vertical transistor cell of the semiconductor device 100 by an implantation process under the protection of the patterned trench formation mask 503. In an embodiment, dopants of a second conductivity type (e.g., P-type) may be implanted at a first predetermined angle α with respect to a second surface of the substrate (e.g., a top surface S1 of the epitaxial layer 102 shown in fig. 5E) and into the epitaxial layer 102 through a first side (e.g., a right side in the example of fig. 5E) of each gate trench 1071 such that the first sidewall body region 105 may be disposed under the MOSFET source region 103 of each vertical transistor cell in the epitaxial layer 102. For example, the first sidewall body region 105 may be disposed between the first source region 103 and the second source region 108. In an example of implanting dopants of the second conductivity type through the first sidewall of each trench 1071 to form the second sidewall body region 105, the concentration of the dopants of the second conductivity type may be lower than the second source region doping concentration of the second source region 108 and the first source region doping concentration of the first source region 103. In an embodiment, the first preset angle α may range from 45 ° to 85 °. The location and doping concentration of the first sidewall body region 105 of each vertical transistor cell of the semiconductor device 100 has been described in detail in the example of fig. 1 and will not be described here again. In another embodiment, the step of implanting the first sidewall body regions 105 of each vertical transistor cell of the semiconductor device 100 may be replaced by the step of forming the lightly doped regions 104 as described in fig. 5B, under the protection of the patterned first implantation mask 501. In this case, the step of implanting to form the first sidewall body region 105 as described in fig. 5E may be omitted.

According to one embodiment of the present invention, as shown in fig. 5E, a second sidewall body region 109 having a second conductivity type (e.g., P-type) may be selectively formed in each vertical type transistor cell of the semiconductor device 100. The second sidewall body region 109 may be implanted at the same time as the first sidewall body region 105 is implanted as described in fig. 5E, with the protection of the patterned trench formation mask 503. At this time, the second sidewall body region 109 may be disposed under the second source region 108 of each vertical transistor cell in the epitaxial layer 102. In each vertical transistor cell, the first source region 103, the lightly doped region 104 (if any), the first sidewall body region 105, the second source region 108, and the second sidewall body region 109 (if any) may be vertically distributed along the first sidewall (e.g., the right sidewall as shown in fig. 5E) of the gate trench 1071 of each gate region 107. It should be appreciated that for each of the plurality of gate trenches 1071/gates 107 of the plurality of vertical transistor cells, the second sidewall body region 109 (if present) thereof may extend vertically downward from the bottom surface of the second source region 108 thereof along the first sidewall (e.g., the right sidewall as shown in fig. 5E) of the single gate region 107 until it wraps around the first bottom corner (e.g., the right bottom corner as shown in fig. 5E) of the single gate trench 1071. The location and doping concentration of the second sidewall body 109 of each vertical transistor cell of the semiconductor device 100 has been described in detail in the example of fig. 1 and will not be described here again.

According to one embodiment of the present invention, as shown in fig. 5F, a connection region 110 having a second conductivity type (e.g., P-type) may be formed in each vertical type transistor cell of the semiconductor device 100 by an implantation process, also under the protection of the patterned trench formation mask 503. In an embodiment, the dopant of the second conductivity type (e.g., P-type) may be implanted at a second predetermined angle β with respect to the second surface of the substrate (e.g., the top surface S1 of the epitaxial layer 102 shown in fig. 5F) and into the epitaxial layer 102 through the second sidewall of each gate trench 1071 (e.g., the left sidewall of the gate trench shown in fig. 5F), thereby forming the connection region 110 under the body contact region 106 of the vertical transistor cell in each epitaxial layer 102. In the single vertical transistor cell shown in fig. 5F, it is to be appreciated or understood that the connection region 110 of the single vertical transistor cell may be formed by implantation, which may be performed through a second sidewall (e.g., the left sidewall shown in fig. 5F) of the gate trench 1071 of the adjacent vertical transistor cell to the right side of the single vertical transistor cell and at a second predetermined angle β with respect to a second surface of the substrate (e.g., the top surface S1 of the epitaxial layer 102 shown in fig. 5F). It should be appreciated that in each vertical-type transistor cell, its connection region 110 may extend vertically downward from the second surface of its substrate or the bottom surface of its body contact region 106 along the second sidewall (e.g., the left sidewall as shown in fig. 5F) of the gate trench 107 of the adjacent vertical-type transistor cell to wrap around the second bottom corner (e.g., the left bottom corner as shown in fig. 5F) of the gate trench 1071 of the adjacent vertical-type transistor cell. Likewise, it should be appreciated that in each of the plurality of gate trenches 1071/gates 107 of the plurality of vertical transistor cells, the connection region 110 thereof may extend vertically down the second sidewall (e.g., the left sidewall as shown in fig. 5F) of the single gate 107 until wrapping around the first bottom corner (e.g., the left bottom corner as shown in fig. 5F) of the single gate trench 1071. In an embodiment, the second preset angle β may range from 45 ° to 85 °. The doping concentration of the connection region 110 is already described in detail in the example of fig. 1, and will not be described here again. The location of the connection regions 110 of a plurality of vertical transistor cells may be better understood in connection with the description of fig. 1.

According to one embodiment of the present invention, as shown in fig. 5G, a JFET channel implant region 111 having a first conductivity type (e.g., N-type) may be selectively formed in each vertical transistor cell of the semiconductor device 100. The JFET channel implant region 111 may be formed by implantation under the protection of the patterned trench formation mask 503. In an embodiment, the dopant having the first conductivity type (e.g., N-type) may be implanted at a third predetermined angle δ with respect to the second surface of the substrate (e.g., the top surface S1 of the epitaxial layer 102 shown in fig. 5G) and into the epitaxial layer 102 through the second sidewall (e.g., the left sidewall shown in fig. 5G) of each gate trench 1071, thereby forming a JFET channel implant region 111 at an adjacent region of the connection region 110 of each vertical transistor cell of the substrate (e.g., the epitaxial layer 102 shown in fig. 5G). In one embodiment, the third predetermined angle δ may range from 45 ° to 85 °. In the example of fig. 5G, in each vertical transistor cell, its JFET channel implant region 111 may be formed along the connection region 110 and conformal with the connection region 110. In one embodiment, the top of the JFET channel implant region 111 of each vertical transistor cell may be in contact with the body contact region 106 and may be laterally in contact with the connection region 110. The location and doping concentration of the JFET channel implant region 111 of each vertical transistor cell is described in detail in the example of fig. 1 and is not described here.

According to one embodiment of the present invention, as shown in fig. 5H, a protection region 112 having a second conductivity type (e.g., P-type) may be formed under each gate trench 1071 (or each gate region 107) by implantation under the protection of the patterned trench formation mask 503. In an embodiment, the dopants of the second conductivity type (e.g., P-type) may be vertically implanted into the epitaxial layer 102 through the opening of each gate trench 1071 under the protection of the trench forming mask 503. The location and doping concentration of the guard region 112 of each vertical transistor cell is described in detail in the example of fig. 1 and will not be described again here.

In accordance with one embodiment of the present invention, after the first sidewall body region 105, the second sidewall body region 109 (if any), the connection region 110, the JFET channel implant region 111 (if any), and the protection region 112 (if any) are implanted, the patterned trench formation mask 503 may be removed.

As shown in fig. 5I, an implant activation step may be performed to electrically activate dopant atoms of the first conductivity type and the second conductivity type implanted into the substrate (e.g., epitaxial layer 102) in the foregoing implant step. In one embodiment, the step of implant activation may include: after removal of the patterned trench formation mask 503, the remaining entire structure is annealed. Wherein the entire structure includes the semiconductor 101 and the gate recess 1071 openings of the epitaxial layer 102, as well as the implanted regions of dopants of the first conductivity type and the second conductivity type in the foregoing implantation steps.

According to one embodiment of the present invention, as shown in fig. 5J, a gate insulating layer 1072 may be formed to cover and overlie the sidewalls and bottom of each gate trench 1071 and the second surface of the substrate (e.g., the top surface S1 of the epitaxial layer 102 shown in fig. 5J). In an embodiment, when the substrate or epitaxial layer 102 is a semiconductor material capable of being oxidized (e.g., si, ge, siC, etc.), the gate insulating layer 1072 may be formed by thermal oxidation or deposition of an insulating material (e.g., TEOS (ethyl silicate) gate oxide, etc.), or a combination of both. In one embodiment, when the substrate or epitaxial layer 102 is a semiconductor material that cannot be oxidized (e.g., gaN, gaAs, etc.), the gate insulating layer 1072 may be formed by depositing an insulating material (e.g., TEOS gate oxide, etc.). In one embodiment, the gate insulating layer 1072 may be formed with a predetermined gate insulating layer thickness T1. In an embodiment, the predetermined gate insulation layer thickness T1 may range from 20nm to 100nm.

According to one embodiment of the invention, as shown in fig. 5K, a gate conductive material 1073 (e.g., heavily doped polysilicon) may be formed to fill each gate trench 1071 until an excessive thickness of gate conductive material 1073 (e.g., the thickness of gate conductive material 1073 shown in fig. 5K exceeds the top surface S1 of epitaxial layer 102) has accumulated on the second surface of the substrate (e.g., the top surface S1 of epitaxial layer 102 shown in fig. 5K). In one embodiment, the gate conductive material 1073 may be formed by deposition to fill the gate trenches 1071.

According to one embodiment of the invention, as shown in fig. 5L, the gate conductive material 1073 may be removed from the second surface of the substrate (e.g., the top surface S1 of the epitaxial layer 102 shown in fig. 5L) using a post-etch process until the gate insulating layer 1072 on the second surface of the substrate (e.g., the top surface S1 of the epitaxial layer 102) is exposed.

According to one embodiment of the present invention, as shown in fig. 5M, the uppermost region of the gate conductive material 1073 in each gate trench 1071 may be oxidized by an oxidation step to form a gate cap layer 1074. During oxidation of the gate conductive material 1073, portions of the substrate (e.g., the epitaxial layer 102) covered/protected by the gate insulating layer 1072 are not oxidized, for example, particularly when the substrate (e.g., the epitaxial layer 102) is formed of SiC or other similar semiconductor material. In an embodiment, in the oxidizing step, the thickness T3 of the gate cap layer 1074 may be greater than the predetermined thickness T1 of the gate insulating layer 1072.

According to one embodiment of the present invention, as shown in fig. 5N, the gate insulating layer 1072 on the top surface S1 of the epitaxial layer 102 may be removed by a post-etch treatment process to expose a portion of the second surface of the substrate (e.g., the top surface S1 of the epitaxial layer 102) that is not protected by the gate cap layer 1074. During this process, a portion of the surface of the gate cap 1074 may be removed simultaneously, resulting in a reduction in its thickness. That is, after processing, the pre-set gate cap layer thickness T2 of the remaining gate cap layer 1074 may be less than the thickness T3. In other words, during this process, the thickness of the gate cap 1074 is reduced from T3 to a preset gate cap thickness T2. In an embodiment, the thickness T3 should be greater than the sum of the preset gate insulation layer thickness T1 and the preset gate cap layer thickness T2 to ensure that the gate cap layer 1074 remaining after the post-etch treatment may have the preset gate cap layer thickness T2.

According to one embodiment of the present invention, as shown in fig. 5O, after the step shown in fig. 5N, a metal layer 507 may be deposited over the entire exposed top surface of the resulting structure for subsequent silicidation. In one embodiment, the metal layer 507 may comprise a nickel layer. In another embodiment, the metal layer 507 may include other materials that may react with the epitaxial layer 102.

According to one embodiment of the present invention, as shown in fig. 5P, a silicide layer 113 may be formed on a second surface of the substrate (e.g., the top surface S1 of the epitaxial layer 102 shown in fig. 5P) by a silicidation step. The silicide layer 113 may be formed by reacting the metal layer 507 with the semiconductor material of the substrate (e.g., the epitaxial layer 102) so that the silicide layer 113 may be self-aligned to the exposed semiconductor material of the substrate (e.g., the epitaxial layer 102) (i.e., the portion not covered by the gate cap 1074). That is, the silicide layer 113 may be self-aligned to a portion of the substrate (e.g., a portion of the epitaxial layer 102) that is not occupied by the gate regions 107 of the plurality of vertical transistor cells. After silicidation, the remaining non-silicided (i.e., the portions that do not react with epitaxial layer 102) metal layer 507 (e.g., the nickel layers on both sides of silicide layer 113 shown in fig. 5P) may be removed using a lift-off process.

According to one embodiment of the invention, as shown in fig. 5Q, after the step shown in fig. 5P, an interlayer dielectric layer (Interlayer Dielectric Layer, ILD) 114 may be obtained by depositing a dielectric material over the entire top surface of the resulting structure.

According to one embodiment of the present invention, as shown in fig. 5R, a source contact trench and a gate contact trench may be formed in the interlayer dielectric layer 114 of each vertical transistor cell by etching the interlayer dielectric layer 114. The source contact trench of each vertical transistor cell may extend from the top surface of the interlayer dielectric layer 114, through the interlayer dielectric layer 114, down to at least a portion of the silicide layer 113 above the first source region 103, the body contact region 106 (if present), and/or the connection region 110 (if the connection region extends vertically down from the second surface of the substrate) of each vertical transistor cell. The gate contact trench of each vertical transistor cell may extend from the interlayer dielectric layer 114, through the interlayer dielectric layer 114, and down to the gate conductive material 1073 of at least a portion of each vertical transistor cell.

According to one embodiment of the present invention, as shown in fig. 5S-5T, source metal contact 115 and gate metal contact 116 may be formed by a process such as metal deposition to fill the source contact trench and gate contact trench of each semiconductor device and to separate the source metal contact 115 and the gate metal contact 116 in a subsequent etching step. In the example of fig. 5S, metal deposition may be achieved by electroplating. A conductive seed layer 508 (e.g., ti or TiW) may be formed over all exposed surfaces of the resulting structure (e.g., including the sidewalls and bottom surfaces of the exposed source and gate contact trenches and the top surface of the interlayer dielectric layer 114) after the step shown in fig. 5R. In a subsequent step, a metal layer 509 (e.g., al or Cu) may be formed by electroplating over the conductive seed layer 508 to fill the source contact trench and the gate contact trench while leaving the cumulative metal layer 509 thickness over the top surface of the interlayer dielectric layer 114. In the example of fig. 5T, the metal layer (e.g., including the metal layer 509 and the conductive seed layer 508) formed in the metal deposition step of fig. 5S may be etched using an etching step, thereby dividing the deposited metal layer into the source metal contact 115 and the gate metal contact 116 of each vertical transistor cell of the semiconductor device 100. A plurality of vertical transistor cells are exemplarily shown in the cross-sectional view shown in fig. 5T to facilitate a better understanding of embodiments of the present invention.

Fig. 6 illustrates a partial cross-sectional schematic view of a semiconductor device 200 according to another embodiment of the invention. In comparison to the semiconductor device 100 shown in fig. 1, the semiconductor device 200 in fig. 6 may further include a thick bottom oxide layer 118 (Thick Bottom Oxide, TBO) formed at the bottom of the gate region 107 (e.g., the bottom of the gate trench 1071) of each vertical transistor cell. In one embodiment, the TBO layer 118 may be formed by depositing an insulating material (e.g., the same insulating material as the gate insulating material 1072) at the bottom of each gate trench 1071 such that the thickness of the insulating material at the bottom of each gate trench 1071 reaches a predetermined bottom insulating thickness T4, and T4 is greater than the predetermined gate insulating layer thickness T1. The predetermined bottom insulation thickness T4 may be a sum of a predetermined gate insulation layer thickness T1 and a thickness of the TBO layer 118. In one embodiment, the predetermined bottom insulation thickness T4 may range from 50nm to 1um. TBO layer 118 helps reduce the gate charge of semiconductor device 200 as compared to semiconductor device 100, thereby reducing switching losses of semiconductor device 200 during switching in practical applications. It will be understood by those skilled in the art that the gate charge of semiconductor device 200 refers to the charge that needs to be provided to the gate of the semiconductor device when the semiconductor device is switched.

Those skilled in the art will appreciate that the description of the various embodiments of the semiconductor device 100 and the associated fabrication methods described above with respect to fig. 1-5T apply to the semiconductor device 200 of fig. 6. Accordingly, disclosure and understanding of the manufacturing method of the semiconductor device 200 may refer to the above description of the cross-sectional views shown in fig. 5A to 5T. Compared to the semiconductor device 100, the fabrication of the semiconductor device 200 adds a TBO layer formation step, which may be between the steps shown in fig. 5J and 5K, as shown in the partial cross-sectional schematic view of fig. 7. Referring to fig. 7, after the forming step of the gate insulating layer 1072 (as shown in fig. 5J), the TBO layer 118 may be formed by depositing an insulating material (e.g., the same material as the gate insulating layer 1072) at the bottom of each gate trench 1071 such that the thickness of the insulating material at the bottom of each gate trench 1071 reaches a preset bottom insulating thickness T4 that is greater than the preset gate insulating layer thickness T1. After the formation step of the TBO layer shown in fig. 7, the semiconductor device 200 can be manufactured with reference to the steps shown in fig. 5K to 5T. That is, the manufacturing method of the semiconductor device 200 may include fig. 5A to 5J, fig. 7, and fig. 5K to 5T.

Fig. 8 shows a schematic partial cross-sectional view of a semiconductor device 300 according to another embodiment of the invention. In comparison to the semiconductor device 100 shown in fig. 1, the semiconductor device 300 may use a buried layer 308 of a first conductivity type (e.g., N-type) to implement the second source region 108 of each vertical-type transistor cell shown in fig. 1. In other words, the buried layer 308 may serve as a second source region or JFET source region for each vertical transistor cell of the semiconductor device 300. The doping type, doping concentration and function of the buried layer 308 may be the same as those of the second source region 108, and will not be described herein.

Those skilled in the art will appreciate that the description of the various embodiments of the semiconductor device 100 and associated fabrication methods described above with respect to fig. 1-5T are applicable to the semiconductor device 300 of fig. 8. Accordingly, disclosure and understanding of the manufacturing method of the semiconductor device 300 may refer to the above description of the cross-sectional views shown in fig. 5A to 5T. The manufacturing method of the semiconductor device 300 differs from the semiconductor device 100 in that an additional buried layer manufacturing step is added after the epitaxial layer 102 is manufactured, i.e. the step shown in the partial cross-sectional schematic view of fig. 9A may replace the step shown in fig. 5A. The manufacturing method of the semiconductor device 300 is different in that the step shown in the partial cross-sectional schematic view of fig. 9B may replace the step of forming the second source region 108 by implantation shown in fig. 5B, as compared to the semiconductor device 100, and thus the step shown in fig. 5B may be omitted.

As shown in fig. 9A, a first portion (e.g., a lower portion) of epitaxial layer 102 may be formed on semiconductor layer 101 (described with reference to fig. 5A). A buried layer 308 having a first conductivity type (e.g., N-type) may then be formed on/in the first portion of the epitaxial layer 102, and a second portion (e.g., an upper portion) of the epitaxial layer 102 may then be formed on the buried layer 308. In an embodiment, the buried layer 308 may be formed by implanting dopants of a first conductivity type into a first portion (e.g., a lower portion) of the epitaxial layer 102. In another embodiment, the buried layer 308 may be formed on a first portion (e.g., a lower portion) of the epitaxial layer 102 by an epitaxial process. For example, an epitaxial process to form buried layer 308 may include: the buried layer 308 is grown by vapor phase epitaxial deposition of a semiconductor material doped with dopants of the first conductivity type. In this method, it will be appreciated by those skilled in the art that the buried layer 308 may be sandwiched between a first portion (lower portion) and a second portion (upper portion) of the epitaxial layer 102. The buried layer 308 may have a higher doping concentration than the epitaxial doping concentration of the epitaxial layer 102. The buried layer 308 may serve as a second source region (i.e., JFET source region) of the semiconductor device 300, and the buried layer 308 may have the same doping concentration as the second source region 108 of the semiconductor device 100. Advantages of using the buried layer 308 as the second source region of the semiconductor device 300 include at least: the second source region 308 may be placed deeper from the second surface of the substrate (e.g., the top surface S1 of the epitaxial layer 102) without the use of a high energy implantation process, which may help to further improve the performance of the semiconductor device 300. In an embodiment, the buried layer 308 may have a thickness ranging from 0.1 μm to 1.0 μm. In another embodiment, the upper portion of the epitaxial layer 102 may have a thickness ranging from 0.1 μm to 1.0 μm.

After the step shown in fig. 9A, referring to fig. 9B, under the protection of the patterned first implantation mask 501, a lightly doped region (e.g., lightly doped region 104) and a MOSFET source region (e.g., first source region 103) may be formed in a second portion (i.e., upper portion) of the epitaxial layer 102 by implanting each vertical-type transistor cell of the semiconductor device 300. As shown in fig. 9B, unlike the step shown in fig. 5B, the step of implanting to form the second source region 108 may be skipped or omitted. The patterned first implantation mask 501 may be formed on a second surface of the substrate (e.g., the top surface S1 of the epitaxial layer 102) and patterned to expose a predetermined region on the second surface of the substrate (e.g., the top surface S1 of the epitaxial layer 102). Dopants may be implanted from the predetermined regions to form lightly doped regions 104 (if any) and first source regions 103 of each vertical transistor cell of semiconductor device 300. The patterned first implantation mask 501 may be removed after implantation to form lightly doped regions 104 (if any) and first source regions 103. In one embodiment, the formation of lightly doped region 104 is optional, so the step of implanting to form lightly doped region 104 may be omitted. The conductivity type (or doping type) and doping concentration of the lightly doped region 104 (if any) and the first source region 103 are already described in detail in fig. 1, and will not be described here again.

After the flow shown in fig. 9B, the semiconductor device 300 will be prepared with reference to the steps shown in fig. 5C to 5T. That is, the fabrication of the semiconductor device 300 may include the fabrication steps shown in fig. 9A, 9B, and 5C to 5T.

Fig. 10 illustrates a partial cross-sectional schematic view of a semiconductor device 400 according to another embodiment of the present invention. In comparison with the semiconductor device 300 shown in fig. 8, the semiconductor device 400 shown in fig. 10 further includes the TBO layer 118 formed at the bottom of the gate region 107 of each vertical transistor cell. The TBO layer 118 is described in the same manner as fig. 6, and will not be described again here.

Those skilled in the art will appreciate that the descriptions above with respect to fig. 1-5T and fig. 9A, 9B for various embodiments of semiconductor device 300 and associated methods of fabrication apply to semiconductor device 400 in fig. 10. Accordingly, disclosure and understanding of the manufacturing method of the semiconductor device 400 may refer to the above description of the cross-sectional views shown in fig. 5A to 5T and fig. 9A, 9B. The manufacturing method of the semiconductor device 400 differs from that of the semiconductor device 300 in that a TBO layer formation step shown in the partial cross-sectional schematic view of fig. 7 is added between the steps of fig. 5I and 5J. That is, the steps of preparing the semiconductor device 400 include the steps shown in fig. 9A, 9B, 5C to 5J, 7, and 5K to 5T.

The advantages of the embodiments of the present invention are not limited to the above description. Advantages of embodiments of the invention will become apparent upon reading the entire detailed description and studying the various figures.

While the invention has been described with reference to several exemplary embodiments, it is to be understood that the terminology used is intended to be in the nature of words of description and of limitation. As the present invention may be embodied in several forms without departing from the spirit or essential characteristics thereof, it should also be understood that the above-described embodiments are not limited by any of the details of the foregoing description, but rather should be construed broadly within its spirit and scope as defined in the appended claims, and therefore all changes and modifications that fall within the meets and bounds of the claims, or equivalences of such meets and bounds are therefore intended to be embraced by the appended claims.

Claims

1. A method of making a semiconductor device, comprising:

forming a substrate of a first conductivity type, the substrate comprising a drain region doped in a partial region of a first surface of an adjacent substrate;

forming a first source region having a first conductivity type and a second source region having a first conductivity type in the substrate, wherein the first source region is formed in a partial region adjacent to a second surface of the substrate, wherein the second source region is formed below and spaced apart from the first source region, the second surface of the substrate being opposite to the first surface of the substrate;

Forming a gate groove of a gate region in the substrate so that the gate groove is adjacent to/close to the first source region;

forming a first sidewall body region having a second conductivity type under the first source region to separate the first source region and the second source region;

forming a connection region having a second conductivity type such that the connection region and the gate trench are disposed on a first side of the first source region and a second side of the first source region, respectively, wherein the first side of the first source region is opposite to the second side of the first source region;

forming a gate insulating layer to cover the side wall and the bottom of the gate trench; and

the gate trenches are filled with a gate conductive material.

2. The method of claim 1, wherein forming the substrate comprises forming a semiconductor layer having the first conductivity type and forming an epitaxial layer having the first conductivity type over the semiconductor layer, the semiconductor layer including a drain region formed by doping a portion of the first surface of an adjacent semiconductor layer.

3. The method of claim 2, wherein the step of forming the second source region comprises forming a buried layer of the first conductivity type between the first portion of the epitaxial layer and the second portion of the epitaxial layer, wherein a doping concentration of the buried layer is the same as a doping concentration of the second source region.

4. A method as claimed in claim 2 or 3, wherein the first source region has a first doping concentration and the second source region has a second source region doping concentration, wherein the first source region doping concentration and the second source region doping concentration are higher than the epitaxial doping concentration of the epitaxial layer.

5. A method as claimed in claim 2 or 3, wherein the drain region has a drain region doping concentration higher than the epitaxial doping concentration of the epitaxial layer.

6. A method as claimed in any one of claims 1 to 3, further comprising:

a body contact region of the second conductivity type is formed in the substrate adjacent a partial region of the second surface of the substrate, the body contact region being adjacent the first source region on a first side of the first source region, wherein the body contact region has a higher body contact region doping concentration than the first body region doping concentration of the first sidewall body region.

7. A method as claimed in any one of claims 1 to 3, wherein the connection region has a higher doping concentration of the connection region than the first body region of the first sidewall body region.

8. A method as claimed in any one of claims 1 to 3, wherein the connection region has a higher doping concentration of the connection region than the second source region.

9. A method as in any of claims 1-3, wherein the step of forming the first sidewall body region comprises implanting dopants of the second conductivity type into the substrate after forming the second source region and before forming the first source region.

10. A method as claimed in any one of claims 1 to 3, further comprising:

an oxidation step is performed to oxidize an uppermost portion of the gate conductive material in the gate trench to form a gate cap layer, wherein a predetermined gate cap thickness of the gate cap layer is thicker than a predetermined gate insulation thickness of the gate insulation layer.

11. A method as in any of claims 1-3 wherein the first source region, the first sidewall body region, and the second source region are vertically aligned along a first sidewall of the gate region.

12. A method as in any of claims 1-3, wherein the step of forming the first sidewall body region comprises implanting dopants of the second conductivity type into the substrate at a first predetermined angle relative to the second surface of the substrate and through the first sidewall of the gate trench.

13. A method as in any of claims 1-3, wherein the formed connection region extends vertically downward along the second sidewall of the adjacent gate region until wrapping around the second bottom corner of the adjacent gate region.

14. A method as in any of claims 1-3, wherein the step of forming the connection region comprises implanting dopants of a second conductivity type into the substrate at a second predetermined angle relative to the second surface of the substrate and through the second sidewalls of the gate trenches of adjacent gate regions.

15. A method as claimed in claim 3, wherein the connection region formed extends vertically down into the first portion of the epitaxial layer through the buried layer.

16. A method as claimed in any one of claims 1 to 3, further comprising:

after forming the second source region and before forming the first source region, a lightly doped region having the second conductivity type is formed.

17. The method of claim 16, wherein forming the first sidewall body region comprises implanting dopants of the second conductivity type into the lightly doped region, wherein the lightly doped region extends laterally beyond the first sidewall body region.

18. A method as claimed in any one of claims 1 to 3, further comprising:

a second sidewall body region of a second conductivity type is formed under the second source region, wherein the connection region is isolated from the second sidewall body region.

19. The method of claim 18 wherein forming the second sidewall body regions comprises implanting dopants of the second conductivity type into the substrate at a first predetermined angle relative to the second surface of the substrate and through the first sidewalls of the gate trenches.

20. The method of claim 18 wherein the second sidewall body region extends vertically downward from a bottom surface of the second source region along the first sidewall of the gate region to wrap around the first bottom corner of the gate region.

21. A method as claimed in any one of claims 1 to 3, further comprising:

a JFET channel implant region of a first conductivity type is formed at a partial region adjacent the connection region, the JFET channel implant region conformal with the connection region.

22. A method as claimed in any one of claims 1 to 3, further comprising:

a protection region having a second conductivity type is formed under the gate trench, wherein the protection region has a higher doping concentration than the first body region of the first sidewall body region.

23. A method as claimed in any one of claims 1 to 3, further comprising:

after forming the gate insulating layer and before filling the gate trench with the gate conductive material, a thick bottom oxide layer is formed at the bottom of the gate trench.

24. The method of claim 10, further comprising:

a post-etch treatment step to expose portions of the second surface of the substrate not covered by the gate cap layer;

a deposition step to form a metal layer on the entire exposed top surface of the structure formed after the post-etch treatment step;

a silicidation step of forming a silicide layer on a portion of the second surface of the substrate not covered by the gate capping layer;

a deposition step to form an interlayer dielectric layer covering the silicide layer and the gate cover layer;

an etching step to form a source contact trench and a gate contact trench, wherein the source contact trench is formed by etching the interlayer dielectric layer to expose at least a portion of the silicide layer located over the first source region, and the gate contact trench is formed by etching the interlayer dielectric layer to expose at least a portion of the gate conductive material in the gate trench; and

And a metal deposition step to fill the source contact trench and the gate contact trench to form a source metal contact and a gate metal contact, respectively.