CN117174139B - Signal generation circuit and memory - Google Patents
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- CN117174139B CN117174139B CN202311083433.3A CN202311083433A CN117174139B CN 117174139 B CN117174139 B CN 117174139B CN 202311083433 A CN202311083433 A CN 202311083433A CN 117174139 B CN117174139 B CN 117174139B
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Abstract
The invention provides a signal generating circuit and a memory, comprising: the first module and the second module control the pre-charging operation and control gating between corresponding ports; when the precharge operation is not performed, the first module and the second module enable the signal generating circuit to generate a bit line signal for performing data writing operation on the memory cell; when the precharge operation is performed, the third module causes the signal generating circuit to generate a bit line signal for performing a read data operation on the memory cell; in the precharge operation, the fourth module causes the signal generating circuit to generate a bit line signal for performing a read data operation on the memory cell. On the premise of not increasing the area, the static random access memory has the capability of simultaneously carrying out dual-port read-write operation and even multi-port read-write operation, greatly improves the read-write efficiency of the static random access memory, effectively reduces the static power consumption and has wide applicability.
Description
Technical Field
The present invention relates to the field of integrated circuit design and application technology, and in particular, to a signal generating circuit and a memory.
Background
The Static Random-Access Memory (SRAM) is a cache Memory arranged between a CPU and a main Memory, and along with the development of an integrated circuit system toward micromation, the number of times and the frequency of reading and writing of the SRAM are also greatly increased, so that the SRAM needs to have two ports or more ports for performing reading and writing operations at the same time, and in addition, under the advanced process node, the reduction of layout area can bring greater benefit, and how to combine the area with the reading and writing efficiency of the SRAM is one of the current technical difficulties.
It should be noted that the foregoing description of the background art is only for the purpose of providing a clear and complete description of the technical solution of the present application and is presented for the convenience of understanding by those skilled in the art. The above-described solutions are not considered to be known to the person skilled in the art simply because they are set forth in the background of the application section.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a signal generating circuit and a memory for solving the problem of how to improve the read/write efficiency of the read sram without increasing the area in the prior art.
To achieve the above and other related objects, the present invention provides a signal generating circuit including at least: the first module, the second module, the third module and the fourth module, wherein:
The first module controls the pre-charging operation of the first upper port and the second upper port based on the accessed upper control signal, controls the gating of the first upper port and the first data port based on the accessed upper write enable signal, and controls the gating of the second upper port and the second data port; the second module controls the pre-charging operation of the first lower port and the second lower port based on the accessed lower control signal, controls gating of the first lower port and the first data port based on the accessed lower write enable signal, and controls gating of the second lower port and the second data port;
When the precharge operation is not performed, the first module and the second module are connected with the data of the first data port and the second data port so that the signal generating circuit generates a bit line signal for performing data writing operation on the memory unit;
The third module is connected between the first upper port and the first lower port, and when the precharge operation is performed, the third module enables the signal generating circuit to generate a bit line signal for performing data reading operation on the memory cell based on the accessed upper first read enable signal and the lower first read enable signal; the fourth module is connected between the second upper port and the second lower port, and when the precharge operation is performed, the fourth module causes the signal generating circuit to generate a bit line signal for performing a read data operation on the memory cell based on the accessed upper second read enable signal and the lower second read enable signal.
Optionally, the first upper port is connected to a first bit line of each memory cell in the upper bank; the second upper port is connected with a second bit line of each memory cell in the upper memory bank; the first lower port is connected with a first bit line of each memory cell in the lower memory bank; the second lower port is connected to a second bit line of each memory cell in the lower bank.
Optionally, the upper control signal, the upper write enable signal, the lower control signal, the lower write enable signal, the upper first read enable signal, the upper second read enable signal, the lower first read enable signal, and the lower second read enable signal are all obtained by a decoding operation.
Optionally, the first module includes: the first PMOS tube, the second PMOS tube, the first NMOS tube, the second NMOS tube and the first NOT gate, wherein: the source electrode of the first PMOS tube is connected with the working voltage, the grid electrode of the first PMOS tube is connected with an upper control signal, and the drain electrode of the first PMOS tube is connected with a first upper port; the source electrode of the second PMOS tube is connected with the source electrode of the first PMOS tube, the grid electrode of the second PMOS tube is connected with the grid electrode of the first PMOS tube, and the drain electrode of the second PMOS tube is connected with the second upper port; the input end of the first NOT gate is connected with an upper write enable signal; the drain electrode of the first NMOS tube is connected with the drain electrode of the first PMOS tube, the grid electrode of the first NMOS tube is connected with the output end of the first NOT gate, and the source electrode of the first NMOS tube is connected with the first data port; the drain electrode of the second NMOS tube is connected with the drain electrode of the second PMOS tube, the grid electrode of the second NMOS tube is connected with the grid electrode of the first NMOS tube, and the source electrode of the second NMOS tube is connected with the second data port.
Optionally, the second module includes: the third PMOS tube, the fourth PMOS tube, the third NMOS tube, the fourth NMOS tube and the second NOT gate, wherein: the source electrode of the third PMOS tube is connected with the working voltage, the grid electrode of the third PMOS tube is connected with a lower control signal, and the drain electrode of the third PMOS tube is connected with a first lower port; the source electrode of the fourth PMOS tube is connected with the source electrode of the third PMOS tube, the grid electrode of the fourth PMOS tube is connected with the grid electrode of the third PMOS tube, and the drain electrode of the fourth PMOS tube is connected with the second lower port; the input end of the second NOT gate is connected with a lower write enable signal; the drain electrode of the third NMOS tube is connected with the drain electrode of the third PMOS tube, the grid electrode of the third NMOS tube is connected with the output end of the second NOT gate, and the source electrode of the third NMOS tube is connected with the first data port; the drain electrode of the fourth NMOS tube is connected with the drain electrode of the fourth PMOS tube, the grid electrode of the fourth NMOS tube is connected with the grid electrode of the third NMOS tube, and the source electrode of the fourth NMOS tube is connected with the second data port.
Optionally, the third module includes: a third NOT gate, a fourth NOT gate and a fifth NMOS transistor, wherein: the input end of the third NOT gate is connected with an upper first reading enable signal, the input end of the fourth NOT gate is connected with a lower first reading enable signal, the first control end of the third NOT gate is connected with a first upper port, the first control end of the fourth NOT gate is connected with the second control end and a first lower port of the third NOT gate, and the second control end of the fourth NOT gate is connected with the first control end of the third gate; the grid electrode of the fifth NMOS tube is connected with the output end of the third NOT gate and the output end of the fourth NOT gate, the source electrode of the fifth NMOS tube is connected with the reference ground, and the drain electrode of the fifth NMOS tube is connected with a first bit line assembly port of the memory bank, wherein the first bit line assembly port of the memory bank is used for collecting data stored by a first bit line of each memory cell in an upper memory bank and data stored by a first bit line of each memory cell in a lower memory bank.
Optionally, the fourth module includes: fifth NOT gate, sixth NOT gate and sixth NMOS transistor, wherein: the input end of the fifth NOT gate is connected with an upper second reading enable signal, the input end of the sixth NOT gate is connected with a lower second reading enable signal, the first control end of the fifth NOT gate is connected with a second upper port, the first control end of the sixth NOT gate is connected with the second control end and a second lower port of the fifth NOT gate, and the second control end of the sixth NOT gate is connected with the first control end of the fifth gate; the grid electrode of the sixth NMOS tube is connected with the output end of the fifth NOT gate and the output end of the sixth NOT gate, the source electrode of the sixth NMOS tube is connected with the reference ground, and the drain electrode of the sixth NMOS tube is connected with a second bit line summarizing port of the memory bank, wherein the second bit line summarizing port of the memory bank is used for collecting data stored by the second bit line of each memory cell in the upper memory bank and data stored by the second bit line of each memory cell in the lower memory bank.
Optionally, when performing a data writing operation on a storage unit in the upper storage library, the data reading operation cannot be performed on the upper storage library; when the data writing operation is performed on the storage units in the lower storage library, the data reading operation cannot be performed on the lower storage library.
Optionally, when one of the upper first read enable signal and the upper second read enable signal is asserted, the signal generating circuit performs a read data operation on one port of the memory cells in the upper bank; when the upper first reading enabling signal and the upper second reading enabling signal are both effective, the signal generating circuit performs reading operation on two ports of a storage unit in the upper storage library; when one of the lower first reading enabling signal and the lower second reading enabling signal is effective, the signal generating circuit performs reading operation on one port of a storage unit in the lower storage library; when the lower first read enable signal and the lower second read enable signal are both asserted, the signal generation circuit performs a read data operation on both ports of the memory cells in the lower memory bank.
To achieve the above and other related objects, the present invention provides a memory, the memory includes a plurality of memory modules arranged longitudinally and at intervals, each memory module includes an upper memory bank and a lower memory bank arranged longitudinally, the upper memory bank and the lower memory bank have the same number of rows M and the same number of columns N, wherein M and N are natural numbers greater than 1, and the upper memory bank and the lower memory bank each include m×n memory cells, wherein the memory cells include a first port and a second port; and N signal generating circuits are arranged in the same memory module, each signal generating circuit is connected between corresponding columns of the upper memory bank and the lower memory bank, wherein the signal generating circuits are connected between corresponding bit lines of the upper memory bank and corresponding bit lines of the lower memory bank, and a kth signal generating circuit is connected between corresponding bit lines of a kth column of the upper memory bank and corresponding bit lines of a kth column of the lower memory bank, wherein k is a natural number, and k is more than or equal to 1 and less than or equal to N.
As described above, the signal generating circuit and the memory of the present invention have the following advantages:
The signal generating circuit and the memory enable the static random access memory to have the capability of simultaneously performing dual-port read-write operation and even multi-port read-write operation on the premise of not increasing the area, greatly improve the read-write efficiency of the static random access memory, effectively reduce the static power consumption and have wide applicability.
Drawings
Fig. 1 shows a circuit schematic of a first exemplary 6T SRAM.
Fig. 2 shows a circuit schematic of a second exemplary 8T SRAM.
Fig. 3 is a schematic diagram of a signal generating circuit according to the present invention.
Fig. 4 is a circuit diagram of a memory cell according to the present invention.
Fig. 5 shows a circuit schematic of the memory according to the present invention.
Description of the reference numerals
1. Signal generating circuit
11. First module
12. Second module
13. Third module
14. Fourth module
2. Memory cell
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
Please refer to fig. 1 to 5. It should be noted that the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complicated.
Fig. 1 shows a 6T SRAM circuit, 6T referring to 6 transistors including MOSFETs, MOS being Metal Oxide Semiconductor, an abbreviation for metal oxide semiconductor, FET being an abbreviation for FIELD EFFECT Transistor field effect Transistor, comprising: PMOS tube P11, PMOS tube P12, NMOS tube N11, NMOS tube N12, NMOS tube N13 and NMOS tube N14, wherein: the drain of NMOS transistor N13 is connected to bit line FBLT, the drain of NMOS transistor N14 is connected to bit line FBLC, and the gates of NMOS transistor N13 and NMOS transistor N14 are both connected to bit line FWL. In the data writing operation, the bit line FWL is turned on at a high level, and based on the data to be written currently (including data "0" and data "1"), the bit line FBLT rewrites the data of the node T, and the bit line FBLC rewrites the data of the node C, wherein the level of the bit line FBLT is opposite to the level of the bit line FBLC; during a data reading operation, the NMOS transistor N13 and the NMOS transistor N14 are turned on via the bit line FWL, and the difference between the bit lines FBLT and FBLC is detected for data reading. Fig. 2 shows a circuit of an 8T SRAM, 8T referring to 8 transistors, comprising: the PMOS tube P21, the PMOS tube P22, the NMOS tube N21, the NMOS tube N22, the NMOS tube N23, the NMOS tube N24, the NMOS tube N25 and the NMOS tube N26, wherein the drain electrode of the NMOS tube N23 is connected with the bit line SBLT, the drain electrode of the NMOS tube N24 is connected with the bit line SBLC, and the grid electrodes of the NMOS tube N23 and the NMOS tube N24 are connected with the bit line SWL. In the data writing operation, the bit line SWL is turned on at a high level, and based on the data to be written currently (including data "0" and data "1"), the bit line SBLT rewrites the data of the node T, and the bit line SBLC rewrites the data of the node C, wherein the level of the bit line SBLT is opposite to the level of the bit line SBLC; when the read data operation is performed, the word line RWL is connected with a high level, the bit line RBL is precharged to the high level, and when the node C is at the high level, the bit line RBL is pulled down to the reference ground; when node C is low, the signal of bit line RBL remains unchanged. If the number of read operations is to be increased, the number of MOS transistors can be increased on the basis of 8T to accomplish the purpose of multi-reading, but the area of the SRAM is increased, because the smaller the area of the SRAM can bring more benefit as the integrated circuit system is advanced toward the micromation.
Therefore, the invention provides a signal generating circuit and a memory, which are implemented as follows:
As shown in fig. 3, the present embodiment provides a signal generating circuit 1, the signal generating circuit 1 including: a first module 11, a second module 12, a third module 13 and a fourth module 14, wherein:
As shown in fig. 3, a first end of the first module 11 is connected to the first upper port blt_u and the second upper port blc_u, and a second end of the first module 11 is connected to the first data port WBLT and the second data port WBLC; the control terminal of the first module 11 controls the precharge operation of the first and second upper ports blt_u and blc_u based on the accessed upper control signal PRCHB _u, controls the gating of the first upper port blt_u and the first data port WBLT based on the accessed upper write enable signal wrt_ BKENB _u, and controls the gating of the second upper port blc_u and the second data port WBLC.
As shown in fig. 3, a first end of the second module 12 is connected to the first lower port blt_d and the second lower port blc_d, and a second end of the second module 12 is connected to the first data port WBLT and the second data port WBLC; the control terminal of the second module 12 controls the precharge operation of the first lower port blt_d and the second lower port blc_d based on the accessed lower control signal PRCHB _d, controls the gating of the first lower port blt_d and the first data port WBLT based on the accessed lower write enable signal wrt_ BKENB _d, and controls the gating of the second lower port blc_d and the second data port WBLC. In the data reading operation, the first and second upper ports blt_u and blc_u are precharged to a high level, and the first and second lower ports blt_d and blc_d are precharged to a high level; when the data writing operation is performed, the first upper port blt_u, the second upper port blc_u, the first lower port blt_d, and the second lower port blc_d do not perform the precharge operation.
It should be noted that there is an important concept BANK in the memory, where BANK is a meaning of a memory BANK, that is, a plurality of memory BANKs are partitioned in a memory, when accessing, a memory BANK number is specified, and the specified memory BANK can be accessed, how many memory BANKs are partitioned in the memory, and if there are several BANKs addresses in an address line, if there are two bits, 4 BANKs are illustrated in the memory, and if there are 3 bits, 8 BANKs are illustrated in the memory. Fig. 4 illustrates a circuit of a memory cell, the memory cell comprising: PMOS tube P31, PMOS tube P32, NMOS tube N31, NMOS tube N32, NMOS tube N33 and NMOS tube N34, wherein: the drain electrode of the NMOS tube N33 is connected with the first bit line TBLT, and the grid electrode of the NMOS tube N33 is connected with the first word line WLT; the drain of the NMOS transistor N34 is connected to the second bit line TBLC, and the gate of the NMOS transistor N34 is connected to the second word line WLC. In each BANK, memory cells in the same row share the same first and second word lines WLT and WLC, and memory cells in the same column share the same first and second bit lines TBLT and TBLC.
Specifically, as shown in fig. 3 and 4, the first upper port blt_u is connected to the first bit line TBLT of each memory cell in the upper bank; the second upper port blc_u is connected to a second bit line TBLC of each memory cell in the upper bank. The upper control signal PRCHB _u, the upper write enable signal wrt_ BKENB _u are obtained through a decoding operation. The decoding operation is the inverse of the encoding operation, and each binary code is given a specific meaning, i.e. represents a certain signal or object, when encoded. The process of translating the specific meaning of the code state is called decoding, the circuit for realizing decoding operation is called a decoder, the line number of decoding input is set according to the number of signals output by decoding, and the specific relation is as follows: the number of input lines N corresponds to 2 N output signals, and N is a natural number greater than or equal to 1. It should be noted that, the process of acquiring the upper control signal PRCHB _u and the upper write enable signal wrt_ BKENB _u includes, but is not limited to, decoding operations, and may also be implemented by adopting a combination logic circuit, where the specific form of the combination logic circuit is not described herein.
Specifically, as shown in fig. 3, the first module includes: the first PMOS tube P1, the second PMOS tube P2, the first NMOS tube N1, the second NMOS tube N2 and the first NOT1, wherein: the source electrode of the first PMOS tube P1 is connected with the working voltage VDD, the grid electrode of the first PMOS tube P1 is connected with an upper control signal, and the drain electrode of the first PMOS tube P1 is connected with a first upper port BLT_U; the source electrode of the second PMOS tube P2 is connected with the source electrode of the first PMOS tube P1, the grid electrode of the second PMOS tube P2 is connected with the grid electrode of the first PMOS tube P1, and the drain electrode of the second PMOS tube P2 is connected with the second upper port BLC_U; the input end of the first NOT gate NOT1 is connected with an upper write enable signal WRT_ BKENB _U; the drain electrode of the first NMOS tube N1 is connected with the drain electrode of the first PMOS tube P1, the grid electrode of the first NMOS tube N1 is connected with the output end of the first NOT1, and the source electrode of the first NMOS tube N1 is connected with the first data port WBLT; the drain electrode of the second NMOS tube N2 is connected with the drain electrode of the second PMOS tube P2, the grid electrode of the second NMOS tube N2 is connected with the grid electrode of the first NMOS tube N1, and the source electrode of the second NMOS tube N2 is connected with the second data port WBLC.
Specifically, as shown in fig. 3, the second module 12 includes: the third PMOS transistor P3, the fourth PMOS transistor P4, the third NMOS transistor N3, the fourth NMOS transistor N4, and the second NOT2, wherein: the source electrode of the third PMOS tube P3 is connected with the working voltage VDD, the grid electrode of the third PMOS tube P3 is connected with the lower control signal PRCHB _D, and the drain electrode of the third PMOS tube P3 is connected with the first lower port BLT_D; the source electrode of the fourth PMOS tube P4 is connected with the source electrode of the third PMOS tube P3, the grid electrode of the fourth PMOS tube P4 is connected with the grid electrode of the third PMOS tube P3, and the drain electrode of the fourth PMOS tube P4 is connected with the second lower port BLC_D; the input end of the second NOT gate NOT2 is connected with a lower write enable signal WRT_ BKENB _D; the drain electrode of the third NMOS tube N3 is connected with the drain electrode of the third PMOS tube P3, the grid electrode of the third NMOS tube N3 is connected with the output end of the second NOT2, and the source electrode of the third NMOS tube N3 is connected with the first data port WBLT; the drain electrode of the fourth NMOS tube N4 is connected with the drain electrode of the fourth PMOS tube P4, the grid electrode of the fourth NMOS tube N4 is connected with the grid electrode of the third NMOS tube N3, and the source electrode of the fourth NMOS tube N4 is connected with the second data port WBLC.
It should be noted that, when performing a data writing operation, external valid data is transferred to the first data port WBLT and the second data port WBLC. And when one row in the upper memory bank is selected, the upper control signal PRCHB _U is at a high level, so that the first PMOS tube P1 and the second PMOS tube P2 are not conducted, and the influence of the pre-charging line on the write data line is isolated. The upper write enable signal wrt_bken_u is low, and the first NMOS transistor N1 is turned on with the second NMOS transistor N2, the first upper port blt_u is connected with the first data port WBLT, and the second upper port blc_u is connected with the second data port WBLC. The first word line WLT of the selected row is high, connected to the gate of the NMOS transistor N33 in fig. 4, the second word line WLC is high, connected to the gate of the NMOS transistor N34 in fig. 4, and external valid data is transferred to the first upper port blt_u through the first data port WBLT and to the second upper port blc_u through the second data port WBLC, so that the data of the memory cell is modified according to the data of the write data line through the NMOS transistor N33 and the NMOS transistor N34. The first lower port blt_d is connected to a first bit line TBLT of each memory cell in the lower bank; the second lower port blc_d is connected to a second bit line TBLC of each memory cell in the lower bank. The lower control signal PRCHB _d and the lower write enable signal wrt_ BKENB _d are also obtained through a decoding operation, and the same principle as the acquisition process of the upper control signal PRCHB _u and the upper write enable signal wrt_ BKENB _u is not described in detail herein.
It should be noted that, the principle of writing data to the lower memory bank is the same as that of writing data to the upper memory bank, and will not be described in detail here. In this embodiment, when performing a data writing operation on one of the banks in the memory, the data cannot be read from the bank that is performing the data writing operation.
To sum up, as shown in fig. 3, during the data writing operation, external valid data is transmitted to the first data port WBLT and the second data port WBLC. At this time, when the first and second upper ports blt_u and blc_u do not perform the precharge operation, bit line signals for performing the write data operation on the memory cells in the upper bank are generated through the communication of the first upper port blt_u and the first data port WBLT and the communication of the second upper port blc_u and the second data port WBLC; when the first and second lower ports blt_d and blc_d do not perform the precharge operation, a bit line signal for performing a write data operation on a memory cell in the lower bank is generated through communication of the first lower port blt_d with the first data port WBLT and communication of the second lower port blc_d with the second data port WBLC.
As shown in fig. 3, the third module 13 is connected between the first upper port blt_u and the first lower port blt_d, and during the precharge operation, the third module 13 causes the signal generating circuit 1 to generate a bit line signal for performing a data reading operation on the memory cell based on the accessed upper first read enable signal rd1_ BKENB _u and the lower first read enable signal rd1_ BKENB _d, the bit line signal performs a data reading operation on the first port of the memory cell, wherein the input terminal of the third module 13 is connected to the upper first read enable signal rd1_ BKENB _u and the lower first read enable signal rd1_ BKENB _d, and the control terminal of the third module 13 is connected to the first upper port blt_u and the first lower port blt_d; the fourth module 14 is connected between the second upper port blc_u and the second lower port blc_d, when the precharge operation is performed, the fourth module 14 causes the signal generating circuit 1 to generate a bit line signal for performing a data reading operation on the memory cell based on the accessed upper second read enable signal rd2_ BKENB _u and the lower second read enable signal rd2_ BKENB _d, the bit line signal performs a data reading operation on the second port of the memory cell, wherein the input terminal of the fourth module 14 is connected to the upper second read enable signal rd2_ BKENB _u and the lower second read enable signal rd2_ BKENB _d, the control terminal of the fourth module 14 is connected to the second upper port blc_u and the second lower port blc_d, and after the first upper port blt_u or the second upper port blc_u completes the precharge operation, the state of the second port is generated based on the upper first read enable signal rd1_ BKENB _u or the upper second read enable signal rd2_ BKENB _u, and the state of the second port blc_4_u is disconnected from the second data storage cell; after the precharge operation is completed on the first lower port blt_d or the second lower port blc_d, a bit line signal for performing a read data operation on the memory cells in the lower bank is generated based on the asserted state of the lower first read enable signal rd1_ BKENB _d or the lower second read enable signal rd2_ BKENB _d, and the disconnected state of the first lower port blt_d and the first data port WBLT and the disconnected state of the second lower port blc_d and the second data port WBLC.
Specifically, as shown in fig. 3 and 4, as an example, the third module 13 includes: a third NOT gate NOT3, a fourth NOT gate NOT4 and a fifth NMOS transistor N5, wherein: the input end of the third NOT3 is connected with an upper first reading enable signal RD1_ BKENB _U, the input end of the fourth NOT4 is connected with a lower first reading enable signal RD1_ BKENB _D, a first control end of the third NOT3 is connected with a first upper port BLT_U, a first control end of the fourth NOT4 is connected with a second control end of the third NOT3 and a first lower port BLT_D, and a second control end of the fourth NOT4 is connected with a first control end of the third NOT 3; the gate of the fifth NMOS transistor N5 is connected to the output end of the third NOT gate NOT3 and the output end of the fourth NOT gate NOT4, the source of the fifth NMOS transistor N5 is connected to the reference ground, and the drain of the fifth NMOS transistor N5 is connected to the first bitline pooling port GRBL _t of the memory bank, where the first bitline pooling port GRBL _t of the memory bank is used to collect data stored in the first bitline of each memory cell in the upper memory bank and data stored in the first bitline of each memory cell in the lower memory bank, and the operation procedure of collecting data by the first bitline pooling port GRBL _t of the memory bank is NOT described herein. The fourth module 14 includes: fifth NOT5, sixth NOT6 and sixth NMOS transistor N6, wherein: the input end of the fifth NOT5 is connected with an upper second reading enable signal RD2_ BKENB _U, the input end of the sixth NOT6 is connected with a lower second reading enable signal RD2_ BKENB _D, a first control end of the fifth NOT5 is connected with a second upper port BLC_U, a first control end of the sixth NOT6 is connected with a second control end of the fifth NOT5 and a second lower port BLC_D, and a second control end of the sixth NOT6 is connected with a first control end of the fifth NOT 5; the gate of the sixth NMOS transistor N6 is connected to the output end of the fifth NOT gate NOT5 and the output end of the sixth NOT gate NOT6, the source of the sixth NMOS transistor N6 is connected to the reference ground, and the drain of the sixth NMOS transistor N6 is connected to the second bit line summary port GRBL _c of the memory bank, where the second bit line summary port GRBL _c of the memory bank is used to collect data stored in the second bit line of each memory cell in the upper memory bank and data stored in the second bit line of each memory cell in the lower memory bank, and the process of collecting data by the second bit line summary port GRBL _c of the memory bank is NOT repeated herein.
Further, as shown in fig. 3 and 4, when one of the first read enable signal rd1_ BKENB _u and the second read enable signal rd2_ BKENB _u is asserted, the signal generating circuit 1 performs a read operation on one port of the memory cells in the upper memory bank; when the upper first read enable signal rd1_ BKENB _u and the upper second read enable signal rd2_ BKENB _u are both asserted, the signal generating circuit 1 performs a data reading operation on two ports of the memory cells in the upper memory bank; when one of the lower first read enable signal rd1_ BKENB _d and the lower second read enable signal rd2_ BKENB _d is asserted, the signal generating circuit 1 performs a read data operation on one port of the memory cells in the lower bank; when the lower first read enable signal rd1_ BKENB _d and the lower second read enable signal rd2_ BKENB _d are both asserted, the signal generating circuit 1 performs a data reading operation on two ports of the memory cells in the lower bank.
As shown in fig. 3 and 4, when performing a single-port read data operation, it is assumed that the first row and the first column of memory cells in the upper memory bank are read. First, the upper control signal PRCHB _u is at a low level, the first PMOS transistor P1 and the second PMOS transistor P2 are turned on, and then the first upper port blt_u and the second upper port blc_u are precharged, at this time, the first NMOS transistor N1 and the second NMOS transistor N2 are turned off when the upper write enable signal wrt_ BKENB _u is at a high level, so as to isolate external data accessed by the first data port WBLT and the second data port WBLC. After the pre-charge is finished, the upper control signal PRCHB _u is adjusted to a high level, so that the first PMOS transistor P1 and the second PMOS transistor P2 are turned off, and when the upper first read enable signal rd1_ BKENB _u is at a low level, the fifth NMOS transistor N5 is turned off and the first bitline aggregate port GRBL _t of the memory bank cannot be pulled down, so that the data "1" is read, and the data "1" is read through the first bitline TBLT of the corresponding memory cell; when the first upper port blt_u contains data "0", the fifth NMOS transistor N5 is turned on, the bank first bitline pooling port GRBL _t is pulled down to ground, and the data "0" is read through the first bitline TBLT of the corresponding memory cell. It should be noted that, when the control ends of the third NOT3 and the fourth NOT4 access the data "0", that is, access the low level, the third NOT3 and the fourth NOT4 operate. Further, in fig. 4, the NMOS transistor N33 connected to the first bit line TBLT corresponds to the first port of the memory cell, that is, the data reading operation on the first port is completed. Similarly, the NMOS transistor N34 connected to the second bit line TBLC corresponds to the second port of the memory cell, and the data reading operation on the second port can be completed based on the above process.
When the data reading operation of the two ports is performed, it is assumed that the node T is at a high level and the node C is at a low level in the memory cell 2. Firstly, performing a precharge operation on a first upper port blt_u and a second upper port blc_u, wherein after the precharge operation is finished, an upper first read enable signal rd1_ BKENB _u and an upper second read enable signal rd2_ BKENB _u are both low level, and according to the data actually stored, the blt_u is high level, a third NOT3 controlled by the blt_u is NOT conducted, and a first bit line summary port GRBL _t of a memory bank is kept high level; at this time, blc_u is low, the fifth NOT gate NOT5 controlled by blc_u is turned on, and the second bitline bus port GRBL _c of the memory bank is pulled down to ground. Similarly, a two-port read operation can be performed on a memory cell with node T being low and node C being high. The process of reading data from a single port and two ports of the lower memory bank is not described here in detail. It should also be noted that the data at node T of memory cell 2 is typically located at the value actually stored by the memory cell, and the data read by second bit line TBLC typically requires a negation operation to correspond to the value actually stored by the memory cell, as determined by the existing properties of the memory cell. It should be noted that, the first module 11, the second module 12, the third module 13, and the fourth module 14 may also be configured in the form of a combinational logic circuit to generate a bit line signal for performing a data writing operation on a memory cell in the upper memory bank, generate a bit line signal for performing a data writing operation on a memory cell in the lower memory bank, generate a bit line signal for performing a data reading operation on a memory cell in the upper memory bank, and generate a bit line signal for performing a data reading operation on a memory cell in the lower memory bank, where the configuration of the combinational logic circuit is not described herein.
As shown in fig. 5, the present embodiment further provides a memory, where the memory includes a plurality of memory modules arranged longitudinally and at intervals, each memory module includes an upper memory BANK (1) and a lower memory BANK (2) arranged longitudinally, the upper memory BANK (1) and the lower memory BANK (2) have the same number of rows M and the same number of columns N, where M and N are natural numbers greater than 1, and each of the upper memory BANK (1) and the lower memory BANK (2) includes m×n memory cells, where the memory cells include a first port and a second port, the memory cells are arranged in a manner shown in fig. 4, the NMOS transistor N33 connected to the first bit line TBLT corresponds to the first port of the memory cell, and the NMOS transistor N34 connected to the second bit line TBLC corresponds to the second port of the memory cell. In the same memory module, N signal generating circuits 1 provided in this embodiment are provided, each signal generating circuit 1 is connected between corresponding columns of the upper BANK (1) and the lower BANK (2), wherein the signal generating circuit 1 is connected between corresponding bit lines of the upper BANK (a first upper port blt_u of the signal generating circuit 1 is connected to a first bit line TBLT of the upper BANK, a second upper port blc_u is connected to a second bit line TBLC of the upper BANK) and corresponding bit lines of the lower BANK (a first lower port blt_d of the signal generating circuit 1 is connected to a first bit line TBLT of the lower BANK, a second lower port blc_d is connected to a second bit line TBLC of the lower BANK), and a kth signal generating circuit is connected between corresponding bit lines of a kth column of the upper BANK and corresponding bit lines of a kth column of the lower BANK, wherein k is a natural number, and k is 1 Σn. Note that the memory cell in fig. 5 is a simplification of the memory cell in fig. 4.
Specifically, as an example, performing data writing operation on the upper BANK (1) in the memory module, performing data reading operation (including single-port data reading operation and two-port data reading operation) on other BANKs (including the lower BANK (2) in the memory module and the upper BANK and the lower BANK corresponding to other memory modules) except for the BANK (1); the number of signal generating circuits 1 may be increased between each column of the upper memory bank and the corresponding column of the lower memory bank to implement the multiple read multiple write function, and the specific configuration operation process will not be described here.
In summary, the signal generating circuit and the memory according to the present invention include: the first module, the second module, the third module and the fourth module, wherein: the first module controls the pre-charging operation of the first upper port and the second upper port based on the accessed upper control signal, controls the gating of the first upper port and the first data port based on the accessed upper write enable signal, and controls the gating of the second upper port and the second data port; the second module controls the pre-charging operation of the first lower port and the second lower port based on the accessed lower control signal, controls gating of the first lower port and the first data port based on the accessed lower write enable signal, and controls gating of the second lower port and the second data port; when the precharge operation is not performed, the first module and the second module are connected with the data of the first data port and the second data port so that the signal generating circuit generates a bit line signal for performing data writing operation on the memory unit; the third module is connected between the first upper port and the first lower port, and when the precharge operation is performed, the third module enables the signal generating circuit to generate a bit line signal for performing data reading operation on the memory cell based on the accessed upper first read enable signal and the lower first read enable signal; the fourth module is connected between the second upper port and the second lower port, and when the precharge operation is performed, the fourth module causes the signal generating circuit to generate a bit line signal for performing a read data operation on the memory cell based on the accessed upper second read enable signal and the lower second read enable signal. The signal generating circuit and the memory enable the static random access memory to have the capability of simultaneously performing dual-port read-write operation and even multi-port read-write operation on the premise of not increasing the area, greatly improve the read-write efficiency of the static random access memory, effectively reduce the static power consumption and have wide applicability. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.
Claims (9)
1. A signal generation circuit, the signal generation circuit comprising at least: the first module, the second module, the third module and the fourth module, wherein:
The first module controls the pre-charging operation of the first upper port and the second upper port based on the accessed upper control signal, controls the gating of the first upper port and the first data port based on the accessed upper write enable signal, and controls the gating of the second upper port and the second data port; the second module controls the pre-charging operation of the first lower port and the second lower port based on the accessed lower control signal, controls gating of the first lower port and the first data port based on the accessed lower write enable signal, and controls gating of the second lower port and the second data port;
When the precharge operation is not performed, the first module and the second module are connected with the data of the first data port and the second data port so that the signal generating circuit generates a bit line signal for performing data writing operation on the memory unit;
The third module is connected between the first upper port and the first lower port, and when the precharge operation is performed, the third module enables the signal generating circuit to generate a bit line signal for performing data reading operation on the memory cell based on the accessed upper first read enable signal and the lower first read enable signal; the fourth module is connected between the second upper port and the second lower port, and when the precharge operation is performed, the fourth module enables the signal generating circuit to generate a bit line signal for performing data reading operation on the memory cell based on the accessed upper second read enable signal and the lower second read enable signal;
Wherein the first upper port is connected with a first bit line of each memory cell in the upper memory bank; the second upper port is connected with a second bit line of each memory cell in the upper memory bank; the first lower port is connected with a first bit line of each memory cell in the lower memory bank; the second lower port is connected to a second bit line of each memory cell in the lower bank.
2. The signal generation circuit of claim 1, wherein: the upper control signal, the upper write enable signal, the lower control signal, the lower write enable signal, the upper first read enable signal, the upper second read enable signal, the lower first read enable signal, and the lower second read enable signal are all obtained by a decoding operation.
3. The signal generation circuit of claim 1, wherein: the first module includes: the first PMOS tube, the second PMOS tube, the first NMOS tube, the second NMOS tube and the first NOT gate, wherein: the source electrode of the first PMOS tube is connected with the working voltage, the grid electrode of the first PMOS tube is connected with an upper control signal, and the drain electrode of the first PMOS tube is connected with a first upper port; the source electrode of the second PMOS tube is connected with the source electrode of the first PMOS tube, the grid electrode of the second PMOS tube is connected with the grid electrode of the first PMOS tube, and the drain electrode of the second PMOS tube is connected with the second upper port; the input end of the first NOT gate is connected with an upper write enable signal; the drain electrode of the first NMOS tube is connected with the drain electrode of the first PMOS tube, the grid electrode of the first NMOS tube is connected with the output end of the first NOT gate, and the source electrode of the first NMOS tube is connected with the first data port; the drain electrode of the second NMOS tube is connected with the drain electrode of the second PMOS tube, the grid electrode of the second NMOS tube is connected with the grid electrode of the first NMOS tube, and the source electrode of the second NMOS tube is connected with the second data port.
4. The signal generation circuit of claim 1, wherein: the second module includes: the third PMOS tube, the fourth PMOS tube, the third NMOS tube, the fourth NMOS tube and the second NOT gate, wherein: the source electrode of the third PMOS tube is connected with the working voltage, the grid electrode of the third PMOS tube is connected with a lower control signal, and the drain electrode of the third PMOS tube is connected with a first lower port; the source electrode of the fourth PMOS tube is connected with the source electrode of the third PMOS tube, the grid electrode of the fourth PMOS tube is connected with the grid electrode of the third PMOS tube, and the drain electrode of the fourth PMOS tube is connected with the second lower port; the input end of the second NOT gate is connected with a lower write enable signal; the drain electrode of the third NMOS tube is connected with the drain electrode of the third PMOS tube, the grid electrode of the third NMOS tube is connected with the output end of the second NOT gate, and the source electrode of the third NMOS tube is connected with the first data port; the drain electrode of the fourth NMOS tube is connected with the drain electrode of the fourth PMOS tube, the grid electrode of the fourth NMOS tube is connected with the grid electrode of the third NMOS tube, and the source electrode of the fourth NMOS tube is connected with the second data port.
5. The signal generation circuit of claim 1, wherein: the third module includes: a third NOT gate, a fourth NOT gate and a fifth NMOS transistor, wherein: the input end of the third NOT gate is connected with an upper first reading enable signal, the input end of the fourth NOT gate is connected with a lower first reading enable signal, the first control end of the third NOT gate is connected with a first upper port, the first control end of the fourth NOT gate is connected with the second control end and a first lower port of the third NOT gate, and the second control end of the fourth NOT gate is connected with the first control end of the third NOT gate; the grid electrode of the fifth NMOS tube is connected with the output end of the third NOT gate and the output end of the fourth NOT gate, the source electrode of the fifth NMOS tube is connected with the reference ground, and the drain electrode of the fifth NMOS tube is connected with a first bit line assembly port of the memory bank, wherein the first bit line assembly port of the memory bank is used for collecting data stored by a first bit line of each memory cell in an upper memory bank and data stored by a first bit line of each memory cell in a lower memory bank.
6. The signal generation circuit of claim 1, wherein: the fourth module includes: fifth NOT gate, sixth NOT gate and sixth NMOS transistor, wherein: the input end of the fifth NOT gate is connected with an upper second reading enable signal, the input end of the sixth NOT gate is connected with a lower second reading enable signal, the first control end of the fifth NOT gate is connected with a second upper port, the first control end of the sixth NOT gate is connected with the second control end and a second lower port of the fifth NOT gate, and the second control end of the sixth NOT gate is connected with the first control end of the fifth NOT gate; the grid electrode of the sixth NMOS tube is connected with the output end of the fifth NOT gate and the output end of the sixth NOT gate, the source electrode of the sixth NMOS tube is connected with the reference ground, and the drain electrode of the sixth NMOS tube is connected with a second bit line summarizing port of the memory bank, wherein the second bit line summarizing port of the memory bank is used for collecting data stored by the second bit line of each memory cell in the upper memory bank and data stored by the second bit line of each memory cell in the lower memory bank.
7. The signal generation circuit of claim 1, wherein: when the data writing operation is carried out on the storage units in the upper storage library, the data reading operation cannot be carried out on the upper storage library; when the data writing operation is performed on the storage units in the lower storage library, the data reading operation cannot be performed on the lower storage library.
8. The signal generation circuit of claim 1, wherein: when one of the upper first reading enable signal and the upper second reading enable signal is effective, the signal generating circuit performs reading operation on one port of a storage unit in the upper storage library; when the upper first reading enabling signal and the upper second reading enabling signal are both effective, the signal generating circuit performs reading operation on two ports of a storage unit in the upper storage library; when one of the lower first reading enabling signal and the lower second reading enabling signal is effective, the signal generating circuit performs reading operation on one port of a storage unit in the lower storage library; when the lower first read enable signal and the lower second read enable signal are both asserted, the signal generation circuit performs a read data operation on both ports of the memory cells in the lower memory bank.
9. A memory, characterized in that: the memory comprises a plurality of memory modules which are longitudinally arranged at intervals, each memory module comprises an upper memory bank and a lower memory bank which are longitudinally arranged, the upper memory bank and the lower memory bank have the same row number M and the same column number N, wherein M and N are natural numbers which are larger than 1, each memory module comprises M x N memory units, and each memory unit comprises a first port and a second port; the signal generating circuits according to any one of claims 1 to 8 are arranged in the same memory module, each signal generating circuit is connected between the corresponding columns of the upper memory bank and the lower memory bank, wherein the signal generating circuit is connected between the corresponding bit line of the upper memory bank and the corresponding bit line of the lower memory bank, and the kth signal generating circuit is connected between the corresponding bit line of the kth column of the upper memory bank and the corresponding bit line of the kth column of the lower memory bank, wherein k is a natural number, and k is more than or equal to 1 and less than or equal to N.
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|---|---|---|---|---|
| CN103219037A (en) * | 2013-04-22 | 2013-07-24 | 中国科学院半导体研究所 | In-chip memory with multi-port read-write |
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Family Cites Families (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
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| CN1317799A (en) * | 2000-04-10 | 2001-10-17 | 黄松柏 | On-line programmable computer ICs for autoamtic control |
| KR100735612B1 (en) * | 2005-12-22 | 2007-07-04 | 삼성전자주식회사 | Multi-path accessible semiconductor memory device |
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