CN117171082A - Low-power consumption chip and electronic equipment - Google Patents
Low-power consumption chip and electronic equipment Download PDFInfo
- Publication number
- CN117171082A CN117171082A CN202311446113.XA CN202311446113A CN117171082A CN 117171082 A CN117171082 A CN 117171082A CN 202311446113 A CN202311446113 A CN 202311446113A CN 117171082 A CN117171082 A CN 117171082A
- Authority
- CN
- China
- Prior art keywords
- gate
- input
- data
- output
- module
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000012360 testing method Methods 0.000 claims abstract description 55
- 230000005540 biological transmission Effects 0.000 claims abstract description 41
- 238000013524 data verification Methods 0.000 claims description 47
- 238000012545 processing Methods 0.000 claims description 12
- 230000006870 function Effects 0.000 claims description 11
- 238000012795 verification Methods 0.000 claims description 7
- 238000012423 maintenance Methods 0.000 claims description 6
- 102100029469 WD repeat and HMG-box DNA-binding protein 1 Human genes 0.000 description 18
- 101710097421 WD repeat and HMG-box DNA-binding protein 1 Proteins 0.000 description 18
- 238000010586 diagram Methods 0.000 description 8
- 238000000034 method Methods 0.000 description 8
- 238000012937 correction Methods 0.000 description 6
- 230000008569 process Effects 0.000 description 4
- 125000004122 cyclic group Chemical group 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000003491 array Methods 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 210000001503 joint Anatomy 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000008676 import Effects 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 239000013307 optical fiber Substances 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The invention discloses a low-power consumption chip and an electronic device, the low-power consumption chip comprises: the system comprises a plurality of functional logic modules, a plurality of serial shift input/output logic circuits and a test control module, wherein the functional logic modules, the serial shift input/output logic circuits and the test control module are arranged in a power supply normally-open domain, a holding memory, a data checking module and a low-power control circuit are arranged in the power supply normally-open domain, the low-power control circuit is configured to control a first data transmission channel between the data checking module and the test control module to be opened under the condition that a chip enters a low-power holding state, so that the test control module integrates state data and then sends the integrated state data to the data checking module through the first data transmission channel, and the data checking module is configured to check the integrated state data to generate a check code and send the integrated state data and the check code to the holding memory for storage. The chip can greatly shorten the time for entering the low-power consumption holding state and can improve the reliability of the chip.
Description
Technical Field
The present invention relates to the field of chip technologies, and in particular, to a low power chip and an electronic device.
Background
With the rapid development of chip technology and the application of some special scenes, low-power consumption technology is increasingly emphasized. Among the various low power techniques, the power control and register holding techniques are the more commonly used ones.
In the related art, in the process of entering the low power consumption state by the chip, the state data storage usually uses a one-way read-write mode, and the time for entering the low power consumption state by the chip is long. In addition, the state data stored in the chip may have errors such as data flip in the memory, and the reliability is poor.
Disclosure of Invention
The present invention aims to solve at least one of the technical problems in the related art to some extent. To this end, a first object of the present invention is to propose a low power chip.
A second object of the invention is to propose an electronic device.
In order to achieve the above object, an embodiment of a first aspect of the present invention provides a low power chip, including: the device comprises a plurality of functional logic modules, a plurality of serial shift input output logic circuits and a test control module, wherein the functional logic modules are arranged in a power-off domain, each serial shift input output logic circuit is arranged corresponding to one functional logic module, and each serial shift input output logic circuit is suitable for outputting state data of the corresponding functional logic module to the test control module; the low-power consumption control circuit is configured to control a first data transmission channel between the data verification module and the test control module to be opened under the condition that the chip enters a low-power consumption maintenance state, so that the test control module integrates state data of a corresponding functional logic module through at least part of serial shift input/output logic circuits, then sends the integrated state data to the data verification module through the first data transmission channel, and the data verification module is configured to verify the integrated state data to generate a verification code and send the integrated state data and the verification code to the maintenance memory for storage.
According to the low-power consumption chip provided by the embodiment of the invention, when the chip needs to enter a low-power consumption holding state, the low-power consumption control circuit controls the first data transmission channel between the data checking module and the test control module to be communicated, each serial shift input/output logic circuit serially outputs the state data stored in the corresponding functional logic module to the test control module, the test control module integrates the state data and then sends the integrated state data to the data checking module through the first data transmission channel to perform data checking, and generates a corresponding check code, and the data checking module sends the integrated state data and the check code to the holding memory to be stored. Therefore, when the chip enters the low-power-consumption holding state, the serial shift input/output logic circuits are in butt joint with the test control module in a read-write mode of a plurality of links, so that the time for the chip to enter the low-power-consumption holding state is greatly shortened, the state data is checked before the state data is stored, and the reliability of the chip is improved.
In addition, the low power chip according to the above embodiment of the present invention may further have the following additional technical features:
according to one embodiment of the present invention, the low power consumption control circuit is further configured to control a second data transmission channel between the data verification module and the test control module to be opened when the chip exits the low power consumption holding state, so that the data verification module sends the verified state data to the test control module through the second data transmission channel, and the test control module is further configured to integrate the verified state data and guide the integrated state data into the corresponding serial shift input output logic circuit, so that the corresponding functional logic module is called.
According to an embodiment of the present invention, the low power chip further includes: and the functional safety processing module is suitable for processing the error reporting of the chip safety function and configuring whether the data checking module works or not.
According to one embodiment of the present invention, a first gate is disposed on the first data transmission channel, a first end of the first gate is connected to a first output end of the test control module, a second end of the first gate is respectively connected to an output end of any one of the functional logic modules, a third end of the first gate is connected to a first input end of the data verification module, and the low power consumption control circuit controls the first end and the third end of the first gate to communicate when the chip enters a low power consumption holding state, so that the test control module sends integrated status data to the data verification module through the first data transmission channel.
According to an embodiment of the present invention, the low power consumption control circuit is further configured to, in a case where the chip is in a normal operating state, control the second terminal of the first gate to communicate with the third terminal if the data verification module is configured to be in a stop operating state, so that each functional logic module sends corresponding logic data to the holding memory for storage, and control a third data transmission channel between the data verification module and each functional logic module to be opened, so that each functional logic module invokes the logic data stored in the holding memory.
According to one embodiment of the present invention, the third data transmission channel is provided with a first and gate, a first input end of the first and gate is connected to a first output end of the data verification module, a second input end of the first and gate is connected to a memory input/output control end of the low power consumption control circuit after being inverted, and output ends of the first and gate are respectively connected to input ends of the functional logic modules, where, under a condition that the chip is in a normal working state, the first and gate is in an on state under control of the low power consumption control circuit; and under the control of the low-power-consumption control circuit, the first AND gate is in a closed state under the condition that the chip enters a low-power-consumption holding state.
According to one embodiment of the invention, the second data transmission channel is provided with a second and gate, a first input end of the second and gate is connected with a first output end of the data verification module, a second input end of the second and gate is connected with a memory input/output control end of the low-power consumption control circuit, and an output end of the second and gate is connected with a first input end of the test control module, wherein the second and gate is in an on state under the control of the low-power consumption control circuit under the condition that the chip exits from the low-power consumption holding state.
According to one embodiment of the invention, the functional logic module includes: the first input end and the second input end of the third AND gate are used as input ends of the functional logic module, and the output end of the third AND gate is connected with the corresponding serial shift input/output logic circuit; the first input end of the first NAND gate is connected with the output end of the third AND gate, the second input end of the first NAND gate is connected with the serial shift input output logic circuit, and the output end of the first NAND gate is connected with the serial shift input output logic circuit; a first or gate, a first input end of which is connected with a first input end of the third and gate, and a second input end of which is connected with the serial shift input output logic circuit; the first input end of the fourth AND gate is connected with the output end of the first OR gate, the second input end of the fourth AND gate is connected with the serial shift input output logic circuit, and the output end of the fourth AND gate is connected with the serial shift input output logic circuit; the first input end of the second OR gate is connected with the first input end of the fourth AND gate, the second input end of the second OR gate is connected with the serial shift input output logic circuit, and the output end of the second OR gate is used as the output end of the functional logic module.
According to one embodiment of the present invention, the serial shift input output logic circuit includes: the first input end of the second gating device is connected with the output end of the third AND gate, and the second input end of the second gating device is used as the scanning input end of the serial shift input-output logic circuit; the input end of the first trigger is connected with the output end of the second gating device, and the output end of the first trigger is connected with the second input end of the first NAND gate; the first input end of the third gating device is connected with the output end of the first NAND gate, and the second input end of the third gating device is connected with the output end of the first trigger; the input end of the second trigger is connected with the output end of the third gating device, and the output end of the second trigger is connected with the second input end of the fourth AND gate; the first input end of the fourth gating device is connected with the output end of the fourth AND gate, and the second input end of the fourth gating device is connected with the output end of the second trigger; the input end of the third trigger is connected with the output end of the fourth gate, and the output end of the third trigger is connected with the second input end of the second OR gate and serves as the output end of the serial shift input-output logic circuit; the enabling end of the second gating device, the enabling end of the third gating device and the enabling end of the fourth gating device are connected and are suitable for receiving enabling signals; the clock end of the first trigger, the clock end of the second trigger and the clock end of the third trigger are connected and are suitable for receiving clock signals.
In order to achieve the above objective, an embodiment of a second aspect of the present invention provides an electronic device, which includes the above low power chip.
According to the electronic equipment provided by the embodiment of the invention, through the low-power chip, the time for entering the low-power holding state can be greatly shortened, and the reliability of the equipment can be improved.
Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.
Drawings
FIG. 1 is a block diagram of a low power chip according to an embodiment of the invention;
FIG. 2 is a block diagram of a low power chip according to one embodiment of the invention;
FIG. 3 is a hardware topology of functional logic and serial shift input-output logic according to one embodiment of the present invention;
FIG. 4 is a diagram illustrating a data flow when an enable signal is "0" according to one embodiment of the present invention;
FIG. 5 is a diagram illustrating a data flow when an enable signal is "1" according to one embodiment of the present invention;
FIG. 6 is a schematic diagram of waveforms of steps in operation of the serial shift input-output logic circuit according to one embodiment of the present invention;
fig. 7 is a block schematic diagram of an electronic device according to an embodiment of the invention.
Detailed Description
Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements or elements having like or similar functions throughout. The embodiments described below by referring to the drawings are illustrative and intended to explain the present invention and should not be construed as limiting the invention.
The low power chip and the electronic device according to the embodiments of the present invention are described below with reference to the accompanying drawings.
Fig. 1 is a block diagram of a low power chip according to an embodiment of the invention.
As shown in fig. 1, a low power chip 100 according to an embodiment of the present invention includes: the power supply system comprises a plurality of functional logic modules 110, a plurality of serial shift input output logic circuits 120 and a test control module 130, wherein the functional logic modules 110 are arranged in a power-off domain, each serial shift input output logic circuit 120 is arranged corresponding to one functional logic module 110, and each serial shift input output logic circuit 120 is suitable for outputting state data of the corresponding functional logic module 110 to the test control module 130; the low power consumption control circuit 160 is configured to control the first data transmission channel between the data verification module 150 and the test control module 130 to be opened when the chip 100 enters the low power consumption maintenance state, so that the test control module 130 integrates the state data of the corresponding functional logic module 110 through at least part of the serial shift input/output logic circuit 120, then sends the integrated state data to the data verification module 150 through the first data transmission channel, and the data verification module 150 is configured to verify the integrated state data to generate a verification code and send the integrated state data and the verification code to the maintenance memory 140 for storage.
Specifically, each functional logic module 110 may be tested by the test control module 130 using the corresponding serial shift input output logic circuit 120. When the chip 100 needs to enter the low power consumption holding state, the low power consumption control circuit 160 controls the first data transmission channel between the data checking module 150 and the test control module 130 to be opened, the serial shift input output logic circuit 120 outputs the state data stored in the functional logic module 110 to the test control module 130 in series, the test control module 130 integrates (such as data bit width or format conversion) the state data, and then sends the integrated state data to the data checking module 150 through the first data transmission channel to perform data checking, for example, the data checking can be performed through the checking modes such as CRC (Cyclic Redundancy Check), cyclic redundancy check) or ECC (Error Correcting Code, error checking and correction), and a corresponding check code is generated, and the data checking module 150 sends the integrated state data and the check code to the holding memory 140 to store. Then, the chip 100 enters a low power consumption holding state. In some embodiments of the present invention, the holding Memory 140 may be an SRAM (Static Random-Access Memory), which is a volatile Memory, and has the advantage of fast reading and writing, and the use of the SRAM can greatly shorten the time for entering the low-power-consumption holding state compared with the use of the SRAM stored in a non-volatile Memory such as Flash. In addition, the use of the holding memory 140 can provide a chip with a smaller circuit area and can hold power consumption in a lower state than in the case of using a digital holding unit.
According to one embodiment of the present invention, the low power consumption control circuit 160 is further configured to control the second data transmission channel between the data verification module 150 and the test control module 130 to be opened in case that the chip 100 exits the low power consumption holding state, so that the data verification module 150 transmits the verified state data to the test control module 130 through the second data transmission channel, and the test control module 130 is further configured to integrate the verified state data and import the integrated state data into the corresponding serial shift input output logic circuit 120, so that the corresponding functional logic module 110 is invoked.
Specifically, when the chip 100 needs to exit the low power consumption holding state, for example, an external wake-up source sends a wake-up signal to the chip 100, the low power consumption control circuit 160 controls the data checking module 150 and the test control module 130 to open a second data transmission channel according to the received wake-up signal, the data checking module 150 reads the status data and the check code from the holding memory 140, and performs automatic correction and checking of the data CRC value or the ECC value, for example, checking whether the data is flipped in the low power consumption holding state, and if the data is flipped, performing error correction, or performing error reporting or global reset for uncorrectable errors. After the status data passes the verification, the data verification module 150 sends the verified status data to the test control module 130 through the second data transmission channel, and the test control module 130 performs data integration on the verified status data and directs the integrated status data into the corresponding serial shift input output logic circuit 120 so as to be called by the corresponding functional logic module 110.
According to an embodiment of the present invention, as shown in fig. 2, the low power chip 100 further includes: the functional security processing module 170 is adapted to process the error reporting of the security function of the chip 100 and to configure whether the data checking module 150 works.
Specifically, the functional security processing module 170 may pre-configure the data verification module 150, configuring the data verification module 150 to enable or disable data verification. When the chip 100 needs to enter a low power consumption holding state, if the functional security processing module 170 configures the data checking module 150 to enable data checking, the data checking module 150 performs data checking on the integrated state data, for example, performs data checking in a checking mode such as a CRC (cyclic redundancy check) or ECC (error correction code) mode, and generates a corresponding check code; if the functional security processing module 170 configures the data verification module 150 to shut down the data verification, the data verification module 150 does not operate. When the chip 100 needs to exit the low power consumption holding state, if the functional security processing module 170 configures the data checking module 150 to enable data checking, the data checking module 150 reads the state data and the check code from the holding memory 140 and performs automatic correction and checking of the data CRC value or ECC value; if the functional security processing module 170 configures the data verification module 150 to shut down the data verification, the data verification module 150 does not operate.
Further, the functional security processing module 170 may also process the error reporting of the security function of the chip 100 in a centralized manner. If the chip 100 encounters an uncorrectable error in the previous step, an error may be reported (the next step is not performed). The functional safety processing module 170 may also perform global reset (not perform the next step) when an uncorrectable error is encountered in the previous step according to a predetermined configuration; or ignore the error (continue to execute the next step). If no uncorrectable errors are encountered, the next step is continued.
According to an embodiment of the present invention, as shown in fig. 2, a first data transmission channel is provided with a first strobe XT1, a first end of the first strobe XT1 is connected to a first output end of the test control module 130, a second end of the first strobe XT1 is respectively connected to an output end of any one of the functional logic modules 110, a third end of the first strobe XT1 is connected to a first input end of the data verification module 150, and the low power consumption control circuit 160 controls the first end and the third end of the first strobe XT1 to communicate when the chip 100 enters a low power consumption holding state, so that the test control module 130 transmits the integrated status data to the data verification module 150 through the first data transmission channel.
Specifically, when the chip 100 needs to enter the low power consumption holding state, the low power consumption control circuit 160 controls the first end of the first strobe XT1 to communicate with the third end, so that the first data transmission channel between the data checking module 150 and the test control module 130 is opened, the serial shift input output logic circuit 120 serially outputs the state data stored in the functional logic module 110 to the test control module 130, and after the test control module 130 integrates the state data, the integrated state data is sent to the data checking module 150 through the first data transmission channel to perform data checking.
According to one embodiment of the present invention, as shown in fig. 2, the low power consumption control circuit 160 is further configured to, in a case where the chip 100 is in a normal operation state, control the second terminal of the first strobe XT1 to communicate with the third terminal so that each functional logic module 110 transmits corresponding logic data to the holding memory 140 to store, and control the third data transmission path between the data verification module 150 and each functional logic module 110 to open so that each functional logic module 110 invokes the logic data stored in the holding memory 140, if the data verification module 150 is configured to be in a stop operation state.
Specifically, if the data verification module 150 is configured to be in a deactivated state, i.e., the data verification module 150 turns off the data verification, when the chip 100 is in a normal operation state, the low power consumption control circuit 160 may control the second terminal of the first strobe XT1 to communicate with the third terminal, and each functional logic module 110 may transmit corresponding logic data to the holding memory 140 for storage through the first strobe XT1 without performing data verification on the logic data. And, the low power consumption control circuit 160 may control the third data transmission channel to be opened, and each functional logic module 110 may call the logic data stored in the holding memory 140 through the third data transmission channel to implement the normal function of the chip 100.
According to one embodiment of the present invention, as shown in fig. 2, the third data transmission channel is provided with a first AND gate AND1, a first input terminal of the first AND gate AND1 is connected to a first output terminal of the data verification module 150, a second input terminal of the first AND gate AND1 is connected to a memory input/output control terminal of the low power consumption control circuit 160 after being inverted, AND output terminals of the first AND gate AND1 are respectively connected to input terminals of the functional logic modules 110, wherein, under the control of the low power consumption control circuit 160, the first AND gate AND1 is in an on state under the condition that the chip 100 is in a normal operation state; in the case where the chip 100 enters the low power consumption holding state, the first AND gate AND1 is in an off state under the control of the low power consumption control circuit 160.
Specifically, when the chip 100 is in a normal operating state, the memory input/output control terminal of the low power consumption control circuit 160 outputs a low level signal to the second input terminal of the first AND gate AND1, AND converts the low level signal into a high level signal after inverting the low level signal, so that the first AND gate AND1 is turned on, AND each functional logic module 110 may call the logic data stored in the holding memory 140 through the first AND gate AND1 to implement the normal function of the chip 100. When the chip 100 enters the low power consumption holding state, the memory input/output control terminal of the low power consumption control circuit 160 outputs a high level signal to the second input terminal of the first AND gate AND1, AND converts the high level signal into a low level signal after inverting the phase, so that the first AND gate AND1 is turned off.
According to one embodiment of the present invention, as shown in fig. 2, the second data transmission channel is provided with a second AND gate AND2, a first input terminal of the second AND gate AND2 is connected to the first output terminal of the data verification module 150, a second input terminal of the second AND gate AND2 is connected to the memory input/output control terminal of the low power consumption control circuit 160, AND an output terminal of the second AND gate AND2 is connected to the first input terminal of the test control module 130, wherein, in case that the chip 100 exits the low power consumption holding state, the second AND gate AND2 is in an on state under the control of the low power consumption control circuit 160.
Specifically, when the chip 100 needs to exit the low power consumption holding state, for example, the external wake-up source sends a wake-up signal to the chip 100, the memory input/output control terminal of the low power consumption control circuit 160 outputs a high level signal to the second input terminal of the second AND gate AND2, so that the second AND gate AND2 is turned on. The data checking module 150 reads the status data AND the check code from the holding memory 140, performs automatic correction AND checking of the data CRC value or the ECC value, AND after the status data passes the check, the data checking module 150 sends the checked status data to the test control module 130 through the second AND gate AND2, AND the test control module 130 performs data integration on the checked status data, AND directs the integrated status data to the corresponding serial shift input output logic circuit 120 for the corresponding functional logic module 110 to call.
According to one embodiment of the present invention, as shown in fig. 3, the functional logic 110 includes: a third AND gate AND3, a first NAND gate NAND1, a first OR gate OR1, a fourth AND gate AND1, AND a second OR gate OR2. Wherein the first input end AND the second input end of the third AND gate AND3 are used as input ends of the functional logic module 110, AND the output end of the third AND gate AND3 is connected with the corresponding serial shift input output logic circuit 120; a first input end of the first NAND gate NAND1 is connected with an output end of the third AND gate AND3, a second input end of the first NAND gate NAND1 is connected with the serial shift input output logic circuit 120, AND an output end of the first NAND gate NAND1 is connected with the serial shift input output logic circuit 120; a first input end of the first OR gate OR1 is connected with a first input end of the third AND gate AND3, AND a second input end of the first OR gate OR1 is connected with the serial shift input output logic circuit 120; a first input end of the fourth AND gate AND1 is connected with an output end of the first OR gate OR1, a second input end of the fourth AND gate AND1 is connected with the serial shift input output logic circuit 120, AND an output end of the fourth AND gate AND1 is connected with the serial shift input output logic circuit 120; the first input terminal of the second OR gate OR2 is connected to the first input terminal of the fourth AND gate AND1, the second input terminal of the second OR gate OR2 is connected to the serial shift input output logic circuit 120, AND the output terminal of the second OR gate OR2 is used as the output terminal of the functional logic module 110. It should be noted that the third AND gate AND3, the first NAND gate NAND1, the first OR gate OR1, the fourth AND gate AND1, AND the second OR gate OR2 herein are merely exemplary, AND represent the combinational logic circuit constituting the functional logic block 110, AND are not particularly limited.
Further, according to an embodiment of the present invention, as shown in fig. 3, the serial shift input output logic circuit 120 includes: the second gate XT2, the first flip-flop 121, the third gate XT3, the second flip-flop 122, the fourth gate XT4, and the third flip-flop 123. Wherein, the first input end of the second gate XT2 is connected with the output end of the third AND gate AND3, the second input end of the second gate XT2 is used as the scanning input end of the serial shift input output logic circuit 120; an input end of the first flip-flop 121 is connected with an output end of the second gate XT2, and an output end of the first flip-flop 121 is connected with a second input end of the first NAND gate NAND 1; a first input end of the third gating device XT3 is connected with an output end of the first NAND gate NAND1, and a second input end of the third gating device XT3 is connected with an output end of the first trigger 121; an input terminal of the second flip-flop 122 is connected to an output terminal of the third gate XT3, AND an output terminal of the second flip-flop 122 is connected to a second input terminal of the fourth AND gate AND 1; a first input terminal of the fourth gate XT4 is connected to an output terminal of the fourth AND gate AND1, AND a second input terminal of the fourth gate XT4 is connected to an output terminal of the second flip-flop 122; an input terminal of the third flip-flop 123 is connected to an output terminal of the fourth gate XT4, and an output terminal of the third flip-flop 123 is connected to a second input terminal of the second OR gate OR2 and serves as an output terminal of the serial shift input output logic circuit 120; wherein the enabling terminal of the second gate XT2, the enabling terminal of the third gate XT3 and the enabling terminal of the fourth gate XT4 are connected and adapted to receive an enabling signal; the clock terminal of the first flip-flop 121, the clock terminal of the second flip-flop 122 and the clock terminal of the third flip-flop 123 are connected and adapted to receive a clock signal. The first flip-flop 121, the second flip-flop 122, and the third flip-flop 123 may be D flip-flops. In fig. 3, SE denotes an enable signal, CLK denotes a clock signal, SI denotes a Scan Input (Scan Input). It should be noted that the second gate XT2, the first flip-flop 121, the third gate XT3, the second flip-flop 122, the fourth gate XT4, and the third flip-flop 123 are only exemplary, and represent the combinational logic circuit and the sequential logic circuit that constitute the serial shift input output logic circuit 120, and are not particularly limited.
Specifically, fig. 3 shows a circuit structure common to the functional logic block 110 and the serial shift input/output logic circuit 120. After the functional design of the chip 100 is completed, the entire circuit is composed of several flip-flops and combinational logic. The insertion of the serial shift input output logic 120 refers to the process of replacing the flip-flops with scan registers. The enable signal is its switching signal. In normal operation mode, the enable signal SE is 0, the function of the scan register is completely identical to that of the flip-flop, the data path is D to Q, and the function of the chip 100 is maintained, and the data path is shown by the dashed line in FIG. 4. When the enable signal SE is switched to 1, the scan register performs its scan attribute at this time, the data path is SI to Q, and the data path at this time is shown by the dotted line in fig. 5. SI is the data flow entry at the time of testing. The scan registers Q-SI on the chip are connected together to form the serial shift input output logic 120. The SI end of each flip-flop can be serially input with data by the serial Shift input/output logic circuit 120 in a Shift manner, so as to achieve the purpose of controlling each flip-flop. In the Capture mode, feedback of the chip 100 combinational logic is transmitted back to each flip-flop, achieving the effect of observing the inside of the chip 100.
Specifically, the serial shift input/output logic 120 is mainly divided into three steps in operation: load- > Capture- > Unload. Load is the Input waveform that is driven into the serial shift Input output logic 120 (corresponding to time periods 2,3,4 in fig. 6) by Scan Input (SI); capture is the result of each stage of combinational logic is entered into the next stage register (corresponding to time period 6 in FIG. 6); the Unload is an Output waveform (corresponding to the 8,9,10 time periods in FIG. 6) obtained by serially outputting the data in the serial shift input Output logic 120 through Scan Output (SO).
In summary, according to the low power consumption chip of the embodiment of the present invention, when the chip needs to enter a low power consumption holding state, the low power consumption control circuit controls the first data transmission channel between the data checking module and the test control module to be opened, each serial shift input/output logic circuit serially outputs the state data stored in the corresponding functional logic module to the test control module, the test control module integrates the state data, and then sends the integrated state data to the data checking module through the first data transmission channel to perform data checking, and generates a corresponding check code, and the data checking module sends the integrated state data and the check code to the holding memory to store. Therefore, when the chip enters the low-power-consumption holding state, the serial shift input/output logic circuits are in butt joint with the test control module in a read-write mode of a plurality of links, so that the time for the chip to enter the low-power-consumption holding state is greatly shortened, the state data is checked before the state data is stored, and the reliability of the chip is improved.
Corresponding to the embodiment, the invention also provides electronic equipment.
Fig. 7 is a block schematic diagram of an electronic device according to an embodiment of the invention.
As shown in fig. 7, an electronic device 200 according to an embodiment of the present invention includes the low power chip 100 described above.
According to the electronic equipment provided by the embodiment of the invention, through the low-power chip, the time for entering the low-power holding state can be greatly shortened, and the reliability of the equipment can be improved.
It should be noted that the logic and/or steps represented in the flowcharts or otherwise described herein, for example, may be considered as a ordered listing of executable instructions for implementing logical functions, and may be embodied in any computer-readable medium for use by or in connection with an instruction execution system, apparatus, or device, such as a computer-based system, processor-containing system, or other system that can fetch the instructions from the instruction execution system, apparatus, or device and execute the instructions. For the purposes of this description, a "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of the computer-readable medium would include the following: an electrical connection (electronic device) having one or more wires, a portable computer diskette (magnetic device), a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disc read-only memory (CDROM). In addition, the computer readable medium may even be paper or other suitable medium on which the program is printed, as the program may be electronically captured, via, for instance, optical scanning of the paper or other medium, then compiled, interpreted or otherwise processed in a suitable manner, if necessary, and then stored in a computer memory.
It is to be understood that portions of the present invention may be implemented in hardware, software, firmware, or a combination thereof. In the above-described embodiments, the various steps or methods may be implemented in software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, may be implemented using any one or combination of the following techniques, as is well known in the art: discrete logic circuits having logic gates for implementing logic functions on data signals, application specific integrated circuits having suitable combinational logic gates, programmable Gate Arrays (PGAs), field Programmable Gate Arrays (FPGAs), and the like.
In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In the description of the present invention, the meaning of "plurality" means at least two, for example, two, three, etc., unless specifically defined otherwise.
In the present invention, unless explicitly specified and limited otherwise, the terms "mounted," "connected," "secured," and the like are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; either directly or indirectly, through intermediaries, or both, may be in communication with each other or in interaction with each other, unless expressly defined otherwise. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art according to the specific circumstances.
While embodiments of the present invention have been shown and described above, it will be understood that the above embodiments are illustrative and not to be construed as limiting the invention, and that variations, modifications, alternatives and variations may be made to the above embodiments by one of ordinary skill in the art within the scope of the invention.
Claims (10)
1. A low power chip, comprising:
the device comprises a plurality of functional logic modules, a plurality of serial shift input output logic circuits and a test control module, wherein the functional logic modules are arranged in a power-off domain, each serial shift input output logic circuit is arranged corresponding to one functional logic module, and each serial shift input output logic circuit is suitable for outputting state data of the corresponding functional logic module to the test control module;
the low-power consumption control circuit is configured to control a first data transmission channel between the data verification module and the test control module to be opened under the condition that the chip enters a low-power consumption maintenance state, so that the test control module integrates state data of a corresponding functional logic module through at least part of serial shift input/output logic circuits, then sends the integrated state data to the data verification module through the first data transmission channel, and the data verification module is configured to verify the integrated state data to generate a verification code and send the integrated state data and the verification code to the maintenance memory for storage.
2. The low power chip of claim 1, wherein the low power control circuit is further configured to control a second data transmission channel between the data verification module and the test control module to be opened so that the data verification module transmits the verified state data to the test control module through the second data transmission channel in a case that the chip exits the low power holding state, and the test control module is further configured to integrate the verified state data and guide the integrated state data into the corresponding serial shift input output logic circuit so that the corresponding functional logic module is invoked.
3. The low power chip of claim 1 or2, further comprising: and the functional safety processing module is suitable for processing the error reporting of the chip safety function and configuring whether the data checking module works or not.
4. The low power consumption chip as claimed in claim 3, wherein a first gate is provided on the first data transmission channel, a first end of the first gate is connected to a first output end of the test control module, a second end of the first gate is connected to an output end of any one of the functional logic modules, a third end of the first gate is connected to a first input end of the data verification module, and the low power consumption control circuit controls the first end and the third end of the first gate to communicate with each other when the chip enters a low power consumption holding state, so that the test control module transmits the integrated status data to the data verification module through the first data transmission channel.
5. The low power chip of claim 4, wherein the low power control circuit is further configured to, in a case where the chip is in a normal operation state, control the second terminal and the third terminal of the first gate to communicate if the data verification module is configured to be in a stop operation state, so that each functional logic module sends corresponding logic data to the holding memory to store, and control a third data transmission channel between the data verification module and each functional logic module to open, so that each functional logic module invokes the logic data stored in the holding memory.
6. The low power chip of claim 5, wherein the third data transmission channel is provided with a first and gate, a first input terminal of the first and gate is connected to a first output terminal of the data verification module, a second input terminal of the first and gate is connected to a memory input/output control terminal of the low power control circuit after being inverted, and output terminals of the first and gate are respectively connected to input terminals of respective functional logic modules,
under the condition that the chip is in a normal working state, the first AND gate is in an on state under the control of the low-power consumption control circuit;
and under the control of the low-power-consumption control circuit, the first AND gate is in a closed state under the condition that the chip enters a low-power-consumption holding state.
7. The low power chip of claim 2, wherein the second data transmission channel is provided with a second and gate, a first input terminal of the second and gate is connected to a first output terminal of the data verification module, a second input terminal of the second and gate is connected to a memory input/output control terminal of the low power control circuit, and an output terminal of the second and gate is connected to a first input terminal of the test control module, wherein, in a case that the chip exits from the low power holding state, the second and gate is in an on state under the control of the low power control circuit.
8. The low power chip of claim 1 or2, wherein the functional logic module comprises:
the first input end and the second input end of the third AND gate are used as input ends of the functional logic module, and the output end of the third AND gate is connected with the corresponding serial shift input/output logic circuit;
the first input end of the first NAND gate is connected with the output end of the third AND gate, the second input end of the first NAND gate is connected with the serial shift input output logic circuit, and the output end of the first NAND gate is connected with the serial shift input output logic circuit;
a first or gate, a first input end of which is connected with a first input end of the third and gate, and a second input end of which is connected with the serial shift input output logic circuit;
the first input end of the fourth AND gate is connected with the output end of the first OR gate, the second input end of the fourth AND gate is connected with the serial shift input output logic circuit, and the output end of the fourth AND gate is connected with the serial shift input output logic circuit;
the first input end of the second OR gate is connected with the first input end of the fourth AND gate, the second input end of the second OR gate is connected with the serial shift input output logic circuit, and the output end of the second OR gate is used as the output end of the functional logic module.
9. The low power chip of claim 8, wherein the serial shift input-output logic circuit comprises:
the first input end of the second gating device is connected with the output end of the third AND gate, and the second input end of the second gating device is used as the scanning input end of the serial shift input-output logic circuit;
the input end of the first trigger is connected with the output end of the second gating device, and the output end of the first trigger is connected with the second input end of the first NAND gate;
the first input end of the third gating device is connected with the output end of the first NAND gate, and the second input end of the third gating device is connected with the output end of the first trigger;
the input end of the second trigger is connected with the output end of the third gating device, and the output end of the second trigger is connected with the second input end of the fourth AND gate;
the first input end of the fourth gating device is connected with the output end of the fourth AND gate, and the second input end of the fourth gating device is connected with the output end of the second trigger;
the input end of the third trigger is connected with the output end of the fourth gate, and the output end of the third trigger is connected with the second input end of the second OR gate and serves as the output end of the serial shift input-output logic circuit;
the enabling end of the second gating device, the enabling end of the third gating device and the enabling end of the fourth gating device are connected and are suitable for receiving enabling signals; the clock end of the first trigger, the clock end of the second trigger and the clock end of the third trigger are connected and are suitable for receiving clock signals.
10. An electronic device comprising a low power chip according to any of claims 1-9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311446113.XA CN117171082B (en) | 2023-11-02 | 2023-11-02 | Low-power consumption chip and electronic equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311446113.XA CN117171082B (en) | 2023-11-02 | 2023-11-02 | Low-power consumption chip and electronic equipment |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN117171082A true CN117171082A (en) | 2023-12-05 |
| CN117171082B CN117171082B (en) | 2024-01-26 |
Family
ID=88943514
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202311446113.XA Active CN117171082B (en) | 2023-11-02 | 2023-11-02 | Low-power consumption chip and electronic equipment |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN117171082B (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107290650A (en) * | 2017-07-17 | 2017-10-24 | 青岛海信电器股份有限公司 | BIST logic circuit, low-power chip, the method for testing of memory and electronic equipment |
| CN113656232A (en) * | 2021-08-23 | 2021-11-16 | 北京炬力北方微电子股份有限公司 | System level testing device of SOC chip high-speed serial differential bus |
| CN115278143A (en) * | 2022-05-23 | 2022-11-01 | 北京航宇创通技术股份有限公司 | Method for realizing CML digital video interface based on FPGA |
-
2023
- 2023-11-02 CN CN202311446113.XA patent/CN117171082B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107290650A (en) * | 2017-07-17 | 2017-10-24 | 青岛海信电器股份有限公司 | BIST logic circuit, low-power chip, the method for testing of memory and electronic equipment |
| CN113656232A (en) * | 2021-08-23 | 2021-11-16 | 北京炬力北方微电子股份有限公司 | System level testing device of SOC chip high-speed serial differential bus |
| CN115278143A (en) * | 2022-05-23 | 2022-11-01 | 北京航宇创通技术股份有限公司 | Method for realizing CML digital video interface based on FPGA |
Also Published As
| Publication number | Publication date |
|---|---|
| CN117171082B (en) | 2024-01-26 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN108020821B (en) | Phased array radar antenna beam control circuit detection system and implementation method thereof | |
| US6502212B1 (en) | Method and apparatus for bus parameter optimization using probes of system configurations | |
| US10598728B2 (en) | Scan chain circuit supporting logic self test pattern injection during run time | |
| KR101149270B1 (en) | Systems and methods for testing integrated circuit devices | |
| US20040088630A1 (en) | Integrated circuit device | |
| EP0898284B1 (en) | Semiconductor memory having a test circuit | |
| WO2022142528A1 (en) | Functionally safe switching value output module and diagnostic processing method | |
| KR20060117367A (en) | Integrated post-amplifier, laser driver, and controller | |
| US7872488B2 (en) | Tester for testing semiconductor device | |
| CN108062267A (en) | Configurable register file self-testing method and generating device | |
| US20230195994A1 (en) | Chip design verification system, chip design verification method, and computer readable recording media with stored program | |
| US7734974B2 (en) | Serial scan chain control within an integrated circuit | |
| KR100925371B1 (en) | Test Circuit of Semiconductor Integrated Circuit | |
| US20030120989A1 (en) | Method and circuit to implement double data rate testing | |
| CN117171082B (en) | Low-power consumption chip and electronic equipment | |
| US20030226079A1 (en) | Scan-path flip-flop circuit for integrated circuit memory | |
| JPH1082839A (en) | Diagnostic system for electronic device using fpga | |
| US8209571B2 (en) | Valid-transmission verifying circuit and a semiconductor device including the same | |
| US20230393198A1 (en) | Circuit arrangement for validation of operation of a logic module in a multipower logic architecture and corresponding validation method | |
| CN101944392A (en) | Test system of PROM | |
| US7839717B2 (en) | Semiconductor device with reduced standby failures | |
| CN105335177A (en) | Test method, test device and test system of embedded system | |
| KR100404020B1 (en) | Circuit arrangement for burn-in-test of a semiconductor module | |
| CN115562925B (en) | Chip interface test system, method, device and storage medium | |
| TWI507843B (en) | Control method and electronic device utilizing the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |