CN117156006A - Data route control architecture of network on chip - Google Patents
Data route control architecture of network on chip Download PDFInfo
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- CN117156006A CN117156006A CN202311435181.6A CN202311435181A CN117156006A CN 117156006 A CN117156006 A CN 117156006A CN 202311435181 A CN202311435181 A CN 202311435181A CN 117156006 A CN117156006 A CN 117156006A
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Abstract
The present invention relates to the field of embedded processors, and in particular, to a data routing control architecture for a network on chip. Comprising the following steps: an input port and an output port; the input port interacts with the source node, and the output port interacts with the destination node; wherein the input port comprises: input buffering, decoding module, input state machine and read enable logic; the output port includes: a round robin arbiter, an output state machine, packet level transmission logic, stations and fixed priorities; the invention processes the data packets with different data packet formats uniformly, encapsulates the data packets into a universal IP module without designing a plurality of processing units, and has stronger universality only by carrying out instantiation according to the number of virtual channels when the codes are realized; meanwhile, the problem of data flower arrangement of the same virtual channel of different source nodes is solved, and the efficiency of data processing is improved.
Description
Technical Field
The present invention relates to the field of embedded processors, and in particular, to a data routing control architecture for a network on chip.
Background
With the increasing number of processor chips, system On Chip (SOC) has shown a trend from multi-core to many-core. The interconnection between processor cores needs to have the advantages of high throughput, low delay and strong expandability, but the traditional interconnection architecture based on the shared bus is difficult to meet the current requirements, and the Network On Chip (NOC) technology for performing data communication by using a crossbar is a new on-Chip communication architecture because of the advantages of strong expandability, high parallelism and the like.
Disclosure of Invention
The invention aims to provide a data routing control architecture of a network on chip, solves the problem of data transmission between core and non-core hardware units on chip, and provides a feasibility scheme of communication on chip; the problem of unified processing of the data packets of different virtual channels is solved, and the universality is improved; the method solves the problem of data flower arrangement of different virtual channels, facilitates the processing of a destination node, and improves the efficiency of data processing.
In order to solve the above technical problems, the present invention provides a data routing control architecture of a network on chip, including: an input port and an output port; the input port interacts with the source node, and the output port interacts with the destination node;
wherein the input port comprises: input buffering, decoding module, input state machine and read enable logic; the input buffer is in the form of a first-in first-out FIFO (first-out FIFO) for buffering the data from the source node; the data channels between the network on chip and each node have only one physical channel, but are divided into a plurality of virtual channels, each virtual channel represents one type of data, and each virtual channel is provided with a group of write enabling signals and read enabling signals; the decoding module is used for decoding the data in the input buffer, acquiring a destination node of the data according to a decoding result, and initiating a Req request to the destination node (namely, the decoding module can acquire the destination node of the data according to DstID and TYPE fields of side information of the buffered data; the decoding is effective, namely, the Req request can be initiated to the destination node); the input end state machine is used for controlling the transmission of the source node virtual channel data request; the read enabling logic is used for controlling when the input port sends a read enabling signal to the source node, and the available depth value of the FIFO in the input port can be obtained according to the count of the read enabling signal by the source node;
the output port includes: a round robin arbiter, an output state machine, packet level transmission logic, stations and fixed priorities; the round-robin arbiter is used for arbitrating requests initiated by the same virtual channel from different source nodes, as long as the FIFO is not empty, each beat has requests to participate in arbitration and generates an arbitration result when the beat; the output end state machine is used for controlling the priority of the round robin arbiter to be switched according to the state of the output end state machine after the transmission of the data packet of one source node is completed, and transmitting the data packet of the next source node (namely, the round robin arbiter arbitrates the request of the same virtual channel from different source nodes, and only if the data of the last source node is arbitrated, the priority is switched if the transmission of the whole packet data of the source node is completed); the packet-level transmission logic realizes the whole packet transmission of data under the control of an output end state machine; in particular, once a request of a source node is arbitrated by the round robin arbiter, only the request of the source node participates in arbitration before the source node transmits complete packet data, and the requests of other request sources cannot participate in arbitration (namely, when the round robin arbiter arbitrates the request of the last source node, the packet-level transmission logic can shield the requests of other source nodes according to the arbitration result; the station is used for ensuring that data transmission is designed in a pipelining way; the fixed priority is used for arbitrating the data output by the stations with different virtual channels of the output port, and the arbitrated virtual channel data is transmitted to the destination node through the physical channel.
Preferably, the input buffer depth is 8, and the width is 328 bits; wherein the low 288 bits are data bits, containing 256 bits of data and 32 bits of ECC check; the upper 40 bits are sideband information, and include even check information of SrcID source node, dstID destination node, data TYPE TYPE (data virtual channel TYPE), MAF number and sideband information.
Preferably, the control architecture has three packet formats, the first packet format has only 1 flow control unit, and the packet format contains sideband information and data; the second data packet format comprises 5 flow control units, specifically 1 packet header and 4 data, wherein the packet header only comprises sideband information without data, and the data bit is all 0; the data does not contain sideband information and only contains data, and the sideband information bit is all 0; the third packet format contains 4 flow control units, each containing sideband information and data.
Preferably, the input state machine further comprises two states of arbitration and transmission; decoding the Req request in an arbitration state; in a transmission state, maintaining the Req request; and a counter is also arranged in the input end state machine and is used for counting the transmitted data.
Preferably, when the round robin arbiter of the output port outputs an arbitration grant signal to the input port, the read enable logic initiates a read pulse to the source node, and the source node adds 1 to the credit value every time the source node receives each pulse signal, and the source node initial credit value is the depth of the FIFO in the input port, and the generated signal is 1 to be valid, the read pointer of the FIFO adds 1.
Preferably, the flow design is specifically: the data packets from one source node need to be continuously transmitted before the data packets of the next source node are transmitted, and a station is arranged on each virtual channel of each node output port.
Preferably, the round robin arbiter is further provided with arbitration enable, which is defined as the request for the same virtual channel of different source nodes with credit, i.e. capable of writing data to the lower level station.
Preferably, the state and state jump conditions of the output end state machine and the input end state machine are the same, and the difference is different in meaning.
Preferably, the fixed priority is set to Data0> Data1> Data2, and the fixed priority is further provided with arbitration enable, wherein the arbitration enable is defined as that each virtual channel of the destination node has credit, i.e. the Data can be written into the internal buffer of the destination node.
Compared with the prior art, the invention has the following beneficial effects:
1. the invention processes the data packets with different data packet formats uniformly, encapsulates the data packets into a universal IP module without designing a plurality of processing units, and has stronger universality.
2. The whole packet data of the same virtual channel continuously passes through the platform to reach the output port, and cannot be subjected to flower arrangement by the data of the same virtual channel of different source nodes, so that the processing of a destination node is facilitated, and the data processing efficiency is improved.
Drawings
Fig. 1 is a schematic diagram of a classical router microarchitecture.
Fig. 2 is a schematic diagram of the overall data routing control architecture of the present invention.
Fig. 3 is a schematic diagram of an input port virtual channel of the present invention.
Fig. 4 is a schematic diagram of an output port virtual channel of the present invention.
Fig. 5 is a state diagram of the state machine of the present invention.
FIG. 6 is a diagram of round robin arbitration of the present invention.
Detailed Description
The invention is described in further detail below with reference to the drawings and the specific examples. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.
As shown in fig. 1, fig. 1 is a classical router micro-architecture, comprising 5 source nodes, 5 destination nodes, several input buffering and control logic and a crossbar. The overall architecture of the present invention refers to a classical router micro-architecture design.
As shown in fig. 2-4, an embodiment of the present invention provides a data routing control architecture of a network on chip, where the data routing control architecture includes a plurality of input port virtual channels shown in fig. 3 and output port virtual channels shown in fig. 4. The input port interacts with the source node and comprises an input buffer, a decoding module, an input end state machine and a read enabling logic; the output port interacts with the destination node, including round robin arbitration, output state machines, packet level transmission logic, stations, and fixed priorities.
An input buffer for buffering data from the source node in a first-in first-out (FIFO) format; the data channels between the network on chip and the nodes have only one physical channel, but are divided into a plurality of virtual channels, each virtual channel representing a type of data, and each virtual channel is provided with a set of write enable and read enable signals. Where src0_data0_fifo_empty represents a non-Empty signal of the input port FIFO, src02fab_data0_wr_en represents write enable initiated by the source node to the network-on-chip FIFO, and fab2src0_data0_rd_en represents read enable initiated by the network-on-chip to the source node. When the source node writes a datum to the FIFO, the write enable is active and the FIFO write pointer is incremented by 1; when the arbitration grant signal output by the round robin arbiter of the virtual channel at the output port is valid, the read enable of the FIFO is valid and the read pointer of the FIFO is incremented by 1.
The decoding module can know the destination node of the data according to the DstID and TYPE domain of the sideband information of the FIFO data; the decoding is valid, so that a Req request of a corresponding type can be initiated to the destination node, such as signals of Src02 dst0_Dat0_req in FIG. 3. For the second data packet, the packet head only contains sideband information without data, and the data bit is all 0; the data contains no sideband information and only data, the sideband information bit is all 0. Therefore, when the packet header decoding is valid, the Req request is latched by a register under the control of a state machine, and the Req request is valid all the time in a transmission state.
As shown in fig. 5, the input state machine controls the sending of virtual channel data requests from the source node, including both arbitration and transmission states. Decoding according to the side information in the arbitration state; in the transfer state, the latching request will not switch to the arbitration state until the counter expires, otherwise it remains in that state.
The round robin arbiter for each virtual channel of the output ports outputs an arbitration Grant signal, such as Dstj2Src0_Dat0_Grant in FIG. 3, to the input ports. The Fab2Src0_Data0_Rd_En signals generated after all arbitration grant signals pass through one OR gate are read pulses initiated to a source node, and the credit value is increased by 1 when the source node receives one pulse signal; meanwhile, when the pulse signal is 1, the read pointer of the FIFO is added with 1 and Src02 Dst0_Dat0 [327:0] is written into the station of the Data virtual channel corresponding to the output port.
As shown in fig. 6, the round robin arbiter arbitrates requests from the same virtual channel from different source nodes, as shown by the srci2dst0_data0_req1 signal. When Data can be written to the station, assuming that the input request is 3'b011, the arbiter beats the output arbitration Grant signal Dat0_Grant [2:0] as 3' b001. In the transmission state of the output end state machine, the arbitration grant signal is kept at 3' b001 until the whole packet data of the source node is transmitted, and the output end state machine can not jump to the arbitration state. At this time, the arbiter arbitrates the request of another source node, and the output arbitration grant signal is 3' b010. The arbitration grant signal is only 1, indicating that the data must be written to the station.
And the packet level transmission logic is used for realizing the switching priority after the transmission of the whole data packet is completed. Assuming that Req initiated from an input port to an output port is 3'b011 in an arbitration state, and an arbitration Grant signal Data0_Grant [2:0] output by the output port round robin arbiter is 3' b010; when the transmission is multi-beat data, in the transmission state, the arbitration grant signal output in the arbitration state is beaten one beat to generate a request enabling signal with the same bit width, at this time, the request enabling signal is also 3'b010, and the signal and the Req signal are bit-wise and then 3' b010. I.e. in the transmission state, only requests of the request source on arbitration in the arbitration state participate in the arbitration.
And the platform ensures that the data transmission is designed in a pipelining way. The bits corresponding to the arbitration Grant signal Dat0_Grant [2:0] of the round robin arbiter are Valid to indicate that Data may be written to the station, and the station Valid bit Dat0_Stage_valid is 1. When the station Valid bit Dat0_Stage_Valid is 0, no request to participate in arbitration is indicated. When the stage_Grant [ i ] is the arbitration result output by the fixed priority and is 1 effective, the Sr02Fab_Data0 [327:0] Data of the corresponding Data virtual channel station can be written into the destination node.
Fixed priority, arbitrating Data of different virtual channel stations of output ports, setting the fixed priority as Data0> Data1> Data2, and enabling arbitration as Dst0_Datai_Credit. When all the Data of the three virtual channels are useful, the whole packet Data of the Data1 is transmitted after the Data packet of the Data0 is transmitted, and finally the whole packet Data of the Data2 is transmitted. When the virtual channel data with high priority has no credit, the virtual channel data with low priority is transmitted at the moment; once the virtual channel data with high priority has credit, switching back to the virtual channel data with high priority for transmission.
The invention processes the data packets with different data packet formats uniformly, encapsulates the data packets into a universal IP module without designing a plurality of processing units, and has stronger universality only by carrying out instantiation according to the number of virtual channels when the codes are realized; meanwhile, the problem of data flower arrangement of the same virtual channel of different source nodes is solved, and the efficiency of data processing is improved.
The above description is only illustrative of the preferred embodiments of the present invention and is not intended to limit the scope of the present invention, and any alterations and modifications made by those skilled in the art based on the above disclosure shall fall within the scope of the appended claims.
Claims (9)
1. A data routing control architecture for a network on chip, comprising: an input port and an output port; the input port interacts with the source node, and the output port interacts with the destination node;
wherein the input port comprises: input buffering, decoding module, input state machine and read enable logic; the input buffer is in the form of a first-in first-out FIFO (first-out FIFO) for buffering the data from the source node; the data channels between the network on chip and each node have only one physical channel, but are divided into a plurality of virtual channels, each virtual channel represents one type of data, and each virtual channel is provided with a group of write enabling signals and read enabling signals; the decoding module is used for decoding the data in the input buffer, acquiring a destination node of the data according to a decoding result, and initiating a Req request to the destination node; the input end state machine is used for controlling the transmission of the source node virtual channel data request; the read enabling logic is used for controlling when the input port sends a read enabling signal to the source node, and the available depth value of the FIFO in the input port can be obtained according to the count of the read enabling signal by the source node;
the output port includes: a round robin arbiter, an output state machine, packet level transmission logic, stations and fixed priorities; the round-robin arbiter is used for arbitrating requests initiated by the same virtual channel from different source nodes, as long as the FIFO is not empty, each beat has requests to participate in arbitration and generates an arbitration result when the beat; the output end state machine is used for controlling the priority of the round robin arbiter according to the state of the output end state machine after the transmission of the data packet of one source node is completed, and transmitting the data packet of the next source node; the packet-level transmission logic realizes the whole packet transmission of data under the control of an output end state machine; in particular, once a request of a source node is arbitrated by a round robin arbiter, only the request of the source node participates in arbitration before the source node transmits complete packet data; the station is used for ensuring that data transmission is designed in a pipelining way; the fixed priority is used for arbitrating the data output by the stations with different virtual channels of the output port, and the arbitrated virtual channel data is transmitted to the destination node through the physical channel.
2. The network-on-chip data routing control architecture of claim 1, wherein the input buffer depth is 8 and the width is 328 bits; wherein the low 288 bits are data bits, containing 256 bits of data and 32 bits of ECC check; the upper 40 bits are sideband information, and comprise even check information of SrcID source node, dstID destination node, data virtual channel TYPE TYPE, MAF number and sideband information.
3. A network-on-chip data routing control architecture as claimed in claim 2, wherein the control architecture has three packet formats, the first packet format having only 1 flow control unit, the packet format containing sideband information and data; the second data packet format comprises 5 flow control units, specifically 1 packet header and 4 data, wherein the packet header only comprises sideband information without data, and the data bit is all 0; the data does not contain sideband information and only contains data, and the sideband information bit is all 0; the third packet format contains 4 flow control units, each containing sideband information and data.
4. The network-on-chip data routing control architecture of claim 2, wherein the input state machine further comprises two states, arbitrated and transmitted; decoding the Req request in an arbitration state; in a transmission state, maintaining the Req request; and a counter is also arranged in the input end state machine and is used for counting the transmitted data.
5. The network-on-chip data routing control architecture of claim 1, wherein the read enable logic, when the round robin arbiter of the output port outputs an arbitration grant signal to the input port, initiates a read enable pulse to a source node, the source node adds 1 to the credit value for each pulse received by the source node, the source node initial credit value is the depth of the FIFO in the input port, and the generated signal is 1 to be valid, the read pointer of the FIFO adds 1 to the read pointer of the FIFO.
6. The network-on-chip data routing control architecture of claim 1, wherein the pipelined design is specifically: the data packets from one source node need to be continuously transmitted before the data packets of the next source node are transmitted, and a station is arranged on each virtual channel of each node output port.
7. A network-on-chip data routing control architecture as recited in claim 1, wherein the round robin arbiter is further provided with arbitration enables requests for the same virtual channel defined as different source nodes to have credits, i.e. to be able to write data to a lower level station.
8. The network-on-chip data routing control architecture of claim 4, wherein the output state machine is identical to the input state machine in terms of state and state jump conditions, except for meaning.
9. The network-on-chip Data routing control architecture of claim 1, wherein the fixed priority is set to Data0> Data1> Data2, and wherein the fixed priority is further provided with arbitration enable defined as the destination node's respective virtual channel has credits, i.e., internal buffering capable of writing Data to the destination node.
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