CN117155382A

CN117155382A - Self-starting charge pump based on current steering

Info

Publication number: CN117155382A
Application number: CN202311168807.1A
Authority: CN
Inventors: 宋鑫宇; 孙玉龙; 徐玉婷; 杨煜
Original assignee: Wuxi Zhongwei Yixin Co Ltd
Current assignee: Wuxi Zhongwei Yixin Co Ltd
Priority date: 2023-09-11
Filing date: 2023-09-11
Publication date: 2023-12-01

Abstract

The invention relates to a self-starting charge pump based on current steering. It comprises the following steps: a current steering circuit for converting a phase difference signal between the clock signal up and the clock signal dn into a current signal and outputting the current signal; the mirror image bias circuit comprises a bias voltage first generation circuit and a bias voltage second generation circuit which is adaptively and electrically connected with the bias voltage first generation circuit, wherein the bias voltage first generation circuit generates bias voltage vbn based on a reference current ibg, and the bias voltage second generation circuit generates bias voltage vbp based on a voltage Vout of an output end of the current steering circuit; when the current steering circuit is configured to enter an operating state based on the bias voltage vbn and the bias voltage vbp, the potential of the node E formed by the adaptive connection of the first bias voltage generating circuit and the second bias voltage generating circuit is clamped to be consistent with the potential of the voltage Vout. The invention effectively inhibits the influence of non-ideal factors and improves the matching property and stability of the output current.

Description

Self-starting charge pump based on current steering

Technical Field

The invention relates to a charge pump, in particular to a self-starting charge pump based on current steering.

Background

A phase locked loop is a circuit device capable of generating stable frequency, and is widely used in digital circuits and communication systems. A typical phase-locked loop circuit includes a phase frequency detector, a charge pump, a loop filter, an oscillator, and a feedback frequency divider, where the charge pump circuit is a key circuit of the phase-locked loop and is configured to convert a pulse signal output by the phase frequency detector into a current signal, and the current signal charges and discharges the loop filter circuit, thereby adjusting an output clock frequency of the oscillator.

Clock jitter is the most critical performance index of a phase-locked loop circuit, and mismatch or fluctuation of output current of a charge pump affects the quality of an output clock of an oscillator, so that the output current of the charge pump circuit must have high matching property and stability.

In order to improve the matching property and stability of the output current of the charge pump, the following measures are mainly adopted in the prior art: one is to improve the current mirror circuit, for example, increase the cascade mode of the common gate device to improve the current matching by increasing the device size in the current mirror; another is to improve the output circuit of the charge pump, for example, the voltage of the output end of the charge pump is clamped by adding an operational amplifier, and the influence of non-ideal factors of parasitic devices is reduced by a current steering structure, so that the stability of the output current is improved.

Based on the current method for improving the matching property and stability of the output current of the charge pump, the charge pump still has larger mismatch, and the introduction of an additional operational amplifier may cause the failure of stable starting during power-up. Therefore, it is very interesting to study how to realize a higher performance and more stable charge pump with a simpler structure for practical applications of the chip.

Disclosure of Invention

The invention aims to overcome the defects in the prior art and provide a self-starting charge pump based on current steering, which effectively inhibits the influence of non-ideal factors and improves the matching property and stability of output current.

According to the technical scheme provided by the invention, the self-starting charge pump based on current steering comprises:

a current steering circuit for converting a phase difference signal between the clock signal up and the clock signal dn into a current signal and outputting the current signal;

the mirror image bias circuit comprises a bias voltage first generating circuit and a bias voltage second generating circuit which is adaptively and electrically connected with the bias voltage first generating circuit,

the bias voltage first generating circuit generates bias voltage vbn based on reference current ibg, and the bias voltage second generating circuit generates bias voltage vbp based on voltage Vout of the current steering circuit output terminal;

When the current steering circuit is configured to enter an operating state based on the bias voltage vbn and the bias voltage vbp, the potential of the node E formed by the adaptive connection of the first bias voltage generating circuit and the second bias voltage generating circuit is clamped to be consistent with the potential of the voltage Vout.

The self-starting charge pump further comprises a soft start circuit adaptively connected with the current steering circuit and the mirror bias circuit, wherein,

the soft start circuit works under the bias voltage vbn generated by the mirror image bias circuit and the bias voltage vbp;

the working state of the current steering circuit comprises a power-on adjusting stage and a frequency locking stage, wherein the power-on adjusting stage is used for configuring a soft start circuit to load current istp to the current steering circuit so as to assist in raising voltage Vout at the output end of the current steering circuit based on the current istp;

and based on the auxiliary raised voltage Vout, configuring a bias voltage second generation circuit to generate bias voltage vbp required by normal operation of the driving current steering circuit.

The soft start circuit also draws current from within the current steering circuit to form a current istn flowing from the current steering circuit into the soft start circuit;

when the current steering circuit enters a frequency locking stage, the mirror bias circuit loads a frequency locking clamping voltage into the soft start circuit.

The bias voltage second generation circuit includes an operational amplifier AMP2, wherein,

the inverting terminal of the operational amplifier AMP2 is connected with the voltage Vout, and the non-inverting terminal of the operational amplifier AMP2 is connected with the node E and the frequency locking clamping voltage generating circuit in an adapting way;

the output end of the operational amplifier AMP2 generates bias voltage vbp, the output end of the operational amplifier AMP2 is also connected with the gate end of the PMOS tube PM6, and the source end of the PMOS tube PM6 is connected with a power supply vs;

the drain end of the PMOS tube PM6 is connected with the source end of the PMOS tube PM7, the drain end of the PMOS tube PM7 is connected with the node E, and the grid end of the PMOS tube PM7 is connected with the power supply vs;

the frequency locked clamp voltage applied to the soft start circuit is generated by a frequency locked clamp voltage generating circuit.

The soft start circuit comprises a current generating part for generating a current istp and a current extracting part for extracting a current istn, wherein,

the current generation part comprises an NMOS tube NS3, an NMOS tube NS2, a PMOS tube PM3, a PMOS tube PM4 and a PMOS tube PM5;

the source end of the PMOS tube PM4 and the source end of the PMOS tube PM3 are connected with a power supply vs, and the drain end of the NMOS tube NS3 is connected with a bias voltage vbp;

the gate end of the PMOS tube PM4, the gate end of the PMOS tube PM3 are connected with the source end of the NMOS tube NS3 and the drain end of the NMOS tube NS 2;

The drain end of the PMOS tube PM4 is connected with the source end of the PMOS tube PM5, and the drain end of the PMOS tube PM5 is connected with the source end of the NMOS tube NS2, the output end of the frequency locking clamping voltage generating circuit and the current extraction part in an adaptive manner;

the source end of the PMOS tube PM3 is adaptively connected with a current steering circuit so as to load current istp to the current steering circuit;

in the power-on regulation stage, the NMOS transistor NS2 is turned on and the NMOS transistor NS3 is turned off;

in the frequency locking stage, the NMOS transistor NS2 is turned off and the NMOS transistor NS3 is turned on.

The frequency locked clamp voltage generating circuit includes an NMOS transistor NS1, wherein,

the drain end of the NMOS tube NS1 is connected with the node E, and the source end of the NMOS tube NS1 is connected with the source end of the NMOS tube NS2, the drain end of the PMOS tube PM5 and the current extraction part in an adaptive manner;

the NMOS transistor NS1 is turned on in the frequency locking stage, and the on states of the NMOS transistor NS1 and the NMOS transistor NS3 are all regulated by the same signal selp.

The current steering circuit comprises a conversion part circuit for converting a phase difference signal into a current signal, an upper current source which is connected with the conversion part circuit in an adapting way, and a lower current source which is connected with the conversion part circuit in an adapting way,

the conversion part circuit comprises a PMOS tube PM1 for receiving a clock signal up, a PMOS tube PM2 for receiving a clock signal upn, an NMOS tube NM2 for receiving a clock signal dn, and an NMOS tube NM1 for receiving a clock signal dnn, wherein the clock signal upn is an inverted clock signal of the clock signal up, and the clock signal dnn is a directional clock signal of the clock signal dn;

The grid electrode of the PMOS tube PM1 is connected with a clock signal up, the grid electrode of the PMOS tube PM2 is connected with a clock signal upn, the source electrode of the PMOS tube PM1 and the source electrode of the PMOS tube PM2 are connected with an upper current source in an adaptive manner, so that a node A is formed after connection, and a current istp generated by a soft start circuit is loaded to the node A;

the gate end of the NMOS tube NM1 is connected with a clock signal dnn, the gate end of the NMOS tube NM2 is connected with a clock signal dn, the source end of the NMOS tube NM1 and the source end of the NMOS tube NM2 are connected with a lower current source in an adapting mode, so that a node B is formed after connection, and when current is extracted, a current istn flows from the node B to a soft start circuit;

the drain electrode of the PMOS tube PM1 is connected with the drain electrode of the NMOS tube NM1 to form a node C after connection;

the drain end of the PMOS tube PM2 is connected with the drain end of the NMOS tube NM2 to form a node D after connection, and an output end out of the current steering circuit is formed based on the node D;

the circuit further comprises a node clamping circuit for clamping the potential clamp of the node C and the potential clamp of the node D, wherein the node clamping circuit comprises an operational amplifier AMP1, the non-inverting terminal of the operational amplifier AMP1 is connected with the node D, and the inverting terminal of the operational amplifier AMP1 and the output terminal of the operational amplifier AMP1 are connected with the node C.

And a conversion protection circuit for reducing the effect of channel charge injection and clock feedthrough, wherein,

the conversion protection circuit comprises a capacitor PC1, a capacitor PC2, a capacitor NC1 and a capacitor NC2, wherein a first end of the capacitor PC1 is connected with a gate end of the PMOS tube PM1, and a second end of the capacitor PC1 is connected with a node D;

the first end of the capacitor PC2 is connected with the gate end of the PMOS tube PM2, and the second end of the capacitor PC2 is connected with the node C;

the first end of the capacitor NC1 is connected with the gate end of the NMOS tube NM1, and the second end of the capacitor NC1 is connected with the node D;

the first end of the capacitor NC2 is connected to the gate end of the NMOS transistor NM2, and the second end of the capacitor NC2 is connected to the node C.

The capacitor PC1 and the capacitor PC2 are formed based on PMOS tubes, the capacitor NC1 and the capacitor NC2 are formed based on NMOS tubes, wherein,

when forming the capacitor PC1 and the capacitor PC2 based on the PMOS tube, configuring the grid end of the PMOS tube as a first end corresponding to the capacitor PC1 and the capacitor PC2, and connecting the source end of the PMOS tube and the drain end of the PMOS tube to each other and configuring the source end of the PMOS tube as a second end corresponding to the capacitor PC1 and the capacitor PC 2;

when forming the capacitors NC1 and NC2 based on the NMOS tube, the grid end of the NMOS tube is configured as a first end corresponding to the capacitors NC1 and NC2, and the source end of the NMOS tube and the drain end of the NMOS tube are connected with each other and are configured as a second end corresponding to the capacitors NC1 and NC 2.

The PMOS tubes forming the capacitor PC1 and the capacitor PC2 have a first width-to-length ratio of a conducting channel;

NMOS transistors forming a capacitor NC1 and a capacitor NC2 have a second width-to-length ratio of a conducting channel;

the PMOS tube PM1 and the PMOS tube PM2 have a third width-to-length ratio of the conducting channel;

the NMOS tube NM1 and the NMOS tube NM2 have a fourth width-to-length ratio of a conducting channel;

the first aspect ratio of the conductive channel is half the third aspect ratio of the conductive channel, and the second aspect ratio of the conductive channel is half the fourth aspect ratio of the conductive channel.

The invention has the advantages that: compared with the existing structure, the self-starting charge pump based on current steering has the advantages that the self-starting charge pump based on current steering is simple in structure, the influence of non-ideal factors of a switch and a parasitic device is effectively restrained, the matching performance of output current is improved, a soft starting circuit is introduced, the stability of the charge pump circuit is improved, and the self-starting charge pump based on current steering can be applied to a high-speed low-jitter phase-locked loop module and the output quality is effectively improved.

Drawings

FIG. 1 is a block diagram of a self-priming charge pump according to one embodiment of the present invention.

Fig. 2 is a schematic circuit diagram of a self-starting charge pump according to an embodiment of the present invention.

Detailed Description

The invention will be further described with reference to the following specific drawings and examples.

In order to effectively suppress the influence of non-ideal factors of the switch and the parasitic device and improve the matching and stability of the output current, in one embodiment of the present invention, the self-starting charge pump includes:

As can be seen from the above description, the charge pump may employ a current steering circuit, and the phase difference signal between the clock signal up and the clock signal dn may be converted into a current signal by the current steering circuit and output, and in particular, the implementation manner and process of converting the phase difference signal into the current signal may be consistent with the existing one. The non-ideal factor influence of the switch and the parasitic device is effectively restrained, specifically, the non-ideal factor caused by the switch and the parasitic device in the current steering circuit is restrained, and the specific non-ideal situation will be described below.

The mirror bias circuit can provide bias voltages required by the current steering circuit during operation, wherein the bias voltages provided by the mirror bias circuit comprise bias voltages vbn and vbp, the bias voltages vbn are generated based on a reference current ibg, the bias voltages vbp are generated based on a voltage vout at the output end of the current steering circuit, and the condition of the reference current ibg can be consistent with the prior art. In specific implementation, the output end of the current steering circuit outputs the converted current signal, but the voltage Vout corresponding to the output current signal can be obtained by adopting a technical means commonly used in the technical field. The bias voltage vbn and the bias voltage vbp generated by the mirror bias circuit are loaded to the current steering circuit, and specifically, the current steering circuit is configured to enter an operating state based on the bias voltage vbn and the bias voltage vbp, and the current steering circuit enters the operating state as will be described in detail below.

Within the mirror bias circuit, a bias voltage first generating circuit is adapted to be connected with a bias voltage second generating circuit to form a node E when connected. In order to realize the matching with the output current of the current steering circuit, in one embodiment of the invention, the potential of the node E is clamped to be consistent with the potential of the voltage Vout, namely, the potential of the node E is equal to the potential of the voltage Vout, at the moment, the current mismatch caused by the groove length modulation effect of a current source device in the current steering circuit can be eliminated, and the stability of the output signal of the current steering circuit is improved; the specific case of current source devices within the current steering circuit will be specified in the following description.

In one embodiment of the invention, the self-starting charge pump further comprises a soft start circuit adapted to connect with the current steering circuit and the mirror bias circuit, wherein,

As is clear from the above description, in the conventional charge pump, there is a case where the current steering circuit is not stably started. According to the operating characteristics of the current steering circuit, the operating state can be divided into a power-on adjustment stage and a frequency locking stage. When the current steering circuit is started, the power-on regulation stage is first entered, and generally, when the reference current ibg is loaded to the mirror bias circuit, the mirror bias circuit loads the generated bias voltage vbn and the bias voltage vbp to the current steering circuit, and at this time, the current steering circuit enters the power-on regulation stage.

A block diagram of one embodiment of a self-starting charge pump is shown in fig. 1, which also includes a soft start circuit adapted to couple with the mirror bias circuit and the current steering circuit in order to allow the current steering circuit to start steadily. In the figure, the bias voltage vbn and the bias voltage vbp generated by the mirror bias circuit are also loaded to the soft start circuit, and the bias voltage vbn and the bias voltage vbp are loaded to the soft start circuit, so that the normal operation of the soft start circuit is mainly satisfied.

Specifically, during the power-up regulation phase, the soft-start circuit may load current istp into the current steering circuit. Typically, the voltage Vout at the output of the current steering circuit is at 0 level before entering the power-up regulation phase. When the current istp is loaded into the current steering circuit, the voltage Vout at the output end of the current steering circuit is larger than 0 level, at this time, the bias voltage second generation circuit can generate bias voltage vbp based on the voltage state of the voltage Vout, and the voltage state of the bias voltage vbp can meet the requirement of the current steering circuit. The bias voltage vbp generated by the bias voltage second generation circuit is an analog voltage.

In practice, the output end of the current steering circuit is generally connected with a capacitor, and the current signal converted and output by the current steering circuit charges the connected capacitor. When the current istp is loaded to the current steering circuit, the capacitor is charged through the current istp, and the voltage Vout at the output end of the current steering circuit can be raised after the capacitor is charged.

In addition, the soft start circuit also draws current from within the current diversion circuit to form a current istn flowing from the current diversion circuit into the soft start circuit;

Specifically, in the power-on adjustment stage and the frequency locking stage, the magnitude of the current istn is equal to that of the current istp, and at this time, a current loop can be formed between the soft start circuit and the current steering circuit, so that the specific working state of the current steering circuit cannot be affected after the current istp is loaded into the current steering circuit.

The mirror bias circuit loads the soft start circuit with a frequency lock clamp voltage upon entering the frequency lock phase will be explained in detail below.

A schematic circuit diagram of the self-starting charge pump in fig. 1 is shown in fig. 2, and the self-starting charge pump of the present invention will be described in detail with reference to the schematic circuit diagram in fig. 2.

In fig. 2, the bias voltage first generating circuit includes an NMOS transistor NM6, an NMOS transistor NM7, an NMOS transistor 10, and an NMOS transistor NM11, wherein,

the drain end of the NMOS tube NM11 is connected with the gate end of the NMOS tube NM10 and the gate end of the NMOS tube NM6, the source end of the NMOS tube NM11 is connected with the drain end of the NMOS tube NM10, the source end of the NMOS tube NM7 is connected with the drain end of the NMOS tube NM6, and the source ends of the NMOS tube NM10 and the NMOS tube NM6 are grounded gs;

The gate end of the NMOS tube NM11 and the gate end of the NMOS tube NM7 are connected with a power supply vs;

the reference current ibg is loaded to the drain terminal of the NMOS transistor NM11 and the gate terminal of the NMOS transistor NM10, and the bias power vbn is generated and output through the gate terminal of the NMOS transistor NM 6;

the drain terminal of the NMOS transistor NM7 is connected to the bias second voltage generating circuit to form a node E based on a position where the drain terminal of the NMOS transistor NM7 is connected to the bias second voltage generating circuit.

In addition, the bias voltage second generation circuit includes an operational amplifier AMP2, wherein,

Specifically, after the drain terminal of the PMOS PM7 and the drain terminal of the NMOS NM7 are connected to each other, the node E is formed. The power supply vs can be in the existing common mode, and the output power voltage of the power supply vs can be determined according to the requirement, so that the working requirement of the whole self-starting charge pump can be met.

In operation, the reference current ibg provided by the external circuit is first applied to the bias voltage first generating circuit, and the bias voltage first generating circuit generates the bias voltage vbn first, and generally, when the reference current ibg is stable, the bias voltage vbn generated by the bias voltage first generating circuit is unchanged.

As can be seen from the above description, the voltage Vout at the output terminal of the current steering circuit is at 0 level during power-up, and therefore, based on the characteristics of the operational amplifier AMP2, the bias voltage vbp generated at the output terminal of the operational amplifier AMP2 is pulled up to be in a high voltage state, and at this time, the bias voltage vbp in the high voltage state cannot meet the operation requirement of the current source in the current steering circuit.

After power-on, when the voltage Vout at the output end of the current steering circuit automatically rises or rises under the action of current istp, based on the connection characteristic of the operational amplifier AMP2, the low-voltage bias voltage vbp is generated at the output end of the operational amplifier AMP2, and the low-voltage bias voltage vbp can meet the working requirement of a current source in the current steering circuit.

In one embodiment of the invention, the current steering circuit comprises a conversion part circuit for converting a phase difference signal into a current signal, an upper current source adaptively connected with the conversion part circuit, and a lower current source adaptively connected with the conversion part circuit,

Fig. 2 shows an embodiment of a current steering circuit, which is known from a schematic diagram of the current steering circuit in fig. 2, where the current steering circuit includes a conversion portion circuit, an upper current source, and a lower current source, the conversion portion circuit is mainly implemented to convert a phase difference signal into a current signal, that is, the conversion portion circuit is a main body of the current steering circuit, and the upper current source and the lower current source are used to provide a current required by the conversion portion circuit to operate, and in fig. 2, the current source corresponding to the bias voltage vbp is the upper current source, and the current source corresponding to the bias voltage vbn is the lower current source.

In fig. 2, the upper current source includes a PMOS tube PM0, a PMOS tube PM8 and a PMOS tube PM9, wherein the source end of the PMOS tube PM0 and the source end of the PMOS tube PM8 are connected to a power supply vs, the gate end of the PMOS tube PM0 and the gate end of the PMOS tube PM8 are connected to a bias voltage vbp, and the drain end of the PMOS tube PM0 and the drain end of the PMOS tube PM9 are connected to a node a, that is, the drain end of the PMOS tube PM0 and the drain end of the PMOS tube PM9 are connected to the source end of the PMOS tube PM1, the source end of the PMOS tube PM2 and a soft start circuit.

From the above description, when the bias voltage vbp is low, the PMOS transistor PM0 is turned on, and the PMOS transistor PM8 is also turned on; when the bias voltage vbp is in a high voltage state, the PMOS tube PM0 and the PMOS tube PM8 cannot pass; therefore, in the above description, the bias voltage vbp meets the working requirement of the current source in the current steering circuit, specifically, meets the working requirement of the upper current source. In the power-on adjustment stage, the PMOS tube PM9 is in an on state, but in the frequency locking stage, the PMOS tube PM9 is in an off state.

In fig. 2, the lower current source includes an NMOS transistor NM0, an NMOS transistor NM8, and an NMOS transistor NM9, wherein the gate terminal of the NMOS transistor NM0 and the gate terminal of the NMOS transistor NM8 are connected to the bias voltage vbn, the source terminal of the NMOS transistor NM0 and the source terminal of the NMOS transistor NM8 are grounded gs, the drain terminal of the NMOS transistor NM8 is connected to the NMOS transistor NM9, the drain terminal of the NMOS transistor NM0 and the drain terminal of the NMOS transistor NM9 are connected to the node B, that is, the drain terminal of the NMOS transistor NM0, the drain terminal of the NMOS transistor NM90 is connected to the source terminal of the NMOS transistor NM1 and the source terminal of the NMOS transistor NM 2.

From the above description, the bias voltage first generation circuit generates the bias voltage vbn even based on the reference current ibg, the NMOS transistor NM0 is turned on, and the NMOS transistor NM8 is also kept in the on state. In the power-on regulation stage, the NMOS tube NM9 is in a conducting state, and in the frequency locking stage, the NMOS tube NM9 is in a cutting-off state.

In summary, in the power-on adjustment stage and the frequency locking stage, the PMOS tube PM0 and the NMOS tube NM0 are kept in the on state, and when the PMOS tube PM9 is turned on and the NMOS tube NM9 is turned on in the power-on adjustment stage, the current output by the current steering circuit can be increased, and at this time, the frequency adjustment can be accelerated. When the PMOS tube PM9 is turned off and the NMOS tube NM9 is also turned off in the frequency locking stage, the frequency locking stage can be used for fine tuning and locking the frequency and the phase of the phase-locked loop.

Specifically, in the above description, the elimination of the current mismatch caused by the channel length modulation effect of the current source device in the current steering circuit is specifically to eliminate the current adaptation caused by the channel length modulation effect of the PMOS tube PM0 and the NMOS tube NM0 in the current steering circuit.

In addition, the influence of non-ideal factors of the switch and the parasitic device is suppressed, and the non-ideal factors of the switch specifically refer to non-ideal factors brought by using the PMOS tube PM1, the PMOS tube PM2, the NMOS tube NM1 and the NMOS tube NM2 as the switching devices. The non-ideal factors of the parasitic device refer to the non-ideal factors caused by the parasitic capacitance of the node a and the parasitic capacitance of the node B.

The clock signal up and the clock signal upn are a pair of mutually inverted signals, for example, when the clock signal up is 1, the clock signal upn is 0, and other inverted conditions, and the clock signal dn and the clock signal dnn are described herein. In specific implementation, the switching devices (the PMOS tube PM1, the PMOS tube PM2, the NMOS tube NM1 and the NMOS tube NM2 mentioned in the above description) are controlled by the clock signal up and the clock signal dn, so that the time from the corresponding current of the upper current source and the lower current source to the output end is different, and the specific process is consistent with that of the current steering circuit.

In fig. 2, the operational amplifier AMP1 forms a voltage follower, the operational amplifier AMP1 is used to clamp the potentials of the node C and the node D to be equal, the operational amplifier AMP1 clamps the potentials of the node C and the node D to provide conduction conditions for the PMOS transistor PM1 and the NMOS transistor NM1, so that the potentials of the node a, the node B and the node D are clamped, and the operational amplifier AMP1 is used to divert current to maintain the path current, so that the PMOS transistor PM0 and the NMOS transistor NM0 are always in a conduction state, thereby eliminating the charge sharing effect caused by parasitic capacitance, and effectively improving the opening and closing speeds of the charge pump. From the above description, the PMOS transistor PM0 is always in the on state, specifically, after the power-up, the bias voltage vbp is at the low level, and the PMOS transistor PM0 is always in the on state.

Specifically, the operational amplifier AMP1 can maintain the current of the PMOS tube PM0 and the NMOS tube NM0, wherein the current through the PMOS tube PM0 flows to the output terminal of the operational amplifier AMP1 through the operational amplifier AMP1 or flows to the output terminal of the current steering circuit through the PMOS tube PM 0.

Similarly, the current through the NMOS transistor NM0 is either drawn from the output of the operational amplifier AMP1 through the NMOS transistor NM1 or from the output of the current steering circuit through the NMOS transistor NM 0.

Because the NMOS tube NM0 and the PMOS tube PM0 are kept on, the influence of charge sharing effect caused by on-off switching can be avoided. In one embodiment of the invention, a switching protection circuit for reducing the effects of channel charge injection and clock feedthrough is also included, wherein,

In fig. 2, the capacitor PC1 and the capacitor PC2 are formed based on PMOS transistors, the capacitor NC1 and the capacitor NC2 are formed based on NMOS transistors, wherein,

In one embodiment of the invention, the PMOS tubes forming the capacitors PC1 and PC2 have a first width-to-length ratio of the conductive channel;

In specific implementation, the effect of channel charge injection and clock feedthrough can be reduced by the conversion protection circuit, and the channel charge injection is reduced, specifically, when the PMOS transistor PM1, the PMOS transistor PM2, the NMOS transistor NM1 and the NMOS transistor NM2 are used as switching devices, the effect of channel charge injection during switching is reduced.

The clock feedthrough effect, for example, the clock signal up at the gate end of the PMOS transistor PM1 is switched from 0 to 1, so that the potential at the node C is slightly raised. The clock feedthrough represents that the up conversion of the clock signal at the gate end of the PMOS tube PM1 directly affects the drain end of the PMOS tube PM 1. Channel charge injection, i.e., the change in the source-drain potential of the switching device when the switch is switched.

In one embodiment of the invention, the first width-to-length ratio of the conductive channel is half of the third width-to-length ratio of the conductive channel, and the second width-to-length ratio of the conductive channel is half of the fourth width-to-length ratio of the conductive channel, so that the charge pump has smaller area and improved integration level. In particular embodiments, the third aspect ratio of the conductive channel may be equal to the fourth aspect ratio of the conductive channel.

In addition, the node C is grounded through the capacitor CAP0, and the voltage of the node C can be stabilized by utilizing the capacitor CAP0, so that the voltage stability of the output end is further improved, and the clock jitter is reduced.

In one embodiment of the invention, the soft start circuit comprises a current generating part for generating a current istp and a current extracting part for extracting the current istn, wherein,

As can be seen from fig. 2 and the above description, when the operational amplifier AMP1 is present in the current steering circuit, the current steering circuit may not be stably started up during power-up, that is, the voltage Vout at the output terminal of the current steering circuit may not be high. To assist in the start-up of the current steering circuit, the soft start circuit generates a current istp and loads the generated current istp to node a.

In fig. 2, the current istp is obtained through the source terminal of the PMOS tube PM3, and at this time, the source terminal of the PMOS tube PM3 needs to be connected to the drain terminal of the PMOS tube PM0, the source terminal of the PMOS tube PM1, the source terminal of the PMOS tube PM2, and the drain terminal of the PMOS tube PM 9.

In the power-on regulation stage, the feedback clock frequency of the phase-locked loop is smaller than the input clock frequency, the pulse width of an output clock signal up of a front-stage circuit phase frequency detector of the charge pump is larger than the pulse width of a clock signal dn, and the current istp of a current source device PMOS tube PM3 flows to the output end of the current steering circuit through a switching device PMOS tube PM2, so that the capacitor at the rear stage of the current steering circuit is charged, and the voltage Vout at the output end of the current steering circuit is raised.

In one embodiment of the present invention, the frequency locked clamping voltage generating circuit includes an NMOS transistor NS1, wherein,

In fig. 2, the current extraction portion includes an NMOS transistor NM3, an NMOS transistor NM4, and an NMOS transistor NM5, wherein the source terminal of the NMOS transistor NM4 and the source terminal of the NMOS transistor NM3 are all grounded, and the gate terminal of the NMOS transistor NM4 and the gate terminal of the NMOS transistor NM3 are all connected to the gate terminal of the NMOS transistor NM6, i.e., the bias voltage vbn of the gate terminal of the NMOS transistor NM6 is applied to the gate terminal of the NMOS transistor NM3 and the gate terminal of the NMOS transistor NM 4.

The drain terminal of the NMOS tube NM4 is connected with the source terminal of the NMOS tube NM5, the grid terminal of the NMOS tube NM5 is connected with the power supply vs, and the drain terminal of the NMOS tube NM5 is connected with the drain terminal of the PMOS tube PM5, the source terminal of the NMOS tube NS1 and the source terminal of the NMOS tube NS 2.

The drain terminal of NMOS tube NM3 is connected with the source terminal of NMOS tube NM1, the source terminal of NMOS tube NM2, the drain terminal of NMOS tube NM0 and the drain terminal of NMOS tube NM9, and at this time, the current of node B can form a path to ground gs through NMOS tube NS 3.

In fig. 2, the gate terminals of the NMOS transistor NS1, the NMOS transistor NS3, and the PMOS transistor PM9 all receive the signal selp, and the gate terminal of the NMOS transistor NS2 and the gate terminal of the NMOS transistor NM9 all receive the signal seln. Specifically, under the action of the bias voltage vbn, the NMOS transistor NM3, the NMOS transistor NM4, and the NMOS transistor NM5 are all in a conductive state.

In the frequency locking stage, the NMOS transistor NS1 is turned on, and at this time, a clamp voltage vbc may be provided to the soft start circuit, and the potential voltage vbc is loaded to the drain terminal of the NMOS transistor NM5, the source terminal of the NMOS transistor NS2, and the drain terminal of the PMOS transistor PM 5.

As can be seen from the above description, the operating state of the current steering circuit includes a power-on adjustment phase and a frequency locking phase, and the dividing conditions of the power-on adjustment phase and the frequency locking phase can be referred to the above description. Generally, the working state of the current steering circuit can be configured in a time mode and the like, when the current steering circuit is powered on, the current steering circuit firstly enters a power-on adjustment stage, after a preset time, the current steering circuit is configured to enter a frequency locking stage, and the magnitude of the preset time can be selected according to the needs so as to meet the working requirements of the current steering circuit.

The specific operation of the power-up regulation phase and the frequency lock phase will be described with reference to the schematic diagram of the charge pump circuit shown in fig. 2.

And (3) a power-on adjusting stage: the NMOS tube NS1 and the NMOS tube NS3 are turned off, the NMOS tube NS2 is turned on, the PMOS tube PM4 is in a diode connection state, the soft start circuit enters a working state, current istp and current istn are provided for the current steering circuit, the situation that the voltage Vout at the output end of the current steering circuit cannot be raised to enable the operational amplifier AMP2 to be in a high-level output state is avoided, and the auxiliary operational amplifier AMP2 and an upper current source in the current steering circuit normally enter the working state. Specifically, the gate terminal of the PMOS transistor PM4 is controlled by the voltage of the drain terminal of the PMOS transistor PM5, so as to ensure that the PMOS transistor PM4 is turned on in the power-up stage. Therefore, the situation that the PMOS tube PM0 cannot be conducted because the bias voltage vbp is high voltage does not occur.

In addition, the NMOS tube NM9 and the PMOS tube PM9 can be configured to be in a conducting state, and meanwhile, the NMOS tube NM8 and the PMOS tube PM8 are conducted, so that the output current of the current steering circuit is increased, and the frequency adjustment is quickened.

Frequency locking phase: the NMOS tube NM9 and the PMOS tube PM9 are both turned off, at the moment, the current path through the NMOS tube NM8 and the current path through the PMOS tube PM8 are both disconnected, the output current of the current steering circuit is reduced, and the fine adjustment locking of the frequency and the phase is performed according to the phase difference of the clock signal up and the clock signal dn.

In order to improve the matching of the upper current source and the lower current source in the fine adjustment stage, the NMOS tube NS1 and the NMOS tube NS3 are conducted, the NMOS tube NS2 is turned off, the connection state of the PMOS tube PM4 is changed, namely, the connection state of the diode is switched to a state controlled by the bias voltage vbp, at the moment, the gate end of the PMOS tube PM3 in the soft start circuit is controlled by the bias voltage vbp, the drain end of the PMOS tube PM5 is clamped by the clamping voltage vbc, and therefore, the current mismatch of a current source device in the current steering circuit due to the ditch length modulation effect can be further eliminated, the stability of an output signal is improved, and the output signal is matched with a current steering circuit path.

When the clock signal up=1 and the clock signal dn=1, the PMOS transistor PM1 and the NMOS transistor NM1 are turned off, the PMOS transistor PM2 and the NMOS transistor NM2 are turned on, the output currents of the PMOS transistor PM0 and the PMOS transistor PM3 are accumulated, and then flow to the NMOS transistor NM0 in the lower current source and the NMOS transistor NM3 in the soft start circuit through the right branch of the conversion part circuit, and the potential of the node D remains unchanged.

When the clock signal up=1 and dn=0, the PMOS transistor PM1 and the NMOS transistor NM2 are turned off, the PMOS transistor PM2 and the NMOS transistor NM1 are turned on, the current flowing through the NMOS transistor NM0 and the NMOS transistor NM3 is provided by the operational amplifier AMP1, the output currents of the PMOS transistor PM0 and the PMOS transistor PM3 are accumulated and then flow to the output terminal out, and the potential of the node D is raised.

When the clock signal up=0 and the clock signal dn=1, the PMOS transistor PM2 and the NMOS transistor NM1 are turned off, the PMOS transistor PM1 and the NMOS transistor NM2 are turned on, the output currents through the PMOS transistor PM0 and the PMOS transistor PM3 are accumulated and flow into the operational amplifier AMP1, the current flowing through the NMOS transistor NM0 and the NMOS transistor NM3 is extracted from the output terminal out, and the potential of the node D is reduced.

When the clock signal up=0 and the clock signal dn=0, the PMOS transistor PM1 and the NMOS transistor NM1 are turned on, the PMOS transistor PM2 and the NMOS transistor NM2 are turned off, the currents istp output by the PMOS transistor PM0 and the PMOS transistor PM3 are accumulated, the current flows to the NMOS transistor NM0 and the NMOS transistor NM3 through the left branch of the converting part circuit, and the potential of the node D is kept stable. Specifically, the voltage at node D stabilizes, specifically, fluctuates over a range. After being loaded to the inverting terminal of the operational amplifier AMP2, the offset voltage vbp of the analog quantity is generated and kept stable. As is clear from the above description, the node D is connected to the capacitor, and the potential of the node D is regulated by charging the capacitor or preventing the current, so that the potential of the node D is kept stable.

As is clear from the above description, the clamping action of the operational amplifier AMP1 can divert the current to the sustaining path current, eliminate the charge sharing effect caused by parasitic capacitance, and increase the turn-on and turn-off speed of the charge pump.

Compared with the existing structure, the self-starting charge pump based on current steering has the advantages that the self-starting charge pump based on current steering is simple in structure, the influence of non-ideal factors of a switch and a parasitic device is effectively restrained, the output current matching performance is improved, a soft starting circuit is introduced, the stability of the charge pump circuit is improved, the self-starting charge pump based on current steering can be applied to a high-speed low-jitter phase-locked loop module, and the output clock quality is effectively improved.

Those of ordinary skill in the art will appreciate that: the above embodiments are merely illustrative of the present invention and are not intended to limit the present invention, and any modifications, equivalent substitutions, improvements, etc. within the spirit of the present invention should be included in the scope of the present invention.

Claims

1. A self-starting charge pump based on current steering, the self-starting charge pump comprising:

2. The current steering based self-starting charge pump of claim 1, wherein: the self-starting charge pump further comprises a soft start circuit adaptively connected with the current steering circuit and the mirror bias circuit, wherein,

3. The current steering based self-starting charge pump of claim 2, wherein: the soft start circuit also draws current from within the current steering circuit to form a current istn flowing from the current steering circuit into the soft start circuit;

4. The current steering based self-starting charge pump of claim 3 wherein: the bias voltage second generation circuit includes an operational amplifier AMP2, wherein,

5. The current steering based self-starting charge pump of claim 4, wherein: the soft start circuit comprises a current generating part for generating a current istp and a current extracting part for extracting a current istn, wherein,

6. The current steering based self-starting charge pump of claim 5, wherein: the frequency locked clamp voltage generating circuit includes an NMOS transistor NS1, wherein,

7. The current steering based self-starting charge pump of any of claims 3-6, wherein: the current steering circuit comprises a conversion part circuit for converting a phase difference signal into a current signal, an upper current source which is connected with the conversion part circuit in an adapting way, and a lower current source which is connected with the conversion part circuit in an adapting way,

8. The current steering based self-starting charge pump of claim 7, wherein: and a conversion protection circuit for reducing the effect of channel charge injection and clock feedthrough, wherein,

9. The current steering based self-starting charge pump of claim 8, wherein: the capacitor PC1 and the capacitor PC2 are formed based on PMOS tubes, the capacitor NC1 and the capacitor NC2 are formed based on NMOS tubes, wherein,

10. The current steering based self-starting charge pump of claim 8, wherein: the PMOS tubes forming the capacitor PC1 and the capacitor PC2 have a first width-to-length ratio of a conducting channel;