CN117153210A

CN117153210A - Maximum memory clock estimation program

Info

Publication number: CN117153210A
Application number: CN202310639665.6A
Authority: CN
Inventors: E·V·铂尔曼
Original assignee: Micron Technology Inc
Current assignee: Micron Technology Inc
Priority date: 2022-06-01
Filing date: 2023-05-31
Publication date: 2023-12-01

Abstract

The present application relates to a maximum memory clock estimation program. For example, a device, such as a host device, may truncate a value of a first parameter associated with a first duration of a clock execution clock cycle coupled with a memory array and may estimate a value of a second parameter inversely proportional to the truncated value of the first parameter. The device may determine a number of clock cycles associated with a maximum duration for accessing one or more memory cells of the memory array based on adjusting the second parameter. The device may access the one or more memory cells of the memory array based on the determined number of clock cycles associated with the maximum duration.

Description

Maximum memory clock estimation program

Cross reference to

This patent application claims priority from U.S. patent application No. 17/929,970 entitled "maximum memory clock estimation procedure (MAXIMUM MEMORY CLOCK ESTIMATION PROCEDURES)" filed by palman (Pohlmann) at 9, month 6, and from U.S. provisional patent application No. 63/365,684 entitled "maximum memory clock estimation procedure (MAXIMUM MEMORY CLOCK ESTIMATION PROCEDURES)" filed by palman at 6, month 1, 2022, each of which is assigned to its assignee and each of which is expressly incorporated herein by reference in its entirety.

Technical Field

The field relates to maximum memory clock estimation procedures.

Background

Memory devices are widely used to store information in a variety of electronic devices, such as computers, user devices, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming memory cells within a memory device to various states. For example, a binary memory cell may be programmed to one of two support states, typically represented by a logic 1 or a logic 0. In some examples, a single memory cell may support more than two states, any of which may be stored. To access the stored information, the component may read (e.g., sense, detect, retrieve, identify, determine, evaluate) the stored state in the memory device. To store information, the component may write (e.g., program, set, assign) the state in the memory device.

There are various types of memory devices including magnetic hard disk, random Access Memory (RAM), read Only Memory (ROM), dynamic RAM (DRAM), synchronous Dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase Change Memory (PCM), self-selected memory, chalcogenide memory technology, NOR (NOR) and NAND (NAND) memory devices, and the like. The memory cells may be described in terms of a volatile configuration or a non-volatile configuration. Memory cells configured in a non-volatile configuration can maintain a stored logic state for a long period of time even in the absence of an external power source. Memory cells configured in a volatile configuration may lose the stored state when disconnected from an external power source.

Disclosure of Invention

A method is described. The method may comprise: truncating a value of a first parameter associated with a first duration of a clock execution clock cycle coupled to the memory array; estimating a value of a second parameter inversely proportional to the truncated value of the first parameter; determining a number of clock cycles associated with a maximum duration for accessing one or more memory cells of the memory array based at least in part on adjusting the second parameter; and accessing the one or more memory cells of the memory array based at least in part on the determined number of clock cycles associated with the maximum duration.

An apparatus is described. The apparatus may include: a memory array comprising an array of memory cells each comprising a capacitive storage element; and circuitry coupled with the memory array and configured to cause the apparatus to: truncating a value of a first parameter associated with a first duration of a clock execution clock cycle coupled to the memory array; estimating a value of a second parameter inversely proportional to the truncated value of the first parameter; determining a number of clock cycles associated with a maximum duration for accessing one or more memory cells of the memory array based at least in part on adjusting the second parameter; and accessing the one or more memory cells of the memory array based at least in part on the determined number of clock cycles associated with the maximum duration.

An apparatus is described. The apparatus may include: a processor; a memory coupled with the processor; and instructions stored in the memory and executable by the processor to cause the apparatus to: truncating a value of a first parameter associated with a first duration of a clock execution clock cycle coupled to the memory array; estimating a value of a second parameter inversely proportional to the truncated value of the first parameter; determining a number of clock cycles associated with a maximum duration for accessing one or more memory cells of the memory array based at least in part on adjusting the second parameter; and accessing the one or more memory cells of the memory array based at least in part on the determined number of clock cycles associated with the maximum duration.

A non-transitory computer-readable medium is described. The non-transitory readable medium may store code comprising instructions executable by a processor to: truncating a value of a first parameter associated with a first duration of a clock execution clock cycle coupled to the memory array; estimating a value of a second parameter inversely proportional to the truncated value of the first parameter; determining a number of clock cycles associated with a maximum duration for accessing one or more memory cells of the memory array based at least in part on adjusting the second parameter; and accessing the one or more memory cells of the memory array based at least in part on the determined number of clock cycles associated with the maximum duration.

An apparatus is described. The apparatus may include: means for truncating a value of a first parameter associated with a first duration of a clock execution clock cycle coupled to the memory array; means for estimating a value of a second parameter inversely proportional to the truncated value of the first parameter; means for determining a number of clock cycles associated with a maximum duration for accessing one or more memory cells of the memory array based at least in part on adjusting the second parameter; and means for accessing the one or more memory cells of the memory array based at least in part on the determined number of clock cycles associated with the maximum duration.

Drawings

FIG. 1 illustrates an example of a system supporting a maximum memory clock estimation procedure according to examples as disclosed herein.

FIG. 2 illustrates an example of a process flow supporting a maximum memory clock estimation procedure according to an example as disclosed herein.

FIG. 3 shows a block diagram of a device supporting a maximum memory clock estimation procedure according to an example as disclosed herein.

Fig. 4 and 5 show flowcharts illustrating one or several methods of supporting a maximum memory clock estimation procedure in accordance with examples as disclosed herein.

Detailed Description

The host device may perform operations using a clock that repeats according to a clock cycle. For example, the host device may identify a duration associated with accessing one or more memory cells of a memory array of the memory device (e.g., write recovery delay, row address to column address delay), and may determine a number of clock cycles that is time-equivalent to the duration. However, if the host device quantizes (e.g., truncates) the value of the clock cycles, the number of clock cycles may not be equivalent in time to the identified duration.

In some examples, the host device may attempt to determine (e.g., estimate) a number of clock cycles corresponding to a duration for performing one or more access operations. For example, the host device may determine the number of clock cycles by determining a ratio that is inversely proportional to the quantized value of the clock cycles and proportional to the correction factor. However, in instances where the duration is the maximum duration for performing the access operation, determining the number of clock cycles in this manner may result in determining a number that fails to account for errors associated with performing quantization. Failure to take into account timing errors that may lead to reduced performance, as well as other problems.

The example descriptions herein may enable a host device to determine one or several methods corresponding to a number of clock cycles for a duration (e.g., a maximum duration) of performing one or more access operations while accounting for errors. For example, examples herein may describe one or several methods by which a host device determines the number of clock cycles by determining a ratio that is related (e.g., inversely proportional) to a quantized clock cycle duration and related (e.g., directly proportional) to a quantized value of a duration (e.g., a maximum duration) for performing an access operation. In some examples, determining the number of clock cycles may include the host device quantizing (e.g., truncating) the ratio. Determining the number of clock cycles in this manner may enable the host device to account for errors. Thus, the methods described herein may enable a host device to execute memory access programs with fewer timing errors and also have other advantages.

Features of the present disclosure are initially described in the context of a system as described with reference to fig. 1. Features of the present disclosure are described in the context of a process flow as described with reference to fig. 2. These and other features of the present disclosure are further illustrated and described with reference to apparatus diagrams and flow charts relating to a maximum memory clock estimation procedure as described with reference to fig. 3-5.

Fig. 1 illustrates an example of a system 100 supporting a maximum memory clock estimation procedure according to examples as disclosed herein. The system 100 may include a host device 105, a memory device 110, and a plurality of channels 115 coupling the host device 105 with the memory device 110. The system 100 may include one or more memory devices 110, but aspects of one or more memory devices 110 may be described in the context of a single memory device (e.g., memory device 110).

The system 100 may include portions of an electronic device such as a computing device, mobile computing device, wireless device, graphics processing device, vehicle, or other system. For example, system 100 may illustrate aspects of a computer, laptop computer, tablet computer, smart phone, cellular phone, wearable device, internet connection device, vehicle controller, or the like. Memory device 110 may be a component of the system operable to store data of one or more other components of system 100.

At least part of the system 100 may be an example of the host device 105. Host device 105 may be an example of a processor or other circuitry within a device that uses memory to perform a process, such as within a computing device, mobile computing device, wireless device, graphics processing device, computer, laptop, tablet, smart phone, cellular telephone, wearable device, internet connection device, vehicle controller, system on a chip (SoC) or some other fixed or portable electronic device, among other examples. In some examples, host device 105 may refer to hardware, firmware, software, or any combination thereof that implements the functionality of external memory controller 120. In some examples, the external memory controller 120 may be referred to as a host or host device 105.

Memory device 110 may be a stand-alone device or component operable to provide physical memory addresses/space that may be used or referenced by system 100. In some examples, memory device 110 may be configurable to work with one or more different types of host devices. Signaling between the host device 105 and the memory device 110 is operable to support one or more of: the modulation scheme used to modulate the signals, the various pin configurations used to pass the signals, the various form factors of the physical packaging of the host device 105 and the memory device 110, the clock signaling and synchronization between the host device 105 and the memory device 110, timing conventions, or other factors.

The memory device 110 is operable to store data for components of the host device 105. In some examples, the memory device 110 may act as a slave type device for the host device 105 (e.g., in response to and executing commands provided by the host device 105 through the external memory controller 120). Such commands may include one or more of write commands for write operations, read commands for read operations, refresh commands for refresh operations, or other commands.

The host device 105 may include one or more of an external memory controller 120, a processor 125, a basic input/output system (BIOS) component 130, or other components, such as one or more peripheral components or one or more input/output controllers. Components of host device 105 may be coupled to each other using bus 135.

The processor 125 is operable to provide control or other functionality for at least a portion of the system 100 or at least a portion of the host device 105. The processor 125 may be a general purpose processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination of these components. In such examples, processor 125 may be an instance of a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), a General Purpose GPU (GPGPU), or a SoC, among other instances. In some examples, the external memory controller 120 may be implemented by the processor 125 or a portion of the processor 125.

The BIOS component 130 may be a software component that includes a BIOS that operates as firmware, which may initialize and run various hardware components of the system 100 or host device 105. The BIOS component 130 may also manage the flow of data between the processor 125 and various components of the system 100 or host device 105. The BIOS component 130 may include programs or software stored in one or more of Read Only Memory (ROM), flash memory, or other non-volatile memory.

In some examples, the system 100 or host device 105 may include various peripheral components. The peripheral component may be any input device or output device, or interface for such devices (e.g., bus, set of pins), which may be integrated into the system 100 or host device 105 or integrated with the system 100 or host device 105. Examples may include one or more of the following: disk controllers, voice controllers, graphics controllers, ethernet controllers, modems, universal Serial Bus (USB) controllers, serial or parallel ports, or peripheral card slots (e.g., peripheral Component Interconnect (PCI) or dedicated graphics ports). The peripheral component(s) may be other components understood by those of ordinary skill in the art as peripheral devices.

In some examples, the system 100 or host device 105 may include an I/O controller. The I/O controller may manage data communication between the processor 125 and the peripheral component(s), input devices, or output devices. The I/O controller may manage peripheral devices that are not integrated into the system 100 or host device 105 or that are not integrated with the system 100 or host device 105. In some examples, an I/O controller may represent a physical connection or port to an external peripheral component.

In some examples, the system 100 or host device 105 may include an input component, an output component, or both. The input component may represent a device or signal external to the system 100 that provides information, signals, or data to the system 100 or components of the system 100. In some examples, the input component may include a user interface or interfaces with or between other devices. In some examples, the input component may be a peripheral device that interfaces with the system 100 via one or more peripheral components or may be managed by an I/O controller. The output component may represent a device or signal external to the system 100 that is operable to receive output from the system 100 or any component of the system 100. Examples of output components may include a display, an audio speaker, a printing device, another processor on a printed circuit board, and so forth. In some examples, the output may be a peripheral device that interfaces with system 100 via one or more peripheral components or may be managed by an I/O controller.

The memory device 110 may include a device memory controller 155 and one or more memory dies 160 (e.g., memory chips) to support a desired capacity or a specified capacity for data storage. Each memory die 160 (e.g., memory die 160-a, 160-b, and 160-N) may include a local memory controller 165 (e.g., local memory controller 165-a, local memory controller 165-b, local memory controller 165-N) and a memory array 170 (e.g., memory array 170-a, memory array 170-b, memory array 170-N). The memory array 170 may be a set of memory cells (e.g., one or more grids, one or more banks, one or more tiles, one or more sections), where each memory cell is operable to store at least one bit of data. The memory device 110 including two or more memory dies may be referred to as a multi-die memory or a multi-die package or a multi-chip memory or a multi-chip package.

Memory die 160 may be an example of a two-dimensional (2D) array of memory cells or may be an example of a three-dimensional (3D) array of memory cells. The 2D memory die 160 may include a single memory array 170. The 3D memory die 160 may include two or more memory arrays 170, which memory arrays 170 may be stacked on top of each other or positioned in close proximity to each other (e.g., relative to a substrate). In some examples, the memory array 170 in the 3D memory die 160 may be referred to as a level, hierarchy, layer, or die. The 3D memory die 160 may include any number of stacked memory arrays 170 (e.g., two high, three high, four high, five high, six high, seven high, eight high). In some 3D memory dies 160, different levels may share at least one common access line such that some levels may share one or more of a word line, a digit line, or a plate line.

The device memory controller 155 may include circuitry, logic, or components operable to control the operation of the memory device 110. The device memory controller 155 may include hardware, firmware, or instructions that enable the memory device 110 to perform various operations and may be operable to receive, transmit, or execute commands, data, or control information related to the components of the memory device 110. The device memory controller 155 is operable to communicate with one or more of the external memory controller 120, one or more memory dies 160, or the processor 125. In some examples, the device memory controller 155 may control operations of the memory device 110 described herein in conjunction with a local memory controller 165 of the memory die 160.

In some examples, memory device 110 may receive data or commands, or both, from host device 105. For example, the memory device 110 may receive a write command indicating that the memory device 110 is to store data of the host device 105 or a read command indicating that the memory device 110 is to provide data stored in the memory die 160 to the host device 105.

The local memory controller 165 (e.g., local to the memory die 160) may include circuitry, logic, or components operable to control the operation of the memory die 160. In some examples, local memory controller 165 is operable to communicate (e.g., receive or transmit data or commands, or both) with device memory controller 155. In some examples, memory device 110 may not include device memory controller 155 and local memory controller 165, or external memory controller 120 may perform various functions described herein. Thus, the local memory controller 165 is operable to communicate with the device memory controller 155, with other local memory controllers 165, or directly with the external memory controller 120 or the processor 125, or any combination thereof. Examples of components that may be included in the device memory controller 155 or the local memory controller 165, or both, may include a receiver for receiving a signal (e.g., from the external memory controller 120), a transmitter for transmitting a signal (e.g., to the external memory controller 120), a decoder for decoding or demodulating the received signal, an encoder for encoding or modulating a signal to be transmitted, or various other circuits or controllers operable to support the described operations of the device memory controller 155 or the local memory controller 165, or both.

The external memory controller 120 is operable to be able to communicate one or more of information, data, or commands between the system 100 or a component of the host device 105 (e.g., the processor 125) and the memory device 110. The external memory controller 120 may translate or translate communications exchanged between the components of the host device 105 and the memory device 110. In some examples, the external memory controller 120, or other components of the system 100 or host device 105, or functions thereof described herein, may be implemented by the processor 125. For example, the external memory controller 120 may be hardware, firmware, or software implemented by the processor 125 or other components of the system 100 or host device 105, or some combination thereof. Although the external memory controller 120 is depicted as being external to the memory device 110, in some examples, the external memory controller 120 or its functions described herein may be implemented by one or more components of the memory device 110 (e.g., the device memory controller 155, the local memory controller 165) or vice versa.

Components of host device 105 may exchange information with memory device 110 using one or more channels 115. Channel 115 is operable to support communication between external memory controller 120 and memory device 110. Each channel 115 may be an example of a transmission medium that carries information between the host device 105 and the memory device. Each channel 115 may include one or more signal paths or transmission media (e.g., conductors) between terminals associated with components of the system 100. The signal path may be an example of a conductive path operable to carry a signal. For example, channel 115 may include a first terminal that includes one or more pins or pads at host device 105 and one or more pins or pads at memory device 110. A pin may be an example of a conductive input or output point of a device of system 100, and the pin may be operable to act as part of a channel.

Channels 115 (and associated signal paths and terminals) may be dedicated to conveying one or more types of information. For example, lanes 115 may include one or more Command and Address (CA) lanes 186, one or more clock signal (CK) lanes 188, one or more Data (DQ) lanes 190, one or more other lanes 192, or any combination thereof. In some examples, signaling may be communicated over channel 115 using Single Data Rate (SDR) signaling or Double Data Rate (DDR) signaling. In SDR signaling, one modulation symbol (e.g., signal level) of a signal may be registered for each clock cycle (e.g., on a rising or falling edge of a clock signal). In DDR signaling, two modulation symbols (e.g., signal levels) of a signal may be registered for each clock cycle (e.g., on both rising and falling edges of a clock signal).

In some examples, CA channel 186 is operable to pass commands between host device 105 and memory device 110 that include control information (e.g., address information) associated with the commands. For example, the commands carried by CA channel 186 may include read commands having addresses of desired data. In some examples, CA channel 186 may include any number of signal paths (e.g., eight or nine signal paths) to decode one or more of the address or command data.

In some examples, the clock signal channel 188 is operable to pass one or more clock signals between the host device 105 and the memory device 110. Each clock signal is operable to oscillate between a high state and a low state and may support coordination (e.g., in time) between the actions of the host device 105 and the actions of the memory device 110. In some examples, the clock signal may be single ended. In some examples, the clock signals may provide timing references for command and address operations of the memory device 110 or other system-wide operations of the memory device 110. Thus, the clock signal may be referred to as a control clock signal, a command clock signal, or a system clock signal. The system clock signal may be generated by a system clock, which may include one or more hardware components (e.g., oscillators, crystals, logic gates, transistors).

In some examples, the data channel 190 is operable to communicate one or more of data or control information between the host device 105 and the memory device 110. For example, the data channel 190 may communicate information to be written to the memory device 110 (e.g., bi-directional) or information read from the memory device 110.

Channel 115 may include any number of signal paths (including a single signal path). In some examples, channel 115 may include multiple individual signal paths. For example, a channel may be x4 (e.g., including four signal paths), x8 (e.g., including eight signal paths), x16 (including sixteen signal paths), and so on.

In some examples, one or more other channels 192 may include one or more Error Detection Code (EDC) channels. The EDC channel is operable to pass error detection signals, such as checksums, to improve system reliability. The EDC channel may include any number of signal paths.

The signal communicated over channel 115 may be modulated using one or more different modulation schemes. In some examples, a binary symbol (or binary level) modulation scheme may be used to modulate signals communicated between host device 105 and memory device 110. The binary symbol modulation scheme may be an example of an M-ary modulation scheme, where M is equal to two. Each symbol of the binary symbol modulation scheme is operable to represent one bit of digital data (e.g., a symbol may represent a logic 1 or a logic 0). Examples of binary symbol modulation schemes include, but are not limited to, non-return to zero (NRZ), unipolar encoding, bipolar encoding, manchester encoding, pulse Amplitude Modulation (PAM) with two symbols (e.g., PAM 2), and/or other modulation schemes.

In some examples, a multi-symbol (or multi-level) modulation scheme may be used to modulate signals communicated between host device 105 and memory device 110. The multi-symbol modulation scheme may be an example of an M-ary modulation scheme, where M is greater than or equal to three. Each symbol of the multi-symbol modulation scheme may be operable to represent more than one bit of digital data (e.g., a symbol may represent a logic 00, a logic 01, a logic 10, or a logic 11). Examples of multi-symbol modulation schemes include, but are not limited to, PAM3, PAM4, PAM8, etc., quadrature Amplitude Modulation (QAM), quadrature Phase Shift Keying (QPSK), and/or other modulation schemes. A multi-symbol signal (e.g., PAM3 signal or PAM4 signal) may be a signal modulated using a modulation scheme that includes at least three levels to encode more than one bit of information. Multi-symbol modulation schemes and symbols may alternatively be referred to as non-binary, multi-bit, or higher order modulation schemes and symbols.

In some examples, host device 105 or memory device 110 may perform operations using clocks that repeat according to clock cycles. For example, the host device 105 or the memory device 110 may identify a maximum duration (e.g., a maximum refresh interval) associated with accessing one or more memory cells of the memory array 170, and may determine a number of clock cycles that are equivalent in time to the duration. In some examples, the host device may access a register (e.g., a Serial Presence Detect (SPD) register) of the memory device (e.g., read, retrieve data from) to identify a maximum duration associated with one or more memory cells of the access memory array. Additionally or alternatively, the host device may access memory cells of the memory device to identify a maximum duration. However, if the host device 105 or the memory device 110 quantizes (e.g., truncates) the duration of the clock cycles using a correction factor, the number of clock cycles may fail to account for the error.

The method used to calculate the timing parameters may be affected by rounding errors from one or more sources. For example, a system (e.g., host device 105, memory device 110) may use a memory clock having a particular nominal frequency (e.g., 2200 megahertz or 44 hundred million transfers per second) for a speed interval (speed bin), which may mathematically produce a particular clock period (e.g., 454545 nanosecond repetition). In some examples, it is not possible or actually difficult to express each number after a decimal point accurately and rounding may be used by the host device or the memory device to simplify the method or methods. In some examples, the timing parameters may have a minimum granularity (e.g., 1 picosecond).

Methods for rounding may be defined to achieve improved performance (e.g., optimization of device performance) without violating device parameters (e.g., industry standards or specifications). Each timing parameter may be specified in the time domain (e.g., in nanoseconds, picoseconds), which may then be converted to the clock domain (e.g., nCK units), and may be defined to be consistent with (e.g., follow, use) these methods the timing parameters (e.g., minimum timing parameter, maximum timing parameter) may use the same or similar rounding methods used to define the application memory clock period (e.g., minimum application memory clock period (e.g., tCK (AVG) min) or maximum application memory clock period (e.g., tCK (AVG) max)).

Such rules or methods may include that, for a given speed interval, one or more timing parameter values, such as one or more minimum timing parameter values, such as tCK (AVG) min, or one or more maximum timing parameter values, such as tCK (AVG) max, may be rounded down and defined to a particular accuracy granularity, such as 1 picosecond, based on non-rounded nominal values, such as tCK (AVG) values. If a nominal value, e.g., a nominal timing parameter (e.g., minimum timing parameter, maximum timing parameter) value, is to use more than a particular accuracy granularity (e.g., 1 picosecond), the nominal timing parameter value may be rounded down to the next value of the particular granularity (e.g., 1 picosecond) according to a rounding algorithm or method.

For a maximum timing parameter (e.g., including tCK (max)), the nominal value of the timing parameter may be increased by an error that is used to define one or more timing parameter (e.g., maximum timing parameter) values (e.g., tCK (AVG) max). Increasing the nominal value in this manner may enable the host device or memory device to avoid degrading performance due to additional erroneous clock domains (e.g., nCK), and may enable the host device or memory device to calculate a more accurate (e.g., true) maximum value (e.g., true maximum value). For example, the maximum recovery interval may have a nominal value of 3.9 microseconds. For a nominal clock period of 0.238095 nanoseconds (e.g., tCK (AVG)), there may be a theoretical maximum percentage error of.42% (e.g., of ). Because ofWhereas, the true (e.g., true) maximum interval duration may be as high as 3.916386 microseconds (e.g., calculated as +.>。

In some examples, host device 105 may implement a rounding algorithm for a maximum timing parameter (e.g., a maximum refresh interval). The maximum refresh interval may be stored in units of clock numbers (nCK), but may also be expressed in units of time (e.g., picoseconds (ps)). In some examples, the host device 105 may quantize (e.g., truncate, round down) the maximum timing parameter prior to dividing the maximum timing parameter by the quantized (e.g., truncated, round down) application memory clock period, resulting in a quantized (e.g., truncated, round down) number of clocks. In some examples, each of the maximum timing parameters, the application memory clock period, and the number of clocks may be quantized. For example, the number of clock cycles may be expressed as

Where nominal_max_parameter_in_ps may correspond to a nominal maximum timing parameter (e.g., a nominal maximum refresh interval in picoseconds) and tCK (AVG) real_in_ps may correspond to a real application memory clock period in picoseconds.

Host device 105 or memory device 110 implementing the methods as described herein may be associated with one or more advantages. For example, determining the number of clock cycles according to the techniques described herein may enable the host device 105 or the memory device 110 to account for errors (e.g., account for a maximum percentage of errors that may occur). Thus, the host device 105 or the memory device 110 that determines the number of clock cycles may experience reduced timing errors and improved performance. Additional details regarding the implementation of the methods described herein may be described with reference to fig. 2.

FIG. 2 illustrates an example of a process flow 200 supporting a memory clock management and estimation procedure according to an example as disclosed herein. In some examples, one or more components may perform aspects of process flow 200. For example, an external memory controller of a memory device (e.g., external memory controller 120 of host device 105 as described with reference to fig. 1), a device memory controller (e.g., device memory controller 155 as described with reference to fig. 1), a local memory controller (e.g., local memory controller 165 as described with reference to fig. 1), or any combination thereof, may perform the method associated with process flow 200.

As described herein (e.g., with reference to fig. 1), a host device or a memory device may perform operations using a clock that repeats according to a clock cycle. For example, the host device or memory device may identify a maximum duration (stored on the SPD of the memory device) associated with accessing one or more memory cells of the memory array (e.g., write recovery delay, row address to column address delay), and may determine a number of clock cycles corresponding to (e.g., less than, equal to, greater than) the identified maximum duration. The method as described herein (e.g., with reference to fig. 2) may enable a host device or a memory device to determine a number of clock cycles corresponding to an identified maximum duration.

At 205, the host device or memory device may identify (e.g., select) a clock rate (e.g., a clock rate of the host device compatible with a clock rate indicated by a register (e.g., SPD) or one or more memory cells of the memory device) and may determine a value of a first parameter (e.g., tCK (AVG) real in ps, which may be an example of a real application memory clock period) associated with a first duration of a clock execution clock period based on the clock rate. For example, the value of the first parameter may be the inverse of the value of the clock rate. In some examples, the host device or the memory device may identify the clock rate based on receiving a request to adjust the clock rate (e.g., from the host device). Additionally or alternatively, the host device or memory device may identify a condition at the host device or memory device and may adjust the clock rate based on the condition.

At 210, the host device or the memory device may truncate the value of the first parameter. For example, the host device or the memory device may execute truncate (tCK (AVG) real_in_ps). In some examples, the host device or the memory device may truncate the first parameter to a particular granularity (e.g., to the picosecond level).

At 215, the host device or memory device may estimate a second parameter (e.g.,) Is a value of (2). For example, the second parameter may be inversely proportional to the truncated value of the first parameter. In some examples, the second parameter may be proportional to a truncated third parameter associated with accessing one or more memory cells of the memory array (e.g., truncated nominal_max_parameter_in_ps or truncate (nominal_max_parameter_in_ps):

at 220, the host device or the memory device may determine, based on the second parameter (e.g.,) A fifth parameter (e.g., nCK (max)) is determined. For example, the host device or the memory device may adjust the second parameter from a first value to a second value that is different (e.g., lower) than the first value. Additionally or alternatively, the host device or the memory device may truncate the second parameter. The host device or the memory device may determine the number of clock cycles as: />

At 225, the host device or memory device may access one or more memory cells of the memory array based on the determined number of clock cycles. For example, the host device or the memory device may employ the refresh interval while performing a refresh operation on one or more cells according to the determined number of clock cycles.

A host device or memory device implementing a method as described herein (e.g., with reference to fig. 2) may be associated with one or more advantages. For example, determining the number of clock cycles of the maximum timing parameter according to the methods described herein may account for errors, while a host device or memory device that determines the number of clock cycles according to the same correction factor used to determine the number of clock cycles of the minimum timing parameter may fail to account for errors. Thus, the methods described herein may enable a host device to more accurately execute memory access programs and also have other advantages.

Fig. 3 shows a block diagram 300 of a device 320 supporting a maximum memory clock estimation procedure according to an example as disclosed herein. Device 320 may be an example of aspects of a device as described with reference to fig. 1-2. The device 320 or various components thereof may be an example of means for performing aspects of the maximum memory clock estimation procedure as described herein. For example, the device 320 may include a truncating component 325, an estimating component 330, a clock cycle number component 335, a memory access component 340, or any combination thereof. Each of these components may communicate with each other directly or indirectly (e.g., via one or more buses).

The truncating component 325 may be configured or otherwise support means (e.g., a circuit or controller configured to truncate a value of a first parameter associated with a first duration of a clock execution clock cycle coupled to a memory array). The estimating component 330 may be configured or otherwise support means (e.g., circuitry or a controller configured to estimate a value of a second parameter) for estimating the value of the second parameter inversely proportional to the truncated value of the first parameter. The number of clock cycles component 335 may be configured or otherwise support means (e.g., circuitry or a controller configured to determine a number of clock cycles) for determining a number of clock cycles associated with a maximum duration for accessing one or more memory cells of a memory array based at least in part on adjusting the second parameter. Memory access component 340 may be configured or otherwise support means (e.g., circuitry or a controller configured to access one or more memory cells of a memory array based at least in part on a determined number of clock cycles associated with a maximum duration).

In some examples, to support accessing one or more memory cells of a memory array based at least in part on a determined number of clock cycles associated with a maximum duration, memory access component 340 may be configured or otherwise support means (e.g., circuitry or a controller configured to access the one or more memory cells) for accessing the one or more memory cells within a total number of clock cycles less than or equal to the determined number of clock cycles.

In some examples, the truncating component 325 may be configured or otherwise support means for truncating a first value of a second parameter to adjust the second parameter from the first value to a second value (e.g., a circuit or controller configured to truncate the first value of the second parameter), wherein determining the number of clock cycles is based at least in part on truncating the first value of the second parameter.

In some examples, truncation component 325 may be configured to or otherwise support means for truncating a value of a third parameter (e.g., a circuit or controller configured to truncate the value of the third parameter), wherein estimating a value of a second parameter is based at least in part on truncating the value of the third parameter.

In some examples, the second parameter is proportional to the truncated value of the third parameter.

In some examples, the third parameter includes a total duration of time that the memory operation is performed.

In some examples, the number of clock cycles corresponds to an upper limit of clock cycles used to access one or more memory cells.

In some examples, the maximum duration includes a maximum value of the refresh interval.

Fig. 4 shows a flow chart illustrating a method 400 of supporting a maximum memory clock estimation procedure according to an example as disclosed herein. The operations of method 400 may be implemented by a device or components thereof as described herein. For example, the operations of method 400 may be performed by an apparatus as described with reference to fig. 1-3. In some examples, a device may execute a set of instructions to control functional elements of the device to perform the described functions. Additionally or alternatively, the device may perform aspects of the described functions using dedicated hardware.

At 405, the method may include truncating a value of a first parameter associated with a first duration of a clock execution clock cycle coupled with a memory array. Operation 405 may be performed in accordance with examples as disclosed herein. In some examples, aspects of operation 405 may be performed by the truncating component 325 as described with reference to fig. 3.

At 410, the method may include estimating a value of a second parameter inversely proportional to the truncated value of the first parameter. Operation 410 may be performed in accordance with examples as disclosed herein. In some examples, aspects of operation 410 may be performed by the estimation component 330 as described with reference to fig. 3.

At 415, the method may include determining a number of clock cycles associated with a maximum duration for accessing one or more memory cells of the memory array based at least in part on adjusting the second parameter. Operation 415 may be performed according to examples as disclosed herein. In some examples, aspects of operation 415 may be performed by the clock cycle number component 335 as described with reference to fig. 3.

At 420, the method may include accessing one or more memory cells of a memory array based at least in part on the determined number of clock cycles associated with the maximum duration. Operation 420 may be performed according to examples as disclosed herein. In some examples, aspects of operation 420 may be performed by memory access component 340 as described with reference to fig. 3.

In some examples, an apparatus described herein may perform one or several methods, such as method 400. The apparatus may include operations, features, circuitry, logic, means, or instructions for performing the following aspects of the disclosure (e.g., a non-transitory computer-readable medium storing instructions executable by a processor), or any combination thereof:

Aspect 1: a method, apparatus, or non-transitory computer readable medium comprising operations, features, circuitry, logic, means, or instructions, or any combination thereof, for: truncating a value of a first parameter associated with a first duration of a clock execution clock cycle coupled to the memory array; estimating a value of a second parameter inversely proportional to the truncated value of the first parameter; determining a number of clock cycles associated with a maximum duration for accessing one or more memory cells of the memory array based at least in part on adjusting the second parameter; and accessing the one or more memory cells of the memory array based at least in part on the determined number of clock cycles associated with the maximum duration.

Aspect 2: the method, apparatus, or non-transitory computer-readable medium of aspect 1, wherein accessing the one or more memory cells of the memory array based at least in part on the determined number of clock cycles associated with the maximum duration includes operations, features, circuitry, logic, means, or instructions, or any combination thereof, for: the one or more memory cells are accessed within a total number of clock cycles less than or equal to the determined number of clock cycles.

Aspect 3: the method, apparatus, or non-transitory computer-readable medium of any one of aspects 1-2, further comprising operations, features, circuitry, logic, means, or instructions, or any combination thereof, for: truncating a first value of the second parameter to adjust the second parameter from the first value to a second value, wherein determining the number of clock cycles is based at least in part on truncating the first value of the second parameter.

Aspect 4: the method, apparatus, or non-transitory computer-readable medium of any one of aspects 1-3, further comprising operations, features, circuitry, logic, means, or instructions, or any combination thereof, for: truncating a value of a third parameter, wherein estimating the value of the second parameter is based at least in part on truncating the value of the third parameter.

Aspect 5: the method, apparatus, or non-transitory computer-readable medium of aspect 4, wherein the second parameter is proportional to the truncated value of the third parameter.

Aspect 6: the method, apparatus, or non-transitory computer-readable medium of aspect 5, wherein the third parameter includes a total duration for performing a memory operation.

Aspect 7: the method, apparatus, or non-transitory computer-readable medium of any one of aspects 1-6, wherein the number of clock cycles corresponds to an upper bound of clock cycles used to access the one or more memory cells.

Aspect 8: the method, apparatus, or non-transitory computer-readable medium of any one of aspects 1-7, wherein the maximum duration comprises a maximum value of a refresh interval.

Fig. 5 shows a flow chart illustrating a method 500 of supporting a maximum memory clock estimation procedure according to an example as disclosed herein. The operations of method 500 may be implemented by a device or components thereof as described herein. For example, the operations of method 500 may be performed by an apparatus as described with reference to fig. 1-3. In some examples, a device may execute a set of instructions to control functional elements of the device to perform the described functions. Additionally or alternatively, the device may perform aspects of the described functions using dedicated hardware.

At 505, the method may include truncating a value of a first parameter associated with a first duration of a clock execution clock cycle coupled to the memory array. Operation 505 may be performed according to examples as disclosed herein. In some examples, aspects of operation 505 may be performed by the truncating component 325 as described with reference to fig. 3.

At 510, the method may include estimating a value of a second parameter inversely proportional to the truncated value of the first parameter. Operation 510 may be performed in accordance with examples as disclosed herein. In some examples, aspects of operation 510 may be performed by the estimation component 330 as described with reference to fig. 3.

At 515, the method may include determining a number of clock cycles associated with a maximum duration for accessing one or more memory cells of the memory array based at least in part on adjusting the second parameter. Operation 515 may be performed in accordance with examples as disclosed herein. In some examples, aspects of operation 515 may be performed by the number of clock cycles component 335 as described with reference to fig. 3.

At 520, the method may include accessing one or more memory cells of a memory array for a total number of clock cycles less than or equal to the determined number of clock cycles associated with the maximum duration. Operation 520 may be performed in accordance with examples as disclosed herein. In some examples, aspects of operation 520 may be performed by memory access component 340 as described with reference to fig. 3.

It should be noted that the methods described herein describe possible implementations, and that the operations and steps may be rearranged or otherwise modified, and that other implementations are possible. Furthermore, portions from two or more methods may be combined.

An apparatus is described. The following provides an overview of aspects of the apparatus as described herein:

aspect 9: an apparatus, comprising: a memory array comprising an array of memory cells each comprising a capacitive storage element; and circuitry coupled with the memory array and configured to cause the apparatus to: truncating a value of a first parameter associated with a first duration of a clock execution clock cycle coupled to the memory array; estimating a value of a second parameter inversely proportional to the truncated value of the first parameter; determining a number of clock cycles associated with a maximum duration for accessing one or more memory cells of the memory array based at least in part on adjusting the second parameter; and accessing the one or more memory cells of the memory array based at least in part on the determined number of clock cycles associated with the maximum duration.

Aspect 10: the apparatus of aspect 9, wherein the circuitry that accesses the one or more memory cells of the memory array based at least in part on the determined number of clock cycles associated with the maximum duration is configured to cause the apparatus to: the one or more memory cells are accessed within a total number of clock cycles less than or equal to the determined number of clock cycles.

Aspect 11: the apparatus of any one of aspects 9-10, wherein the circuitry is further configured to cause the apparatus to: truncating a first value of the second parameter to adjust the second parameter from the first value to a second value, wherein determining the number of clock cycles is based at least in part on truncating the first value of the second parameter.

Aspect 12: the apparatus of any one of aspects 9-11, wherein the circuitry is further configured to cause the apparatus to: truncating a value of a third parameter, wherein estimating the value of the second parameter is based at least in part on truncating the value of the third parameter.

Aspect 13: the apparatus of aspect 12, wherein the second parameter is proportional to the truncated value of the third parameter.

Aspect 14: the apparatus of aspect 13, wherein the third parameter includes a total duration for performing a memory operation.

Aspect 15: the apparatus of any one of aspects 9-14, wherein the number of clock cycles corresponds to an upper limit of clock cycles used to access the one or more memory cells.

Aspect 16: the apparatus of any one of aspects 9-15, wherein the maximum duration comprises a maximum value of a refresh interval.

An apparatus is described. The following provides an overview of aspects of the apparatus described herein:

aspect 17: an apparatus, comprising: a processor; a memory coupled with the processor; and instructions stored in the memory and executable by the processor to cause the apparatus to: truncating a value of a first parameter associated with a first duration of a clock execution clock cycle coupled to the memory array; estimating a value of a second parameter inversely proportional to the truncated value of the first parameter; determining a number of clock cycles associated with a maximum duration for accessing one or more memory cells of the memory array based at least in part on adjusting the second parameter; and accessing the one or more memory cells of the memory array based at least in part on the determined number of clock cycles associated with the maximum duration.

Aspect 18: the apparatus of aspect 17, wherein the instructions that access the one or more memory cells of the memory array based at least in part on the determined number of clock cycles associated with the maximum duration are executable by the processor to cause the apparatus to: the one or more memory cells are accessed within a total number of clock cycles less than or equal to the determined number of clock cycles.

Aspect 19: the apparatus of any one of aspects 17-18, wherein the instructions are further executable by the processor to cause the apparatus to: truncating a first value of the second parameter to adjust the second parameter from the first value to a second value, wherein determining the number of clock cycles is based at least in part on truncating the first value of the second parameter.

Aspect 20: the apparatus of any one of aspects 17-19, wherein the instructions are further executable by the processor to cause the apparatus to: truncating a value of a third parameter, wherein estimating the value of the second parameter is based at least in part on truncating the value of the third parameter.

Aspect 21: the apparatus of aspect 20, wherein the second parameter is proportional to the truncated value of the third parameter.

Aspect 22: the apparatus of aspect 21, wherein the third parameter includes a total duration for performing a memory operation.

Aspect 23: the apparatus of any one of aspects 17-22, wherein the number of clock cycles corresponds to an upper limit of clock cycles used to access the one or more memory cells.

Aspect 24: the apparatus of any one of aspects 17-23, wherein the maximum duration comprises a maximum value of a refresh interval.

The information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some figures may illustrate signals as a single signal; however, a signal may represent a signal bus, where the bus may have a variety of bit widths.

The devices discussed herein, including memory arrays, may be formed on semiconductor substrates such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, and the like. In some examples, the substrate is a semiconductor wafer. In other examples, the substrate may be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-Sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or a sub-region of the substrate may be controlled by doping using various chemicals including, but not limited to, phosphorus, boron or arsenic. Doping may be performed by ion implantation or any other doping means during the initial formation or growth of the substrate.

The switching components (e.g., transistors) discussed herein may represent Field Effect Transistors (FETs) and may include three terminal components including a source (e.g., source terminal), a drain (e.g., drain terminal), and a gate (e.g., gate terminal). The terminals may be connected to other electronic components by conductive materials (e.g., metals, alloys). The source and drain may be conductive and may include doped (e.g., heavily doped, degenerate) semiconductor regions. The source and drain may be separated by a doped (e.g., lightly doped) semiconductor region or channel. If the channel is n-type (e.g., the majority carriers are electrons), the FET may be referred to as an n-type FET. If the channel is p-type (e.g., the majority carriers are holes), the FET may be referred to as a p-type FET. The channel may be covered by an insulated gate oxide. Channel conductivity may be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, may cause the channel to become conductive. A transistor may be "on" or "active" when a voltage greater than or equal to the transistor threshold voltage is applied to the transistor gate. The transistor may be "off" or "deactivated" when a voltage less than the transistor threshold voltage is applied to the transistor gate.

The description set forth herein describes example configurations in connection with the figures and does not represent all examples that may be implemented or within the scope of the claims. The term "exemplary" as used herein means "serving as an example, instance, or illustration" and not "preferred" or "preferred over" other examples. The detailed description includes specific details to provide an understanding of the described technology. However, the techniques may be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form in order to avoid obscuring the concepts of the described examples.

In the drawings, similar components or features may have the same reference label. In addition, various components of the same type may be distinguished by following the reference label by a dash and a second label that distinguishes among the similar components. If only a first reference label is used in the specification, the description may apply to any one of the similar components having the same first reference label, irrespective of the second reference label.

The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software that is executed by a processor, the functions may be stored on or transmitted over as one or more instructions, such as code, on a computer-readable medium. Other examples and implementations are within the scope of the disclosure and the appended claims. For example, due to the nature of software, the functions described herein may be implemented using software executed by a processor, hardware, firmware, hardwired, or a combination of any of these. Features that perform functions may also be physically located at various locations including portions that are distributed such that the functions are performed at different physical locations.

For example, the various illustrative blocks and modules described in connection with the present disclosure may be implemented or performed with a processor, such as DSP, ASIC, FPGA, discrete gate logic, discrete transistor logic, discrete hardware components, other programmable logic devices, or any combination thereof, designed to perform the functions described herein. The processor may be an example of a microprocessor, a controller, a microcontroller, a state machine, or any type of processor. A processor may also be implemented as any combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

As used herein (including in the claims), an "or" as used in an item list (e.g., an item list starting with a phrase such as "at least one of …" or "one or more of …") indicates an inclusive list such that a list of at least one of A, B or C represents a or B or C or AB or AC or BC or ABC (i.e., a and B and C). Moreover, as used herein, the phrase "based on" should not be construed as a reference to a closed set of conditions. For example, an exemplary step described as "based on condition a" may be based on both condition a and condition B without departing from the scope of the present disclosure. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "based at least in part on".

Computer-readable media includes both non-transitory computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. Non-transitory storage media may be any available media that can be accessed by a general purpose or special purpose computer. By way of example, and not limitation, non-transitory computer-readable media can comprise RAM, ROM, electrically erasable programmable read-only memory (EEPROM), compact Disk (CD) ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other non-transitory medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer or processor. Also, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital Subscriber Line (DSL), or wireless technologies such as infrared, radio, and microwave, then the definition of medium includes a coaxial cable, fiber optic cable, twisted pair, digital Subscriber Line (DSL), or wireless technologies such as infrared, radio, and microwave. Disk and disc, as used herein, includes CD, laser disc, optical disc, digital Versatile Disc (DVD), floppy disk and blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above are also included within the scope of computer-readable media.

The description herein is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations without departing from the scope of the disclosure. Thus, the disclosure is not limited to the examples and designs described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method, comprising:

truncating a value of a first parameter associated with a first duration of a clock execution clock cycle coupled to the memory array;

estimating a value of a second parameter inversely proportional to the truncated value of the first parameter;

determining a number of clock cycles associated with a maximum duration for accessing one or more memory cells of the memory array based at least in part on adjusting the second parameter; a kind of electronic device with high-pressure air-conditioning system

The one or more memory cells of the memory array are accessed based at least in part on the determined number of clock cycles associated with the maximum duration.

2. The method of claim 1, wherein accessing the one or more memory cells of the memory array based at least in part on the determined number of clock cycles associated with the maximum duration comprises:

The one or more memory cells are accessed within a total number of clock cycles less than or equal to the determined number of clock cycles.

3. The method as recited in claim 1, further comprising:

truncating a first value of the second parameter to adjust the second parameter from the first value to a second value, wherein determining the number of clock cycles is based at least in part on truncating the first value of the second parameter.

4. The method as recited in claim 1, further comprising:

truncating a value of a third parameter, wherein estimating the value of the second parameter is based at least in part on truncating the value of the third parameter.

5. The method of claim 4, wherein the second parameter is proportional to the truncated value of the third parameter.

6. The method of claim 5, wherein the third parameter comprises a total duration for performing a memory operation.

7. The method of claim 1, wherein the number of clock cycles corresponds to an upper limit of clock cycles used to access the one or more memory cells.

8. The method of claim 1, wherein the maximum duration comprises a maximum value of a refresh interval.

9. An apparatus, comprising:

a memory array comprising an array of memory cells each comprising a capacitive storage element; and circuitry coupled with the memory array and configured to cause the apparatus to:

10. The apparatus of claim 9, wherein the circuitry that accesses the one or more memory cells of the memory array based at least in part on the determined number of clock cycles associated with the maximum duration is configured to cause the apparatus to:

11. The apparatus of claim 9, wherein the circuitry is further configured to cause the apparatus to:

12. The apparatus of claim 9, wherein the circuitry is further configured to cause the apparatus to:

13. The apparatus of claim 12, wherein the second parameter is proportional to the truncated value of the third parameter.

14. The apparatus of claim 13, wherein the third parameter comprises a total duration for performing a memory operation.

15. The apparatus of claim 9, wherein the number of clock cycles corresponds to an upper limit of clock cycles used to access the one or more memory cells.

16. The apparatus of claim 9, wherein the maximum duration comprises a maximum value of a refresh interval.

17. An apparatus, comprising:

a processor;

a memory coupled with the processor; a kind of electronic device with high-pressure air-conditioning system

Instructions stored in the memory and executable by the processor to cause the apparatus to:

18. The apparatus of claim 17, wherein the instructions that access the one or more memory cells of the memory array based at least in part on the determined number of clock cycles associated with the maximum duration are executable by the processor to cause the apparatus to:

19. The apparatus of claim 17, wherein the instructions are further executable by the processor to cause the apparatus to:

20. The apparatus of claim 17, wherein the instructions are further executable by the processor to cause the apparatus to:

21. The apparatus of claim 20, wherein the second parameter is proportional to the truncated value of the third parameter.

22. The apparatus of claim 21, wherein the third parameter comprises a total duration for performing a memory operation.

23. The apparatus of claim 17, wherein the number of clock cycles corresponds to an upper limit of clock cycles used to access the one or more memory cells.

24. The apparatus of claim 17, wherein the maximum duration comprises a maximum value of a refresh interval.

25. A non-transitory computer-readable medium storing code comprising instructions executable by a processor to:

26. The non-transitory computer-readable medium of claim 25, wherein the instructions that access the one or more memory cells of the memory array based at least in part on the determined number of clock cycles associated with the maximum duration are executable by the processor to:

27. The non-transitory computer-readable medium of claim 25, wherein the instructions are further executable by the processor to:

28. The non-transitory computer-readable medium of claim 25, wherein the instructions are further executable by the processor to:

29. The non-transitory computer-readable medium of claim 28, wherein the second parameter is proportional to the truncated value of the third parameter.

30. The non-transitory computer-readable medium of claim 29, wherein the third parameter comprises a total duration for performing a memory operation.

31. The non-transitory computer-readable medium of claim 25, wherein the number of clock cycles corresponds to an upper bound of clock cycles used to access the one or more memory cells.

32. The non-transitory computer-readable medium of claim 25, wherein the maximum duration comprises a maximum value of a refresh interval.

33. An apparatus, comprising:

means for truncating a value of a first parameter associated with a first duration of a clock execution clock cycle coupled to the memory array;

means for estimating a value of a second parameter inversely proportional to the truncated value of the first parameter;

means for determining a number of clock cycles associated with a maximum duration for accessing one or more memory cells of the memory array based at least in part on adjusting the second parameter; a kind of electronic device with high-pressure air-conditioning system

Means for accessing the one or more memory cells of the memory array based at least in part on the determined number of clock cycles associated with the maximum duration.

34. The apparatus of claim 33, wherein the means for accessing the one or more memory cells of the memory array based at least in part on the determined number of clock cycles associated with the maximum duration comprises:

means for accessing the one or more memory cells for a total number of clock cycles less than or equal to the determined number of clock cycles.

35. The apparatus of claim 33, further comprising:

means for truncating a first value of the second parameter to adjust the second parameter from the first value to a second value, wherein determining the number of clock cycles is based at least in part on truncating the first value of the second parameter.