CN117170988A

CN117170988A - Method and apparatus for differential gating fault indication

Info

Publication number: CN117170988A
Application number: CN202310640130.0A
Authority: CN
Inventors: S·E·谢弗
Original assignee: Micron Technology Inc
Current assignee: Micron Technology Inc
Priority date: 2022-06-02
Filing date: 2023-06-01
Publication date: 2023-12-05

Abstract

The application relates to a method and apparatus for differential gating fault indication. The memory device may be configured to indicate a failure using a read strobe signal. The read strobe signal may be a read data strobe (RDQS) signal, such as a true RDQS (RDQS_t) signal or a complement RDQS (RDQS_c) signal. In some examples, the memory device may indicate the failure based on a characteristic of the read strobe signal, such as a mode of the read strobe signal, a voltage level of the read strobe signal, a difference between a first read strobe signal and a second read strobe signal, or any combination thereof. In some examples, a host device may indicate to the memory device which characteristic of the read strobe signal the memory device is to use to indicate the failure.

Description

Method and apparatus for differential gating fault indication

Cross reference

This patent application claims priority from U.S. patent application Ser. No. 17/862,082 entitled "differential gating failure indication (DIFFERENTIAL STROBE FAULT INDICATION)" filed by Schaefer (Schaefer) at 7.11 of 2022 and U.S. provisional patent application Ser. No. 63/348,303 entitled "differential gating failure indication (DIFFERENTIAL STROBE FAULT INDICATION)" filed by Schaefer (Schaefer) at 2.6, each of which is assigned to the present assignee and each of which is expressly incorporated herein by reference in its entirety.

Technical Field

The field relates to differential gating fault indication.

Background

Memory devices are widely used to store information in a variety of electronic devices, such as computers, user devices, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming memory cells within a memory device to various states. For example, a binary memory cell can be programmed to one of two support states, often represented by a logic 1 or a logic 0. In some examples, a single memory cell may support more than two states, any of which may be stored. To access the stored information, the component may read (e.g., sense, detect, retrieve, identify, determine, evaluate) the stored state in the memory device. To store information, the component may write (e.g., program, set, specify) a state in the memory device.

There are various types of memory devices including magnetic hard disks, random Access Memories (RAMs), read Only Memories (ROMs), dynamic RAMs (DRAMs), synchronous Dynamic RAMs (SDRAM), static RAMs (SRAMs), ferroelectric RAMs (ferams), magnetic RAMs (MRAM), resistive RAMs (RRAMs), flash memories, phase Change Memories (PCM), self-selected memories, chalcogenide memory technologies, "NOR" (NOR) and "NAND" (NAND) memory devices, and the like. The memory cells may be described with respect to a volatile configuration or a non-volatile configuration. Memory cells configured in a non-volatile configuration can maintain a stored logic state for a long period of time even in the absence of an external power source. Memory cells configured in a volatile configuration may lose a stored state when disconnected from an external power source.

Disclosure of Invention

A method is described. The method may comprise: receiving, at a memory device, one or more commands to perform one or more operations on a memory array of the memory device; determining a fault associated with performing the one or more operations; indicating a plurality of clock cycles for outputting data associated with a first command of the one or more commands using a first read strobe signal of a set of read strobe signals; and indicating the fault using a second read strobe signal in the set of read strobe signals.

A method is described. The method may comprise: transmitting one or more commands to a memory device to perform one or more operations on a memory array of the memory device; identifying a plurality of clock cycles for receiving data associated with a first command of the one or more commands from the memory device based at least in part on a first read strobe signal of a set of read strobe signals; and identify a fault based at least in part on a second read strobe signal in the set of read strobe signals, the fault associated with performing the one or more operations.

An apparatus is described. The apparatus may include: a controller associated with a memory device, wherein the controller is configured to cause the apparatus to: receiving, at the memory device, one or more commands to perform one or more operations on a memory array of the memory device; determining a fault associated with performing the one or more operations; indicating a plurality of clock cycles for outputting data associated with a first command of the one or more commands using a first read strobe signal of a set of read strobe signals; and indicating the fault using a second read strobe signal in the set of read strobe signals.

An apparatus is described. The apparatus may include: a controller associated with a memory device, wherein the controller is configured to cause the apparatus to: transmitting one or more commands to the memory device to perform one or more operations on a memory array of the memory device; identifying a plurality of clock cycles for receiving data associated with a first command of the one or more commands from the memory device based at least in part on a first read strobe signal of a set of read strobe signals; and identify a fault based at least in part on a second read strobe signal in the set of read strobe signals, the fault associated with performing the one or more operations.

Drawings

Fig. 1 illustrates an example of a system supporting differential gating fault indication according to examples disclosed herein.

Fig. 2 illustrates an example of a memory die supporting differential strobe failure indication in accordance with examples disclosed herein.

Fig. 3 illustrates an example of a timing diagram supporting differential strobe fault indication in accordance with examples disclosed herein.

Fig. 4 illustrates an example of a timing diagram supporting differential strobe fault indication in accordance with examples disclosed herein.

FIG. 5 illustrates a block diagram of a memory device supporting differential strobe failure indication in accordance with an example disclosed herein.

Fig. 6 illustrates a block diagram of a host device supporting differential strobe fault indication in accordance with an example disclosed herein.

Fig. 7 and 8 show flowcharts illustrating one or more methods of supporting differential gating fault indication in accordance with examples disclosed herein.

Detailed Description

The system may include a memory device and a host device that may communicate with each other using a bus. Different packages (e.g., packages that vary in size, density, architecture, other aspects, or any combination thereof) may be used to contain the memory device. Packages containing memory devices may include a plurality of pins that are coupled with a bus and provide access to and from components within the memory device. In some examples, one or more of the pins may be coupled with a data line of a bus, and one or more of the pins may be coupled with a control line of the bus. Although the systems, methods, and techniques are described herein using pins, it should be understood that the term pin may refer to other types of connections to a memory device, such as balls (e.g., solder balls), pillars, or other types of interconnects for coupling the memory device to a bus.

In some cases, a failure at the memory device may affect the reliability of the system. A failure may be associated with an operation (e.g., an access operation) to a memory array of a memory device. For example, an application at the host device (e.g., a functional security application or a high reliability, availability, serviceability (RAS) application) may request notification of a memory failure. However, in some systems, including systems with Low Power Dynamic Random Access Memory (LPDRAM) devices, the system may not include dedicated pins for marking or indicating faults or errors at the memory device. It may be advantageous to configure the memory device to use one or more existing pins of the system to indicate a failure to the host device.

As described herein, a memory device may be configured to indicate a failure using a read strobe signal. The memory device may receive (e.g., from a host device) one or more commands to perform an operation (e.g., an access operation, such as a read operation or a write operation) on a memory array of the memory device. The memory device may determine or identify a failure associated with performing the operation. The memory device may be configured to output data associated with the command using a set of data signals (e.g., DQ pins). The memory device may indicate a set of clock cycles to output data for a command using the first strobe signal. The memory device may additionally indicate a failure using a second read strobe signal configured by the host device, for example.

The read strobe signal may include a read data strobe (RDQS) signal, such as a true RDQS (RDQS_t) signal or a complement RDQS (RDQS_c) signal. In some examples, the memory device may indicate a failure based on a characteristic of the read strobe signal, such as a mode of the read strobe signal, a voltage level of the read strobe signal, a difference between the first read strobe signal and the second read strobe signal, or any combination thereof. In some examples, the host device may indicate to the memory device which characteristics of the read strobe signal the memory device will use to indicate the failure. Thus, using a read strobe signal to indicate a failure improves the reliability of memory operation at the memory device.

Features of the present disclosure are first described in the context of systems and dies as described with reference to fig. 1 and 2. Features of the present disclosure are described in the context of the timing diagrams described with reference to fig. 3 and 4. These and other features of the present disclosure are further illustrated and described with reference to apparatus diagrams and flow charts relating to differential gating fault indications described with reference to fig. 5-8.

Fig. 1 illustrates an example of a system 100 supporting differential gating fault indication according to examples disclosed herein. The system 100 may include a host device 105, a memory device 110, and a plurality of channels 115 coupling the host device 105 with the memory device 110. The system 100 may include one or more memory devices 110, but aspects of the one or more memory devices 110 may be described in the context of a single memory device (e.g., memory device 110).

The system 100 may include portions of an electronic device such as a computing device, mobile computing device, wireless device, graphics processing device, vehicle, or other system. For example, system 100 may illustrate aspects of a computer, a laptop computer, a tablet computer, a smart phone, a cellular phone, a wearable device, an internet connection device, a vehicle controller, and the like. Memory device 110 may be a component of system 100 that may be used to store data for one or more other components of system 100.

Portions of system 100 may be examples of host device 105. Host device 105 may be an instance of a processor (e.g., circuitry, processing components) within a device that uses memory to perform processes within, for example, a computing device, a mobile computing device, a wireless device, a graphics processing device, a computer, a laptop computer, a tablet computer, a smartphone, a cellular telephone, a wearable device, a networking device, a vehicle controller, a system on chip (SoC), or some other fixed or portable electronic device, among other instances. In some examples, host device 105 may refer to hardware, firmware, software, or any combination thereof that implements the functionality of external memory controller 120. In some examples, the external memory controller 120 may be referred to as a host (e.g., host device 105).

Memory device 110 may be a stand-alone device or component that may be used to provide physical memory addresses/space that may be used or referenced by system 100. In some examples, memory device 110 may be configurable to work with one or more different types of host devices. Signaling between host device 105 and memory device 110 may be used to support one or more of the following: modulation schemes for modulating signals, various pin configurations for conveying signals, various form factors for the physical packaging of host device 105 and memory device 110, clock signaling and synchronization between host device 105 and memory device 110, timing conventions, or other functions.

The memory device 110 may be used to store data for components of the host device 105. In some examples, the memory device 110 (e.g., an auxiliary device acting as the host device 105, a dependent device acting as the host device 105) may respond to and execute commands provided by the host device 105 through the external memory controller 120. Such commands may include one or more of the following: a write command for a write operation, a read command for a read operation, a refresh command for a refresh operation, or other commands.

The host device 105 may include one or more of an external memory controller 120, a processor 125, a basic input/output system (BIOS) component 130, or other components such as one or more peripheral components or one or more input/output controllers. Components of host device 105 may be coupled to each other using bus 135.

The processor 125 may be used to provide functionality (e.g., control functionality) for the system 100 or the host device 105. The processor 125 may be a general purpose processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination of these components. In such examples, processor 125 may be an instance of a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), a General Purpose GPU (GPGPU), or a SoC, among other instances. In some examples, the external memory controller 120 may be implemented by or part of the processor 125.

The BIOS component 130 may be a software component that includes a BIOS that acts as firmware that may initialize and run the various hardware components of the system 100 or host device 105. The BIOS component 130 may also manage data flow between the processor 125 and various components of the system 100 or host device 105. The BIOS component 130 may include instructions (e.g., programs, software) stored in one or more of Read Only Memory (ROM), flash memory, or other non-volatile memory.

In some examples, the system 100 or host device 105 may include various peripheral components. The peripheral component may be any input device or output device, or interface for such devices, which may be integrated into or with the system 100 or host device 105. Examples may include one or more of the following: disk controllers, voice controllers, graphics controllers, ethernet controllers, modems, universal Serial Bus (USB) controllers, serial or parallel ports, or peripheral card slots, such as Peripheral Component Interconnect (PCI) or dedicated graphics ports. The peripheral components may be other components understood by those of ordinary skill in the art as peripheral devices.

In some examples, the system 100 or host device 105 may include an I/O controller. The I/O controller may manage data communication between the processor 125 and peripheral components (e.g., input devices, output devices). The I/O controller may manage peripheral devices that are not integrated into or with the system 100 or host device 105. In some examples, an I/O controller may represent a physical connection (e.g., one or more ports) with external peripheral components.

In some examples, the system 100 or host device 105 may include an input component, an output component, or both. The input component may represent a device or signal external to the system 100 that provides information (e.g., signals, data) to the system 100 or components thereof. In some examples, the input component may include an interface (e.g., an interface between user interfaces or other devices). In some examples, the input component may be a peripheral device that interfaces with the system 100 via one or more peripheral components or is manageable by an I/O controller. The output component may represent a device or signal external to the system 100 that may be used to receive output from the system 100 or any of its components. Examples of output components may include a display, an audio speaker, a printing device, another processor on a printed circuit board, and so forth. In some examples, the output component may be a peripheral device that interfaces with the system 100 via one or more peripheral components or is manageable by an I/O controller.

The memory device 110 may include a device memory controller 155 and one or more memory dies 160 (e.g., memory chips) to support capacity (e.g., desired capacity, specified capacity) for data storage. Each memory die 160 (e.g., memory die 160-a, memory die 160-b, memory die 160-N) may include a local memory controller 165 (e.g., local memory controller 165-a, local memory controller 165-b, local memory controller 165-N) and a memory array 170 (e.g., memory array 170-a, memory array 170-b, memory array 170-N). The memory array 170 may be a collection of memory cells (e.g., one or more grids, one or more banks, one or more tiles, one or more sections), where each memory cell may be used to store one or more bits of data. The memory device 110 including two or more memory dies 160 can be referred to as a multi-die memory or a multi-die package, or a multi-chip memory or a multi-chip package.

The device memory controller 155 may comprise components (e.g., circuitry, logic) that may be used to control the operation of the memory device 110. The device memory controller 155 may include hardware, firmware, or instructions that enable the memory device 110 to perform various operations, and may be used to receive, transmit, or execute commands, data, or control information related to the components of the memory device 110. The device memory controller 155 may be used to communicate with one or more of the external memory controller 120, one or more memory dies 160, or the processor 125. In some examples, the device memory controller 155 may control operations of the memory devices 110 described herein in conjunction with a local memory controller 165 of the memory die 160.

In some examples, the memory device 110 may communicate information (e.g., data, commands, or both) with the host device 105. For example, memory device 110 may receive a write command indicating that memory device 110 is to store data received from host device 105, or receive a read command indicating that memory device 110 is to provide host device 105 with data stored in memory die 160, as well as other types of information communication.

The local memory controller 165 (e.g., local to the memory die 160) may include components (e.g., circuitry, logic) that may be used to control the operation of the memory die 160. In some examples, local memory controller 165 may be used to communicate (e.g., receive or transmit data or commands, or both) with device memory controller 155. In some examples, memory device 110 may not include a device memory controller 155 and a local memory controller 165 or an external memory controller 120 that may perform the various functions described herein. Thus, the local memory controller 165 may be used to communicate with the device memory controller 155, with other local memory controllers 165, or directly with the external memory controller 120 or the processor 125, or any combination thereof. Examples of components that may be included in the device memory controller 155 or the local memory controller 165, or both, may include a receiver for receiving signals (e.g., from the external memory controller 120), a transmitter for transmitting signals (e.g., to the external memory controller 120), a decoder for decoding or demodulating received signals, an encoder for encoding or modulating signals to be transmitted, or various other components that may be used to support the operation of the described device memory controller 155 or the local memory controller 165, or both.

The external memory controller 120 may be used to enable communication of information (e.g., data, commands, or both) between components of the system 100 (e.g., between components of the host device 105, such as the processor 125 and the memory device 110). The external memory controller 120 may handle (e.g., convert, transform) communications exchanged between components of the host device 105 and the memory device 110. In some examples, the external memory controller 120 or other components of the system 100 or host device 105 or functions thereof described herein may be implemented by the processor 125. For example, the external memory controller 120 may be hardware, firmware, or software implemented by the processor 125 or other components of the system 100 or host device 105, or some combination thereof. Although the external memory controller 120 is depicted as being external to the memory device 110, in some examples, the external memory controller 120 or functions thereof described herein may be implemented by one or more components of the memory device 110 (e.g., the device memory controller 155, the local memory controller 165), and vice versa.

Components of host device 105 may exchange information with memory device 110 using one or more channels 115. The channel 115 may be used to support communication between the external memory controller 120 and the memory device 110. Each channel 115 may be an example of a transmission medium that carries information between host device 105 and memory device 110. Each channel 115 may include one or more signal paths (e.g., transmission media, conductors) between terminals associated with components of the system 100. The signal paths may be examples of conductive paths that may be used to carry signals. For example, channel 115 may be associated with a first terminal (e.g., including one or more pins, including one or more pads) at host device 105 and a second terminal at memory device 110. Terminals may be examples of conductive input or output points of the devices of system 100, and terminals may be used to act as part of the channels.

Channels 115 (and associated signal paths and terminals) may be dedicated to conveying one or more types of information. For example, lanes 115 may include one or more Command and Address (CA) lanes 186, one or more clock signal (CK) lanes 188, one or more Data (DQ) lanes 190, one or more other lanes 192, or any combination thereof. In some examples, signaling may be communicated over channel 115 using Single Data Rate (SDR) signaling or Double Data Rate (DDR) signaling. In SDR signaling, one modulation symbol (e.g., signal level) of a signal may be registered for each clock cycle (e.g., on a rising or falling edge of a clock signal). In DDR signaling, two modulation symbols (e.g., signal levels) of a signal may be registered for each clock cycle (e.g., on both rising and falling edges of a clock signal).

In some examples, CA channel 186 can be used to communicate commands between host device 105 and memory device 110 that include control information (e.g., address information) associated with the commands. For example, the commands carried by CA channel 186 may include read commands having addresses of desired data. In some examples, CA channel 186 may include any number of signal paths (e.g., eight or nine signal paths) to convey control information (e.g., commands or addresses).

In some examples, clock signal channel 188 may be used to communicate one or more clock signals between host device 105 and memory device 110. The clock signal may be used to oscillate between a high state and a low state, and may support coordination (e.g., in time) between the actions of the host device 105 and the memory device 110. In some examples, the clock signal may be single ended. In some examples, the clock signal may provide a timing reference for command and address operations of the memory device 110 or other system level operations of the memory device 110. The clock signal may be referred to as a control clock signal, a command clock signal, or a system clock signal. The system clock signal may be generated by a system clock, which may include one or more hardware components (e.g., oscillators, crystals, logic gates, transistors).

In some examples, the data channel 190 may be used to communicate information (e.g., data, control information) between the host device 105 and the memory device 110. For example, the data channel 190 may convey (e.g., bi-directionally) information to be written to the memory device 110 or information read from the memory device 110.

Channel 115 may include any number of signal paths (including a single signal path). In some examples, channel 115 may include multiple individual signal paths. For example, a channel may be x4 (e.g., including four signal paths), x8 (e.g., including eight signal paths), x16 (including sixteen signal paths), and so on.

In some examples, one or more other channels 192 may include one or more Error Detection Code (EDC) channels. The EDC channel may be used to communicate error detection signals, such as checksums, to improve system reliability. The EDC channel may include any number of signal paths.

As described herein, the memory device 110 may be configured to indicate a failure using a read strobe signal (e.g., an RDQS signal), which may be communicated using one or more channels 115. In some examples, the memory device 110 may indicate a failure based on a characteristic of the read strobe signal, such as a mode of the read strobe signal, a voltage level of the read strobe signal, a difference between the first read strobe signal and the second read strobe signal, or any combination thereof. In some examples, host device 105 may indicate to memory device 110 which characteristics of the read strobe signal memory device 110 will use to indicate the failure.

Fig. 2 illustrates an example of a memory die 200 supporting differential strobe failure indication in accordance with examples disclosed herein. Memory die 200 may be an example of memory die 160 described with reference to fig. 1. In some examples, the memory die 200 may be referred to as a memory chip, a memory device, or an electronic memory apparatus. The memory die 200 may include one or more memory cells 205, which may be programmable to store different logic states (e.g., programmed to one of a set of two or more possible states). For example, memory cell 205 may be used to store one bit of information at a time (e.g., a logic 0 or a logic 1). In some examples, memory cell 205 (e.g., a multi-level memory cell) may be used to store more than one bit of information at a time (e.g., logic 00, logic 01, logic 10, logic 11). In some examples, the memory cells 205 may be arranged in an array, such as the memory array 170 described with reference to fig. 1.

In some examples, the memory cell 205 may store a charge in a capacitor that represents a programmable state. The DRAM architecture may include a capacitor that includes a dielectric material to store a charge representing a programmable state. Other storage devices and components are also possible in other memory architectures. For example, a nonlinear dielectric material may be used. The memory cell 205 may include logic storage components such as a capacitor 230 and a switch component 235 (e.g., a cell selection component). Capacitor 230 may be an example of a dielectric capacitor or a ferroelectric capacitor. The node of capacitor 230 may be coupled to a voltage source 240, which may be a cell plate reference voltage, e.g., vpl, or may be ground, e.g., vss.

The memory die 200 may include access lines (e.g., word lines 210, digit lines 215) arranged in a pattern such as a grid-like pattern. The access line may be a wire coupled to the memory cell 205 and may be used to perform access operations to the memory cell 205. In some examples, word line 210 may be referred to as a row line. In some examples, the digit line 215 may be referred to as a column line or a bit line. References to access lines, row lines, column lines, word lines, digit lines, or bit lines, or the like, may be interchanged without affecting the understanding. Memory cell 205 may be positioned at the intersection of word line 210 and digit line 215.

Operations such as reading and writing to memory cells 205 may be performed by activating access lines such as word line 210 and/or digit line 215. By biasing word line 210 and digit line 215 (e.g., applying a voltage to word line 210 or digit line 215), a single memory cell 205 can be accessed at its intersection. The intersection of word line 210 and digit line 215 in a two-dimensional or three-dimensional configuration may be referred to as an address of memory cell 205. Activating either word line 210 or digit line 215 may include applying a voltage to the respective line.

Access to the memory cells 205 may be controlled by a row decoder 220 or a column decoder 225, or any combination thereof. For example, the row decoder 220 may receive a row address from the local memory controller 260 and activate the word line 210 based on the received row address. Column decoder 225 may receive a column address from local memory controller 260 and may activate digit line 215 based on the received column address.

Selecting or deselecting the memory cell 205 may be accomplished by activating or deactivating the switch component 235 using the word line 210. Capacitor 230 may be coupled to digit line 215 using a switching component 235. For example, the capacitor 230 may be isolated from the digit line 215 when the switch component 235 is deactivated, and the capacitor 230 may be coupled to the digit line 215 when the switch component 235 is activated.

The sensing component 245 may be used to detect a state (e.g., charge) stored on the capacitor 230 of the memory cell 205 and determine a logic state of the memory cell 205 based on (e.g., using) the stored state. The sensing component 245 may include one or more sense amplifiers to amplify or otherwise convert signals generated by accessing the memory cells 205. The sensing component 245 may compare a signal detected from the memory cell 205 to a reference 250 (e.g., a reference voltage). The detected logic state of the memory cell 205 may be provided as an output of the sensing component 245 (e.g., to the input/output 255) and may be indicated to another component of the memory device (e.g., the memory device 110) that includes the memory die 200.

The local memory controller 260 may control access of the memory cells 205 through various components (e.g., row decoder 220, column decoder 225, sensing component 245). The local memory controller 260 may be an example of the local memory controller 165 described with reference to fig. 1. In some examples, one or more of row decoder 220, column decoder 225, and sensing component 245 may be co-located with local memory controller 260. The local memory controller 260 can be used to receive one or more of commands or data from one or more different memory controllers (e.g., an external memory controller 120 associated with the host device 105, another controller associated with the memory die 200), transform the commands or data (or both) into information usable by the memory die 200, perform one or more operations on the memory die 200, and transfer data from the memory die 200 to a host (e.g., the host device 105) based on performing the one or more operations. The local memory controller 260 may generate row and column address signals to activate the target word line 210 and the target digit line 215. The local memory controller 260 can also generate and control various signals (e.g., voltages, currents) used during operation of the memory die 200. In general, the amplitude, shape, or duration of the applied voltages or currents discussed herein may vary, and may be different for the various operations discussed in the process of operating the memory die 200.

The local memory controller 260 can be used to perform one or more access operations to one or more memory cells 205 of the memory die 200. Examples of access operations may include write operations, read operations, refresh operations, precharge operations, or activate operations, among others. In some examples, the access operations may be performed or otherwise coordinated by the local memory controller 260 in response to various access commands (e.g., from the host device 105). The local memory controller 260 may be used to perform other access operations not listed herein or other operations related to the operation of the memory die 200 that are not directly related to accessing the memory cells 205.

The local memory controller 260 can be used to perform write operations (e.g., programming operations) to one or more memory cells 205 of the memory die 200. During a write operation, the memory cells 205 of the memory die 200 may be programmed to store a desired state (e.g., logic state, charge state). The local memory controller 260 may identify the target memory cell 205 that will perform the write operation. The local memory controller 260 can identify a target word line 210 and a target digit line 215 coupled to a target memory cell 205 (e.g., an address of the target memory cell 205). The local memory controller 260 can activate the target word line 210 and the target digit line 215 (e.g., apply a voltage to the word line 210 or the digit line 215) to access the target memory cell 205. The local memory controller 260 can apply a signal (e.g., write pulse, write voltage) to the digit line 215 during a write operation to store a particular state (e.g., charge) in the capacitor 230 of the memory cell 205. The pulse used as part of the write operation may include one or more voltage levels over a duration.

The local memory controller 260 can be used to perform read operations (e.g., sense operations) on one or more memory cells 205 of the memory die 200. During a read operation, a state (e.g., logic state, charge state) stored in the memory cells 205 of the memory die 200 may be evaluated (e.g., read, determined, identified). The local memory controller 260 may identify the target memory cell 205 that will perform the read operation. The local memory controller 260 can identify a target word line 210 and a target digit line 215 coupled to a target memory cell 205 (e.g., an address of the target memory cell 205). The local memory controller 260 can activate the target word line 210 and the target digit line 215 (e.g., apply a voltage to the word line 210 or the digit line 215) to access the target memory cell 205. The target memory cell 205 may communicate a signal (e.g., charge, voltage) to the sensing component 245 in response to biasing the access line. The sensing component 245 may amplify the signal. The local memory controller 260 can activate the sensing component 245 (e.g., latch the sensing component) and compare the signal received from the memory cell 205 to a reference (e.g., reference 250). Based on the comparison, the sensing component 245 can determine a logic state stored on the memory cell 205.

Packages may be used to contain and provide access to and from a memory device, such as memory device 110 in fig. 1, which may include memory die 200. The package may include pins that provide access to and from components within the memory device 110 (e.g., the memory die 200). For example, a memory controller in a memory device (e.g., device memory controller 155 in FIG. 1, local memory controller 165 in FIG. 1, local memory controller 260) may be coupled with a set of DQ pins that allow data to be input to or output from the memory controller. The package may also contain an RDQS pin that is used by the memory controller to output a clock signal (e.g., an RDQS signal) for sampling the data signal on the DQ pin-e.g., when the memory device is configured to operate using frequencies within a frequency range. Further, the package may contain a Data Mask Inversion (DMI) pin for outputting error management information-e.g., information for detecting and/or correcting errors.

The pins of the package may also be coupled to a bus (or transmission bus) containing wires (or transmission lines). The bus may be used to provide a communication path between the memory device and a host device (e.g., host device 105 of fig. 1). The transmission lines of the bus may include data lines and control lines. In some examples, the DQ pins may be coupled with data lines of a bus, the RDQS pins may be coupled with control (or clock) lines of the bus, and the DMI pins may be coupled with control lines of the bus. In some examples, the pins of the package and/or the transmission lines of the bus may be terminated (e.g., weakly terminated) to a voltage source or a voltage sink (e.g., ground reference). Thus, when the bus is not in use (e.g., in an idle, inactive, or floating state), the voltage of the pins and transmission lines may tend towards the voltage of the voltage source or sink. Alternatively, the voltage of the transmission line may be driven by the memory device or host device when the memory device or host device is using the bus (e.g., in an active state).

In some examples, a unit interval of a read operation may be determined based on a read clock signal (which may include one or more read strobe signals) output on the RDQS pin, where each unit interval may correspond to a duration between a falling edge of the read clock and a subsequent rising edge of the read clock. The read data signal may be aligned with the output of the data packet on the DQ pin. In some examples, the memory device may output the read clock signal when the memory device is operating within a particular frequency range. When operating outside the frequency range, the memory device may not output the read clock signal. In this case, the unit interval may be determined based on a Write Clock (WCK) signal generated at the host device. In some examples, the RDQS signal may be generated using a differential signal corresponding to the WCK signal received from the host device (which may be referred to as a differential gating technique or differential mode). For example, the RDQS signal may be generated using inverted and non-inverted versions of the WCK signal, which may correspond to the RDQS_c signal and the RDQS_t signal, respectively. In other examples, the RDQS signal may be generated using a non-inverted version of the WCK signal received from the host device (which may be referred to as single-ended gating techniques or single-ended modes).

As described herein, a memory device may be configured to indicate a failure using a read strobe signal. In some examples, the memory device may indicate a failure based on a characteristic of the read strobe signal, such as a mode of the read strobe signal, a voltage level of the read strobe signal, a difference between the first read strobe signal and the second read strobe signal, or any combination thereof. In some examples, the memory device may use the read strobe signal that is not enabled to indicate a failure, such as when generating the RDQS signal using single-ended mode. For example, if the RDQS_t signal is enabled to perform RDQS gating functions (e.g., as part of a write link Error Correction Code (ECC) function) and the RDQS_c signal does not gate data to the host device, the RDQS_c signal may be used to indicate a failure. In some examples, the host device may indicate to the memory device which characteristics of the read strobe signal the memory device will use to indicate the failure. Thus, using a read strobe signal to indicate a failure improves the reliability of memory operation at the memory device.

Fig. 3 illustrates an example of a timing diagram 300 supporting differential strobe fault indication according to examples disclosed herein. Timing diagram 300 depicts signaling exchanges between a host device and a memory device, which may be examples of the host device and memory device described in fig. 1 and 2. Timing diagram 300 may depict signals that may be transmitted on one or more lines of a bus, including CA line 305, control line 310, WCK line 315, DQ line 320, and RDQS line 325, among other lines. In some examples, CA line 305 and control line 305 may be examples of CA lanes 186, WCK line 315 and RDQS line 325 may be examples of CK lanes 188, and DQ line may be examples of DQ lanes 190 described with reference to FIG. 1.

In some examples, timing diagram 300 may describe an exemplary read operation between a host device and a memory device. To initiate a read operation, the host device may transmit a read command 311 to the memory device via control line 310 requesting data 322 stored in the memory array. Simultaneously with read command 311, the host device may transmit authentication signal 306 and bank group signal 307 via CA line 305 to authenticate read command 311 and identify the bank group associated with the requested data 322. After successfully receiving and/or decoding the read command 311, the memory device may initiate a sequence of operations for outputting the data 322 requested by the read command 311. In this case, the memory device may retrieve data and error management information (e.g., parity bits) from one or more memory locations addressed by the read command 311.

In some examples, the host device may transmit (e.g., issue) a number of deselect commands 312 (which may be referred to as DES commands, DSEL commands, device deselect commands, or command inhibit commands) between activate or data access commands via control line 310 to satisfy timing constraints, such as a read latency 313 (which may be referred to as RL or t) associated with executing a sequence of operations for outputting data 322 _RL ). In some examples, the read delay 313 may correspond to a number of clock cycles of the WCK signal 316 on the WCK line 315. For example, the host device may transmit a WCK signal 316-a (which may be referred to as a true WCK (WCK_t) signal) and a WCK signal 316-b, which may be an inverted version of the WCK signal 316-a, and may be referred to as a complement WCK (WCK_c) signal, via the WCK line 315.

The memory device may output data 322 requested by read command 311 via DQ lines 320. The memory device may also output a read strobe signal 326 over the RDQS line 325 of the bus, where the read strobe signal 326 may be used to synchronize the sampling of the DQ lines 320 at the host device with the output of the data 322 from the memory device. For example, the memory device may output a read strobe signal 326-a to indicate the clock cycle for outputting the requested data 322 via DQ line 320. In some examples, the new subset of the requested data is output on the rising edge of the read strobe signal 326-a and the falling edge of the read strobe signal 326-a.

Each rising and falling edge of the read strobe signal 326-a may be spaced apart from the unit of data output operation 323 (which may be referred to as t _DQSQ ) And (5) associating. In some examples, the unit interval 323 for outputting data on the DQ line 320 may be offset from the clock period of the WCK signal 316-a by a read response time 321, which may be referred to as t _WCK2DQO . In some examples, the memory device may output the read strobe signal 326-a for a read preamble duration 327, which may be referred to as t _RPRE . Reading the preamble duration may include indicating to the host device the requested numberThe number of clock cycles (e.g., 2 clock cycles, 4 clock cycles) entered on DQ line 320 by 322.

In some examples (e.g., when differential gating techniques or differential modes are used), the inverted and non-inverted versions of the WCK signal 316-a may be used to generate a read clock signal output on RDQS line 325, which may correspond to the RDQS_c signal (e.g., read gate signal 326-b) and the RDQS_t signal (e.g., read gate signal 326-a), respectively. In other examples, a non-inverted version of the WCK signal 316-a received from the host device may be used to generate a read clock signal (which may be referred to as a single ended strobe technique or a single ended mode).

As described herein, a memory device may be configured to indicate a failure using one or more read strobe signals 326. In some examples, the memory device may indicate a failure based on a characteristic of the read strobe signal 326, such as a mode of the read strobe signal 326, a voltage level of the read strobe signal 326, a difference between the read strobe signal 326-a and the read strobe signal 326-b, or any combination thereof. In some examples, such as when generating a read clock signal using single-ended mode, the memory device may indicate a failure using a read strobe signal 326 that is not used to generate the read clock signal. For example, if the RDQS_t signal (e.g., read strobe signal 326-a) is enabled to perform the RDQS strobe function (e.g., as part of a write link ECC function) and the RDQS_c signal (e.g., read strobe signal 326-b) is not gating data to the host device, the RDQS_c signal may be used to indicate a failure. In some cases, the RDQS_c signal may indicate a fault that occurs concurrently with a clock cycle of a data signal (e.g., DQ) associated with the fault. Alternatively, the read clock signal may be generated using the RDQS_c signal and the RDQS_t signal using a differential mode. In such cases, either or both of the RDQS_c signal or the RDQS_t signal may be used to indicate a fault, and may indicate a fault that occurs concurrently with a clock cycle of a data signal (e.g., DQ) associated with the fault. In some examples, the host device may indicate to the memory device which characteristics of the read strobe 326 the memory device will use to indicate the failure. Thus, using the read strobe signal 326 to indicate a failure improves the reliability of memory operations at the memory device.

Fig. 4 illustrates an example of a timing diagram 400 supporting differential strobe fault indication in accordance with examples disclosed herein. Timing diagram 400 depicts an example of signaling exchange between a host device and a memory device, which may be the examples of host devices and memory devices described in fig. 1 and 2.

Timing diagram 400 depicts an example read strobe signal 326 (e.g., RDQS signal) that may be transmitted from a memory device to a host device over one or more data lines of a bus. In some examples, the host device may capture the differential signal 405 (e.g., a read clock signal) based on a difference between two read strobe signals 326-c and 326-d that are inverted relative to each other (e.g., have a phase offset of 180 °), and the differential signal 405 may be converted to an internal strobe signal 410-a. The host device may use the internal strobe signal 410-a to identify a clock cycle for capturing read data output by the memory device, for example in response to a read command as described with reference to fig. 3.

In some cases, for example, based on a command from a host device, a memory device may determine or identify a failure associated with performing an operation (e.g., an access operation) at the memory device. Thus, in addition to using the first read strobe signal 326 to indicate read data, the memory device may be configured to use the second read strobe signal 326 to indicate a failure starting at time 415. For example, the first read strobe signal 326 may be the RDQS_t signal and the second read strobe signal 326 may be the RDQS_c signal (or vice versa). In some examples, time 415 may correspond to a time after the indication of the data output. For example, the memory device may indicate a failure after a certain number of cycles corresponding to a read preamble indicating the presence of data on the DQ lines. Alternatively, time 415 may correspond to a time other than the duration associated with the data output (e.g., when read strobe 326 may be idle). For example, the failure may be based on one or more operations (e.g., internal maintenance operations) that were not directly performed due to commands from the host device. Additionally or alternatively, time 415 may be based on when the memory device detected a failure. For example, the memory device may indicate a fault that occurs concurrently with a clock cycle of a DQ line associated with the fault. Based on the internal strobe signal 410 generated based on the first and second read strobe signals 326, the host device may identify a fault at the memory device. Thus, using the read strobe signal 326 to indicate a failure improves the reliability of memory operations at the memory device.

In some examples, to indicate a failure, the memory device may output a stable voltage level on the read strobe signal 326-f (e.g., drive the read strobe signal 326-f at a stable voltage, such as a low voltage) while outputting a read data pulse on the read strobe signal 326-e. Thus, based on the internal strobe signal 410-b generated based on the read strobe signals 326-e and 326-f, the host device can detect the read data while also identifying the failure indicated by the memory device.

In some examples, to indicate a failure, the memory device may output read data pulses on read strobe signal 326-h according to a periodicity different from the periodicity of the read data pulses output on read strobe signal 326-g. For example, the memory device may switch the read strobe 326-g between a first voltage level and a second voltage level according to a first periodicity and switch the read strobe 326-h between the first voltage level and the second voltage level according to a second periodicity. The memory device may indicate a failure based on a difference between the first period and the second period, and the host device may identify the failure according to the internal strobe signal 410-c generated based on the read strobe signals 326-g and 326-h.

In some examples, to indicate a failure, the memory device may output a read data pulse on read strobe signal 326-i that is in phase (or has a phase offset other than 180 °) with respect to the read data pulse output on read strobe signal 326-j. For example, the memory device may switch the read strobe 326-i between a first voltage level and a second voltage level according to a first periodicity, and switch the read strobe 326-j between the first voltage level and the second voltage level according to the same first periodicity. The memory device may indicate a failure based on the in-phase read strobe signals 326-i and 326-j, and the host device may identify the failure from the internal strobe signal 410-d generated based on the read strobe signals 326-i and 326-j. That is, the internal strobe signal 410-d may be a steady state voltage (e.g., zero voltage) based on the in-phase read strobe signals 326-i and 326-j, and the host device may easily detect the in-phase read strobe signals 326-i and 326-j.

In some examples, to indicate a failure, the memory device may output a first voltage level (e.g., a stable voltage level having a first polarity) using the read strobe signal 326-k and a second voltage level (e.g., a stable voltage level having a second polarity) using the read strobe signal 326-l. The memory device may indicate a failure based on a difference between the first voltage level and the second voltage level, and the host device may identify the failure according to the internal strobe signal 410-e generated based on the read strobe signals 326-k and 326-l. That is, the internal strobe signal 410-e may be a steady state voltage based on a difference between the first voltage level and the second voltage level.

In some examples, the memory device may use the read strobe signal 326 to indicate a fault (e.g., use the read strobe signal 326 to drive a fault flag condition) for a configured duration (e.g., from time 415). For example, the memory device may indicate a failure according to a defined or programmed timeout, or until the host device acknowledges the failure indication. Additionally or alternatively, the host device may indicate to the memory device which faults (e.g., which types of faults) are configured to trigger the fault indication.

Fig. 5 illustrates a block diagram 500 of a memory device 520 supporting differential strobe failure indication according to an example disclosed herein. Memory device 520 may be an example of aspects of the memory devices described with reference to fig. 1-4. The memory device 520, or various components thereof, may be an example of means for performing aspects of differential strobe failure indication as described herein. For example, memory device 520 may include command manager 525, failure component 530, read strobe component 535, error component 540, or any combination thereof. Each of these components may communicate with each other directly or indirectly (e.g., via one or more buses).

Command manager 525 may be configured or otherwise support means for: one or more commands are received at a memory device to perform one or more operations on a memory array of the memory device. The fault component 530 may be configured or otherwise support means for: a fault associated with performing the one or more operations is determined. The read strobe assembly 535 may be configured or otherwise support means for: a first read strobe in the set of read strobe signals is used to indicate a plurality of clock cycles for outputting data associated with a first command of the one or more commands. In some examples, the read strobe assembly 535 may be configured or otherwise support means for: a fault is indicated using a second read strobe signal in the set of read strobe signals.

In some examples, command manager 525 may be configured or otherwise support means for: before indicating the plurality of clock cycles for outputting data, an indication is received that the memory device is configured to use the first read strobe signal in a single ended mode.

In some examples, the one or more commands include a write command, and error component 540 may be configured or otherwise support means for: an error associated with executing the write command is detected, wherein determining the failure is based at least in part on detecting the error. In some examples, the one or more commands include a write command, and the read strobe component 535 may be configured or otherwise support means for: based at least in part on the write command, one or more parity bits are output for a duration using the first read strobe signal. In some examples, the one or more commands include a write command, and the read strobe component 535 may be configured or otherwise support means for: an error is indicated using the second read strobe during the duration, wherein indicating the fault is based at least in part on the indicating the error.

In some examples, the read strobe assembly 535 may be configured or otherwise support means for: a voltage level for the plurality of clock cycles is output using a second read strobe signal, wherein the fault is indicated based at least in part on the voltage level.

In some examples, the read strobe assembly 535 may be configured or otherwise support means for: the first read strobe signal is switched between a first voltage level and a second voltage level according to a first periodicity, wherein indicating the plurality of clock cycles for outputting data is based at least in part on switching the first read strobe signal. In some examples, the read strobe assembly 535 may be configured or otherwise support means for: the second read strobe signal is switched between the first voltage level and the second voltage level according to a second periodicity, wherein the fault is indicated based at least in part on a difference between the first periodicity and the second periodicity.

In some examples, the read strobe assembly 535 may be configured or otherwise support means for: the first read strobe signal is switched between a first voltage level and a second voltage level according to a first periodicity, wherein indicating the plurality of clock cycles for outputting data is based at least in part on switching the first read strobe signal. In some examples, the read strobe assembly 535 may be configured or otherwise support means for: the second read gate signal is switched between a first voltage level and a second voltage level according to a first periodicity, wherein the fault is indicated based at least in part on being in phase with the first read gate signal according to the first periodicity.

In some examples, the read strobe assembly 535 may be configured or otherwise support means for: a first voltage level for a plurality of clock cycles is output using a first read strobe signal. In some examples, the read strobe assembly 535 may be configured or otherwise support means for: a second voltage level for the plurality of clock cycles is output using a second read strobe signal, wherein the fault is indicated based at least in part on a difference between the first voltage level and the second voltage level.

In some instances, the fault is indicated according to a timeout duration based at least in part on a characteristic of the fault.

Fig. 6 illustrates a block diagram 600 of a host device 620 supporting differential strobe failure indication according to an example disclosed herein. The host device 620 may be an example of aspects of the host devices described with reference to fig. 1-4. The host device 620 or various components thereof may be an example of means for performing aspects of differential strobe failure indication as described herein. For example, the host device 620 can include a command component 625, a read strobe signal component 630, or any combination thereof. Each of these components may communicate with each other directly or indirectly (e.g., via one or more buses).

The command component 625 may be configured or otherwise support means for: one or more commands are transmitted to the memory device to perform one or more operations on a memory array of the memory device. The read strobe signal assembly 630 may be configured or otherwise support means for: a plurality of clock cycles for receiving data associated with a first command of the one or more commands from the memory device is identified based at least in part on a first read strobe signal of the set of read strobe signals. In some examples, the read strobe signal component 630 may be configured or otherwise support means for: a fault is identified based at least in part on a second read strobe signal in a set of read strobe signals, the fault associated with performing the one or more operations.

In some examples, command component 625 may be configured or otherwise support means for: before identifying the plurality of clock cycles for outputting data, transmitting an indication that the memory device is configured to use the first read strobe signal in a single ended mode.

In some examples, the one or more commands include a write command, and the read strobe signal component 630 may be configured or otherwise support means for: based at least in part on the first read strobe signal, one or more parity bits are identified for a duration based at least in part on the write command. In some examples, the one or more commands include a write command, and the read strobe signal component 630 may be configured or otherwise support means for: an error associated with the write command is identified based at least in part on the second read strobe signal and during the duration, wherein identifying the fault is based at least in part on identifying the error.

In some examples, the read strobe signal component 630 may be configured or otherwise support means for: a voltage level of the second read strobe signal output for the plurality of clock cycles is identified, wherein the fault is identified based at least in part on the voltage level.

In some examples, the read strobe signal component 630 may be configured or otherwise support means for: the first read strobe signal is identified as being switched between a first voltage level and a second voltage level according to a first periodicity, wherein identifying the plurality of clock cycles for receiving data is based at least in part on identifying the switching of the first read strobe signal. In some examples, the read strobe signal component 630 may be configured or otherwise support means for: the second read strobe signal is identified to switch between the first voltage level and the second voltage level according to a second periodicity, wherein the fault is identified based at least in part on a difference between the first periodicity and the second periodicity.

In some examples, the read strobe signal component 630 may be configured or otherwise support means for: the first read strobe signal is identified as being switched between a first voltage level and a second voltage level according to a first periodicity, wherein identifying the plurality of clock cycles for receiving data is based at least in part on identifying the switching of the first read strobe signal. In some examples, the read strobe signal component 630 may be configured or otherwise support means for: the second read strobe signal is identified as switching between the first voltage level and the second voltage level according to the first periodicity, wherein the fault is identified based at least in part on the second read strobe signal being in phase with the first read strobe signal according to the first periodicity.

In some examples, the read strobe signal component 630 may be configured or otherwise support means for: a first read strobe signal output is identified for a first voltage level of the plurality of clock cycles. In some examples, the read strobe signal component 630 may be configured or otherwise support means for: a second read strobe signal output is identified for a second voltage level of the plurality of clock cycles, wherein a fault is identified based at least in part on a difference between the first voltage level and the second voltage level.

In some examples, the read strobe signal component 630 may be configured or otherwise support means for: the characteristics of the fault are identified based at least in part on a timeout duration associated with the second read strobe signal.

Fig. 7 shows a flow chart illustrating a method 700 of supporting differential gating fault indication according to examples disclosed herein. The operations of method 700 may be implemented by a memory device or components thereof as described herein. For example, the operations of method 700 may be performed by the memory devices described with reference to fig. 1-5. In some examples, the memory device may execute a set of instructions to control the functional elements of the device to perform the described functions. Additionally or alternatively, the memory device may use dedicated hardware to perform aspects of the described functions.

At 705, the method may include receiving, at a memory device, one or more commands to perform one or more operations on a memory array of the memory device. Operations of 705 may be performed according to examples as disclosed herein. In some examples, aspects of the operations of 705 may be performed by command manager 525 described with reference to fig. 5.

At 710, the method may include determining a fault associated with performing the one or more operations. Operations of 710 may be performed according to examples as disclosed herein. In some examples, aspects of the operation of 710 may be performed by the fault component 530 described with reference to fig. 5.

At 715, the method may include indicating a plurality of clock cycles for outputting data associated with a first command of the one or more commands using a first read strobe signal of a set of read strobe signals. The operations of 715 may be performed according to examples as disclosed herein. In some examples, aspects of the operations of 715 may be performed by the read strobe component 535 described with reference to fig. 5.

At 720, the method may include indicating a fault using a second read strobe signal in the set of read strobe signals. Operations of 720 may be performed according to examples as disclosed herein. In some examples, aspects of the operation of 720 may be performed by the read strobe component 535 described with reference to fig. 5.

In some examples, an apparatus as described herein may perform one or more methods, such as method 700. The apparatus may include features, circuits, logic, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) or any combination thereof for performing the following aspects of the disclosure:

aspect 1: a method, apparatus, or non-transitory computer-readable medium comprising operations, features, circuits, logic, means, or instructions, or any combination thereof, for: receiving, at a memory device, one or more commands to perform one or more operations on a memory array of the memory device; determining a fault associated with performing the one or more operations; indicating a plurality of clock cycles for outputting data associated with a first command of the one or more commands using a first read strobe signal of a set of read strobe signals; and indicating the fault using a second read strobe signal in the set of read strobe signals.

Aspect 2: the method, apparatus, or non-transitory computer-readable medium of aspect 1, further comprising operations, features, circuits, logic, means, or instructions, or any combination thereof, for: an indication is received that the memory device is configured to use the first read strobe signal in a single ended mode prior to indicating the plurality of clock cycles for outputting the data.

Aspect 3: the method, apparatus, or non-transitory computer-readable medium of any one of aspects 1-2, wherein the one or more commands comprise a write command, and the method, apparatus, or non-transitory computer-readable medium further comprises operations, features, circuits, logic, means, or instructions, or any combination thereof, for: detecting an error associated with executing the write command, wherein determining the failure is based at least in part on detecting the error; based at least in part on the write command, outputting one or more parity bits over a duration using the first read strobe signal; and indicating the error using the second read strobe signal during the duration, wherein indicating the fault is based at least in part on indicating the error.

Aspect 4: the method, apparatus, or non-transitory computer-readable medium of any one of aspects 1-3, further comprising operations, features, circuits, logic, means, or instructions, or any combination thereof, for: a voltage level for the plurality of clock cycles is output using the second read strobe signal, wherein the fault is indicated based at least in part on the voltage level.

Aspect 5: the method, apparatus, or non-transitory computer-readable medium of any one of aspects 1-4, further comprising operations, features, circuits, logic, means, or instructions, or any combination thereof, for: switching the first read strobe signal between a first voltage level and a second voltage level according to a first periodicity, wherein indicating the plurality of clock cycles for outputting the data is based at least in part on switching the first read strobe signal; and switching the second read strobe signal between the first voltage level and the second voltage level according to a second periodicity, wherein the fault is indicated based at least in part on a difference between the first periodicity and the second periodicity.

Aspect 6: the method, apparatus, or non-transitory computer-readable medium of any one of aspects 1-5, further comprising operations, features, circuits, logic, means, or instructions, or any combination thereof, for: switching the first read strobe signal between a first voltage level and a second voltage level according to a first periodicity, wherein indicating the plurality of clock cycles for outputting the data is based at least in part on switching the first read strobe signal; and switching the second read strobe signal between the first voltage level and the second voltage level according to the first periodicity, wherein the fault is indicated based at least in part on the second read strobe signal being in phase with the first read strobe signal according to the first periodicity.

Aspect 7: the method, apparatus, or non-transitory computer-readable medium of any one of aspects 1-6, further comprising operations, features, circuits, logic, means, or instructions, or any combination thereof, for: outputting a first voltage level for the plurality of clock cycles using the first read strobe signal; and outputting a second voltage level for the plurality of clock cycles using the second read strobe signal, wherein the fault is indicated based at least in part on a difference between the first voltage level and the second voltage level.

Aspect 8: the method, apparatus, or non-transitory computer-readable medium of any one of aspects 1-7, wherein the failure is indicated according to a timeout duration based at least in part on a characteristic of the failure.

Fig. 8 shows a flow chart illustrating a method 800 of supporting differential gating fault indication according to an example disclosed herein. The operations of method 800 may be implemented by a host device or components thereof as described herein. For example, the operations of method 800 may be performed by the host device described with reference to fig. 1-4 and 6. In some examples, the host device may execute a set of instructions to control the functional elements of the device to perform the described functions. Additionally or alternatively, the host device may use dedicated hardware to perform aspects of the described functions.

At 805, the method may include transmitting, to a memory device, one or more commands to perform one or more operations on a memory array of the memory device. The operations of 805 may be performed according to examples as disclosed herein. In some examples, aspects of the operation of 805 may be performed by command component 625 described with reference to fig. 6.

At 810, the method may include identifying a plurality of clock cycles for receiving data associated with a first command of the one or more commands from the memory device based at least in part on a first read strobe signal of a set of read strobe signals. The operations of 810 may be performed according to examples as disclosed herein. In some examples, aspects of the operation of 810 may be performed by the read strobe signal component 630 described with reference to fig. 6.

At 815, the method may include identifying a fault based at least in part on a second read strobe signal in a set of read strobe signals, the fault associated with performing the one or more operations. Operations of 815 may be performed according to examples as disclosed herein. In some examples, aspects of the operations of 815 may be performed by the read strobe signal component 630 described with reference to fig. 6.

In some examples, an apparatus as described herein may perform one or more methods, such as method 800. The apparatus may include features, circuits, logic, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) or any combination thereof for performing the following aspects of the disclosure:

Aspect 9: a method, apparatus, or non-transitory computer-readable medium comprising operations, features, circuits, logic, means, or instructions, or any combination thereof, for: transmitting one or more commands to a memory device to perform one or more operations on a memory array of the memory device; identifying a plurality of clock cycles for receiving data associated with a first command of the one or more commands from the memory device based at least in part on a first read strobe signal of a set of read strobe signals; and identify a fault based at least in part on a second read strobe signal in the set of read strobe signals, the fault associated with performing the one or more operations.

Aspect 10: the method, apparatus, or non-transitory computer-readable medium of aspect 9, further comprising operations, features, circuits, logic, means, or instructions, or any combination thereof, for: before identifying the plurality of clock cycles for outputting the data, transmitting an indication that the memory device is configured to use the first read strobe signal in single ended mode.

Aspect 11: the method, apparatus, or non-transitory computer-readable medium of any one of aspects 9-10, wherein the one or more commands comprise a write command, and the method, apparatus, or non-transitory computer-readable medium further comprises operations, features, circuits, logic, means, or instructions, or any combination thereof, for: based at least in part on the first read strobe signal, identifying one or more parity bits for a duration based at least in part on the write command; and identifying an error associated with the write command based at least in part on the second read strobe signal and during the duration, wherein identifying the fault is based at least in part on identifying the error.

Aspect 12: the method, apparatus, or non-transitory computer-readable medium of any one of aspects 9-11, further comprising operations, features, circuits, logic, means, or instructions, or any combination thereof, for: the second read strobe signal is identified to output a voltage level for the plurality of clock cycles, wherein the fault is identified based at least in part on the voltage level.

Aspect 13: the method, apparatus, or non-transitory computer-readable medium of any one of aspects 9-12, further comprising operations, features, circuits, logic, means, or instructions, or any combination thereof, for: identifying the first read strobe signal switches between a first voltage level and a second voltage level according to a first periodicity, wherein identifying the plurality of clock cycles for receiving the data is based at least in part on identifying the switching of the first read strobe signal; and identifying that the second read strobe signal switches between the first voltage level and the second voltage level according to a second periodicity, wherein the fault is identified based at least in part on a difference between the first periodicity and the second periodicity.

Aspect 14: the method, apparatus, or non-transitory computer-readable medium of any one of aspects 9-13, further comprising operations, features, circuits, logic, means, or instructions, or any combination thereof, for: identifying the first read strobe signal switches between a first voltage level and a second voltage level according to a first periodicity, wherein identifying the plurality of clock cycles for receiving the data is based at least in part on identifying the switching of the first read strobe signal; and identifying that the second read strobe signal switches between the first voltage level and the second voltage level according to the first periodicity, wherein the fault is identified based at least in part on the second read strobe signal being in phase with the first read strobe signal according to the first periodicity.

Aspect 15: the method, apparatus, or non-transitory computer-readable medium of any one of aspects 9-14, further comprising operations, features, circuits, logic, means, or instructions, or any combination thereof, for: identifying the first read strobe signal output as a first voltage level for the plurality of clock cycles; and identifying the second read strobe signal output for a second voltage level of the plurality of clock cycles, wherein the fault is identified based at least in part on a difference between the first voltage level and the second voltage level.

Aspect 16: the method, apparatus, or non-transitory computer-readable medium of any one of aspects 9-15, further comprising operations, features, circuits, logic, means, or instructions, or any combination thereof, for: a characteristic of the fault is identified based at least in part on a timeout duration associated with the second read strobe signal.

It should be noted that the methods described herein describe possible implementations, and that the operations and steps may be rearranged or otherwise modified, and that other implementations are possible. In addition, moieties from two or more of the methods may be combined.

Information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some figures may illustrate signaling as a single signal; however, a signal may represent a bus of signals, where the bus may have a variety of bit widths.

The terms "electrically connected," "electrically conductive contact," "connected," and "coupled" may refer to a relationship between components that supports the flow of signals between the components. Components are considered to be in electronic communication with each other (e.g., in conductive contact with each other, connected to each other, coupled to each other) if there are any electrical paths (e.g., conductive paths) between the components that can support signal flow (e.g., charge, current voltage) between the components at any time. At any given time, the conductive paths between components that are in electronic communication with each other (or in conductive contact with each other, connected to each other, coupled to each other) may be open or closed based on the operation of the device containing the connected components. The conductive paths between connected components may be direct conductive paths between components or the conductive paths between connected components may be indirect conductive paths that may include intermediate components such as switches, transistors, or other components. In some examples, signal flow between connected components may be interrupted for a period of time, for example, using one or more intermediate components, such as switches or transistors.

The term "coupled" refers to a condition that moves from an open circuit relationship between components in which a signal is not currently able to pass between the components (e.g., through a conductive path) to a closed circuit relationship in which a signal is able to pass between the components (e.g., through the conductive path). When components such as a controller couple other components together, the components initiate a change that allows a signal to flow between the other components via a conductive path that previously did not permit the signal to flow.

The term "isolated" refers to a relationship between components where signals cannot currently flow between the components. If there is an open circuit between the components, the components are isolated from each other. For example, components that are separated by a switch positioned between the two components are isolated from each other when the switch is open. When a controller separates two components, the controller implements the following changes: signals are prevented from flowing between components using conductive paths that previously permitted signal flow.

The devices discussed herein, including memory arrays, may be formed on semiconductor substrates such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, and the like. In some examples, the substrate is a semiconductor wafer. In other examples, the substrate may be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-Sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or sub-regions of the substrate may be controlled by doping with various chemicals including, but not limited to, phosphorus, boron or arsenic. Doping may be performed by ion implantation or by any other doping method during the initial formation or growth of the substrate.

The switch components (e.g., transistors) discussed herein may represent Field Effect Transistors (FETs) and may include three terminal components including a source (e.g., source terminal), a drain (e.g., drain terminal), and a gate (e.g., gate terminal). The terminals may be connected to other electronic components by conductive materials (e.g., metals, alloys). The source and drain may be conductive and may include doped (e.g., heavily doped, degenerate) semiconductor regions. The source and drain may be separated by a doped (e.g., lightly doped) semiconductor region or channel. If the channel is n-type (e.g., most of the carriers are electrons), the FET may be referred to as an n-type FET. If the channel is p-type (e.g., most of the carriers are holes), the FET may be referred to as a p-type FET. The channel may be capped with an insulating gate oxide. Channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, may cause the channel to become conductive. The transistor may be "on" or "active" when a voltage greater than or equal to the threshold voltage of the transistor is applied to the transistor gate. The transistor may be "turned off" or "deactivated" when a voltage less than the threshold voltage of the transistor is applied to the transistor gate.

The description set forth herein in connection with the appended drawings describes example configurations and is not intended to represent all examples that may be practiced or that are within the scope of the claims. The term "exemplary" as used herein means "serving as an example, instance, or illustration," rather than "preferred" or "advantageous over other examples. The detailed description includes specific details that provide an understanding of the described technology. However, the techniques may be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form in order to avoid obscuring the concepts of the described examples.

In the drawings, similar components or features may have the same reference numerals. In addition, various components of the same type may be distinguished by following the reference label by a dash and a second label that distinguishes among the similar components. If only a first reference label is used in the specification, the description applies to any one of the similar components having the same first reference label, irrespective of the second reference label.

The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software that is executed by a processor, the functions may be stored on or transmitted over as one or more instructions, such as code, on a computer-readable medium. Other examples and implementations are within the scope of the disclosure and the appended claims. For example, due to the nature of software, the functions described herein may be implemented using software executed by a processor, hardware, firmware, hardwired, or a combination of any of these. Features that implement the functions may also be physically located at various locations, including being distributed such that portions of the functions are implemented at different physical locations.

For example, the various illustrative blocks and modules described in connection with the disclosure herein may be implemented or performed with a processor, such as DSP, ASIC, FPGA, discrete gate logic, discrete transistor logic, discrete hardware components, or other programmable logic devices, or any combination thereof, designed to perform the functions described herein. The processor may be an example of a microprocessor, a controller, a microcontroller, a state machine, or any type of processor. A processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

As used herein, an "or" as used in an item list (e.g., an item list followed by a phrase such as "at least one of" or "one or more of" indicates a list including endpoints such that a list of at least one of, e.g., A, B or C means a or B or C or AB or AC or BC or ABC (i.e., a and B and C). In addition, as used herein, the phrase "based on" should not be understood as referring to a closed set of conditions. For example, exemplary steps described as "based on condition a" may be based on both condition a and condition B without departing from the scope of the present disclosure. In other words, as used herein, the phrase "based on" should be equally construed as the phrase "based at least in part on".

Computer-readable media includes both non-transitory computer-readable storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. Non-transitory storage media may be any available media that can be accessed by a computer. By way of example, and not limitation, non-transitory computer-readable media can comprise RAM, ROM, electrically erasable programmable read-only memory (EEPROM), compact Disk (CD) ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other non-transitory medium that can be used to carry or store desired program code means in the form of instructions or data structures and that can be accessed by a computer or processor. And any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital Subscriber Line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, digital Subscriber Line (DSL), or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. Disk and disc, as used herein, includes CD, laser disc, optical disc, digital Versatile Disc (DVD), floppy disk and blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above are also included within the scope of computer-readable media.

The description herein is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations without departing from the scope of the disclosure. Thus, the disclosure is not limited to the examples and designs described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method, comprising:

receiving, at a memory device, one or more commands to perform one or more operations on a memory array of the memory device;

determining a fault associated with performing the one or more operations;

indicating a plurality of clock cycles for outputting data associated with a first command of the one or more commands using a first read strobe signal of a set of read strobe signals; and

the fault is indicated using a second read strobe signal in the set of read strobe signals.

2. The method as recited in claim 1, further comprising:

an indication is received that the memory device is configured to use the first read strobe signal in a single ended mode prior to indicating the plurality of clock cycles for outputting the data.

3. The method of claim 1, wherein the one or more commands comprise a write command, the method further comprising:

detecting an error associated with executing the write command, wherein determining the failure is based at least in part on detecting the error;

based at least in part on the write command, outputting one or more parity bits over a duration using the first read strobe signal; and

the error is indicated using the second read strobe signal during the duration, wherein indicating the fault is based at least in part on indicating the error.

4. The method as recited in claim 1, further comprising:

a voltage level for the plurality of clock cycles is output using the second read strobe signal, wherein the fault is indicated based at least in part on the voltage level.

5. The method as recited in claim 1, further comprising:

switching the first read strobe signal between a first voltage level and a second voltage level according to a first periodicity, wherein indicating the plurality of clock cycles for outputting the data is based at least in part on switching the first read strobe signal; and

The second read strobe signal is switched between the first voltage level and the second voltage level according to a second periodicity, wherein the fault is indicated based at least in part on a difference between the first periodicity and the second periodicity.

6. The method as recited in claim 1, further comprising:

the second read strobe signal is switched between the first voltage level and the second voltage level according to the first periodicity, wherein the fault is indicated based at least in part on the second read strobe signal being in phase with the first read strobe signal according to the first periodicity.

7. The method as recited in claim 1, further comprising:

outputting a first voltage level for the plurality of clock cycles using the first read strobe signal; and

a second voltage level for the plurality of clock cycles is output using the second read strobe signal, wherein the fault is indicated based at least in part on a difference between the first voltage level and the second voltage level.

8. The method of claim 1, wherein the fault is indicated according to a timeout duration based at least in part on a characteristic of the fault.

9. A method, comprising:

transmitting one or more commands to a memory device to perform one or more operations on a memory array of the memory device;

identifying a plurality of clock cycles for receiving data associated with a first command of the one or more commands from the memory device based at least in part on a first read strobe signal of a set of read strobe signals; and

a fault is identified based at least in part on a second read strobe signal in the set of read strobe signals, the fault associated with performing the one or more operations.

10. The method as recited in claim 9, further comprising:

before identifying the plurality of clock cycles for outputting the data, transmitting an indication that the memory device is configured to use the first read strobe signal in single ended mode.

11. The method of claim 9, wherein the one or more commands comprise a write command, the method further comprising:

based at least in part on the first read strobe signal, identifying one or more parity bits for a duration based at least in part on the write command; and

An error associated with the write command is identified based at least in part on the second read strobe signal and during the duration, wherein identifying the fault is based at least in part on identifying the error.

12. The method as recited in claim 9, further comprising:

the second read strobe signal is identified to output a voltage level for the plurality of clock cycles, wherein the fault is identified based at least in part on the voltage level.

13. The method as recited in claim 9, further comprising:

identifying the first read strobe signal switches between a first voltage level and a second voltage level according to a first periodicity, wherein identifying the plurality of clock cycles for receiving the data is based at least in part on identifying the switching of the first read strobe signal; and

the second read strobe signal is identified as being switched between the first voltage level and the second voltage level according to a second periodicity, wherein the fault is identified based at least in part on a difference between the first periodicity and the second periodicity.

14. The method as recited in claim 9, further comprising:

the second read strobe signal is identified as being switched between the first voltage level and the second voltage level according to the first periodicity, wherein the fault is identified based at least in part on the second read strobe signal being in phase with the first read strobe signal according to the first periodicity.

15. The method as recited in claim 9, further comprising:

identifying the first read strobe signal output as a first voltage level for the plurality of clock cycles; and

the second read strobe signal is identified to output a second voltage level for the plurality of clock cycles, wherein the fault is identified based at least in part on a difference between the first voltage level and the second voltage level.

16. The method as recited in claim 9, further comprising:

a characteristic of the fault is identified based at least in part on a timeout duration associated with the second read strobe signal.

17. An apparatus, comprising:

a controller associated with a memory device, wherein the controller is configured to cause the apparatus to:

receiving, at the memory device, one or more commands to perform one or more operations on a memory array of the memory device;

determining a fault associated with performing the one or more operations;

18. The apparatus of claim 17, wherein the controller is further configured to cause the apparatus to:

19. The apparatus of claim 17, wherein:

the one or more commands include a write command; and is also provided with

The controller is further configured to cause the device to:

20. The apparatus of claim 17, wherein the controller is further configured to cause the apparatus to:

21. The apparatus of claim 17, wherein the controller is further configured to cause the apparatus to:

22. The apparatus of claim 17, wherein the controller is further configured to cause the apparatus to:

switching the first read strobe signal between a first voltage level and a second voltage level according to a first periodicity, wherein indicating the plurality of clock cycles for outputting data is based at least in part on switching the first read strobe signal; and

23. The apparatus of claim 17, wherein the controller is further configured to cause the apparatus to:

24. The apparatus of claim 17, wherein the failure is indicated according to a timeout duration based at least in part on a characteristic of the failure.

25. An apparatus, comprising:

transmitting one or more commands to the memory device to perform one or more operations on a memory array of the memory device;