CN117150986A

CN117150986A - Access response verification method and device, verification system, platform and system on chip

Info

Publication number: CN117150986A
Application number: CN202311139266.XA
Authority: CN
Inventors: 卢文涛; 潘于
Original assignee: Haiguang Information Technology Co Ltd
Current assignee: Haiguang Information Technology Co Ltd
Priority date: 2023-09-05
Filing date: 2023-09-05
Publication date: 2023-12-01

Abstract

The specification provides an access response verification method and device, a verification system, a platform and a system on chip, wherein the access response verification method comprises the following steps: acquiring a plurality of pieces of test response information by monitoring access response operations of a storage test module to be verified on a plurality of access test requests, wherein each access test request comprises an access test identifier for identification, each test response information comprises a response identification identifier, and each response identification identifier is determined by the access test identifier of the access test request related to the test response information; based on the response identification marks of the plurality of test response information, judging whether the acquisition sequence of the plurality of test response information accords with the expected sequence or not, and determining a verification result. By adopting the scheme, the access response verification efficiency can be improved, and the access response verification method has higher universality.

Description

Access response verification method and device, verification system, platform and system on chip

Technical Field

The embodiment of the specification relates to the technical field of chip design, in particular to an access response verification method and device, a verification system, a platform and a system on chip.

Background

The operation of the memory to process the access request of the processor core and return the access result to the processor core can be understood as an access response operation of the memory. Different access response modes can be set for the memory in face of different access response requirements. However, the hardware logic design of the memory may have a logic bug (bug), which causes the memory to perform an erroneous access response operation, affecting the processing results of the processor core.

Thus, how to provide an efficient and versatile access response verification scheme would be addressed by those skilled in the art.

Disclosure of Invention

In view of this, the embodiments of the present disclosure provide an access response verification method and apparatus, a verification system, a platform, and a system on a chip, which can improve the efficiency of access response verification and have higher versatility.

The embodiment of the specification provides an access response verification method, which comprises the following steps:

acquiring a plurality of pieces of test response information by monitoring access response operations of a storage test module to be verified on a plurality of access test requests, wherein each access test request comprises an access test identifier for identification, each test response information comprises a response identification identifier, and each response identification identifier is determined by the access test identifier of the access test request related to the test response information;

Based on the response identification marks of the plurality of test response information, judging whether the acquisition sequence of the plurality of test response information accords with the expected sequence or not, and determining a verification result.

Optionally, before the determining, based on the response identification of the plurality of test response information, whether the acquisition order of the plurality of test response information meets the expected ordering, the method further includes:

and determining the expected ordering based on the access response mode realized by the storage test module, the sending sequence of a plurality of access test requests and the content included in the plurality of access test requests.

Optionally, before the determining, based on the response identification of the plurality of test response information, whether the acquisition order of the plurality of test response information accords with the expected order, the method further includes:

and judging whether the acquired test response information is valid or not based on an access response mode adopted by the storage test module and an access response mode used for verification by the access test request, wherein the access response mode comprises access sequence response or access disorder response.

Optionally, the determining whether the acquired test response information is valid based on the access response mode adopted by the storage test module and the access response mode used for verification by the access test request includes:

If the storage test module realizes the access sequence response, the obtained test response information is determined to be valid;

if the storage test module realizes the access disorder response, judging whether the access response mode of the access test request for verification is the same as the access response mode adopted by the storage test module, and if so, determining that the acquired test response information is valid, otherwise, determining that the acquired test response information is invalid.

Optionally, the access response verification method further includes:

acquiring an address holding sequence corresponding to a storage address indicated by each piece of test response information, wherein the storage address indicated by the test response information is determined by a related access test request, and the address holding sequence at least comprises an expected identification mark;

and comparing the response identification mark of the test response information in each order with the expected identification mark of the appointed serial number in the address holding sequence corresponding to the test response information, so as to determine a verification result.

Optionally, the obtaining a plurality of test response information by monitoring access response operations performed by the storage test module to be verified on the plurality of access test requests includes:

And acquiring a plurality of response intermediate sub-information by monitoring the intermediate process when the storage test module executes the access response operation on the plurality of access test requests.

and acquiring a plurality of response result sub-information by monitoring the execution result of the access response operation executed by the storage test module on the plurality of access test requests.

and acquiring corresponding test response information of the storage test modules by respectively monitoring access response operations of the storage test modules on the received access test requests.

Optionally, the multiple storage test modules adopt different levels of computer languages, and the multiple storage function programs realize the same access response mode;

the determining whether the acquisition order of the plurality of test response information accords with the expected order based on the response identification identifiers of the plurality of test response information, for determining the verification result, includes:

Judging whether the acquisition sequence of the plurality of test response information of each storage test module accords with the expected sequence or not based on response identification identifiers of the plurality of test response information of each storage test module respectively, so as to be used for determining a verification result;

based on the test response information of the plurality of storage test modules, judging whether the acquisition order of the test response information of the plurality of storage test modules is the same or not, so as to determine a verification result.

Optionally, before the access response operation performed by the storage test module to be verified on the plurality of access test requests is monitored to obtain the plurality of test response information, the method further includes:

and establishing a message interaction channel among a plurality of storage test modules for timing control.

Optionally, before the determining, based on the test response information of the plurality of storage test modules, whether the acquisition orders of the test response information of the plurality of storage test modules are the same, the method further includes:

based on the access response mode adopted by each storage test module and the request response mode identification of the access test request sent to each storage test module, judging whether the test response information corresponding to each storage test module is valid or not.

Optionally, the test response information further includes: the response mode sub-information is used for representing the access command indicated by the related access test request;

the determining whether the acquisition order of the test response information of the plurality of storage test modules is the same based on the test response information of the plurality of storage test modules comprises:

based on the response mode sub-information of the test response information of the plurality of storage test modules, according to the acquisition sequence of the test response information of the plurality of storage test modules, the test response information indicating the same access command is selected for comparison so as to judge whether the acquisition sequence of the test response information of the plurality of storage test modules is the same.

and setting verification object parameters, wherein the verification object parameters are used for indicating the number of the storage test modules, the computer language level of the storage test modules and the access response mode of the storage test modules.

Optionally, the access response operation executed by the storage test module to be verified on the plurality of access test requests includes:

When the storage test module determines that the storage address indicated by the access test request is not hit, sending a data access request to a data storage module, wherein the data access request comprises the missed storage address;

the data storage module determines a plurality of data access request orderings based on a storage type of a storage address indicated by the data access request.

Optionally, the number of the storage test modules is multiple, and each storage test module is configured with a data storage module;

the method further comprises the steps of:

and comparing the data of the same storage address in the data storage modules configured by the plurality of storage test modules for determining the verification result.

Optionally, before obtaining the plurality of test response information by monitoring access response operations performed by the storage test module to be verified on the plurality of access test requests, the method further includes:

setting a working mode parameter of a data storage module, wherein the working mode parameter of the data storage module is used for indicating an access response mode executed by the data storage module.

The embodiment of the specification also provides an access response verification device, which comprises:

the response monitoring module is suitable for monitoring access response operations of the storage testing module to be verified on the plurality of access testing requests so as to acquire a plurality of testing response information; each access test request comprises an access test identifier, the access test identifier is used for identifying the access test request, each test response message comprises a response identification identifier, and each response identification identifier is determined through the access test identifier of the access test request related to the test response message;

And the response checking module is suitable for judging whether the acquisition sequence of the plurality of test response information accords with the expected sequence or not based on response identification marks of the plurality of test response information so as to be used for determining a verification result.

The answer checking module is further adapted to determine the expected ordering based on an access answer manner implemented by the storage testing module, a sending order of the plurality of access test requests, and contents included in the plurality of access test requests.

Optionally, the response checking module is further adapted to determine whether the acquired test response information is valid based on an access response mode adopted by the storage test module and an access response mode used for verification by the access test request, where the access response mode includes an access sequential response or an access out-of-order response.

Optionally, the response checking module is further adapted to obtain an address holding sequence corresponding to the storage address indicated by each test response message, where the storage address indicated by the test response message is determined by the relevant access test request, and the address holding sequence includes at least one expected identification identifier; and comparing the response identification mark of the test response information in each order with the expected identification mark of the appointed sequence number in the address holding sequence corresponding to the test response information, so as to determine a verification result.

The embodiment of the specification also provides a verification platform verification system, which comprises: the memory test module to be verified and the access response verification device according to any of the above embodiments.

The embodiment of the specification also provides a verification platform which comprises a verification component for constructing a verification environment of the access response verification method according to any embodiment.

Optionally, the verification platform further comprises a control component and an interactive interface; wherein:

the control component is used for setting control parameters of the verification environment, and the control parameters comprise at least one of the following: requesting to generate control parameters, response mode checking parameters, verification object parameters and working mode parameters of a data storage module;

the interactive interface is used for visualizing the verification component and the control component.

The embodiment of the specification also provides a system on a chip, which comprises a processor and a memory, wherein the hardware logic design loaded by the memory is verified by the access response verification method in any embodiment.

In the access response verification method provided in the embodiment of the present disclosure, a plurality of test response information may be obtained by monitoring access response operations performed by a storage test module to be verified on a plurality of access test requests, where a response identification identifier included in each test response information is determined by an access test identifier for identifying a related access test request; and then, judging whether the acquisition order of the plurality of test response information accords with the expected order or not based on the response identification marks of the plurality of test response information, so as to be used for determining a verification result. By adopting the scheme, the answer identification identifiers are determined through the access test identifiers of the access test requests related to the test answer information, so that the acquisition source of the test answer information can be determined through the answer test identifiers, namely the access test request of which access answer operation is executed from which the test answer information originates, and the actual sequence of the access answer operation of a plurality of access test requests can be determined through the acquisition sequence of a plurality of test answer information containing the answer test identifiers.

Drawings

Fig. 1 is a flowchart of an access response verification method in an embodiment of the present disclosure.

Fig. 2 is a flowchart of another access response verification method according to an embodiment of the present disclosure.

Fig. 3 is a flowchart of another access response verification method according to an embodiment of the present disclosure.

Fig. 4 is a schematic structural diagram of an access response verification device in the embodiment of the present disclosure.

Fig. 5 is a schematic diagram of a verification platform according to an embodiment of the present disclosure.

Detailed Description

As described in the background, different access response modes may be set for the memory according to different access response requirements.

For example, in order to ensure the accuracy of the access response, the memory performs the access response operation in the order of reception of the access requests; since the access responses of the memory are sequential to the processor core, this access response is an access sequential response.

For another example, to reduce the access delay time of the memory, the memory may adjust the order in which the plurality of access requests perform the access response operations according to the contents of the plurality of access requests, so that the access response operations of the memory are not limited to the receiving order of the access requests; since memory access replies are out-of-order to the processor core, this access reply is an access out-of-order reply.

However, the hardware logic design of the access response may have a logic vulnerability, which causes the memory to execute an erroneous access response operation, affecting the processing results of the processor core. Thus, it is to be addressed by those skilled in the art how to provide an efficient and versatile access response verification scheme in the face of a variety of access response approaches.

In order to cope with the above technical problems or other problems, an embodiment of the present disclosure proposes an access response verification scheme capable of obtaining a plurality of test response information by monitoring access response operations performed by a storage test module to be verified on a plurality of access test requests, where a response identification identifier included in each test response information is determined by an access test identifier for identifying a related access test request; and then, judging whether the acquisition order of the plurality of test response information accords with the expected order or not based on the response identification marks of the plurality of test response information, so as to be used for determining a verification result. Thus, the verification efficiency can be improved, and the method has higher universality. The following detailed description is presented to enable one skilled in the art to more clearly understand and to practice the concepts, implementations and advantages of the technical solutions of the present disclosure.

Referring to fig. 1, a flowchart of an access response verification method in an embodiment of the present disclosure may include:

s11, acquiring a plurality of pieces of test response information by monitoring access response operation of a storage test module to be verified on a plurality of access test requests, wherein each access test request comprises an access test identifier for identification, each test response information comprises a response identification identifier, and each response identification identifier is determined by the access test identifier of the access test request related to the test response information.

In specific implementation, the storage test module is a verification target obtained by instantiating according to the hardware logic design of the memory, the real access response condition of the memory can be simulated, and the test response information can be obtained by monitoring the access response operation of the storage test module on the access test request.

Since there is a correspondence between the test response information and the access test request, in order to be able to characterize the correlation between the test response information and the acquisition source of the test response information (i.e., from which access test request of which access response operation is performed the test response information originates), a response identification flag may be set for each of the test response information, and the response identification flag is determined by the access test flag of the access test request related to the test response information.

For example, for n access test requests, namely access test request Q1 through access test request Qn, access test request Q1 includes access test identification qid1 for identification, and so on, access test request Qn may include access test identification qidn for identification, where n is an integer greater than 1.

After the test response information A1 is obtained by monitoring the access response operation of the storage test module to the access test request Q1, the response identification mark aid1 included in the test response information A1 can be determined according to the access test mark qid1 included in the access test request Q1, and so on, after the test response information An is obtained by monitoring the access response operation of the storage test module to the access test request Qn, the response identification mark aid n included in the test response information An can be determined according to the access test mark qidn included in the access test request Qn. Alternatively, if the access test identifier qid1 is 1, the answer identification identifier aid1 may also be 1. If the access test identifier qidn is n, the answer identification identifier aidn may be n.

The above examples are illustrative. The specific representation of the access test identifier can be set according to actual situations and requirements, for example, the access test identifier can be represented by one or more of characters and numbers. The specification does not limit the specific representation of the access test identifier.

In addition, the specific representation form of the answer identification mark can also be set according to actual situations and requirements, for example, the answer identification mark can adopt the same specific representation form as the access test mark, and can also be modified on the basis of the specific representation form adopted by the access test mark, so long as the answer identification mark can characterize the correlation between the test answer information and the acquisition source thereof, and the specific representation form of the answer identification mark is not limited in the specification.

It can be appreciated that in practical application, the access response mode specifically executed by the storage test module can be determined according to specific verification requirements. For example, if verification of an access out-of-order reply is required, the storage test module performs an access out-of-order reply operation on multiple access test requests. For another example, if verification of the access order reply is required, the storage test module performs an access order reply operation on the plurality of access test requests.

And S12, judging whether the acquisition sequence of the plurality of test response information accords with the expected sequence or not based on the response identification marks of the plurality of test response information, so as to be used for determining a verification result.

In a specific implementation, the response test identifier can determine the acquisition source of the test response information, namely which access test request for executing the access response operation the test response information originates from, so that the acquisition sequence of the multiple test response information containing the response test identifier can reflect the actual sequence in which the multiple access test requests are scheduled to execute the access response operation, therefore, based on the response identification identifiers of the multiple test response information, whether the acquisition sequence of the multiple test response information accords with the expected sequence is judged, namely, whether the actual sequence in which the multiple access test requests are scheduled to execute the access response operation accords with the expected sequence can be determined, thereby reducing the data amount of the verification process, simplifying the verification process and improving the verification efficiency.

For example, the test response information Ai comprises a response test identity aidi, the test response information Aj comprises a response test identity aidj, wherein the response test identity aidi is determined by the access test identity Qi of the associated access test request Qi, and the response test identity aidj is determined by the access test identity qidj of the associated access test request Qj. Wherein i and j are positive integers and i and j are not equal.

Assume that the acquisition order of the test response information Ai and Aj is: the first obtains the test response information Ai and the second obtains the test response information Aj, and then according to the obtaining sequence of the two test response information, based on the response identification aidi, it is judged whether the first obtained test response information Ai accords with the expected sequence, so that it can be determined whether the access test request Qi is the expected first performed access response operation, and based on the response identification aidj, it is judged whether the second obtained test response information Aj accords with the expected sequence, so that it can be determined whether the access test request Qj is the expected second performed access response operation.

According to the judging results of the acquiring orders of the test response information, the verification result can be determined, specifically, if the acquiring orders of the test response information Ai and the test response information Aj are judged not to accord with the expected ordering, the verification result is verification failure, otherwise, the verification result is verification success.

It is to be understood that the above examples are illustrative only. In practical applications, there may be more test response information. Also, one access test request may be associated with one or more test response messages, in other words, one or more test response messages may be obtained by monitoring access response operations performed by the memory test module on one access test request. The number of test response messages and the correspondence relationship between the number of access test requests and the number of test response messages are not particularly limited in the present specification.

It may be further understood that, when determining whether the acquisition order of the plurality of test response messages meets the expected order based on the response identification of the plurality of test response messages, whether the test response messages in each order meet the expected order may be sequentially determined, or whether the test response messages in the plurality of orders meet the expected order may be simultaneously determined, and the specific determination manner of whether the acquisition order of the plurality of test response messages meets the expected order is not limited in this specification.

Note that, the symbols (e.g., "A1", "aid1", "Q1", etc.) in the embodiments of the present disclosure are only used to distinguish technical features (e.g., distinguish multiple access test requests, multiple test response information, etc.) with the same name, and are not used to describe a specific order or sequence. In specific implementation, no matter what access response mode is adopted by the storage test module to be verified, namely the storage test module to be verified adopts access sequence response or access disorder response, judgment can be carried out based on response identification marks of a plurality of pieces of test response information, so that verification of different access response modes can be adapted, and the method has higher universality.

From the above, the access response verification method according to the embodiment of the application can improve the access response verification efficiency and has higher universality.

In a specific implementation, before determining whether the acquisition order of the plurality of test response information accords with the expected order based on the response identification of the plurality of test response information, a plurality of expected identification identifications arranged in the expected order may be acquired, and the expected identification of each order is determined by the access test identification of the access test request for which the access response operation is expected to be performed in the order, for example, the xth expected identification yidx is determined by the xth access test request qidy for which the access response operation is expected to be performed, where x and y are positive integers. Further, if the x-th access test request qidy, on which the access response operation is expected to be performed, is y, the expected identification yidx may also be y. And so on, they are not described in detail herein.

The above examples are illustrative. The specific representation of the expected identification mark may be set according to actual situations and requirements, for example, the expected identification mark may take the same specific representation as the access test mark, or may be modified based on the specific representation taken by the access test mark, so long as the correlation between the expected identification mark and the access test request for which the access response operation is expected to be performed can be characterized, and the specific representation of the expected identification mark is not limited in this specification.

Thus, the plurality of expected identification marks arranged in the expected order may characterize the order in which the plurality of access test requests are expected to be performed with respect to the access response operation, and when judging whether the acquisition order of the plurality of test response information accords with the expected order based on the response identification marks of the plurality of test response information for determining the verification result, the plurality of expected identification marks arranged in the expected order may be used as a reference standard for verification, and whether the acquisition order of the plurality of test response information accords with the expected order may be judged by comparing whether the response identification marks of the test response information in each order are identical with the expected identification marks in the corresponding order.

It should be noted that, according to the actual application scenario and requirements, the access test request may include, in addition to the access test identifier, request information for supporting execution of the access response operation, for example, the access test request may further include access command information, where the access command information is used to indicate an access command, and the access command is a read command or a write command, and optionally, when the access command is a write command, the request information may further include write data, which is used to write into the storage test module. For another example, the access test request may further include access address information indicating a memory address of the access, alternatively, the memory address may be a virtual memory address or a physical memory address. The specific content included in the access test request is not limited in the embodiments of the present specification.

It will be appreciated that, in order to more fully verify whether the logic of the storage test module is correct, at least some of the access test requests sent to the storage test module include partially different request information. For example, there are a plurality of access test requests whose access command information is not identical. For another example, there are a plurality of access test requests having different access address information. Also for example, there are multiple access test requests to which the data is written that are not identical. In actual application, the specific content of the access test request sent to the storage test module can be controlled by the request generation control parameter, so that the specific content of the access test request sent to the storage test module can be adjusted by setting different request generation control parameters.

In a specific implementation, the expected ordering may be determined based on the access response manner implemented by the storage test module, the sending order of the plurality of access test requests, and the content included in the plurality of access test requests. Specifically, based on the access response mode implemented by the storage test module, the sending sequence of a plurality of access test requests and the content included in a plurality of access test requests, determining access test requests of which the access response operation is expected to be executed in each sequence, determining expected identification identifications ordered according to the expected sequence according to access test identifications of the access test requests of which the access response operation is expected to be executed in each sequence, comparing the expected identification identifications with response identification identifications of a plurality of acquired test response information, and determining whether the acquisition sequence of the plurality of test response information accords with the expected ordering.

Therefore, expected ordering can be dynamically adjusted according to the access response mode realized by the storage test module, the sending sequence of a plurality of access test requests and the content included in the plurality of access test requests, and the reliability of the verification result is improved.

In a specific implementation, a plurality of access test requests for verification may be set for different access response modes, for example, a plurality of access test requests for verification of access sequence responses may be set, and a plurality of access test requests for verification of access disorder responses may be set.

However, in the actual operation, there is a case where an access test request is sent in error, for example, an access test request for verifying an access sequence response is sent to a memory test module employing an access out-of-order response. For another example, an access test request for verifying an access out-of-order response is sent to a memory test module that employs the access order response.

The access response operation can still be executed after the storage test module receives the wrong access test request, but because the access response mode for verification of the received access test request is different from the access response mode realized by the storage test module, the acquired test response information may be changed, for example, the response identification identifier of the acquired test response information may be changed.

In a specific implementation, in order to make clear which access response mode the access test request is specifically used for verifying, the access test request may further include a request response mode identifier, so that the access response mode indicating that the access test request is used for verifying is identified by the request response mode identifier.

Therefore, the access response mode for verification of the access test request sent to the storage test module can be determined through the request response mode identification of the access test request, and whether the access response mode for verification of the sent access test request is identical to the access response mode adopted by the storage test module or not is judged, so that the verification process can be monitored, the condition of sending errors of the access test request can be found in time, and the reliability of a verification result is ensured.

In a specific implementation, before the response identification based on the plurality of test response information determines whether the acquisition order of the plurality of test response information accords with the expected order, the method can determine whether the acquired test response information is valid based on an access response mode adopted by the storage test module and an access response mode used for verification by the access test request before determining the verification result.

Specifically, based on the request response mode identifier of the access test request, it may be determined whether the access response mode adopted by the storage test module and the access response mode indicated by the access test request for verification are the same, and when it is determined that the access response mode adopted by the storage test module and the access response mode adopted by the transmitted access test request for verification are the same, the obtained test response information is valid, and may be used to determine the verification result, and when it is determined that the access response mode adopted by the storage test module and the access response mode adopted by the transmitted access test request for verification are different, it is necessary to determine whether the obtained test response information is valid according to the access response mode adopted by the storage test module.

When the access sequence response is realized by the storage test module, because the access sequence response does not involve adjusting the sequence of executing the access response operation by the plurality of access requests, even if an erroneous access test request is sent to the storage test module, that is, an access test request for verifying the access disorder response is sent to the storage test module, the logic of the storage test module can be sufficiently verified by the erroneously sent access test request, and the accuracy of the verification result is not affected by the obtained test response information, so that the obtained test response information can be determined to be valid.

When the storage test module realizes the access disorder response, because the access disorder response involves adjusting the order of executing the access response operation by a plurality of access requests, when an erroneous access test request is sent to the storage test module, that is, when an access test request for verifying the access order response is sent to the storage test module, the erroneously sent access test request may not sufficiently verify the logic of the storage test module, and the acquired test response information may misjudge the storage test module with the logic vulnerability as verification success, thereby affecting the reliability of the verification result, so the acquired test response information may be determined as invalid.

Based on the above, when judging whether the acquired test response information is valid based on the access response mode adopted by the storage test module and the access response mode used for verification by the access test request, if the storage test module realizes access sequence response, the acquired test response information can be determined to be valid; if the storage test module realizes the access disorder response, judging whether the access response mode of the access test request for verification is the same as the access response mode adopted by the storage test module, determining that the acquired test response information is valid when the access response mode of the access test request for verification is the same as the access response mode adopted by the storage test module, and determining that the acquired test response information is invalid when the access response mode of the access test request for verification is different from the access response mode adopted by the storage test module.

In order to make the process of judging whether the acquired test response information is valid or not more clearly known to those skilled in the art, the following description will be made with reference to the accompanying drawings.

Referring to fig. 2, a flowchart of another access response verification method in an embodiment of the present disclosure is shown, where the method may include:

s21, acquiring a plurality of test response information by monitoring access response operations of the storage test module to be verified on the plurality of access test requests.

The specific implementation process of step S21 may refer to the above related description, and will not be described herein.

S22, judging an access response mode realized by the storage test module, executing step 23 when determining that the storage test module realizes the access sequence response, and executing step 25 when determining that the storage test module realizes the access disorder response.

S23, determining that the acquired test response information is valid.

S24, judging whether the acquisition sequence of the plurality of test response information accords with the expected sequence or not based on the response identification marks of the plurality of test response information, and determining a verification result.

The specific implementation process of step S24 may refer to the above related description, and will not be described herein.

And S25, if the storage test module realizes the access disorder response, judging whether the access response mode of the access test request for verification is the same as the access response mode adopted by the storage test module according to the request response mode identification, and executing the step S23 when judging that the access response mode is the same, otherwise executing the step S26.

S26, determining that the acquired test response information is invalid.

Thus, the error rate of the verification result can be reduced, and the reliability of the verification result can be improved.

It can be understood that, in practical application, the determined invalid test response information may be used to determine whether the expected ordering is met, but the determination result determined by the invalid test response information may increase the error rate of the verification result, so that the reliability of the determination result may be determined according to the specific content of the access test request sent by mistake, so as to evaluate the verification result.

In the implementation, in order to facilitate judging whether the acquired test response information is valid, the access response mode specifically implemented by the parameter characterization storage test module can be checked through the response mode. Specifically, before the determining, based on the response identification of the plurality of test response information, whether the acquisition order of the plurality of test response information meets the expected order, the method may further include: setting a response mode checking parameter. Therefore, whether the acquired test response information is valid or not can be judged based on the response mode checking parameter and the request response mode identification of the access test request. The specific determination process may refer to the description of the relevant portion, and will not be repeated here.

In a specific implementation, a response mode effective identifier may be set for the test response information, where the response mode effective identifier determines whether an access response mode used for verification by the access test request is the same as an access response mode implemented by the storage test module, so that whether the test response information is effective is indicated by the response mode effective identifier. The specific determination process may refer to the description of the relevant portion, and will not be repeated here. Therefore, the corresponding verification strategy can be set according to the indication of the effective identification of the response mode. For example, when the response mode valid identifier indicates that the test response information is valid, based on response identification identifiers of a plurality of test response information, whether the acquisition order of the plurality of test response information accords with an expected order is judged, so as to be used for determining a verification result. And when the effective identification of the response mode indicates that the test response information is invalid, not verifying, or judging whether the acquisition sequence of the plurality of test response information accords with the expected sequence based on the response identification of the plurality of test response information, evaluating the credibility of the judgment result, and determining the verification result after the credibility accords with the preset condition.

In particular implementations, when multiple access test requests indicating the same memory address are performed an access response operation, there may be a data collision problem, thereby reading out erroneous data or writing erroneous data. Therefore, it is necessary to verify the logic that the access response operation is performed for a plurality of access test requests indicating the same memory address.

Specifically, when determining whether the acquisition order of the plurality of test response information accords with the expected order based on the response identification identifiers of the plurality of test response information, the method may include: acquiring an address holding sequence corresponding to a storage address indicated by each piece of test response information, wherein the storage address indicated by the test response information is determined by a related access test request, and the address holding sequence at least comprises an expected identification mark; and comparing the response identification mark of the test response information in each order with the expected identification mark of the appointed serial number in the address holding sequence corresponding to the test response information, so as to determine a verification result.

The specific sequence number can be determined according to the data format and the comparison mode of the address holding sequence, and the specification is not particularly limited.

Therefore, the logic for executing the access response operation on the plurality of access test requests indicating the same storage address can be verified, the problem of data collision is avoided, and the reliability of the verification result is further improved.

In a specific implementation, an address holding expected table may be determined based on a sending sequence of a plurality of access test requests, storage addresses indicated by a plurality of access test requests, and access test identifiers of a plurality of access test requests, where the address holding expected table includes index numbers set based on the storage addresses and address holding sequences corresponding to the index numbers. Thus, the index number can be determined through the storage address indicated by each test response information, and the address holding sequence corresponding to the index number can be obtained from the address holding expected table.

In a specific implementation, the test response information may further include: and the response address sub-information is used for representing the storage address indicated by the related access test request.

In an alternative example, three access test requests are sent to the storage test module, wherein the access test of the first access test request QL is identified as L, the indicated storage address is DL, the access test of the second access test request QM is identified as M, the indicated storage address is DM, the access test of the third access test request QN is identified as N, and the indicated storage address is DL.

The address holding expectation table is determined based on the transmission order of the three access test requests QL, QM, and QN, the storage addresses indicated by the three access test requests QL, QM, and QN, and the access test identifications of the three access test requests QL, QM, and QN. In the address holding expected table, establishing index numbers DL and DM based on the storage addresses DL and DM, wherein an expected identification mark included in an address holding sequence XL1 corresponding to the index number DL is L and N; the address holding sequence XL2 corresponding to the index number DL includes the expected identification number M.

Assuming that the address holding sequence adopts a first-in first-out data structure, the expected identification obtained from the address holding sequence XL1 will not be stored in the address holding sequence anymore. After the test response information AN corresponding to the access test request QN is obtained, the index number DL is determined according to the storage address indicated by the response address sub-information of the test response information AN, and AN address holding sequence XL1 corresponding to the index number DL is obtained from AN address holding expected table. The expected identification of the first sequence number in the acquired address holding sequence XL1 is compared with the answer identification of the test answer information AN.

If the comparison result is the same, the test response information AL corresponding to the access test request QL is acquired before the test response information AN and is compared, and the logic indicating that the access test requests QL and QN with the same storage address are executed with the access response operation is correct.

If the comparison result is different, it indicates that the test response information AL corresponding to the access test request QL is not acquired prior to the test response information AN and is compared, and the logic of the access test requests QL and QN indicating the same storage address to be executed has a vulnerability.

In a specific implementation, the monitoring position of the storage test module can be determined according to the monitoring requirement, so that the specific content of the test response information is determined.

Under some monitoring requirements, the test response information may include: and the storage test module monitors response intermediate sub-information acquired by an intermediate process when executing access response operation on a plurality of access test requests. Specifically, the intermediate process when the storage test module executes the access response operation on the multiple access test requests can be monitored, multiple pieces of response intermediate sub-information can be obtained, and whether the obtaining sequence of the multiple pieces of response intermediate sub-information accords with the expected sequence of the intermediate process is judged based on the response identification marks of the multiple pieces of response intermediate sub-information. It will be appreciated that the detailed description of the above process may refer to the description of the relevant parts before, and will not be repeated here.

Therefore, whether the logic in the execution process of the access response operation is correct or not can be paid attention to, and the correctness of the verification result is improved.

It will be appreciated that the intermediate process being monitored may be the critical process when the access response operation is performed as determined by the verification requirements and the internal logic of the memory test module.

In an optional example, when the storage test module performs an access response operation on the multiple access test requests, a recording process of the multiple access test requests may be monitored, so as to obtain multiple response intermediate sub-information related to the recording process, so as to determine whether the obtaining sequence of the multiple response intermediate sub-information accords with the expected sequence of the recording process based on the response identification identifier of the multiple response intermediate sub-information.

Further for example, after receiving the two access test requests Qa and Qb, the storage test module records the access test request Qa and the access test request Qb, respectively, and then sequentially acquires the response intermediate sub-information Aa and the response intermediate sub-information Ab. According to the acquisition sequence of the two pieces of response intermediate sub-information Aa and Ab, judging whether the first acquired piece of response intermediate sub-information Aa accords with the expected ordering of the recording process or not based on the response identification mark of the response intermediate sub-information Aa, so that whether the access test request Qa is expected to be recorded when the access response operation is executed or not can be determined; based on the answer identification of the answer intermediate sub-information Ab, it is judged whether the answer intermediate sub-information Ab second is acquired in conformity with the expected ordering of the recording process, so that it can be determined whether the access test request Qb is the expected second to be recorded when the access answer operation is performed.

In another optional example, when the storage test module performs an access response operation on the multiple access test requests, a calling process of the multiple access test requests may be monitored, so as to obtain multiple pieces of response intermediate sub-information about the calling process, so as to determine whether the obtaining sequence of the multiple pieces of response intermediate sub-information accords with the expected sequence of the calling process based on the response identification of the multiple pieces of response intermediate sub-information.

For further example, after receiving the two access test requests Qc and Qd, the storage test module invokes the access test request Qc and the access test request Qd respectively, and then sequentially obtains the response intermediate sub-information Ac and the response intermediate sub-information Ad. According to the acquisition sequence of the two response intermediate sub-information Ac and Ad, based on the response identification mark of the response intermediate sub-information Ac, judging whether the first acquired response intermediate sub-information Ac accords with the expected ordering of the calling process, thereby determining whether the access test request Qc is the expected first to be called when the access response operation is executed; based on the answer identification of the answer intermediate sub-information Ad, it is judged whether the answer intermediate sub-information Ad second is acquired in conformity with the expected ordering of the retrieval process, so that it can be determined whether the access test request Qd is the expected second to be retrieved when the access answer operation is performed.

In yet another alternative example, when the storage test module performs an access response operation on the multiple access test requests, an address access process of the multiple access test requests may be monitored, so as to obtain multiple pieces of response intermediate sub-information about the address access process, so as to determine whether the obtaining sequence of the multiple pieces of response intermediate sub-information accords with the expected sequence of the address access process based on the response identification identifier of the multiple pieces of response intermediate sub-information.

For further example, after receiving the two access test requests Qe and Qf, the storage test module accesses the storage address indicated by the access test request Qe and the storage address indicated by the access test request Qf respectively, and then sequentially acquires the response intermediate sub-information Ae and the response intermediate sub-information Af. According to the acquisition sequence of the two response intermediate sub-information Ae and Af, based on the response identification mark of the response intermediate sub-information Ae, judging whether the first acquired response intermediate sub-information Ae accords with the expected sequence of the address access process, thereby determining whether the storage address indicated by the access test request Qe is the expected first accessed when the access response operation is executed; based on the answer identification of the answer intermediate sub-information Af, it is judged whether the second one of the answer intermediate sub-information Af is acquired to conform to the expected ordering of the address access process, so that it can be determined whether the storage address indicated by the access test request Qf is the expected second one to be accessed when the access answer operation is performed.

In a specific implementation, after the intermediate process of executing the access response operation on the multiple access test requests by the storage test module is monitored to obtain multiple response intermediate sub-information, an address holding sequence corresponding to each response intermediate sub-information can be obtained, and a response identification identifier of each response intermediate sub-information in each order is compared with an expected identification identifier of a designated sequence number in the address holding sequence corresponding to the response intermediate sub-information, so as to determine a verification result. It will be appreciated that the detailed description of the above process may refer to the description of the relevant parts before, and will not be repeated here.

Therefore, the process logic of executing the access response operation on a plurality of access test requests indicating the same storage address can be verified, the problem of data collision is avoided, and the reliability of a verification result is further improved.

In other monitoring needs, the test response information may include: and the response result sub-information obtained by monitoring the execution results of the access response operation executed by the storage test module on the plurality of access test requests. Specifically, the storage test module may monitor the execution results of the access response operation performed on the multiple access test requests, obtain multiple response result sub-information, and determine whether the acquisition order of the multiple response result sub-information meets the expected order of the execution results based on the response identification identifiers of the multiple response result sub-information. It will be appreciated that the detailed description of the above process may refer to the description of the relevant parts before, and will not be repeated here.

Thus, whether the logic of the execution result of the access response operation is correct or not can be paid attention to, and the correctness of the verification result is improved.

In a specific implementation, after the storage test module executes the execution result of the access response operation on the multiple access test requests to obtain multiple response result sub-information, an address holding sequence corresponding to each response result sub-information can be obtained, and the response identification identifier of each response result sub-information in each order is compared with the expected identification identifier of the designated serial number in the address holding sequence corresponding to the response result sub-information, so as to determine the verification result. It will be appreciated that the detailed description of the above process may refer to the description of the relevant parts, and will not be repeated here.

Therefore, the result logic of executing the access response operation on the plurality of access test requests indicating the same storage address can be verified, the problem of data collision is avoided, and the reliability of the verification result is further improved.

In a specific implementation, access response verification may be performed on a plurality of storage test modules, so that by respectively monitoring access response operations performed by the plurality of storage test modules on a plurality of access test requests received by the plurality of storage test modules, test response information corresponding to the plurality of storage test modules is obtained, and whether the obtaining sequence of the plurality of test response information of each storage test module accords with an expected sequence or not may be determined based on response identification identifiers of a plurality of test response information of each storage test module, so as to determine a verification result. It will be appreciated that the detailed description of the above process may refer to the description of the relevant parts before, and will not be repeated here. Therefore, access response verification of a plurality of storage test modules can be realized, and verification efficiency is improved.

In a specific implementation, the multiple storage test modules may implement different access response modes, so as to send access test requests for verifying the access response modes to each storage test module. It will be appreciated that the detailed description of the above process may refer to the description of the relevant parts before, and will not be repeated here. Therefore, verification of multiple access response modes can be realized, and verification efficiency is improved.

In a specific implementation, the storage test module describes the hardware logic design of the memory through a computer language, and the level of the computer language adopted by the storage test module can be determined according to specific requirements.

In an alternative example, the memory test module may be described in a register transfer level (Register Transfer Level, RTL) language, for example, the memory test module may be described in Verilog HDL (a hardware description language). Thus, access response verification can be performed on the register transfer level storage test module.

In other alternative examples, the storage test module is described in a model-level language, for example, the storage test module may be in C++ (a computer-high-level programming language) or SystemC (a system-level programming language). Thus, the access response verification can be performed on the model-level storage test module. Optionally, after the verification of the model-level storage test module is successful, the model-level storage test module can be used as a reference model (reference model) for verifying the register-level storage test module.

In a specific implementation, access response operations of the multiple storage test modules on the multiple access test requests received by the multiple storage test modules can be monitored respectively to obtain test response information corresponding to the multiple storage test modules, wherein the multiple storage test modules are described by different levels of computer languages, and the multiple storage test modules realize the same access response mode. And then, by respectively monitoring access response operations of the plurality of storage test modules to the plurality of access test requests received by the plurality of storage test modules, test response information corresponding to the plurality of storage test modules is obtained, and whether the obtaining sequence of the plurality of test response information of each storage test module accords with the expected sequence can be judged based on response identification marks of the plurality of test response information of each storage test module respectively, so as to be used for determining a verification result. It will be appreciated that the detailed description of the above process may refer to the description of the relevant parts before, and will not be repeated here.

Therefore, the access response verification of the storage test modules with different computer language levels can be realized, and the verification efficiency is improved.

In a specific implementation, when there are multiple storage test modules that are described in different levels of computer languages, and the multiple storage test modules implement the same access response manner, it may be determined, based on the test response information of the multiple storage test modules, whether the acquisition orders of the test response information of the multiple storage test modules are the same, so as to determine the verification result. Therefore, the access response joint verification of the storage test modules with different computer language levels can be realized, and the accuracy of verification results is improved.

In an alternative example, there may be two memory test modules that are described in different levels of computer language and implement the same access response approach.

It should be noted that, for ease of understanding and distinction, two storage test modules may be referred to as a first storage test module and a second storage test module. Therefore, based on the test response information of the first storage test module and the test response information of the second storage test module, whether the acquisition sequence of the test response information of the first storage test module is the same as the acquisition sequence of the test response information of the second storage test module is judged, so that the verification result is determined.

In particular implementations, separate and joint verification may be performed on multiple memory test modules implementing the same access response approach but employing different levels of computer language. For example, referring to fig. 3, a flowchart of another access response verification method in an embodiment of the present disclosure may include:

s31, access response operations, executed by the storage test modules, on the received access test requests are monitored respectively, so that test response information corresponding to the storage test modules is obtained, wherein the storage test modules are described by adopting different levels of computer languages, and the storage test modules realize the same access response mode.

S32, judging whether the acquisition sequence of the plurality of test response information of each storage test module accords with the expected sequence or not based on response identification identifiers of the plurality of test response information of each storage test module respectively, and determining a verification result.

S33, based on the test response information of the plurality of storage test modules, judging whether the acquisition order of the test response information of the plurality of storage test modules is the same or not, so as to determine a verification result.

Therefore, through respectively verifying and jointly verifying the plurality of storage test modules which realize the same access response mode and are described by adopting different levels of computer languages, when the acquisition order of the test response information of the plurality of storage test modules is the same and the acquisition order of the test response information of each storage test module is different from the expected ordering, the error of the expected ordering can be found in time, and the accuracy of the verification result is further improved.

In a specific implementation, before the access response operation performed on the plurality of access test requests by the storage test module to be verified is monitored to obtain the plurality of test response information, the method may further include: and setting verification object parameters, wherein the verification object parameters are used for indicating the number of the storage test modules, the computer language level of the storage test modules and the access response mode of the storage test modules.

In a specific implementation, the running speeds of the storage test modules adopting different levels of computer languages are inconsistent, and when the acquired test response information is acquired, particularly when the response intermediate sub-information is acquired, timing errors may exist.

For this purpose, before the access response operation performed by the storage test module to be verified on the plurality of access test requests is performed to obtain the plurality of test response information, a message interaction channel may be further established between the plurality of storage test modules for timing control. For example, after the first storage test module performs the first step of the access response operation, the first storage test module informs the next storage test module through the message interaction channel, the next storage test module performs the first step of the access response operation, and so on until all storage test modules perform the first step of the access response operation; then, the first storage test module executes the next step of the access response operation, the next storage test module is informed through the message interaction channel, the next storage test module executes the next step of the access response operation, and the like until all the storage test modules execute the next step of the access response operation. Therefore, time sequence control among a plurality of storage test modules is realized, and the acquisition of test response information with correct time sequence is ensured.

In a specific implementation, before the determining, based on the test response information of the plurality of storage test modules, whether the acquisition orders of the test response information of the plurality of storage test modules are the same, the method may further include:

based on the access response mode adopted by each storage test module and the access response mode used for verification of the access test request sent to each storage test module, judging whether the test response information corresponding to each storage test module is valid or not. It will be appreciated that the detailed description of the above process may refer to the description of the relevant parts before, and will not be repeated here. Therefore, the verification process can be monitored, the condition of sending errors of the access test request can be found in time, and the reliability of a verification result is ensured.

Optionally, if the plurality of storage test modules are described by using different levels of computer languages, and the plurality of storage test modules implement the same access response mode, after determining that the test response information corresponding to each storage test module is invalid, because the same access response mode is implemented, the test response information of the plurality of storage test modules still has a certain referential property, whether a logic vulnerability exists or not may be determined by determining whether the acquisition order of the test response information of the plurality of storage test modules is the same.

In a specific implementation, the test response information may further include: and the response mode sub-information is used for representing the access command indicated by the related access test request. Based on this, when the test response information based on the plurality of storage test modules determines whether the acquisition order of the test response information of the plurality of storage test modules is the same, it may include: based on the response mode sub-information of the test response information of the plurality of storage test modules, according to the acquisition sequence of the test response information of the plurality of storage test modules, the test response information indicating the same access command is selected for comparison so as to judge whether the acquisition sequence of the test response information of the plurality of storage test modules is the same. Thus, the judgment efficiency can be improved.

Taking two storage test modules as an example, based on response mode sub-information of the test response information of the storage test module 01 and response mode sub-information of the test response information of the storage test module 02, according to the acquisition sequence of the test response information of the two storage test modules, selecting the test response information indicating a read command in the test response information of the storage test module 01 and the test response information indicating a read command in the test response information of the storage test module 02, and comparing to judge whether the acquisition sequence of the test response information indicating the read command of the two storage test modules is the same.

And selecting the test response information indicating the write command in the test response information of the memory test module 01 and the test response information indicating the write command in the test response information of the memory test module 02 for comparison according to the acquisition sequence of the test response information of the two memory test modules based on the response mode sub-information of the test response information of the memory test module 01 and the response mode sub-information of the test response information of the memory test module 02 so as to judge whether the acquisition sequences of the test response information indicating the write command of the two memory test modules are the same.

In a specific implementation, in order to facilitate comparing test response information indicating the same access command of a plurality of memory test modules, the test response information of each memory test module may be classified according to the indicated access command and stored in a queue. The queue may be a first-in first-out data structure. In practical application, according to the practical verification scenario of the access response verification method provided in the embodiment of the present disclosure, a sending manner of an access test request and an obtaining manner of test response information may be determined.

For example, in a general verification methodology (Universal Verification Methodology, UVM) verification scenario, an access test request may be sent to a storage test module by sending an excitation signal, a test response signal of the storage test module may be collected, so as to obtain corresponding test response information, and specifically, a response intermediate sub-information may be obtained by collecting a test response signal at a designated location inside the storage test module; and acquiring and storing test response signals of the output positions of the test modules to obtain response result sub-information. The transmission method of the access test request and the acquisition method of the test response information are not particularly limited in this specification.

In specific implementation, signal processing can be performed on the acquired test response signal, so that verification efficiency is improved. Wherein the signal processing may comprise at least one of: the signal filtering is used for filtering irrelevant information in the test response signal; and the signal combination is used for combining the same information in the test response signals.

In practical application, according to different functions, the memory can be divided into a cache and a main memory, when the memory test module simulates the cache, in order to further fully verify whether the logic of the memory test module is correct, a data storage module can be configured for the memory test module, and according to the memory hierarchical structure of the cache simulated by the memory test module in practical application, the data storage module can simulate the next-level memory or simulate the sum of all memories in the downstream, so as to provide data support for the memory test module. For example, when the storage test module simulates a k-level cache, if the memory hierarchy of the k-level cache in practical applications further includes at least a k+1-level cache and a main memory, the data storage module may simulate the k+1-level cache, or may simulate all caches and main memories downstream of the k-level cache, where k is a positive integer.

Specifically, when the storage test module determines that the storage address indicated by the access test request is not hit, a data access request is sent to the data storage module, the data access request comprises the missed storage address, and the data storage module performs access response operation according to the received data access request.

In a specific implementation, the data storage module performs an access response operation on the data access request, and in order to avoid data collision, the ordering of the plurality of data access requests may be determined based on the storage type of the storage address indicated by the data access request. Specifically, if the storage type of the storage address indicated by the data access request is the specified order-preserving type, the order in which the access response operation is executed for the data access request is kept consistent with the order in which the data access request is received, so that the data access request corresponding to the specified order-preserving type can be ensured to be executed for the access response operation according to the received order, and the data access conflict can be effectively prevented.

It will be appreciated that the specified order-preserving type may be determined according to specific requirements. For example, specifying the order-preserving type may include at least one of: a merge Write (Write-complete) type, a Non-Coherent (Non-Coherent) type.

In a specific implementation, when there are multiple storage test modules, one data storage module may be configured for each storage test module, and when the multiple storage test modules implement the same access response mode, after the multiple storage test modules complete access response operations of all access test requests, data of the same storage addresses in the data storage modules configured by the multiple storage test modules may be compared, so as to determine a verification result. Therefore, the accuracy of the verification result can be further improved through the data comparison result of the same storage address in the plurality of data storage modules.

In a specific implementation, the mode of access response executed by the data storage module can be indicated by setting the working mode parameter of the data storage module.

The present specification also provides an access response verification device corresponding to the access response verification method, and the following detailed description will refer to the accompanying drawings by means of specific embodiments. It should be noted that the access response verification apparatus described below may include functional modules that are required to be set for implementing the access response verification method provided in the present specification; the contents of the access response verification apparatus described below may be referred to in correspondence with the contents of the access response verification method described above.

In a specific implementation, referring to fig. 4, which is a schematic structural diagram of an access response verification device in the embodiment of the present disclosure, the device D1 may include:

the response monitoring module M1 is suitable for monitoring access response operations of the storage test module MA to be verified on a plurality of access test requests so as to acquire a plurality of test response information; each access test request comprises an access test identifier, the access test identifier is used for identifying the access test request, each test response message comprises a response identification identifier, and each response identification identifier is determined through the access test identifier of the access test request related to the test response message;

the response checking module M2 is adapted to determine, based on response identification of the plurality of test response messages, whether the acquisition order of the plurality of test response messages meets an expected order, so as to determine a verification result.

It should be noted that, the specific embodiments of the storage test module, the response monitor module, and the response check module may refer to the descriptions of the related parts, and are not described herein.

In a specific implementation, with continued reference to fig. 4, the answer checking module M2 is further adapted to determine the expected ordering based on the access answer manner implemented by the storage test module, the sending order of the plurality of access test requests, and the content included in the plurality of access test requests.

In a specific implementation, with continued reference to fig. 4, the response checking module M2 is further adapted to determine whether the acquired test response information is valid based on an access response mode adopted by the storage test module and an access response mode used for verification by the access test request, where the access response mode includes an access sequential response or an access out-of-order response.

In a specific implementation, with continued reference to fig. 4, the response checking module M2 is further adapted to obtain an address holding sequence corresponding to the storage address indicated by each test response message, where the storage address indicated by the test response message is determined by the relevant access test request, and the address holding sequence includes at least one expected identification identifier; and comparing the response identification mark of the test response information in each order with the expected identification mark of the appointed sequence number in the address holding sequence corresponding to the test response information, so as to determine a verification result.

In a specific implementation, the access response verification device may further include other functional modules according to functional requirements. For example, with continued reference to fig. 4, the access response verification device D1 may further include at least one of the following:

The request generation module M3 is adapted to generate a plurality of access test requests.

The parameter setting module M4 is configured to set control parameters of the access response verification device D1, specifically, may set control parameters of the response checking module M2, control parameters of the request generating module M3, and control parameters of the data storage module M5. For example, the control parameters may include: request generation control parameters, response mode checking parameters, verification object parameters and data storage module working mode parameters.

A data storage module M5 adapted to provide data support for said storage test module MA.

The specification also provides a verification system comprising the access response verification device, which specifically comprises: the device comprises a storage test module to be verified and an access response verification device. The specific embodiments of the storage test module and the access response verification device may refer to the descriptions of the related parts, and are not repeated herein.

The specification also provides a verification platform comprising a verification component for constructing a verification environment of the access response verification method.

In a specific implementation, the verification platform may further include a control component and an interactive interface; wherein: the control component is used for setting control parameters of the verification environment, and the control parameters comprise at least one of the following: requesting to generate control parameters, response mode checking parameters, verification object parameters and working mode parameters of a data storage module; the interactive interface is used for visually verifying the components and controlling the parameter components.

In an alternative example, as shown in fig. 5, which is a schematic diagram of a verification platform in the embodiment of the present disclosure, the verification platform TB1 may include: a verification component 11, a control component 12 and an interactive interface 13. Wherein the verification component 11 may comprise: the system comprises an excitation signal driver, a plurality of monitors, a plurality of processors, a detection module, a plurality of storage test modules (two storage test modules in fig. 5), a plurality of data storage modules (two data storage modules in fig. 5) and a data comparison module.

Specifically, the plurality of monitors may be divided into a plurality of response intermediate signal monitors (two response intermediate signal monitors in fig. 5), a plurality of response result signal monitors (two response result signal monitors in fig. 5), and one excitation signal monitor, according to the specific functions implemented; the plurality of processors may be divided into a plurality of response intermediate signal processors (two response intermediate signal processors in fig. 5) and a plurality of response result signal processors (two response result signal processors in fig. 5).

Each storage test module can comprise a callback interface, an output interface and an interaction interface; each data storage module may include a storage bus function model for modeling the actual bus function of the memory.

The specification also provides a system on a chip comprising a verification component comprising a processor and a memory, wherein the hardware logic design of the memory is verified by the access response verification method.

In implementations, the processor may be a central processing unit (Central Processing Unit, CPU), a graphics processor (Graphics Processing Unit, GPU) or a General-purpose graphics processor (General-Purpose computing on Graphics Processing Units, GPGPU). The memory may be located in the processor or external to the processor. The memory may be a cache or a main memory.

It will be appreciated that the terms "first," "second," and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may include one or more of the feature, either explicitly or implicitly. Moreover, the terms "first," "second," and the like, are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate to enable embodiments of the invention described herein to be implemented in sequences other than those illustrated or otherwise described herein.

Although the embodiments of the present invention are disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims

1. An access response verification method, comprising:

2. The access response verification method according to claim 1, wherein before the response identification based on the plurality of the test response information, determining whether the acquisition order of the plurality of the test response information conforms to the expected order, further comprising:

3. The access response verification method according to claim 1, wherein before the response identification based on the plurality of the test response information, determining whether the order of acquisition of the plurality of the test response information conforms to an expected order for determining a verification result, further comprises:

4. The access response verification method according to claim 3, wherein the determining whether the acquired test response information is valid based on the access response mode adopted by the storage test module and the access response mode used for verification by the access test request includes:

5. The access response verification method according to claim 1, further comprising:

6. The access response verification method according to any one of claims 1 to 5, wherein the obtaining a plurality of test response information by monitoring access response operations performed by a storage test module to be verified on a plurality of access test requests includes:

7. The access response verification method according to any one of claims 1 to 5, wherein the obtaining a plurality of test response information by monitoring access response operations performed by a storage test module to be verified on a plurality of access test requests includes:

8. The access response verification method according to any one of claims 1 to 5, wherein the obtaining a plurality of test response information by monitoring access response operations performed by a storage test module to be verified on a plurality of access test requests includes:

9. The access response verification method according to claim 8, wherein the plurality of memory test modules use different levels of computer languages, and the plurality of memory function programs implement the same access response mode;

10. The access response verification method according to claim 9, wherein a plurality of access response operations performed on a plurality of access test requests by the memory test module to be verified are acquired at the access response operation by monitoring

Before the test response information, the method further comprises:

11. The access response verification method according to claim 9, further comprising, before the determining whether the acquisition order of the test response information of the plurality of memory test modules is the same based on the test response information of the plurality of memory test modules:

12. The access response verification method according to claim 11, wherein the test response information further includes: the response mode sub-information is used for representing the access command indicated by the related access test request;

13. The access response verification method according to claim 8, further comprising, before the access response operation performed on the plurality of access test requests by the storage test module to be verified is monitored, acquiring a plurality of test response information:

14. The access response verification method according to any one of claims 1 to 5, wherein the access response operation performed by the storage test module to be verified on a plurality of access test requests includes:

15. The access response verification method according to claim 11, wherein the number of the storage test modules is plural, and each of the storage test modules is configured with one data storage module;

the method further comprises the steps of:

16. The access response verification method according to claim 14, further comprising, before acquiring the plurality of test response information by monitoring access response operations performed by the memory test module to be verified on the plurality of access test requests:

17. An access response verification apparatus, the apparatus comprising:

18. The access response verification device of claim 17, wherein the response check module is further adapted to determine the expected ordering based on an access response pattern implemented by the storage test module, a transmission order of a plurality of the access test requests, and content included in a plurality of the access test requests.

19. The access response verification device according to claim 17, wherein the response check module is further adapted to determine whether the acquired test response information is valid based on an access response pattern adopted by the storage test module and an access response pattern used for verification by the access test request, wherein the access response pattern includes an access sequential response or an access out-of-order response.

20. The access response verification device of claim 17, wherein the response check module is further adapted to obtain an address holding sequence corresponding to the memory address indicated by each of the test response messages, wherein the memory address indicated by the test response message is determined by the associated access test request, and wherein the address holding sequence includes at least one expected identification; and comparing the response identification mark of the test response information in each order with the expected identification mark of the appointed sequence number in the address holding sequence corresponding to the test response information, so as to determine a verification result.

21. A verification system, comprising: a memory test module to be authenticated and an access response authentication device according to any one of claims 17 to 20.

22. A verification platform comprising a verification component for constructing a verification environment for the access response verification method of any one of claims 1 to 16.

23. The verification platform of claim 22, further comprising a control component and an interactive interface; wherein:

24. A system on chip comprising a processor and a memory, characterized in that the hardware logic design of the memory is verified by the access response verification method of any one of claims 1 to 16.