CN117150584A

CN117150584A - Power supply protection method and main board of PCIE equipment

Info

Publication number: CN117150584A
Application number: CN202311137905.9A
Authority: CN
Inventors: 邓仟; 黄增强; 郑晓晖
Original assignee: Hangzhou Hongjun Microelectronics Technology Co ltd
Current assignee: Hangzhou Hongjun Microelectronics Technology Co ltd
Priority date: 2023-09-04
Filing date: 2023-09-04
Publication date: 2023-12-01

Abstract

The invention relates to the technical field of computers, and provides a power supply protection method and a main board of PCIE equipment. The BMC in the main board is in communication connection with PCIE equipment, the PCIE equipment is electrically connected with the power supply module through a first power supply protection module, and the first power supply protection module is in communication connection with the BMC; the BMC obtains the model of the PCIE equipment, and obtains a current protection value corresponding to the model of the PCIE equipment according to a pre-stored first relation table to obtain a first current protection value; and then setting the first current protection value as an overcurrent protection point of the first power supply protection module so that the first power supply protection module protects PCIE equipment according to the overcurrent protection point. According to the invention, the overcurrent protection point of the power supply protection module is set to be the current protection value matched with the PCIE equipment, so that the PCIE equipment can be protected in time, and the damage of the PCIE equipment can be effectively prevented.

Description

Power supply protection method and main board of PCIE equipment

Technical Field

The invention relates to the technical field of computers, in particular to a power supply protection method and a main board of PCIE equipment.

Background

In recent years, PCIE (Peripheral Component Interconnect Express, high-speed serial computer expansion bus standard) devices are increasingly used, and are often plugged into a motherboard of an electronic device to achieve a specific function. At present, power supply protection is generally required for PCIE devices, but a common power supply protection mode is to use a preset multiple of the maximum power supply current as an overcurrent protection point, which leads to too high protection point, and cannot be timely protected when an abnormal condition occurs, for example, excessive current is continuously consumed when a fault just begins to be short-circuited, so that damage is aggravated, and open fire may also occur when serious fault occurs.

Disclosure of Invention

In view of the above, the present invention aims to provide a power supply protection method and a motherboard of PCIE devices.

In order to achieve the above purpose, the technical scheme adopted by the invention is as follows:

in a first aspect, the present invention provides a power supply protection method for a PCIE device, which is applied to a baseboard management controller BMC in a motherboard, where the motherboard further includes a PCIE device communicatively connected to the BMC, where the PCIE device is electrically connected to a power module through a first power supply protection module, where the first power supply protection module is communicatively connected to the BMC, and the BMC pre-stores a first relationship table, where the first relationship table includes current protection values corresponding to multiple PCIE device models, and the method includes:

obtaining the model of the PCIE equipment;

according to the first relation table, obtaining a current protection value corresponding to the model of the PCIE equipment, and obtaining a first current protection value;

and setting the first current protection value as an overcurrent protection point of the first power supply protection module, so that the first power supply protection module protects the PCIE equipment according to the overcurrent protection point.

In an alternative embodiment, the first power supply protection module includes a first connector and a first power isolation unit electrically connected to the first connector, where the first connector is electrically connected to the PCIE device, and the first power isolation unit is electrically connected to the power module and is communicatively connected to the BMC;

The step of setting the first current protection value to an overcurrent protection point of the first power supply protection module includes:

and writing the first current protection value into the first power isolation unit as an overcurrent protection point of the first power supply protection module.

In an optional embodiment, the first power supply protection module includes a first connector, a first power supply isolation unit, a first resistor module and a first complex programmable logic device CPLD that are electrically connected in sequence, where the first connector is electrically connected with the PCIE device, the first power supply isolation unit is electrically connected with the power supply module, the first CPLD is communicatively connected with the BMC, and the BMC further pre-stores a resistor value corresponding to each current protection value in the first relationship table;

and sending a first control signal to the first CPLD according to the first current protection value, so that the first CPLD controls the total resistance value of the first resistance module to be equal to the resistance value corresponding to the first current protection value according to the first control signal.

In an optional implementation manner, the PCIE device is further electrically connected to the power module through a second power supply protection module, the second power supply protection module is in communication connection with the BMC, the BMC further pre-stores a second relationship table, and the second relationship table includes current protection values corresponding to power consumption of multiple PCIE devices, and the method further includes:

Acquiring the power consumption demand of the PCIE equipment;

determining a power consumption supply amount of the second power supply protection module;

under the condition that the power consumption supply quantity is matched with the power consumption demand quantity, acquiring a current protection value corresponding to the power consumption demand quantity according to the second relation table to obtain a second current protection value;

and setting the second current protection value as an overcurrent protection point of the second power supply protection module, so that the second power supply protection module protects the PCIE equipment according to the overcurrent protection point.

In an optional embodiment, the second power supply protection module includes a second connector and a second CPLD electrically connected to the second connector, where the second connector is electrically connected to the PCIE device, and the second CPLD is communicatively connected to the BMC;

the step of determining the power consumption supply amount of the second power supply protection module includes:

acquiring the model and the pin level of the second connector acquired by the second CPLD;

and determining the power consumption supply amount according to the model number and the pin level of the second connector.

In an alternative embodiment, the second power supply protection module further includes a second power isolation unit electrically connected to the second connector and the power module, respectively, and communicatively connected to the BMC;

The step of setting the second current protection value to an overcurrent protection point of the second power supply protection module includes:

and writing the second current protection value into the second power isolation unit as an overcurrent protection point of the second power protection module.

In an optional embodiment, the second power supply protection module further includes a second power supply isolation unit and a second resistance module, where the second power supply isolation unit is electrically connected to the power supply module, the second connector and the second resistance module, the second resistance module is electrically connected to the second CPLD, and the BMC further pre-stores a resistance value corresponding to each current protection value in the second relationship table;

and sending a second control signal to the second CPLD according to the second current protection value, so that the second CPLD controls the total resistance value of the second resistance module to be equal to the resistance value corresponding to the second current protection value according to the second control signal.

In a second aspect, the invention provides a motherboard, which comprises a BMC, PCIE equipment, a first power module protection module and a power module, wherein the BMC is in communication connection with the PCIE equipment, the PCIE equipment is electrically connected with the power module through the first power module protection module, and the first power module protection module is in communication connection with the BMC;

The BMC is used for obtaining the model of the PCIE equipment; according to the first relation table, obtaining a current protection value corresponding to the model of the PCIE equipment, and obtaining a first current protection value; setting the first current protection value as an overcurrent protection point of the first power supply protection module;

the first power supply protection module is configured to protect the PCIE device according to the overcurrent protection point.

In an optional embodiment, the first power supply protection module includes a first connector, a first power supply isolation unit, a first resistor module and a first CPLD that are electrically connected in sequence, where the first connector is electrically connected with the PCIE device, the first power supply isolation unit is electrically connected with a power supply, the first CPLD is communicatively connected with the BMC, and the BMC further pre-stores a resistor value corresponding to each current protection value in the first relationship table;

the BMC is also used for sending a first control signal to the first CPLD according to the first current protection value;

and the first CPLD is used for controlling the total resistance value of the first resistance module to be equal to the resistance value corresponding to the first current protection value according to the first control signal.

In an optional embodiment, the motherboard further includes a second power supply protection module, the PCIE device is further electrically connected to the power supply module through the second power supply protection module, the second power supply protection module is connected to the BMC in a communication manner, and the BMC further pre-stores a second relationship table, where the second relationship table includes current protection values corresponding to power consumption of multiple PCIE devices;

The BMC is also used for acquiring the power consumption demand of the PCIE equipment; determining a power consumption supply amount of the second power supply protection module; under the condition that the power consumption supply quantity is matched with the power consumption demand quantity, acquiring a current protection value corresponding to the power consumption demand quantity according to the second relation table to obtain a second current protection value; setting the second current protection value as an overcurrent protection point of the second power supply protection module;

the second power supply protection module is configured to protect the PCIE device according to the overcurrent protection point.

According to the power supply protection method and the mainboard for the PCIE equipment, the BMC in the mainboard is in communication connection with the PCIE equipment, the PCIE equipment is electrically connected with the power supply module through the first power supply protection module, and the first power supply protection module is in communication connection with the BMC; the BMC obtains the model of the PCIE equipment, and obtains a current protection value corresponding to the model of the PCIE equipment according to a pre-stored first relation table to obtain a first current protection value; and then setting the first current protection value as an overcurrent protection point of the first power supply protection module so that the first power supply protection module protects PCIE equipment according to the overcurrent protection point. Compared with the prior art, the method and the device have the advantages that the model of the PCIE device is obtained through the BMC, and the current protection value matched with the model is used as the overcurrent protection point of the power supply protection module, so that the overcurrent protection point is matched with the PCIE device, the PCIE device can be protected in time, damage to the PCIE device can be effectively prevented, and the effect of power supply protection of the PCIE device is improved.

In order to make the above objects, features and advantages of the present invention more comprehensible, preferred embodiments accompanied with figures are described in detail below.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 shows one of schematic structural diagrams of a motherboard according to an embodiment of the present invention;

fig. 2 illustrates one of flow diagrams of a power supply protection method of PCIE devices according to an embodiment of the present invention;

fig. 3 shows a second schematic structural diagram of a motherboard according to an embodiment of the present invention;

fig. 4 shows a third schematic structural diagram of a motherboard according to an embodiment of the present invention;

fig. 5 illustrates one example diagram of a power supply protection method of a PCIE device provided by an embodiment of the present invention;

fig. 6 illustrates a second exemplary diagram of a power supply protection method of a PCIE device according to an embodiment of the present invention;

Fig. 7 shows a fourth schematic structural diagram of a motherboard according to an embodiment of the present invention;

fig. 8 illustrates a second flowchart of a power supply protection method of PCIE devices according to an embodiment of the present invention;

fig. 9 shows a fifth schematic structural diagram of a motherboard according to an embodiment of the present invention;

fig. 10 shows a sixth schematic structural diagram of a motherboard according to an embodiment of the present invention;

fig. 11 illustrates a third exemplary diagram of a power supply protection method of a PCIE device according to an embodiment of the present invention;

fig. 12 shows a fourth example diagram of a power supply protection method of PCIE devices provided by an embodiment of the present invention.

Detailed Description

The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. The components of the embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.

Thus, the following detailed description of the embodiments of the invention, as presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be made by a person skilled in the art without making any inventive effort, are intended to be within the scope of the present invention.

It is noted that relational terms such as "first" and "second", and the like, are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

In recent years, PCIE devices have been increasingly used, which are often plugged into a motherboard of an electronic device to achieve a specific function. PCIE devices are typically connected to a Power supply through a connector, such as a CEM connector or a CEM Aux Power connector, and in order to ensure that the PCIE devices can work normally, power protection is often required for the PCIE devices. The existing power supply protection mode takes the maximum power supply current, i.e. the preset multiple of the maximum current which can be provided by the connector, as an overcurrent protection point, but the mode can cause the overcurrent protection point to be too high, so that the fault cannot be timely protected when abnormal conditions occur, for example, the fault just begins to consume excessive current continuously when the fault is not completely shorted, so that damage is aggravated, and open fire can also occur when the fault is serious. Therefore, the embodiment of the invention provides a power supply protection method of PCIE equipment to solve the problems.

Fig. 1 is a schematic structural diagram of a motherboard according to an embodiment of the present invention. The motherboard comprises a BMC (Baseboard Management Controller ), PCIE equipment, a first power supply protection module and a power supply module. The BMC is respectively in communication connection with the PCIE device and the first power supply protection module, for example, the BMC can be in communication connection with the PCIE device and the first power supply protection module through an IIC (Inter-Integrated Circuit, integrated circuit bus); PCIE equipment is connected with the power module through a first power supply protection module.

In order to facilitate understanding, the power supply protection method of the PCIE device provided by the embodiment of the present invention will be described below with reference to the motherboard shown in fig. 1 and using the BMC as an execution body.

Referring to fig. 2, fig. 2 is a flowchart of a power supply protection method for PCIE devices according to an embodiment of the present invention.

Step S202, obtaining the model of PCIE equipment;

it can be understood that the current protection values corresponding to the PCIE device models may be preset, that is, the first relationship table may be obtained, and the first relationship table may be stored in the BMC. For example, the operating current value may be determined based on the operating power consumption of each PCIE device model, and a preset multiple, such as 1.3 times, of the operating current may be used as the corresponding current protection value.

In this embodiment, the BMC may read information in an EEPROM (Electrically Erasable Programmable read only memory, live erasable read-only memory) of the PCIE device through the IIC, and obtain a model of the PCIE device according to the information.

Step S204, obtaining a current protection value corresponding to the model of PCIE equipment according to a first relation table, and obtaining a first current protection value;

step S206, setting the first current protection value as an overcurrent protection point of the first power supply protection module, so that the first power supply protection module protects PCIE equipment according to the overcurrent protection point;

in this embodiment, after the BMC obtains the model of the PCIE device, the current protection value corresponding to the model of the PCIE device may be found in the first relationship table, that is, the first current protection value is obtained, and the first current protection value is set as an overcurrent protection point of the first power supply protection module.

The first power supply protection module protects the PCIE device according to the overcurrent protection point, i.e., the first current protection value. When the current flowing through the first power supply protection module exceeds the first current protection value, the first power supply protection module is disconnected from the power supply module, so that the effect of protecting PCIE equipment is achieved.

Compared with the mode of setting the overcurrent protection point based on the maximum power supply current in the prior art, the embodiment of the invention obtains the model of the PCIE equipment through the BMC, and takes the current protection value matched with the model as the overcurrent protection point of the power supply protection module, so that the overcurrent protection point is matched with the PCIE equipment, the PCIE equipment can be protected in time, damage to the PCIE equipment can be effectively prevented, and the effect of power supply protection of the PCIE equipment is improved.

Based on the steps, the BMC in the main board is in communication connection with PCIE equipment, the PCIE equipment is electrically connected with the power supply module through the first power supply protection module, and the first power supply protection module is in communication connection with the BMC; the BMC obtains the model of the PCIE equipment, and obtains a current protection value corresponding to the model of the PCIE equipment according to a pre-stored first relation table to obtain a first current protection value; and then setting the first current protection value as an overcurrent protection point of the first power supply protection module so that the first power supply protection module protects PCIE equipment according to the overcurrent protection point. Compared with the prior art, the method and the device have the advantages that the model of the PCIE device is obtained through the BMC, and the current protection value matched with the model is used as the overcurrent protection point of the power supply protection module, so that the overcurrent protection point is matched with the PCIE device, the PCIE device can be protected in time, damage to the PCIE device can be effectively prevented, and the effect of power supply protection of the PCIE device is improved.

Optionally, for the first power supply protection module shown in fig. 1, a possible implementation manner is provided in an embodiment of the present invention, please refer to fig. 3. The first power supply protection module comprises a first connector and a first power supply isolation unit electrically connected with the first connector; the first connector is electrically connected with PCIE equipment, and the first power isolation unit is electrically connected with the power module and is in communication connection with the BMC.

Based on the schematic structural diagram of the motherboard shown in fig. 3, for the above step S206, the embodiment of the present invention provides a possible implementation manner, that is: in step S206A, the first current protection value is written into the first power isolation unit as an overcurrent protection point of the first power protection module.

It will be appreciated that the first connector may be a CEM connector and the first power isolation unit may be a eFuse (electronic fuse) chip, which belongs to one-time programmable memory. The first power isolation unit may be communicatively coupled to the BMC through the IIC.

In this embodiment, in the case that the first power isolation unit, such as the first eFuse chip, has the peripheral interface, the first eFuse chip may be communicatively connected to the BMC through the IIC, and then the BMC may directly write the first current protection value into the register of the first eFuse chip, that is, set the first current protection value as the overcurrent protection point of the first power protection module. When the current flowing through the first eFuse chip exceeds the first current protection value, the first eFuse chip disconnects the first eFuse chip from the power supply module so as to achieve the effect of protecting the PCIE device.

Optionally, for the first power supply protection module shown in fig. 1, a further possible implementation manner is provided in the embodiment of the present invention, please refer to fig. 4. The first power supply protection module comprises a first connector, a first power supply isolation unit, a first resistor module and a first CPLD (Complex Programmable Logic Device ) which are electrically connected in sequence, wherein the first connector is electrically connected with PCIE equipment, the first power supply isolation unit is electrically connected with the power supply module, and the first CPLD is in communication connection with the BMC.

Based on the schematic structural diagram of the motherboard shown in fig. 4, for the above step S206, another possible implementation manner is provided in the embodiment of the present invention, that is: step S206B, a first control signal is sent to the first CPLD according to the first current protection value, so that the first CPLD controls the total resistance value of the first resistor module to be equal to the resistance value corresponding to the first current protection value according to the first control signal.

It will be appreciated that the first connector may be a CEM connector and the first power isolation unit may be a eFuse (electronic fuse) chip, which belongs to one-time programmable memory.

In this embodiment, in the case where the first power isolation unit, such as the first eFuse chip, has no peripheral interface, the resistor module may be configured and the CPLD may be used to control the resistor module to set the overcurrent protection point of the first power protection module.

For example, a resistance value corresponding to each current protection value in the first relation table may be stored in the BMC in advance. After the BMC obtains the first current protection value, the BMC may send a first control signal to the first CPLD according to the first current protection value.

And the first CPLD controls a plurality of first resistor branches in the first resistor module to be conducted or disconnected according to the received first control signal, so that the total resistance value of the first resistor module is equal to the resistance value corresponding to the first current protection value, and the first current protection value is set as an overcurrent protection point of the first power supply protection module. When the current flowing through the first eFuse chip exceeds the first current protection value, the first eFuse chip disconnects the first eFuse chip from the power supply module so as to achieve the effect of protecting the PCIE device.

For ease of understanding, an exemplary diagram of the first resistor module is provided in the embodiment of the present invention, and reference is made to fig. 5. The first resistor module comprises a plurality of first resistor branches which are connected in parallel, for example, 3, and each first resistor branch comprises a first resistor and a corresponding first switch unit. For each first resistor branch, one end of the first resistor is electrically connected with the first power isolation unit, the other end of the first resistor is electrically connected with a contact s1 of the first switch unit, a contact s2 of the first switch unit is grounded, and a control end c of the first switch unit is electrically connected with the first CPLD. Wherein the first resistors in the 3 first resistor branches are R1, R2 and R3, respectively.

When the first CPLD receives a first control signal sent by the BMC, the first switch unit is controlled to be turned on or off, so that the first resistor is connected or cut out, and the total resistance of the first resistor module is equal to the resistance value corresponding to the first current protection value.

Optionally, the first switching unit may be a MOS transistor, a triode, or the like. For example, taking the first switch unit as an NMOS transistor as an example, an example diagram is provided in the embodiment of the present invention. As shown in fig. 6, for each first resistor branch, one end of the first resistor is electrically connected to the first power isolation unit, the other end is electrically connected to the drain of the first switching unit, the source of the first switching unit is grounded, and the gate of the first switching unit is electrically connected to the first CPLD.

It is assumed that the current protection values in the first relation table are 8 and I11 to I18, respectively, and that the first switching unit is in an off state by "0" and in an on state by "1". The relationship between the 8 current protection values and the state of each first switching unit and the total resistance of the first resistor module can be represented as table 1 below.

TABLE 1

As can be seen from table 1, according to the embodiment of the present invention, the first switch unit can be controlled to be in different states according to different current protection values in the first relation table, so that the total resistance of the first resistor module is different.

In some scenarios, for some PCIE devices with high power consumption, if only one power supply protection module is used, power supply deficiency may occur, so that the PCIE device is electrically connected to the power supply module through another power supply protection module. Further, the embodiment of the present invention provides a further structural schematic diagram of the motherboard, as shown in fig. 7, where the motherboard further includes a second power supply protection module, where the PCIE device is electrically connected to the power supply module through the second power supply protection module, and the second power supply protection module is connected to the BMC in a communication manner.

It can be appreciated that, in order to ensure that the PCIE device can function normally, an overcurrent protection point needs to be set for the second power supply protection module. Next, a process of setting the overcurrent protection point of the second power protection module through the BMC will be described, with reference to fig. 8.

Step S208, obtaining the power consumption demand of PCIE equipment;

step S210, determining the power consumption supply amount of the second power supply protection module;

it can be understood that the current protection values corresponding to the power consumption of the PCIE devices may be preset, that is, the second relationship table is obtained, and the second relationship table is stored in the BCM.

In this embodiment, the BMC may obtain the working power consumption of the PCIE device through the model of the PCIE device, determine, according to the working power consumption and the power consumption provided by the first power supply protection module, power consumption further required by the PCIE device, that is, the power consumption required amount of the PCIE device, and determine the power consumption that the second power supply protection module may provide, that is, the power consumption provided amount of the second power supply protection module.

Step S212, under the condition that the power consumption supply quantity is matched with the power consumption demand quantity, acquiring a current protection value corresponding to the power consumption demand quantity according to a second relation table to obtain a second current protection value;

step S214, setting a second current protection value as an overcurrent protection point of the second power supply protection module, so that the second power supply protection module protects PCIE equipment according to the overcurrent protection point;

in this embodiment, after obtaining the power consumption requirement of the PCIE device and the power consumption supply of the second power supply protection module, the BMC further compares the power consumption requirement of the PCIE device and the power consumption supply of the second power supply protection module, so as to ensure that the PCIE device can work normally.

If the power consumption supply amount of the second power supply protection module is smaller than the power consumption demand amount of the PCIE equipment, the two power supply protection modules are not matched, which indicates that the power supply demand of the PCIE equipment cannot be met by adopting the second power supply protection module, and the second power supply protection module is checked and upgraded so that the power consumption required by the PCIE equipment can be provided.

If the power consumption supply amount of the second power supply protection module is equal to or greater than the power consumption demand amount of the PCIE equipment, the power consumption supply amount of the second power supply protection module and the power consumption demand amount of the PCIE equipment are judged to be matched, and the power consumption demand amount of the PCIE equipment can be met by adopting the second power supply protection module.

The second power supply protection module protects the PCIE device according to the overcurrent protection point, that is, the second current protection value. When the current flowing through the second power supply protection module exceeds the second current protection value, the second power supply protection module is disconnected from the power supply module, so that the effect of protecting PCIE equipment is achieved.

Optionally, for step S210, one possible implementation is provided by the embodiment of the present invention.

Step S210-1, obtaining the model number and the pin level of a second connector acquired by a second CPLD;

and step S210-3, determining the power consumption supply amount according to the model number and the pin level of the second connector.

In this embodiment, the second power supply protection module includes a second connector and a second CPLD electrically connected to the second connector, where the second connector is electrically connected to the PCIE device, and the second CPLD is communicatively connected to the BMC.

It is understood that the second connector may be a CEM Aux Power connector, which may supply Power to a PCIE device with high Power consumption, and may be added to supply Power to the PCIE device when the CEM connector is not sufficiently powered.

The CEM Aux Power connector has various models, such as 2*3, 2×4, 48V/12VHPWR, etc., and the CEM Aux Power connector of the same model has different Power consumption when the sense pin level is different. Therefore, in the embodiment of the invention, the model and the pin level of the second connector are acquired through the second CPLD, and then the BMC determines the power consumption which can be provided by the second connector according to the model and the pin level of the second connector, namely, the power consumption providing amount is obtained.

Alternatively, for the second power protection module shown in fig. 7, a possible implementation manner is provided in the embodiment of the present invention, please refer to fig. 9. The second power supply protection module comprises a second connector, a second power supply isolation unit and a second CPLD which are electrically connected in sequence, the second connector is electrically connected with PCIE equipment, the second power supply isolation unit is electrically connected with the power supply module and is in communication connection with the BMC, and the second CPLD is in communication connection with the BMC.

Based on the schematic structural diagram of the motherboard shown in fig. 9, for the above step S214, the embodiment of the present invention provides a possible implementation manner, that is: in step S214A, the second current protection value is written into the second power isolation unit as an overcurrent protection point of the second power protection module.

It is understood that the second connector may be a CEM Aux Power connector and the second Power isolation unit may be a eFuse (electronic fuse) chip, which belongs to the one-time programmable memory. The second power isolation unit may be communicatively coupled to the BMC through the IIC.

In this embodiment, in the case that the second power isolation unit, such as the second eFuse chip, has the peripheral interface, the second eFuse chip may be communicatively connected to the BMC through the IIC, and then the BMC may directly write the second current protection value into the register of the second eFuse chip, that is, set the second current protection value as the overcurrent protection point of the second power protection module. When the current flowing through the second eFuse chip exceeds the second current protection value, the second eFuse chip disconnects the second eFuse chip from the power module so as to achieve the effect of protecting the PCIE device.

Alternatively, for the second power protection module shown in fig. 7, a further possible implementation manner is provided in the embodiment of the present invention, please refer to fig. 10. The second power supply protection module comprises a second connector, a second power supply isolation unit, a second resistor module and a second CPLD which are electrically connected in sequence, the second connector is electrically connected with PCIE equipment, the second power supply isolation unit is electrically connected with the power supply module, and the second CPLD is in communication connection with the BMC.

Based on the schematic structural diagram of the motherboard shown in fig. 10, for the above step S214, another possible implementation manner is provided in the embodiment of the present invention, that is: step S214B, a second control signal is sent to the second CPLD according to the second current protection value, so that the second CPLD controls the total resistance value of the second resistor module to be equal to the resistance value corresponding to the second current protection value according to the second control signal.

It is understood that the second connector may be a CEM Aux Power connector and the second Power isolation unit may be a eFuse (electronic fuse) chip, which belongs to the one-time programmable memory.

In this embodiment, in the case where the second power isolation unit, such as the second eFuse chip, has no peripheral interface, the resistor module may be configured and the CPLD may be used to control the resistor module to set the overcurrent protection point of the second power protection module.

For example, a resistance value corresponding to each current protection value in the second relation table may be stored in the BMC in advance. After the BMC obtains the second current protection value, the BMC may send a second control signal to the second CPLD according to the second current protection value.

And the second CPLD controls a plurality of second resistor branches in the second resistor module to be conducted or disconnected according to the received second control signal, so that the total resistance value of the second resistor module is equal to the resistance value corresponding to the second current protection value, and the second current protection value is set as an overcurrent protection point of the second power supply protection module. When the current flowing through the second eFuse chip exceeds the second current protection value, the second eFuse chip disconnects the second eFuse chip from the power module so as to achieve the effect of protecting the PCIE device.

For ease of understanding, an exemplary diagram of the second resistor module is provided in accordance with an embodiment of the present invention, and reference is made to fig. 11. The second resistor module comprises a plurality of, for example, 3 parallel second resistor branches, and each second resistor branch comprises a second resistor and a corresponding second switch unit. For each second resistor branch, one end of the second resistor is electrically connected with the second power isolation unit, the other end of the second resistor is electrically connected with a contact s1 of the second switch unit, a contact s2 of the second switch unit is grounded, and a control end c of the second switch unit is electrically connected with the second CPLD. Wherein the second resistors in the 3 second resistor branches are R4, R5 and R6, respectively.

When the second CPLD receives a second control signal sent by the BMC, the second switch unit is controlled to be turned on or off, so that the second resistor is connected or disconnected, and the total resistance of the second resistor module is equal to the resistance value corresponding to the second current protection value.

Optionally, the second switching unit may be a MOS transistor, a triode, or the like. For example, taking the second switch unit as an NMOS transistor as an example, an example diagram is provided in the embodiment of the present invention. As shown in fig. 12, for each second resistor branch, one end of the second resistor is electrically connected to the second power isolation unit, the other end is electrically connected to the drain of the second switching unit, the source of the second switching unit is grounded, and the gate of the second switching unit is electrically connected to the second CPLD.

It is assumed that the second relation table has 8 current protection values I21 to I28, respectively, and that the second switching unit is in an off state by "0" and in an on state by "1". The relationship between these 8 current protection values and the state of each second switching unit and the total resistance of the second resistance module can be represented as table 2 below.

TABLE 2

As can be seen from table 2, according to the embodiment of the present invention, the second switch unit is controlled to be in different states according to different current protection values in the second relation table, so that the total resistance of the second resistor module is different.

In order to better understand the effects of the present invention, an example is provided in the embodiment of the present invention. For example, assume that the power supply module provides a voltage of 12V and the first power protection module employs a CEM connector and eFuse chip.

According to the prior art, the maximum current that the CEM connector can provide is 5.5A, and 1.3 times of the maximum current is taken as the overcurrent protection point, and then the overcurrent protection point of the first power supply protection module is 7.15A.

According to the method provided by the invention, the working power consumption of the PCIE equipment is 20W according to the model of the PCIE equipment, the working current of the PCIE equipment is 1.67A, and 1.3 times of the working current of the PCIE equipment is adopted as the corresponding current protection value, so that the overcurrent protection point of the first power supply protection module is 2.2A.

Assuming that the power supply capacity is 1A/us, if the overcurrent protection point set by the prior art is adopted, the protection duration is t1= (7.15-1.67)/1=5.48 us; if the overcurrent protection point set by the invention is adopted, the protection time length is t2= (2.2-1.67)/1=0.53 us. It can be seen that the protection time length in the prior art is about 10 times of the protection time length of the invention, that is, the method provided by the invention has a faster protection speed, and can protect PCIE equipment more timely.

And the upper limit of power consumption of the prior art is 85.8W, while the upper limit of power consumption of the present invention is 26.4W. It can be seen that, for the power consumption limitation range of PCIE devices, the present invention is 32.5% of the prior art, that is, the method provided by the present invention can more effectively prevent damage from expanding.

In order to execute the corresponding steps in the foregoing embodiments and various possible manners, an embodiment of the present invention further provides a motherboard. It should be noted that, the basic principle and the technical effects of the motherboard provided in this embodiment are the same as those of the foregoing embodiments, and for brevity, reference may be made to the corresponding contents of the foregoing embodiments.

The main board comprises a BMC, PCIE equipment, a first power module protection module and a power module, wherein the BMC is in communication connection with the PCIE equipment, the PCIE equipment is electrically connected with the power module through the first power module protection module, and the first power module protection module is in communication connection with the BMC;

the BMC is used for obtaining the model of the PCIE equipment; according to the first relation table, obtaining a current protection value corresponding to the model of PCIE equipment, and obtaining a first current protection value; setting the first current protection value as an overcurrent protection point of the first power supply protection module;

the first power supply protection module is used for protecting PCIE equipment according to the overcurrent protection point.

Optionally, the first power supply protection module includes a first connector and a first power supply isolation unit electrically connected with the first connector, the first connector is electrically connected with the PCIE device, and the first power supply isolation unit is electrically connected with the power supply module and is in communication connection with the BMC;

the BMC is also used for writing the first current protection value into the first power isolation unit as an overcurrent protection point of the first power supply protection module.

Optionally, the first power supply protection module includes a first connector, a first power supply isolation unit, a first resistance module and a first complex programmable logic device CPLD that are electrically connected in sequence, the first connector is electrically connected with the PCIE device, the first power supply isolation unit is electrically connected with the power supply module, the first CPLD is in communication connection with the BMC, and the BMC further pre-stores a resistance value corresponding to each current protection value in the first relation table;

the first CPLD is used for controlling the total resistance value of the first resistor module to be equal to the resistance value corresponding to the first current protection value according to the first control signal.

Optionally, the main board further includes a second power supply protection module, the PCIE device is further electrically connected to the power supply module through the second power supply protection module, the second power supply protection module is connected to the BMC in a communication mode, and the BMC further pre-stores a second relationship table, where the second relationship table includes current protection values corresponding to power consumption of multiple PCIE devices;

The BMC is also used for acquiring the power consumption demand of the PCIE equipment; determining a power consumption supply amount of the second power supply protection module; under the condition that the power consumption supply quantity is matched with the power consumption demand quantity, acquiring a current protection value corresponding to the power consumption demand quantity according to a second relation table to obtain a second current protection value; setting the second current protection value as an overcurrent protection point of the second power supply protection module;

the second power supply protection module is used for protecting the PCIE equipment according to the overcurrent protection point.

Optionally, the second power supply protection module includes a second connector and a second CPLD electrically connected with the second connector, the second connector is electrically connected with the PCIE device, and the second CPLD is communicatively connected with the BMC;

the BMC is also used for acquiring the model and the pin level of the second connector acquired by the second CPLD; the power consumption supply amount is determined according to the model number and the pin level of the second connector.

Optionally, the second power supply protection module further includes a second power isolation unit, and the second power isolation unit is electrically connected with the second connector and the power module respectively and is in communication connection with the BMC;

the BMC is also used for writing a second current protection value into the second power isolation unit as an overcurrent protection point of the second power protection module.

Optionally, the second power supply protection module further includes a second power supply isolation unit and a second resistor module, the second power supply isolation unit is electrically connected with the power supply module, the second connector and the second resistor module respectively, the second resistor module is electrically connected with the second CPLD, and the BMC further pre-stores a resistance value corresponding to each current protection value in the second relation table;

the BMC is also used for sending a second control signal to the second CPLD according to the second current protection value;

the second CPLD is used for controlling the total resistance value of the second resistance module to be equal to the resistance value corresponding to the second current protection value according to the second control signal.

In the several embodiments provided in the present invention, it should be understood that the disclosed method and method may be implemented in other manners as well. The above-described embodiments are merely illustrative, for example, of the flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of methods and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

In addition, functional modules in the embodiments of the present invention may be integrated together to form a single part, or each module may exist alone, or two or more modules may be integrated to form a single part.

The functions, if implemented in the form of software functional modules and sold or used as a stand-alone product, may be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention may be embodied essentially or in a part contributing to the prior art or in a part of the technical solution, in the form of a software product stored in a storage medium, comprising several instructions for causing a computer device (which may be a personal computer, a server, a network device, etc.) to perform all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a magnetic disk, or an optical disk, or other various media capable of storing program codes.

The above description is only of the preferred embodiments of the present invention and is not intended to limit the present invention, but various modifications and variations can be made to the present invention by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. The power supply protection method of PCIE equipment is characterized by being applied to a Baseboard Management Controller (BMC) in a main board, wherein the main board further comprises PCIE equipment in communication connection with the BMC, the PCIE equipment is electrically connected with a power supply module through a first power supply protection module, the first power supply protection module is in communication connection with the BMC, a first relation table is prestored in the BMC, the first relation table comprises current protection values corresponding to various PCIE equipment models, and the method comprises the following steps:

obtaining the model of the PCIE equipment;

2. The method of claim 1, wherein the first power protection module comprises a first connector electrically connected to the PCIE device and a first power isolation unit electrically connected to the first connector, the first power isolation unit electrically connected to the power module and communicatively connected to the BMC;

3. The method of claim 1, wherein the first power protection module comprises a first connector, a first power isolation unit, a first resistor module and a first complex programmable logic device CPLD electrically connected in sequence, the first connector is electrically connected with the PCIE device, the first power isolation unit is electrically connected with the power module, the first CPLD is communicatively connected with the BMC, and the BMC further pre-stores a resistance value corresponding to each current protection value in the first relationship table;

4. The method of claim 1, wherein the PCIE devices are further electrically connected to a power module through a second power protection module, the second power protection module is communicatively connected to the BMC, the BMC further stores a second relationship table, the second relationship table includes current protection values corresponding to power consumption of the PCIE devices, and the method further includes:

acquiring the power consumption demand of the PCIE equipment;

5. The method of claim 4, wherein the second power protection module comprises a second connector and a second CPLD electrically connected to the second connector, the second connector being electrically connected to the PCIE device, the second CPLD being communicatively connected to the BMC;

6. The method of claim 5, wherein the second power protection module further comprises a second power isolation unit electrically connected to the second connector and power module, respectively, and communicatively connected to the BMC;

7. The method of claim 5, wherein the second power protection module further comprises a second power isolation unit and a second resistance module, the second power isolation unit is electrically connected to the power module, the second connector, and the second resistance module, respectively, the second resistance module is electrically connected to the second CPLD, and the BMC further pre-stores a resistance value corresponding to each current protection value in the second relationship table;

8. The main board is characterized by comprising a BMC, PCIE equipment, a first power module protection module and a power module, wherein the BMC is in communication connection with the PCIE equipment, the PCIE equipment is electrically connected with the power module through the first power module protection module, and the first power module protection module is in communication connection with the BMC;

9. The motherboard of claim 8, wherein the first power protection module comprises a first connector, a first power isolation unit, a first resistor module and a first CPLD electrically connected in sequence, the first connector is electrically connected with the PCIE device, the first power isolation unit is electrically connected with a power supply, the first CPLD is in communication connection with the BMC, and the BMC further pre-stores a resistor value corresponding to each current protection value in the first relationship table;

10. The motherboard of claim 8, further comprising a second power supply protection module, wherein the PCIE device is further electrically connected to the power supply module through the second power supply protection module, the second power supply protection module is communicatively connected to the BMC, and the BMC further pre-stores a second relationship table, where the second relationship table includes current protection values corresponding to power consumption of multiple PCIE devices;