CN117135966A

CN117135966A - Display device and method of manufacturing the same

Info

Publication number: CN117135966A
Application number: CN202310598718.4A
Authority: CN
Inventors: 吴彦锡; 徐正准; 成泰铉; 洪昇秀; 金相烈; 宋济铉
Original assignee: Samsung Display Co Ltd
Current assignee: Samsung Display Co Ltd
Priority date: 2022-05-27
Filing date: 2023-05-25
Publication date: 2023-11-28
Also published as: US20230413610A1; KR20230165991A

Abstract

A display device and a method of manufacturing the same are provided. The display device in an embodiment includes: a base substrate including a first auxiliary display area and a main display area surrounding the first auxiliary display area; a pixel circuit layer disposed on the base substrate; and a light emitting device layer disposed on the pixel circuit layer and including a plurality of first light emitting devices disposed in the first auxiliary display region, and each of the plurality of first light emitting devices includes a pixel electrode, a light emitting layer disposed on the pixel electrode, and a common electrode disposed on the light emitting layer and defining a plurality of transmission holes, and the plurality of first light emitting devices and the plurality of transmission holes are alternately arranged in a plan view, the plurality of transmission holes being defined in the first auxiliary display region.

Description

Display device and method of manufacturing the same

Technical Field

Embodiments of the invention relate to a display device and a method of manufacturing the same.

Background

The display device may display an image using pixels. The display device may include an area for transmitting external inputs and/or internal outputs. In such a display device, a method for improving the transmittance of the region is being studied.

Disclosure of Invention

The embodiment provides a display device having improved transmittance and improved reliability in a partial region.

Embodiments provide a method of manufacturing a display device.

The display device in an embodiment may include: a base substrate including a first auxiliary display area and a main display area surrounding the first auxiliary display area; a pixel circuit layer disposed on the base substrate; and a light emitting device layer disposed on the pixel circuit layer and including a plurality of first light emitting devices disposed in the first auxiliary display region, and each of the plurality of first light emitting devices may include a pixel electrode, a light emitting layer disposed on the pixel electrode, and a common electrode disposed on the light emitting layer and defining a plurality of transmission holes, and the plurality of first light emitting devices and the plurality of transmission holes may be alternately arranged in a plan view, the plurality of transmission holes being defined in the first auxiliary display region.

In an embodiment, the light emitting device layer may further include a pixel defining pattern exposing a portion of the pixel electrode, and the plurality of transmission holes may be spaced apart from the pixel defining pattern in a plan view.

In an embodiment, the plurality of transmission holes may be repeatedly arranged along the row direction and the column direction in a plan view.

In an embodiment, the plurality of transmission holes may include: a plurality of first transmission holes having a first planar shape; and a plurality of second transmission holes having a second planar shape different from the first planar shape.

In an embodiment, the plurality of first transmission holes may be repeatedly arranged in an odd numbered row of the first auxiliary display area in a plan view, and the plurality of second transmission holes may be repeatedly arranged in an even numbered row of the first auxiliary display area in a plan view.

In an embodiment, at least one of the inner surfaces of the common electrode exposed by the plurality of transmission holes may include a plurality of curves.

In an embodiment, the base substrate may further include a second auxiliary display region adjacent to the first auxiliary display region, and the light emitting device layer may further include a plurality of second light emitting devices disposed in the second auxiliary display region, and the pixel circuit layer may include: a first pixel circuit disposed in the second auxiliary display region and controlling a current transmitted to at least one of the plurality of first light emitting devices; and a second pixel circuit disposed in the second auxiliary display region and controlling a current transmitted to at least one of the plurality of second light emitting devices.

In an embodiment, the pixel circuit layer may further include a connection line electrically connecting at least one of the plurality of first light emitting devices with the first pixel circuit.

In an embodiment, the connection line may comprise a transparent conductive oxide.

In an embodiment, the transmittance of the first auxiliary display region may be higher than the transmittance of the second auxiliary display region and the transmittance of the main display region.

In an embodiment, the display apparatus may further include a light blocking pattern disposed between the base substrate and the light emitting device layer, and the light blocking pattern may overlap the plurality of first light emitting devices in a plan view.

In an embodiment, the light blocking pattern may cover the entire lower surface of the pixel electrode included in each of the plurality of first light emitting devices.

In an embodiment, the light blocking pattern may be spaced apart from the plurality of transmission holes in a plan view.

In an embodiment, the light blocking pattern may include a metal material, and the metal material may absorb or reflect incident infrared laser light.

In an embodiment, the thickness of the light blocking pattern may be about 50 nanometers (nm) to about 500nm.

In an embodiment, the display device may further include an electronic module disposed under the base substrate and overlapping the first auxiliary display region on a plane.

A method of manufacturing the display device in an embodiment may include the steps of: preparing a base substrate including a first auxiliary display area and a main display area surrounding the first auxiliary display area; forming a pixel circuit layer on a base substrate; forming a plurality of first light emitting devices disposed in the first auxiliary display region on the pixel circuit layer; and irradiating laser light from the lower side of the base substrate to the first auxiliary display region, and each of the plurality of first light emitting devices may include a pixel electrode, a light emitting layer disposed on the pixel electrode, and a common electrode disposed on the light emitting layer, and in the step of irradiating the laser light, a plurality of transmission holes may be defined in the common electrode to be alternately arranged with the plurality of first light emitting devices in a plan view.

In an embodiment, the step of irradiating the laser may be to define a plurality of transmission holes by irradiating the laser in a spot shape.

In an embodiment, the method may further include forming a light blocking pattern on the base substrate, and the light blocking pattern may overlap the plurality of first light emitting devices.

Accordingly, the display apparatus in the embodiment of the invention may include a plurality of first light emitting devices. The plurality of first light emitting devices may be disposed in the first auxiliary display region. The plurality of transmission holes may be defined in the common electrode disposed in the first auxiliary display region. In the first auxiliary display region, the plurality of first light emitting devices and the plurality of transmission holes may be alternately arranged. Accordingly, the transmittance of the first auxiliary display region may be improved.

In addition, the plurality of transmission holes may be defined by selectively removing the laser-irradiated portions of the common electrode. The laser light may be irradiated in the form of a spot for each region between the plurality of first light emitting devices. Accordingly, in the process of defining the plurality of transmission holes, damage of the plurality of first light emitting devices, the pixel defining pattern, and the plurality of insulating layers disposed in the first auxiliary display region may be minimized. Therefore, the reliability of the display device can be improved.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.

Drawings

Illustrative, non-limiting embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

Fig. 1 is a diagram showing an embodiment of a display device.

Fig. 2 is a cross-sectional view illustrating a display module included in the display device of fig. 1.

Fig. 3 is a plan view illustrating a display panel included in the display module of fig. 2.

Fig. 4 is an enlarged view showing an enlarged area "a" of fig. 3.

Fig. 5 is a cross-sectional view illustrating a first auxiliary display area and a second auxiliary display area of the display panel of fig. 3.

Fig. 6 is a cross-sectional view illustrating a main display area of the display panel of fig. 3.

Fig. 7 is a plan view illustrating a first auxiliary display area of the display panel of fig. 3.

Fig. 8 is a sectional view taken along line II-II' of fig. 7.

Fig. 9 is an enlarged view showing an enlarged region "B" of fig. 7.

Fig. 10 to 15 are cross-sectional views illustrating a method of manufacturing a display panel included in the display device of fig. 1.

Fig. 16 is a cross-sectional view showing an embodiment of a display panel.

Fig. 17 is a cross-sectional view showing an embodiment of a display panel.

Detailed Description

It will be understood that when an element is referred to as being "on" another element, it can be directly on the other element or intervening elements may be present therebetween. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements present.

It will be understood that, although the terms "first," "second," "third," etc. may be used herein to describe various elements, components, regions, layers and/or components, these elements, components, regions, layers and/or components should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a "first element," "first component," "first region," "first layer," or "first component" discussed below could be termed a second element, a second component, a second region, a second layer, or a second component without departing from the teachings herein.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well as "at least one" unless the context clearly indicates otherwise. "or" means "and/or". As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. It will be further understood that the terms "comprises" and/or "comprising," and/or variations thereof, when used in this specification, specify the presence of stated features, regions, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components, and/or groups thereof.

Furthermore, relative terms such as "lower" or "bottom" and "upper" or "top" may be used herein to describe one element's relationship to another element as illustrated in the figures. It will be understood that relative terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures. For example, if the device in one of the figures is turned over, elements described as being on the "lower" side of other elements would then be oriented on the "upper" side of the other elements. Accordingly, the exemplary term "lower" may include both an orientation of "lower" and "upper" depending on the particular orientation of the drawing. Similarly, if the device in one of the figures is turned over, elements described as "below" or "beneath" other elements would then be oriented "above" the other elements. Thus, the exemplary terms "below" or "beneath" can encompass both an orientation of above and below.

As used herein, "about" or "approximately" includes the stated values and means: taking into account the measurements in question and the errors associated with the measurement of a particular quantity (i.e. limitations of the measurement system), are within an acceptable deviation of a particular value as determined by one of ordinary skill in the art. For example, a term such as "about" may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

Fig. 1 is a diagram showing an embodiment of a display device.

Referring to fig. 1, the display device 1000 in the embodiment may include a display module DM and an electronic module CM. The display module DM may generate an image and sense externally applied pressure. The electronic module CM may be disposed under the display module DM.

The active area AA and the inactive area NAA may be defined in the display module DM. The display device 1000 may display an image through the active area AA of the display module DM. The effective area AA may include a plane defined by a first direction DR1 and a second direction DR2 orthogonal to the first direction DR 1. That is, the display device 1000 may display an image in the third direction DR3 perpendicular to the plane through the active area AA of the display module DM. The ineffective area NAA may be disposed around the effective area AA. In an embodiment, the inactive area NAA may, for example, surround the active area AA.

In an embodiment, the sensing area SA may be defined in the active area AA. In an embodiment, the sensing area SA may be, for example, a portion of the active area AA. That is, the sensing area SA may display an image, and may transmit an external input provided to and/or an output provided from the electronic module CM. The sensing region SA may have a transmittance higher than that of other regions in the effective region AA. Although fig. 1 illustrates that one sensing area SA is defined in the active area AA, the number of sensing areas SA is not necessarily limited thereto.

The electronic module CM may be disposed in a region overlapping the sensing region SA. As described above, the electronic module CM may receive an external input transmitted through the sensing area SA, or may provide an output to the outside through the sensing area SA. In the embodiment, the electronic module CM may be, for example, a camera module, a sensor for measuring a distance, a sensor for recognizing a part of the body of the user, a small lamp outputting light, or the like, but the type of the electronic module CM is not limited thereto.

Fig. 2 is a cross-sectional view illustrating a display module included in the display device of fig. 1. In an embodiment, fig. 2 is a cross-sectional view taken, for example, along line I-I' of fig. 1.

Referring to fig. 1 and 2, the display module DM may include a display panel 100, a sensing layer 200, and an anti-reflection layer 300. The display panel 100 may include a base substrate 110, a pixel circuit layer 120, a light emitting device layer 130, and an encapsulation layer 140.

The display panel 100 may basically generate an image. In an embodiment, the display panel 100 may be, for example, an organic light emitting display panel, an inorganic light emitting display panel, or a quantum dot display panel. Hereinafter, a case in which the display panel 100 is an organic light emitting display panel will be described restrictively, but the configuration of the invention is not necessarily limited thereto.

The base substrate 110 may be an insulating substrate including a transparent or opaque material. The base substrate 110 may have a single-layer or multi-layer structure. In an embodiment, the base substrate 110 may include glass. In this case, the base substrate 110 may be a rigid substrate. In another embodiment, the base substrate 110 may comprise plastic. In this case, the base substrate 110 may be a flexible substrate. In an embodiment, plastics that may be used for the base substrate 110 may include Polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polypropylene (PP), polycarbonate (PC), polystyrene (PS), polysulfone (PSul), polyethylene (PE), polyphthalamide (PPA), polyethersulfone (PEs), polyarylate (PAR), polycarbonate oxide (PCO), modified polyphenylene oxide (MPPO), and the like. These may be used alone or in combination with each other.

The pixel circuit layer 120 may be disposed on the base substrate 110. The pixel circuit layer 120 may include an inorganic layer, an organic layer, and a metal pattern. The pixel circuit may be implemented by an inorganic layer, an organic layer, and a metal pattern.

The light emitting device layer 130 may be disposed on the pixel circuit layer 120. The light emitting device layer 130 may include a plurality of light emitting devices. In an embodiment, the light emitting device layer 130 may include, for example, an organic light emitting material, an inorganic light emitting material, an organic-inorganic light emitting material, quantum dots, and the like. Hereinafter, a case in which the light emitting device layer 130 includes an organic light emitting material will be limitedly described, but the configuration of the invention is not necessarily limited thereto.

The encapsulation layer 140 may be disposed on the light emitting device layer 130. The encapsulation layer 140 may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. In an embodiment, the encapsulation layer 140 may include, for example, a first inorganic encapsulation layer disposed on the light emitting device layer 130, an organic encapsulation layer disposed on the first inorganic encapsulation layer, and a second inorganic encapsulation layer disposed on the organic encapsulation layer. The encapsulation layer 140 may prevent moisture, air, etc. from penetrating into the light emitting device layer 130.

The sensing layer 200 may be disposed on the display panel 100. In other words, the sensing layer 200 may be disposed on the encapsulation layer 140. The sensing layer 200 may sense an external input applied from the outside. In an embodiment, the external input may be, for example, a touch by a user. In an embodiment, the sensing layer 200 may be formed on the display panel 100 through a continuous process. In this case, an additional component (e.g., an adhesive member) may not be disposed between the display panel 100 and the sensing layer 200. In another embodiment, the display panel 100 and the sensing layer 200 may be bonded to each other by an adhesive member.

The anti-reflection layer 300 may be disposed on the sensing layer 200. The anti-reflection layer 300 may suppress reflection of external light incident from the outside of the display module DM. In an embodiment, the anti-reflection layer 300 may include a phase retarder and a polarizer. The phase retarder and the polarizer may be implemented as a single polarizing film. In another embodiment, the anti-reflection layer 300 may include a color filter. The color filters may have a predetermined arrangement. In an embodiment, the color filters may be arranged considering, for example, colors emitted by pixels included in the display panel 100.

In an embodiment, the sensing layer 200 may be omitted. When the sensing layer 200 is omitted, the anti-reflection layer 300 may be disposed on the display panel 100. In an embodiment, the anti-reflection layer 300 may be formed on the display panel 100, for example, through a continuous process. Furthermore, the locations of the sensing layer 200 and the anti-reflection layer 300 may be different from that described above. In an embodiment, the anti-reflection layer 300 may be disposed between the display panel 100 and the sensing layer 200, for example.

Fig. 3 is a plan view illustrating a display panel included in the display module of fig. 2. Fig. 4 is an enlarged view showing an enlarged area "a" of fig. 3.

Referring to fig. 3 and 4, the display panel 100 may include a display area DA and a non-display area NDA. The display area DA may correspond to the active area AA of fig. 1. The non-display area NDA may correspond to the ineffective area NAA of fig. 1. The non-display area NDA may be disposed around the display area DA. In an embodiment, the non-display area NDA may, for example, surround the display area DA.

The display area DA may include a first auxiliary display area SDA1, a second auxiliary display area SDA2, and a main display area MDA. The first auxiliary display area SDA1 may also be referred to as a component area. The second auxiliary display area SDA2 may also be referred to as a middle area or a transition area. The main display area MDA may also be referred to as a general display area.

The first auxiliary display area SDA1 may overlap or correspond to the sensing area SA shown in fig. 1. In other words, the first auxiliary display area SDA1 may overlap the electronic module CM of fig. 1 in a plan view. In an embodiment, for example, an external input may be provided to the electronic module CM through the first auxiliary display area SDA1, and an output from the electronic module CM may be transmitted to the outside through the first auxiliary display area SDA1. Although fig. 3 illustrates that the first auxiliary display area SDA1 has a circular shape, the configuration of the invention is not limited thereto. In an embodiment, the first auxiliary display area SDA1 may, for example, have various shapes such as a polygonal shape, an elliptical shape, or an irregular shape.

The second auxiliary display area SDA2 may be adjacent to the first auxiliary display area SDA1. In an embodiment, the second auxiliary display area SDA2 may, for example, surround the first auxiliary display area SDA1. In an embodiment, the transmittance of the second auxiliary display area SDA2 may be lower than the transmittance of the first auxiliary display area SDA1. In an embodiment, the second auxiliary display area SDA2 may be spaced apart from the non-display area NDA. However, the invention is not limited thereto, and in another embodiment, the second auxiliary display area SDA2 may contact the non-display area NDA.

The main display area MDA may be adjacent to the second auxiliary display area SDA2 and may surround the first auxiliary display area SDA1. In an embodiment, the transmittance of the main display area MDA may be lower than the transmittance of the first auxiliary display area SDA1.

The display panel 100 may include a plurality of pixels PX. A plurality of pixels PX may be disposed in the display area DA. The plurality of pixels PX may include a first pixel PX1, a second pixel PX2, and a third pixel PX3. The first pixel PX1 may emit light in the first auxiliary display area SDA1, the second pixel PX2 may emit light in the second auxiliary display area SDA2, and the third pixel PX3 may emit light in the main display area MDA.

Each of the first, second, and third pixels PX1, PX2, and PX3 may be provided in plurality. In this case, each of the plurality of first, second, and third pixels PX1, PX2, and PX3 may include a red pixel, a green pixel, and a blue pixel. In an embodiment, each of the plurality of first, second, and third pixels PX1, PX2, and PX3 may further include a white pixel.

The first pixel PX1 may include a first light emitting device LD1 and a first pixel circuit PC1. The first pixel circuit PC1 may control a current transmitted to the first light emitting device LD 1. The second pixel PX2 may include a second light emitting device LD2 and a second pixel circuit PC2. The second pixel circuit PC2 may control a current transmitted to the second light emitting device LD 2. The third pixel PX3 may include a third light emitting device LD3 and a third pixel circuit PC3. The third pixel circuit PC3 may control a current transmitted to the third light emitting device LD 3.

In an embodiment, the first light emitting device LD1 may be disposed in the first auxiliary display area SDA1, and the first pixel circuit PC1 may be disposed in the second auxiliary display area SDA 2. In another embodiment, the first pixel circuit PC1 may be disposed in the non-display area NDA. Since the first pixel circuit PC1 is not disposed in the first auxiliary display area SDA1, transmittance of the first auxiliary display area SDA1 may be improved.

In this case, the first light emitting device LD1 and the first pixel circuit PC1 may be electrically connected to each other through a connection line TWL. The connection line TWL may include a transparent conductive material. In an embodiment, the connection line TWL may include a material such as Indium Tin Oxide (ITO), indium Zinc Oxide (IZO), indium Gallium Zinc Oxide (IGZO), zinc oxide (ZnO), or indium oxide (In) ₂ O ₃ ) Transparent Conductive Oxide (TCO).

Specifically, the first light emitting device LD1 may be disposed in the first auxiliary display area SDA1, the first pixel circuit PC1, the second light emitting device LD2, and the second pixel circuit PC2 may be disposed in the second auxiliary display area SDA2, and the third light emitting device LD3 and the third pixel circuit PC3 may be disposed in the main display area MDA.

Accordingly, the transmittance of the second auxiliary display area SDA2 and the transmittance of the main display area MDA may be lower than the transmittance of the first auxiliary display area SDA 1. In addition, since the first pixel circuit PC1 is disposed in the second auxiliary display area SDA2, the number of second pixels PX2 disposed in the second auxiliary display area SDA2 per unit area may be smaller than the number of third pixels PX3 disposed in the main display area MDA.

In the embodiment, each of the first, second, and third light emitting devices LD1, LD2, and LD3 may be provided in plurality. The distance between the two first light emitting devices most adjacent to each other among the plurality of first light emitting devices LD1 may be greater than the distance between the two third light emitting devices most adjacent to each other among the plurality of third light emitting devices LD 3. Further, a distance between two second light emitting devices most adjacent to each other among the plurality of second light emitting devices LD2 may be greater than a distance between two third light emitting devices most adjacent to each other among the plurality of third light emitting devices LD 3.

Fig. 5 is a cross-sectional view illustrating a first auxiliary display area and a second auxiliary display area of the display panel of fig. 3. Fig. 6 is a cross-sectional view illustrating a main display area of the display panel of fig. 3.

Referring to fig. 5 and 6, the display panel 100 may include an inorganic layer, an organic layer, and a metal pattern. As described above, the display panel 100 may include the base substrate 110, the pixel circuit layer 120, the light emitting device layer 130, and the encapsulation layer 140.

The pixel circuit layer 120 may be disposed on the base substrate 110. In an embodiment, the pixel circuit layer 120 may include a buffer layer 120BR, a first insulating layer 121, a second insulating layer 122, a third insulating layer 123, a fourth insulating layer 124, a fifth insulating layer 125, a sixth insulating layer 126, a seventh insulating layer 127, eighth and ninth insulating layers 128 and 129, and first, second and third pixel circuits PC1 and PC3, first and second connection lines TWL1 and TWL2.

Each of the first, second, and third pixel circuits PC1, PC2, and PC3 may include a transistor. In an embodiment, the first pixel circuit PC1 may include a first transistor TFT1, the second pixel circuit PC2 may include a second transistor TFT2, and the third pixel circuit PC3 may include a third transistor TFT3 and a fourth transistor TFT4. For example, each of the first transistor TFT1, the second transistor TFT2, the third transistor TFT3, and the fourth transistor TFT4 may include an active pattern, a gate electrode, and a connection electrode.

The buffer layer 120BR may be disposed on the base substrate 110. The buffer layer 120BR may prevent impurities from diffusing from the base substrate 110 to the first, second, and third pixel circuits PC1, PC2, and PC3. In an embodiment, the buffer layer 120BR may include an insulating material. In an embodiment, materials that may be used for the buffer layer 120BR may include silicon oxide, silicon nitride, silicon oxynitride, and the like. These may be used alone or in combination with each other.

In an embodiment, the back metal layer BML may be disposed between the base substrate 110 and the buffer layer 120 BR. The back metal layer BML may be disposed to overlap the first, second, and third pixel circuits PC1, PC2, and PC3. Furthermore, the back metal layer BML may be disposed to be spaced apart from the first auxiliary display area SDA 1.

In an embodiment, the first, second, and third active patterns ACT1, ACT2, and ACT3 may be disposed on the buffer layer 120 BR. In an embodiment, the first, second, and third active patterns ACT1, ACT2, and ACT3 may include, for example, a silicon semiconductor.

In another embodiment, the first active pattern ACT1 and the second active pattern ACT2 may be disposed on the third insulating layer 123. In this case, the first active pattern ACT1 and the second active pattern ACT2 may include an oxide semiconductor.

The first insulating layer 121 may be disposed on the buffer layer 120BR and cover the first, second, and third active patterns ACT1, ACT2, and ACT3. The first insulating layer 121 may have a single-layer or multi-layer structure. In an embodiment, the first insulating layer 121 may include an insulating material. In an embodiment, a material that may be used as the first insulating layer 121 may include silicon oxide, silicon nitride, silicon oxynitride, or the like. These may be used alone or in combination with each other.

The first, second, and third gate electrodes GAT1, GAT2, and GAT3 may be disposed on the first insulating layer 121. Specifically, the first gate electrode GAT1 may overlap the first active pattern ACT1, the second gate electrode GAT2 may overlap the second active pattern ACT2, and the third gate electrode GAT3 may overlap the third active pattern ACT3. In an embodiment, the first, second and third gate electrodes GAT1, GAT2 and GAT3 may include metals, alloys, conductive metal oxides, transparent conductive materials, and the like. In an embodiment, materials that may be used as the first, second, and third gate electrodes GAT1, GAT2, and GAT3 may include silver (Ag), an alloy containing silver, molybdenum (Mo), an alloy containing molybdenum, aluminum (Al), an alloy containing aluminum, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), nickel (Ni), chromium (Cr), chromium nitride (CrN), titanium (Ti), tantalum (Ta), platinum (Pt), scandium (Sc), ITO, IZO, and the like. These may be used alone or in combination with each other.

The second insulating layer 122 may be disposed on the first insulating layer 121 and cover the first, second, and third gate electrodes GAT1, GAT2, and GAT3. The second insulating layer 122 may have a single-layer or multi-layer structure. In an embodiment, the second insulating layer 122 may include an insulating material. In an embodiment, a material that may be used as the second insulating layer 122 may include silicon oxide, silicon nitride, silicon oxynitride, or the like. These may be used alone or in combination with each other.

The third insulating layer 123 may be disposed on the second insulating layer 122. The third insulating layer 123 may have a single-layer or multi-layer structure. In an embodiment, the third insulating layer 123 may include an insulating material. In an embodiment, a material that may be used as the third insulating layer 123 may include silicon oxide, silicon nitride, silicon oxynitride, or the like. These may be used alone or in combination with each other.

The fourth active pattern ACT4 may be disposed on the third insulating layer 123. The fourth active pattern ACT4 may include an oxide semiconductor.

The fourth insulating layer 124 may be disposed on the third insulating layer 123 and cover the fourth active pattern ACT4. The fourth insulating layer 124 may have a single-layer or multi-layer structure. In an embodiment, the fourth insulating layer 124 may include an insulating material. In an embodiment, a material that may be used as the fourth insulating layer 124 may include silicon oxide, silicon nitride, silicon oxynitride, or the like. These may be used alone or in combination with each other.

The fourth gate electrode GAT4 may be disposed on the fourth insulating layer 124. The fourth gate electrode GAT4 may overlap the fourth active pattern ACT4. In an embodiment, the fourth gate electrode GAT4 may include a metal, an alloy, a conductive metal oxide, a transparent conductive material, or the like. In an embodiment, a material that may be used as the fourth gate electrode GAT4 includes silver (Ag), an alloy containing silver, molybdenum (Mo), an alloy containing molybdenum, aluminum (Al), an alloy containing aluminum, and aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), nickel (Ni), chromium (Cr), chromium nitride (CrN), titanium (Ti), tantalum (Ta), platinum (Pt), scandium (Sc), ITO, IZO, or the like. These may be used alone or in combination with each other.

The fifth insulating layer 125 may be disposed on the fourth insulating layer 124 and cover the fourth gate electrode GAT4. The fifth insulating layer 125 may have a single-layer or multi-layer structure. In an embodiment, the fifth insulating layer 125 may include an insulating material. In an embodiment, a material that may be used as the fifth insulating layer 125 may include silicon oxide, silicon nitride, silicon oxynitride, or the like. These may be used alone or in combination with each other.

The first, second, third, fourth, fifth, sixth, seventh, and eighth connection electrodes CE1, CE2, CE3, CE4, CE5, CE6, CE7, and CE8 may be disposed on the fifth insulating layer 125. The first and second connection electrodes CE1 and CE2 may contact the first active pattern ACT1 through contact holes penetrating the first, second, third, fourth, and fifth insulating layers 121, 122, 123, 124, and 125. The third and fourth connection electrodes CE3 and CE4 may contact the second active pattern ACT2 through contact holes penetrating the first, second, third, fourth, and fifth insulating layers 121, 122, 123, 124, and 125. The fifth and sixth connection electrodes CE5 and CE6 may contact the third active pattern ACT3 through contact holes penetrating the first, second, third, fourth, and fifth insulating layers 121, 122, 123, 124, and 125. The seventh and eighth connection electrodes CE7 and CE8 may contact the fourth active pattern ACT4 through contact holes penetrating the fourth and fifth insulating layers 124 and 125.

In an embodiment, the first, second, third, fourth, fifth, sixth, seventh, and eighth connection electrodes CE1, CE2, CE3, CE4, CE5, CE6, CE7, and CE8 may include a metal, an alloy, a conductive metal oxide, a transparent conductive material, and the like. In an embodiment, materials that may be used as the first, second, third, fourth, fifth, sixth, seventh, and eighth connection electrodes CE1, CE2, CE3, CE4, CE5, CE6, CE7, and CE8 may include silver (Ag), an alloy containing silver, molybdenum (Mo), an alloy containing molybdenum, aluminum (Al), an alloy containing aluminum, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), nickel (Ni), chromium (Cr), chromium nitride (CrN), titanium (Ti), tantalum (Ta), platinum (Pt), scandium (Sc), ITO, IZO, and the like. These may be used alone or in combination with each other.

The first active pattern ACT1, the first gate electrode GAT1, the first connection electrode CE1, and the second connection electrode CE2 may constitute a first transistor TFT1. In addition, the second active pattern ACT2, the second gate electrode GAT2, the third connection electrode CE3, and the fourth connection electrode CE4 may constitute a second transistor TFT2. In addition, the third active pattern ACT3, the third gate electrode GAT3, the fifth connection electrode CE5, and the sixth connection electrode CE6 may constitute a third transistor TFT3. In addition, the fourth active pattern ACT4, the fourth gate electrode GAT4, the seventh connection electrode CE7, and the eighth connection electrode CE8 may constitute a fourth transistor TFT4.

In an embodiment, the third transistor TFT3 may be a silicon-based semiconductor device included in the third pixel circuit PC3, and the fourth transistor TFT4 may be an oxide-based semiconductor device. Therefore, in the third pixel PX3 of the main display area MDA, even when the low frequency driving is performed, the color change of the image according to the voltage drop is not large. That is, since the third pixel circuit PC3 employs the fourth transistor TFT4 as an oxide semiconductor device, low-frequency driving is possible, and thus power consumption can be further reduced. However, the constitution of the invention is not necessarily limited thereto. In the embodiment, the third pixel circuit PC3 may use, for example, only one of a silicon-based semiconductor device and an oxide-based semiconductor device as a transistor.

The sixth insulating layer 126 may be disposed on the fifth insulating layer 125 and cover the first, second, third, fourth, fifth, sixth, seventh, and eighth connection electrodes CE1, CE2, CE3, CE4, CE5, CE6, CE7, and CE8. The sixth insulating layer 126 may have a single-layer or multi-layer structure. In an embodiment, the sixth insulating layer 126 may include an insulating material. In an embodiment, a material that may be used as the sixth insulating layer 126 may include a photoresist, a polyacrylic resin, a polyimide resin, an acrylic resin, or the like. These may be used alone or in combination with each other.

The ninth connection electrode CE9, the tenth connection electrode CE10, and the eleventh connection electrode CE11 may be disposed on the sixth insulating layer 126. The ninth connection electrode CE9 may contact the first connection electrode CE1 through a contact hole penetrating the sixth insulating layer 126, and the tenth connection electrode CE10 may contact the third connection electrode CE3 through a contact hole penetrating the sixth insulating layer 126. The eleventh connection electrode CE11 may contact the fifth connection electrode CE5 through a contact hole penetrating the sixth insulation layer 126.

The first transistor TFT1 and the ninth connection electrode CE9 may constitute a first pixel circuit PC1. In addition, the second transistor TFT2 and the tenth connection electrode CE10 may constitute a second pixel circuit PC2. In addition, the third transistor TFT3, the fourth transistor TFT4, and the eleventh connection electrode CE11 may constitute a third pixel circuit PC3. In this case, the first and second pixel circuits PC1 and PC2 may be disposed in the second auxiliary display area SDA2, and the third pixel circuit PC3 may be disposed in the main display area MDA.

The seventh insulating layer 127 may be disposed on the sixth insulating layer 126 and cover the ninth connection electrode CE9, the tenth connection electrode CE10, and the eleventh connection electrode CE11. The seventh insulating layer 127 may have a single-layer or multi-layer structure. In an embodiment, the seventh insulating layer 127 may include an insulating material. In an embodiment, a material that may be used as the seventh insulating layer 127 may include a photoresist, a polyacrylic resin, a polyimide resin, an acrylic resin, or the like. These may be used alone or in combination with each other.

The first connection line TWL1 may be disposed on the seventh insulating layer 127. The first connection line TWL1 may contact the ninth connection electrode CE9 of the first pixel circuit PC1 through a contact hole penetrating the seventh insulating layer 127. In an embodiment, the first connection line TWL1 may overlap the plurality of transmission holes TH of the common electrode CTE. Accordingly, the first connection line TWL1 may include a light-transmitting material. In an embodiment, the material that may be used as the first connection line TWL1 may include, for example, ITO, IZO, IGZO, zinc oxide (ZnO), or indium oxide (In ₂ O ₃ ) Etc. These may be used alone or in combination with each other.

The eighth insulating layer 128 may be disposed on the seventh insulating layer 127 and cover the first connection line TWL1. The eighth insulating layer 128 may have a single-layer or multi-layer structure. In an embodiment, eighth insulating layer 128 may include an insulating material. In an embodiment, a material that may be used as the eighth insulating layer 128 may include a photoresist, a polyacrylic resin, a polyimide resin, an acrylic resin, or the like. These may be used alone or in combination with each other.

The second connection line TWL2 may be disposed on the eighth insulating layer 128. The second connection line TWL2 may contact the first connection line TWL1 through a contact hole penetrating the eighth insulating layer 128. Further, the second connection line TWL2 may be connected to the first pixel electrode ADE1 of the first light emitting device LD 1. Thus, the first connection line TWL1 and the second connection line T WL2 may electrically connect the first pixel circuit PC1 and the first light emitting device LD 1. In an embodiment, the material that may be used as the second connection line TWL2 may include, for example, ITO, IZO, IGZO, zinc oxide (ZnO), or indium oxide (In ₂ O ₃ ) Etc. These may be used alone or in combination with each other.

The ninth insulating layer 129 may be disposed on the eighth insulating layer 128 and cover the second connection line TWL2. The ninth insulating layer 129 may have a single-layer or multi-layer structure. In an embodiment, the ninth insulating layer 129 may include an insulating material. In an embodiment, a material that may be used as the ninth insulating layer 129 may include a photoresist, a polyacrylic resin, a polyimide resin, an acrylic resin, or the like. These may be used alone or in combination with each other.

The light emitting device layer 130 may be disposed on the pixel circuit layer 120. In an embodiment, the light emitting device layer 130 may include first, second, and third light emitting devices LD1, LD2, and LD3, a pixel defining layer PDL, and a pixel defining pattern PDP. The first light emitting device LD1 may be disposed in the first auxiliary display area SDA1, the second light emitting device LD2 may be disposed in the second auxiliary display area SDA2, and the third light emitting device LD3 may be disposed in the main display area MDA. The first light emitting device LD1 may include a first pixel electrode ADE1, a first light emitting layer EL1, and a common electrode CTE, the second light emitting device LD2 may include a second pixel electrode ADE2, a second light emitting layer EL2, and a common electrode CTE, and the third light emitting device LD3 may include a third pixel electrode ADE3, a third light emitting layer EL3, and a common electrode CTE.

The first, second, and third pixel electrodes ADE1, ADE2, and ADE3 may be disposed on the ninth insulating layer 129. Specifically, the first pixel electrode ADE1 may be disposed in the first auxiliary display area SDA1, the second pixel electrode ADE2 may be disposed in the second auxiliary display area SDA2, and the third pixel electrode ADE3 may be disposed in the main display area MDA.

In an embodiment, each of the first, second, and third pixel electrodes ADE1, ADE2, and ADE3 may be formed as a transmissive electrode or a reflective electrode. When the first pixel electrode ADE1,When each of the second and third pixel electrodes ADE2 and ADE3 is formed as a transmissive electrode, examples of materials that may be used for the first, second and third pixel electrodes ADE1, ADE2 and ADE3 may include ITO, IZO, IGZO, zinc oxide (ZnO), indium oxide (In ₂ O ₃ ) Aluminum doped zinc oxide (AZO), and the like. These may be used alone or in combination with each other. When each of the first, second, and third pixel electrodes ADE1, ADE2, and ADE3 is formed as a reflective electrode, examples of materials that may be used for the first, second, and third pixel electrodes ADE1, ADE2, and ADE3 may include gold (Au), silver (Ag), aluminum (Al), copper (Cu), nickel (Ni), platinum (Pt), magnesium (Mg), chromium (Cr), tungsten (W), molybdenum (Mo), titanium (Ti), and the like. These may be used alone or in combination with each other. Further, these pixel electrodes may have a laminated structure having a material for a transmissive electrode.

As described above, the first pixel electrode ADE1 may be electrically connected to the first pixel circuit PC1 disposed in the second auxiliary display area SDA 2. In an embodiment, the first pixel electrode ADE1 may contact the second connection line TWL2, for example, through a contact hole penetrating the ninth insulating layer 129. Accordingly, the first pixel electrode ADE1 may be electrically connected to the first pixel circuit PC1 through the first and second connection lines TWL1 and TWL2. The second pixel electrode ADE2 may contact the tenth connection electrode CE10 through a contact hole penetrating the seventh insulating layer 127, the eighth insulating layer 128, and the ninth insulating layer 129 to be in electrical contact with the second pixel circuit PC 2. The third pixel electrode ADE3 may contact the eleventh connection electrode CE11 through a contact hole penetrating the seventh insulating layer 127, the eighth insulating layer 128, and the ninth insulating layer 129 to be electrically contacted with the third pixel circuit PC 3.

A pixel defining layer PDL and a pixel defining pattern PDP may be disposed on the ninth insulating layer 129. The pixel defining pattern PDP may be disposed in the first auxiliary display area SDA 1. The pixel defining pattern PDP may expose a portion of the first pixel electrode ADE 1. The pixel defining layer PDL may be disposed in the second auxiliary display area SDA2 and the main display area MDA. The pixel defining layer PDL may expose a portion of each of the second and third pixel electrodes ADE2 and ADE 3.

In an embodiment, the pixel defining layer PDL and the pixel defining pattern PDP may include the same material and may be formed by the same process. In an embodiment, the pixel defining layer PDL and the pixel defining pattern PDP may include, for example, black dye, black pigment, carbon black, metal such as chrome, or an oxide thereof.

The first light emitting layer EL1 may be disposed on the first pixel electrode ADE1, the second light emitting layer EL2 may be disposed on the second pixel electrode ADE2, and the third light emitting layer EL3 may be disposed on the third pixel electrode ADE 3. In an embodiment, each of the first, second, and third light emitting layers EL1, EL2, and EL3 may emit red, green, or blue light.

The common electrode CTE may be disposed on the first, second, and third light emitting layers EL1, EL2, and EL 3. That is, the common electrode CTE may be continuously formed in the display area DA across a plurality of pixels PX (refer to fig. 3). In an embodiment, the common electrode CTE may comprise a transmissive electrode or a reflective electrode. In embodiments, the common electrode CTE may include, for example, a metal, an alloy, a metal nitride, a metal fluoride, a conductive metal oxide, or any combination thereof.

The plurality of transmission holes TH may be defined in the common electrode CTE. A plurality of transmission holes TH may be defined in the first auxiliary display area SDA 1. In an embodiment, after the common electrode CTE is continuously formed for the plurality of pixels PX, laser light may be applied in the form of a spot to each region between the plurality of first light emitting devices LD1 among the common electrode CTE. Accordingly, the plurality of transmission holes TH may be defined by removing the laser-irradiated portions of the common electrode CTE. Accordingly, the plurality of transmission holes TH may be defined to be spaced apart from the pixel defining pattern PDP. Since a portion of the common electrode CTE is removed from the portion in which the plurality of transmission holes TH are provided, the transmittance of the first auxiliary display area SDA1 may be improved.

Although not shown, a hole control layer may be disposed between the first, second, and third pixel electrodes ADE1, ADE2, and ADE3 and the first, second, and third light emitting layers EL1, EL2, and EL 3. The hole control layer may include a hole transport layer, and may further include a hole injection layer. The electronic control layer may be disposed between the first, second, and third light emitting layers EL1, EL2, and EL3 and the common electrode CTE. The electron control layer may include an electron transport layer, and may further include an electron injection layer.

The encapsulation layer 140 may be disposed on the light emitting device layer 130. In an embodiment, the encapsulation layer 140 may include a first inorganic encapsulation layer 141 disposed on the light emitting device layer 130, an organic encapsulation layer 142 disposed on the first inorganic encapsulation layer 141, and a second inorganic encapsulation layer 143 disposed on the organic encapsulation layer 142. However, the configuration of the encapsulation layer 140 is not necessarily limited thereto.

Fig. 7 is a plan view illustrating a first auxiliary display area of the display panel of fig. 3. In an embodiment, fig. 7 is a plan view illustrating the first auxiliary display area SDA1, for example, before the encapsulation layer 140 is formed on the light emitting device layer 130. Fig. 8 is a sectional view taken along line II-II' of fig. 7.

Hereinafter, the plurality of first light emitting devices LD1 and the plurality of transmission holes TH will be described in more detail with reference to fig. 7 and 8. In this case, a description overlapping with the contents described with reference to fig. 5 and 6 regarding the configuration of the display panel 100 will be omitted.

Referring to fig. 7 and 8, a plurality of first light emitting devices LD1 may be disposed in the first auxiliary display area SDA1 of the display panel 100. In an embodiment, the plurality of first light emitting devices LD1 may include a first color light emitting device LD1-R, a second color light emitting device LD1-G, and a third color light emitting device LD1-B. In an embodiment, each of the first, second, and third color light emitting devices LD1-R, LD1-G, and LD1-B may emit red, green, or blue light. In an embodiment, for example, the first color light emitting device LD1-R may emit red light, the second color light emitting device LD1-G may emit green light, and the third color light emitting device LD1-B may emit blue light.

The first color light emitting device LD1-R may include a first color pixel electrode ADE1-R, a first color light emitting layer EL1-R, and a common electrode CTE, the second color light emitting device LD1-G may include a second color pixel electrode ADE1-G, a second color light emitting layer EL1-G, and a common electrode CTE, and the third color light emitting device LD1-B may include a third color pixel electrode ADE1-B, a third color light emitting layer EL1-B, and a common electrode CTE.

Each of the first, second, and third color light emitting devices LD1-R, LD1-G, and LD1-B may be repeatedly arranged along the row and column directions in a plan view. Specifically, each of the first, second, and third color light emitting devices LD1-R, LD1-G, and LD1-B may be repeatedly arranged along the first and second directions DR1 and DR2 in a plan view. In an embodiment, the second color light emitting devices LD1-G may be repeatedly arranged in the odd numbered rows of the first auxiliary display area SDA1, and the first color light emitting devices LD1-R and the third color light emitting devices LD1-B may be repeatedly arranged in the even numbered rows of the first auxiliary display area SDA 1.

In an embodiment, the first color light emitting device LD1-R, the second color light emitting device LD1-G, and the third color light emitting device LD1-B may have different sizes in plan view. In an embodiment, the size in plan view of the second color light emitting device LD1-G may be smaller than the size in plan view of each of the first color light emitting device LD1-R and the third color light emitting device LD 1-B. In this case, the size in plan view of the third color light emitting device LD1-B may be larger than that of the first color light emitting device LD 1-R. However, the configuration of the invention is not necessarily limited thereto, and the size in plan view of each of the first color light emitting device LD1-R, the second color light emitting device LD1-G, and the third color light emitting device LD1-B may be differently set.

Each of the first, second, and third color light emitting devices LD1-R, LD1-G, and LD1-B may have: polygonal planar shape, circular planar shape, and planar shape of elliptical planar shape; track-type planar shape; etc. In an embodiment, each of the first, second, and third color light emitting devices LD1-R, LD1-G, and LD1-B may have a quadrangular (e.g., rectangular) planar shape.

In the first auxiliary display area SDA1, a plurality of transmission holes TH may be defined in the common electrode CTE. In an embodiment, the plurality of transmission holes TH may include a plurality of first transmission holes TH1 and a plurality of second transmission holes TH2.

Each of the plurality of first and second transmission holes TH1 and TH2 may be repeatedly arranged along the row and column directions in a plan view. Specifically, each of the plurality of first and second transmission holes TH1 and TH2 may be repeatedly arranged along the first and second directions DR1 and DR2 in a plan view. In this case, each of the plurality of first and second transmission holes TH1 and TH2 may be disposed between adjacent first light emitting devices among the plurality of first light emitting devices LD 1. Accordingly, the plurality of first light emitting devices LD1 and the plurality of transmission holes TH may be alternately arranged in a plan view.

In an embodiment, the plurality of first transmission holes TH1 may be repeatedly arranged in odd numbered rows of the first auxiliary display area SDA1, and thus the first transmission holes TH1 may be alternately arranged with the second color light emitting devices LD1-G, for example, along the first direction DR 1. The plurality of second transmission holes TH2 may be repeatedly arranged in even rows of the first auxiliary display area SDA1, and thus the second transmission holes TH2 may be alternately arranged with the first and third color light emitting devices LD1-R and LD1-B along the first direction DR 1.

In other words, the plurality of transmission holes TH may be repeatedly arranged in the first and second directions DR1 and DR2 and disposed between adjacent first pixel electrodes among the plurality of first pixel electrodes ADE 1. Accordingly, the plurality of first pixel electrodes ADE1 and the plurality of transmission holes TH may be alternately arranged in a plan view.

In an embodiment, the plurality of transmission holes TH may be defined by selectively removing the laser irradiated portion of the common electrode CTE in the first auxiliary display area SDA 1. In the embodiment, for example, the laser light may be irradiated in the form of a spot for each region between the plurality of first light emitting devices LD 1. Accordingly, the plurality of transmission holes TH may be defined to be spaced apart from the pixel defining pattern PDP.

In an embodiment, as described above, the first color light emitting device LD1-R, the second color light emitting device LD1-G, and the third color light emitting device LD1-B may have different sizes. In this case, the plurality of transmission holes TH may have different shapes according to the sizes of the first light emitting devices LD1 adjacent in the first direction DR 1. In the embodiment, since the plurality of first transmission holes TH1 are adjacent to the second color light emitting devices LD1 to G in the first direction DR1, they may have, for example, a first planar shape. Since the plurality of second transmission holes TH2 are adjacent to the first and third color light emitting devices LD1-R and LD1-B in the first direction DR1, they may have a second plane shape different from the first plane shape. In fig. 7, the first planar shape is shown in a circular shape and the second planar shape is shown in an elliptical shape, but the configuration of the invention is not necessarily limited thereto.

In an embodiment, the inner surface IP of the common electrode CTE exposed by the plurality of transmission holes TH may be perpendicular to the top surface of the common electrode CTE. Accordingly, the cross section of the plurality of transmission holes TH may have a quadrangular (e.g., rectangular) shape. However, the constitution of the invention is not necessarily limited thereto. In an embodiment, the inner surface IP of the common electrode CTE may be inclined, for example, toward the upper surface of the common electrode CTE. In this case, the cross section of the plurality of transmission holes TH may have a trapezoid shape.

Fig. 9 is an enlarged view showing an enlarged region "B" of fig. 7.

Referring to fig. 7 to 9, the plurality of transmission holes TH may include a plurality of curves CV. In detail, a plurality of curves CV may be defined on at least one of the inner surfaces IP of the common electrode CTE exposed by the plurality of transmission holes TH. In an embodiment, the inner surface IP of the common electrode CTE may define a contour of the plurality of transmission holes TH, for example, in a plan view. The contours of the plurality of transmission holes TH may include curves protruding toward the outside of the plurality of transmission holes TH. In other words, the plurality of curves CV may include curves concave toward the interior of the common electrode CTE. The size of the curve may be variously realized according to the spot size and intensity of the laser light irradiated to the common electrode CTE to form the plurality of transmission holes TH.

Fig. 10 to 15 are cross-sectional views illustrating a method of manufacturing a display panel included in the display device of fig. 1. In this case, fig. 10 to 12 are cross-sectional views showing all of the first auxiliary display area SDA1, the second auxiliary display area SDA2, and the main display area MDA of the display panel 100, and fig. 13 to 15 are cross-sectional views showing only the first auxiliary display area SDA1 of the display panel 100 in more detail. Hereinafter, a method of manufacturing the display panel 100 included in the display device 1000 of fig. 1 will be described with reference to fig. 10 to 15.

Referring to fig. 10 and 11, first, a base substrate 110 including a first auxiliary display area SDA1 and a main display area MDA may be prepared. In this case, the base substrate 110 may further include a second auxiliary display area SDA2. Thereafter, the pixel circuit layer 120 may be formed on the base substrate 110. Specifically, by forming an insulating layer, a semiconductor layer, and a metal layer by coating, depositing, or the like, and then selectively patterning the insulating layer, the semiconductor layer, and the metal layer by a photolithography method, the first active pattern ACT1, the second active pattern ACT2, the third active pattern ACT3, the fourth active pattern ACT4, the first gate electrode GAT1, the second gate electrode GAT2, the third gate electrode GAT3, the fourth gate electrode GAT4, the first connection electrode CE1, the second connection electrode CE2, the third connection electrode CE3, the fourth connection electrode CE4, the fifth connection electrode CE5, the sixth connection electrode CE6, the seventh connection electrode CE7, the eighth connection electrode CE8, the ninth connection electrode CE9, the tenth connection electrode CE10, the eleventh connection electrode CE11, the first connection line TWL1, and the second connection line TWL2 may be formed. Accordingly, the first and second pixel circuits PC1 and PC2 may be formed in the second auxiliary display area SDA2, and the third pixel circuit PC3 may be formed in the main display area MDA.

In an embodiment, a back metal layer BML may be additionally formed on the base substrate 110 before the pixel circuit layer 120 is formed. The back metal layer BML may be formed in the second auxiliary display area SDA2 and the main display area MDA in a position overlapping the first, second, and third pixel circuits PC1, PC2, and PC 3.

Referring to fig. 12, a light emitting device layer 130 may be formed on the pixel circuit layer 120. Specifically, after forming the first, second, and third pixel electrodes ADE1, ADE2, and ADE3 on the ninth insulating layer 129, a pixel defining layer PDL and a pixel defining pattern PDP may be formed. In this case, the pixel defining pattern PDP may expose a portion of the first pixel electrode ADE1, and the pixel defining layer PDL may expose a portion of the second and third pixel electrodes ADE2 and ADE 3. Thereafter, the first, second, and third light emitting layers EL1, EL2, and EL3 may be formed on each of the first, second, and third pixel electrodes ADE1, ADE2, and ADE 3. Thereafter, the common electrode CTE may be formed on the first, second, and third light emitting layers EL1, EL2, and EL3. The common electrode CTE may be continuously formed across a plurality of pixels PX (refer to fig. 3).

Referring to fig. 13 and 14, after the light emitting device layer 130 is formed, a plurality of transmission holes TH may be defined by irradiating laser LS from the lower side of the base substrate 110 toward the first auxiliary display area SDA 1. In this case, the laser LS may be an infrared laser.

In the embodiment, the laser LS may be irradiated in the form of a spot for each region between the plurality of first light emitting devices LD1 among the common electrode CTE. Accordingly, a plurality of transmission holes TH may be defined between the plurality of first light emitting devices LD1 by selectively removing portions of the common electrode CTE irradiated with the laser light LS. In other words, the plurality of transmission holes TH may be defined in the first auxiliary display area SDA1 to be alternately arranged with the plurality of first light emitting devices LD 1. Accordingly, in the process of defining the plurality of transmission holes TH, damage of the plurality of first light emitting devices LD1, the pixel defining pattern PDP, and the plurality of insulating layers disposed in the first auxiliary display area SDA1 may be minimized. Accordingly, the reliability of the display panel and the display device including the same can be improved.

Referring to fig. 15, an encapsulation layer 140 may be formed on the light emitting device layer 130. In an embodiment, the encapsulation layer 140 may include a first inorganic encapsulation layer 141 disposed on the light emitting device layer 130, an organic encapsulation layer 142 disposed on the first inorganic encapsulation layer 141, and a second inorganic encapsulation layer 143 disposed on the organic encapsulation layer 142.

Fig. 16 is a cross-sectional view showing an embodiment of a display panel.

Referring to fig. 16, the display panel 100-1 in another embodiment disclosed may be substantially the same as the display panel 100 described with reference to fig. 2 to 15, except that a light blocking pattern BLB is further included.

In an embodiment, as shown in fig. 16, the light blocking pattern BLB may be disposed in the first auxiliary display area SDA1 of the display panel 100-1. In an embodiment, the light blocking pattern BLB may be disposed on the base substrate 110. However, the layer on which the light blocking pattern BLB is disposed is not necessarily limited thereto, and the light blocking pattern BLB may be disposed on any one of the plurality of layers between the base substrate 110 and the light emitting device layer 130. In an embodiment, the light blocking pattern BLB may be disposed on the buffer layer 120BR, for example. In addition, the light blocking pattern BLB may be disposed on any one of the first, second, third, fourth, fifth, and sixth insulating layers 121, 122, 123, 124, 125, and 126. In an embodiment, the light blocking pattern BLB may be formed through the same process as that of the back metal layer BML.

The light blocking pattern BLB may overlap the first light emitting device LD1 in a plan view. In addition, the light blocking pattern BLB may be spaced apart from the plurality of transmission holes TH in a plan view. In an embodiment, in a cross section, a width W1 of the light blocking pattern BLB in the first direction DR1 may be greater than a width W2 of the first pixel electrode ADE1 included in the first light emitting device LD1 in the first direction DR 1. Accordingly, the light blocking pattern BLB may cover the entire lower surface of the first pixel electrode ADE 1. In this case, the width W1 of the light blocking pattern BLB in the first direction DR1 may be narrower than the interval W3 between opposite ends of the pixel defining pattern PDP exposing the first pixel electrode ADE 1.

In an embodiment, the light blocking pattern BLB may include a metal material that absorbs or reflects laser light. In this case, the laser light may be an infrared laser light. In an embodiment, the light blocking pattern BLB may, for example, include the same material as that of the back metal layer BML. In an embodiment, a material that may be used as the light blocking pattern BLB may include molybdenum (Mo), titanium (Ti), aluminum (AL), silver (Ag), copper (Gu), and the like. These may be used alone or in combination with each other. Accordingly, in the process for defining the plurality of transmission holes TH, the light blocking pattern BLB may further minimize damage of the plurality of first light emitting devices LD1, the pixel defining pattern PDP, and the plurality of insulating layers caused by the laser. Accordingly, the reliability of the display panel and the display device including the display panel can be further improved.

In an embodiment, the thickness of the light blocking pattern BLB may be about 50 nanometers (nm) to about 500nm. When the thickness of the light blocking pattern BLB satisfies the above-described range, damage of the plurality of first light emitting devices LD1, the pixel defining pattern PDP, and the plurality of insulating layers caused by the laser light may be further minimized while preventing an excessive increase in the thickness of the display panel 100-1.

Fig. 17 is a cross-sectional view showing an embodiment of a display panel.

Referring to fig. 17, the display panel 100-2 in another embodiment disclosed may be substantially the same as the display panel 100-1 described with reference to fig. 16 except for a width W1 of the light blocking pattern BLB in the first direction DR 1.

In an embodiment, the width W1 of the light blocking pattern BLB in the first direction DR1 may be greater than the interval W3 between opposite ends of the pixel defining pattern PDP exposing the first pixel electrode ADE 1. Accordingly, in the process for defining the plurality of transmission holes TH, the light blocking pattern BLB may further minimize damage of the pixel defining pattern PDP caused by the laser. However, even in this case, the light blocking pattern BLB may be spaced apart from the plurality of transmission holes TH in a plan view.

In an embodiment, the display apparatus may include a plurality of first light emitting devices LD1. The plurality of first light emitting devices LD1 may be disposed in the first auxiliary display area SDA 1. In this case, the plurality of transmission holes TH may be defined in the common electrode CTE disposed in the first auxiliary display area SDA 1. In the first auxiliary display area SDA1, a plurality of first light emitting devices LD1 and a plurality of transmission holes TH may be alternately arranged. Accordingly, the transmittance of the first auxiliary display area SDA1 may be improved.

Further, the plurality of transmission holes TH may be defined by selectively removing the laser-irradiated portions of the common electrode. The laser light may be irradiated in the form of a spot for each region between the plurality of first light emitting devices LD 1. Accordingly, in the process of defining the plurality of transmission holes TH, damage of the plurality of first light emitting devices LD1, the pixel defining pattern PDP, and the plurality of insulating layers disposed in the first auxiliary display area SDA1 may be minimized. Therefore, the reliability of the display device can be further improved.

The disclosure should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art.

While the invention has been particularly shown and described with reference to an embodiment thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit or scope of the invention as defined by the following claims.

Claims

1. A display device, the display device comprising:

a base substrate including a first auxiliary display area and a main display area surrounding the first auxiliary display area;

A pixel circuit layer disposed on the base substrate; and

a light emitting device layer disposed on the pixel circuit layer and including a plurality of first light emitting devices disposed in the first auxiliary display region, each of the plurality of first light emitting devices including: a pixel electrode; a light emitting layer disposed on the pixel electrode; and a common electrode disposed on the light emitting layer and defining a plurality of transmission holes defined in the first auxiliary display region,

wherein the plurality of first light emitting devices and the plurality of transmission holes are alternately arranged in a plan view.

2. The display device according to claim 1, wherein the light emitting device layer further comprises a pixel defining pattern exposing a portion of the pixel electrode, and

wherein the plurality of transmission holes are spaced apart from the pixel defining pattern in a plan view.

3. The display device according to claim 2, wherein the plurality of transmission holes are repeatedly arranged in a row direction and a column direction in a plan view.

4. The display device according to claim 3, wherein the plurality of transmission holes include:

a plurality of first transmission holes having a first planar shape; and

And a plurality of second transmission holes having a second planar shape different from the first planar shape.

5. The display device according to claim 4, wherein the plurality of first transmission holes are repeatedly arranged in an odd-numbered row of the first auxiliary display area in a plan view, and the plurality of second transmission holes are repeatedly arranged in an even-numbered row of the first auxiliary display area in a plan view.

6. The display device of claim 1, wherein the base substrate further comprises a second auxiliary display region adjacent to the first auxiliary display region,

wherein the light emitting device layer further comprises a plurality of second light emitting devices disposed in the second auxiliary display region, and

wherein the pixel circuit layer includes: a first pixel circuit disposed in the second auxiliary display region and controlling a current transmitted to at least one of the plurality of first light emitting devices; and a second pixel circuit disposed in the second auxiliary display region and controlling a current transmitted to at least one of the plurality of second light emitting devices.

7. The display apparatus of claim 6, wherein the pixel circuit layer further comprises a connection line electrically connecting at least one of the plurality of first light emitting devices with the first pixel circuit.

8. The display device according to claim 1, further comprising:

a light blocking pattern disposed between the base substrate and the light emitting device layer, and

wherein the light blocking pattern overlaps the plurality of first light emitting devices in a plan view.

9. The display apparatus according to claim 8, wherein the light blocking pattern covers an entire lower surface of the pixel electrode included in each of the plurality of first light emitting devices.

10. The display device of claim 9, wherein the light blocking pattern is spaced apart from the plurality of transmissive holes in a plan view.

11. The display device of claim 8, wherein the light blocking pattern comprises a metallic material, and

wherein the metallic material absorbs or reflects the incident infrared laser light.

12. A method of manufacturing a display device, the method comprising the steps of:

preparing a base substrate including a first auxiliary display area and a main display area surrounding the first auxiliary display area;

forming a pixel circuit layer on the base substrate;

forming a plurality of first light emitting devices on the pixel circuit layer, the plurality of first light emitting devices being disposed in the first auxiliary display region; and

Irradiating laser light from the lower side of the base substrate to the first auxiliary display area,

wherein each of the plurality of first light emitting devices includes: a pixel electrode; a light emitting layer disposed on the pixel electrode; and a common electrode disposed on the light emitting layer and

wherein, in the step of irradiating the laser light, a plurality of transmission holes are defined in the common electrode to be alternately arranged with the plurality of first light emitting devices in a plan view.

13. The method of claim 12, wherein the step of irradiating the laser light defines the plurality of transmission holes by irradiating the laser light in a spot shape.

14. The method of claim 12, the method further comprising:

forming a light blocking pattern on the base substrate,

wherein the light blocking pattern overlaps the plurality of first light emitting devices.