CN117135900A - integrated circuit - Google Patents

Abstract

An integrated circuit is disclosed. The integrated circuit includes a Static Random Access Memory (SRAM) device. The SRAM device includes an SRAM cell including a first output node and a second output node, the first pull-up transistor, the first pull-down transistor, and the second pull-down transistor being commonly connected to the first output node, the second pull-up transistor, the third pull-down transistor, and the fourth pull-down transistor being commonly connected to the second output node. The first output node is connected to the first gate electrode, the second gate electrode, the first connection wiring, the first node forming pattern, and the first active contact, and a layout of the first output node, the first gate electrode, the second gate electrode, the first connection wiring, the first node forming pattern, and the first active contact forms a first bifurcated shape.

Description

Integrated circuit

The present application claims priority from korean patent application No. 10-2022-0065338, which was filed on day 27 of 5 in 2022, and korean patent application No. 10-2022-0105592, which was filed on day 23 of 8 in 2022, each of which is incorporated herein by reference in its entirety.

Technical Field

The present disclosure relates to integrated circuits including static random access memory devices.

Background

The related art semiconductor devices have achieved significant growth and continued development worldwide due to active demands of semiconductor users and continuous efforts of semiconductor manufacturers. Further, semiconductor manufacturers are not satisfied with this, and strive to achieve further miniaturization, high integration, and large capacity of semiconductor devices, and also accelerate research and development to perform stable and smooth operations at higher speeds. Such efforts by semiconductor manufacturers have brought advances in micro-processing technology, micro-device technology, and circuit design technology, which have shown significant achievements in the technology of semiconductor memory cells such as Dynamic Random Access Memory (DRAM) or Static Random Access Memory (SRAM).

In particular, in the SRAM field, a dual port SRAM capable of performing high-speed read and write operations has been developed, as compared with a conventional single port SRAM.

Disclosure of Invention

One aspect provides an integrated circuit capable of improving device performance and reliability while reducing area.

Another aspect provides an integrated circuit with reduced area occupied by the cascode connection of pull-down transistors.

According to one aspect of one or more embodiments, an integrated circuit is provided, the integrated circuit comprising a Static Random Access Memory (SRAM) device, wherein the SRAM device comprises an SRAM cell, the SRAM cell comprising a first output node and a second output node, a first pull-up transistor, a first pull-down transistor, and a second pull-down transistor are commonly connected to the first output node, a second pull-up transistor, a third pull-down transistor, and a fourth pull-down transistor are commonly connected to the second output node, wherein the first output node is connected to a first gate electrode, a second gate electrode, a first connection wire, a first node forming pattern, and a first active contact, and wherein a first layout of the first output node, the first gate electrode, the second gate electrode, the first connection wire, the first node forming pattern, and the first active contact forms a first bifurcation shape.

According to another aspect of one or more embodiments, there is provided an integrated circuit comprising a plurality of SRAM cell units, each SRAM cell unit comprising: a plurality of fully-around gate transistors; a plurality of active patterns sequentially arranged at intervals in a first direction and extending in a second direction; a first gate electrode extending on the plurality of active patterns along a first direction of a first axis; a second gate electrode extending in a first direction of a second axis on the plurality of active patterns; a first connection wiring extending in the second direction and intersecting the first gate electrode and the second gate electrode on the first gate electrode and the second gate electrode; the first node forms a pattern extending along the second gate electrode and having a first length in the second direction; and a first active contact extending in a first direction of the third axis and crossing the first node forming pattern, wherein the first input/output node of the SRAM cell is connected to the first gate electrode, the second gate electrode, the first connection wiring, the first node forming pattern, and the first active contact, and wherein the first input/output node, the first gate electrode, the second gate electrode, the first connection wiring, the first node forming pattern, and the first layout of the first active contact form a first bifurcation shape.

According to another aspect of one or more embodiments, there is provided an integrated circuit comprising: a first power supply wiring extending in a first direction; a first gate electrode extending in a second direction of the first axis below the first power supply wiring; a second gate electrode extending in a second direction of the first axis below the first power supply wiring and spaced apart from the first gate electrode; a first active contact extending in a second direction of the second shaft under the first power supply wiring; a second active contact extending in a second direction of the second axis and disposed symmetrically to the first active contact with respect to the first power supply wiring; a third gate electrode extending in a second direction of a third axis under the first power supply wiring; a fourth gate electrode under the first power supply wiring and spaced apart from the third gate electrode, the fourth gate electrode extending in a second direction of the third axis; a first connection wiring extending in a first direction and electrically connected to the first gate electrode and the second gate electrode; a second connection wiring extending in the first direction and electrically connected to the third gate electrode and the fourth gate electrode; the first node forms a pattern, extends along a first direction and is configured to electrically connect the second gate electrode and the first active contact; and a second node forming pattern extending along the first direction and configured to electrically connect the third gate electrode and the second active contact, wherein a first layout shape in which the first gate electrode, the first connection wiring, the second gate electrode, the first node forming pattern and the first active contact are connected is point-symmetrical to a second layout shape in which the fourth gate electrode, the second connection wiring, the third gate electrode, the second node forming pattern and the second active contact are connected.

Drawings

The above and other aspects will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings, in which:

FIG. 1 is a block diagram of a semiconductor device including a Static Random Access Memory (SRAM) device, according to some embodiments;

FIG. 2 is a plan view of a semiconductor device including a Static Random Access Memory (SRAM) device configured in accordance with some embodiments;

FIG. 3 is a circuit diagram illustrating an SRAM unit cell of the semiconductor device of FIG. 2, in accordance with some embodiments;

fig. 4 illustrates an example of a layout including various layout patterns formed on active contacts, in accordance with some embodiments;

FIG. 5 illustrates a layout showing front metal lines formed on the layout of FIG. 4, in accordance with some embodiments;

FIG. 6 is a cross-sectional view taken along line A-A' of FIG. 4;

FIG. 7 is a layout diagram of an SRAM unit cell in accordance with some embodiments;

FIG. 8 is a layout diagram of an SRAM unit cell in accordance with some embodiments; and

fig. 9 and 10 are layout diagrams of SRAM cell according to some embodiments.

Detailed Description

In this specification, one side or direction and the other side or direction are used as relative concepts for ease of understanding. Thus, "one side" and "another side" do not denote a particular direction, position, or component, and are interchangeable with one another. For example, "one side" may be interpreted as "another side", and "another side" may be interpreted as "one side". Thus, "one side" and "another side" may be denoted as "first" and "second", respectively, and "another side" and "one side" may be denoted as "first" and "second", respectively. However, in one embodiment, "one side" and "another side" are not used interchangeably. In this specification, two sides mean both one side and the other side.

In this specification, for ease of understanding, the first direction, the second direction, and the third direction, or the D1 direction, the D2 direction, and the D3 direction are used as relative concepts. Thus, the first, second and third directions or the D1, D2 and D3 directions do not represent specific directions and are interchangeable with each other. In the following embodiments, the first direction will be denoted as D2 direction and the second direction will be denoted as D1 direction, but the D1 direction may be denoted as the first direction and the D2 direction may be denoted as the second direction. However, in one embodiment, the first direction and the second direction are not used interchangeably.

In this specification, the term "disposed/arranged" is used as a term similar to, for example, "disposed/placed", "set/disposed".

In a typical single-port SRAM, one unit memory cell includes six transistors (i.e., two load transistors, two drive transistors, and two active transistors) so that read and write operations can be sequentially performed. In contrast, dual port SRAM is configured to perform read and write operations in dual mode (dual mode) by adding two active transistors to a typical single port SRAM, and is thus used in integrated circuits requiring high speed.

Fig. 1 is a block diagram of a semiconductor device including a Static Random Access Memory (SRAM) device, according to some embodiments.

Referring to fig. 1, a semiconductor device 10 may include a memory cell array 11, an input/output (I/O) block 13, a row driver 14, and a control block 15. In some embodiments, semiconductor device 10 may be a memory device. The semiconductor device 10 may receive a command CMD, an address ADDR, a clock CLK, write DATA data_in, and may output read DATA data_out. For example, the semiconductor device 10 may receive a command CMD (may be referred to as a "write command"), an address (may be referred to as a "write address"), and write DATA data_in, which are indicative of a write operation, and the write DATA data_in may be stored IN an area of the memory cell array 11 corresponding to the address. Further, the semiconductor device 10 may receive a command CMD (may be referred to as a "read command") and an address (may be referred to as a "read address") indicating a read operation, and may output the read DATA data_out stored in an area of the memory cell array 11 corresponding to the address to the outside.

The memory cell array 11 may include a plurality of bit cells 12. Each of the bit cells 12 may be connected to one of a plurality of word lines WL and may be connected to at least one of a plurality of bit lines BL.

The row driver 14 may be connected to the memory cell array 11 through a plurality of word lines WL. The ROW driver 14 may activate one of the plurality of word lines WL based on the ROW address ROW. Thus, among the plurality of memory cells, a memory cell connected to an activated word line may be selected. That is, the row driver 14 may select any one of the plurality of word lines WL.

The control block 15 may receive a command CMD, an address ADDR, and a clock CLK, and may generate a ROW address ROW, a column address COL, and a control signal CTR. For example, the control block 15 may recognize a read command by decoding the command CMD, and may generate a ROW address ROW, a column address COL, and a read signal as a control signal CTR to read the read DATA data_out from the memory cell array 11. Further, the control block 15 may recognize a write command by decoding the command CMD, and may generate a ROW address ROW, a column address COL, and a write signal as a control signal CTR to write DATA data_in into the memory cell array 11.

According to some embodiments, the input/output (I/O) block 13 may include bit line precharge circuitry, column drivers, read circuitry, and write circuitry.

According to some embodiments, the semiconductor device 10 may also include another device/circuit module integrated with the SRAM device (e.g., a logic device, a high frequency device, an image sensing device, a Dynamic Random Access Memory (DRAM) device, or a combination thereof).

Fig. 2 is a plan view of a semiconductor device including a Static Random Access Memory (SRAM) device configured in accordance with some embodiments.

Referring to fig. 2, a semiconductor device 10 (e.g., the semiconductor device of fig. 1) according to some embodiments includes a Static Random Access Memory (SRAM) circuit having a bit cell array 12 (also referred to as SRAM array 12) of a plurality of SRAM cell (or SRAM bit cells) 100 configured in an array, and the SRAM cell extending in a plurality of columns along a plurality of rows. That is, the SRAM cell units are arranged in an array of rows and columns.

The semiconductor device 10 may also include another device/circuit module integrated with the SRAM device (e.g., a logic device, a high frequency device, an image sensing device, a Dynamic Random Access Memory (DRAM) device, or a combination thereof).

In some embodiments, each column of SRAM cell 100 in the bit cell array 12 may extend in a first direction X and each row may extend in a second direction Y. For example, each column may include N1 SRAM cell units 100 arranged in a row (column) along a first direction X, and each row may include N2 SRAM cell units 100 arranged in a row (row) along a second direction Y. That is, the bit cell array 12 may include SRAM cell units 100 arranged in N1 rows and N2 columns (n1×n2). In the bit cell array 12 of some embodiments, each column may include 8, 16, 32, 64, or 128 SRAM cell units 100, and each row may include 4, 8, 16, or 32 SRAM cell units 100. In the embodiment shown in fig. 2, the bit cell array 12 includes 4 columns and 8 rows.

The semiconductor device 10 may include corner dummy cells 16 disposed at four corners of the bit cell array 12, and edge strips, such as a word line edge strip (WL edge strip) 18 disposed on a row edge of the bit cell array 12 and a bit line edge strip (BL edge strip) 22 disposed on a column edge of the bit cell array 12. Each WL edge strip 18 may include a plurality of WL edge cells 20 arranged in a row along a first direction X and each BL edge strip 22 may include a plurality of BL edge cells 24 arranged in a row along a second direction Y. These edge strips 18 and 22 may be circuit areas that are not designed to function as SRAM cell 100, but are designed to provide other functions.

Fig. 3 is a circuit diagram illustrating an SRAM cell of the semiconductor device of fig. 2.

Referring to fig. 3, an SRAM cell 100 of a semiconductor device according to some embodiments includes pull-up transistors PU1 and PU2, pull-down transistors PD1, PD2, PD3, and PD4, and pass gate transistors PG1, PG2, PG3, and PG4. In some embodiments, the plurality of transistors included in the SRAM cell 100 may be fully-around gate transistors.

The source, drain, and gate of the pull-down transistor PD1 are connected to the source, drain, and gate of the pull-down transistor PD 2. That is, the sources of the pull-down transistors PD1 and PD2 are commonly connected to the ground voltage node VSS, the drains of the pull-down transistors PD1 and PD2 are commonly connected to the node N1, and the gates of the pull-down transistors PD1 and PD2 are commonly connected to the node N2.

The source, drain, and gate of the pull-down transistor PD3 are connected to the source, drain, and gate of the pull-down transistor PD 4. That is, the sources of the pull-down transistors PD3 and PD4 are commonly connected to the ground voltage node VSS, the drains of the pull-down transistors PD3 and PD4 are commonly connected to the node N2, and the gates of the pull-down transistors PD3 and PD4 are commonly connected to the node N1.

Accordingly, the pull-down transistors PD1 and PD2 and the pull-down transistors PD3 and PD4 operate as a single pull-down transistor.

Pass gate transistors PG1 and PG4 are formed as a first port A of SRAM cell 100. Pass gate transistors PG2 and PG3 are formed as a second port B of SRAM cell 100. The word line a signal wl_a is applied to the gates of pass gate transistors PG1 and PG4, and the word line B signal wl_b is applied to the gates of pass gate transistors PG2 and PG 3. The pull-up transistor PU1 and the pull-down transistors PD1 and PD2 form a first inverter INV1, the pull-up transistor PU2 and the pull-down transistors PD3 and PD4 form a second inverter INV2, an output node N2 of the second inverter INV2 is connected to an input of the inverter INV1, and an output node N1 of the first inverter is connected to an input of the second inverter INV2, thereby forming a latch. The SRAM cell 100 stores bits in latches formed by pull-up transistors PU1 and PU2 and pull-down transistors PD1 and PD 2. The bits stored in the latches may be read through bit line port BL_A and complementary bit line port BLB_A, or may be read through bit line port BL_B and complementary bit line port BLB_B. In addition, bits may be written into latches through bit line port BL_A and complementary bit line port BLB_A, or may be written into latches through bit line port BL_B and complementary bit line port BLB_B.

In dual ports, bits stored in the SRAM cell 100 may be read simultaneously through port a or port B. A dual port SRAM cell comprising port a and port B may perform parallel operations. For example, when a read operation is performed in a first SRAM cell, a write operation may be performed simultaneously in a second SRAM cell that belongs to the same column or row as the first SRAM cell.

Fig. 4 and 5 are layout diagrams of SRAM cell according to some embodiments. Specifically, fig. 4 illustrates various layout patterns formed on active contacts, and fig. 5 illustrates a layout showing front metal lines formed on the layout of fig. 4, in accordance with some embodiments. Fig. 6 is a cross-sectional view taken along line A-A' of fig. 4.

In some embodiments, each row of SRAM cell 100 in the SRAM array 12 may extend in the D1 direction, and each column of SRAM cell 100 may extend in the D2 direction. For example, each row may include N1 SRAM cell cells 100 arranged in a row (column) along the D1 direction, and each column may include N2 SRAM cell cells 100 arranged in a row (row) along the D2 direction. That is, the SRAM array 12 may include a plurality of SRAM cell units 100 arranged in N1 rows and N2 columns.

SRAM cell 100 according to some embodiments may include active patterns AP1, AP2, AP3, AP4, AP5, and AP6; active contacts CA1, CA2, CA3, CA4, CA5, CA6, CA7, CA8, CA9, CA10, CA11, and CA12; gate electrodes PC1, PC2, PC3, PC4, PC5, PC6, PC7, and PC8; active vias VA1, VA2, VA3, VA4, VA5, VA6, VA7, VA8, VA9, and VA10; gate vias CB1, CB3, CB4, CB6, CBWLA, CBWLB, CBWTA and CBWTB; the nodes form patterns CB2 and CB5; and metal wirings m1_wla, m1_wlb, m1_blb, m1_bla, m1_vdd, m1_vss, m1_btb, and m1_bta formed on the substrate.

In some embodiments, the substrate may be a silicon substrate or a silicon-on-insulator (SOI) substrate. In some embodiments, the substrate may include silicon germanium, silicon Germanium On Insulator (SGOI), indium antimonide, lead tellurium compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide, but the embodiments are not limited thereto.

The active patterns AP1, AP2, AP3, AP4, AP5, and AP6 may be disposed in the SRAM unit cell 100. The active patterns AP3 and AP4 may be disposed in a P-channel metal oxide semiconductor (PMOS) region of the SRAM cell 100, and the active patterns AP1, AP2, AP5, and AP6 may be disposed in an N-channel metal oxide semiconductor (NMOS) region of the SRAM cell 100.

The active patterns AP1, AP2, AP3, AP4, AP5, and AP6 may be elongated in the D1 direction. In other words, the active patterns AP1, AP2, AP3, AP4, AP5, and AP6 may extend in the D1 direction. The active patterns AP1, AP2, AP3, AP4, AP5, and AP6 may be disposed to be spaced apart from each other in the D2 direction. For example, the active pattern AP3 may be disposed between the active patterns AP2 and AP4 spaced apart from each other in the D2 direction. The active pattern AP4 may be disposed between the active patterns AP3 and AP5 spaced apart from each other in the D2 direction. The portions of the active patterns AP3 and AP4 extending in the D1 direction may partially overlap in the D2 direction. That is, the active patterns AP3 and AP4 may be placed in a zigzag (zigzag) pattern in the D1 direction such that the ends of the active patterns AP3 and AP4 are staggered in the D1 direction, as shown in fig. 4, the bottom end of the active pattern AP4 is higher than the bottom end of the active pattern AP 3.

The width (width in the D2 direction) of each of the active patterns AP1, AP2, AP5, and AP6 may be greater than the width of each of the active patterns AP3 and AP 4. That is, the widths of the active patterns AP3 and AP4 in which the pull-up transistors PU1 and PU2 are formed may be narrower than the widths of the active patterns AP1, AP2, AP5, and AP6 in which the other transistors (i.e., the pull-down transistor and the transfer gate transistor) are formed. Further, in the SRAM unit cell 100, the lengths of the active patterns AP3 and AP4 in the D1 direction may be shorter than the lengths of the active patterns AP1, AP2, AP5, and AP6 in the D1 direction. In one embodiment, pull-up transistors PU1 and PU2 may be disposed in an N-well (NW).

The active patterns AP1, AP2, AP3, AP4, AP5, and AP6 may be multi-channel active patterns. For example, the multi-channel active pattern may include a lower pattern and a plurality of sheet patterns. According to some embodiments, the lower pattern may be formed by etching a portion of the substrate, and may include an epitaxial layer grown from the substrate. The lower pattern may include silicon or germanium, each of which is an elemental semiconductor material. In some embodiments, the lower patterns BP1, BP2, BP3 and BP4 may include a compound semiconductor, for example, a group IV-IV compound semiconductor or a group III-V compound semiconductor.

The group IV-IV compound semiconductor may be a binary compound or a ternary compound including at least two elements selected from the group consisting of carbon (C), silicon (Si), germanium (Ge), and tin (Sn), or the above-described compound doped with a group IV element.

The group III-V compound semiconductor may be, for example, a binary compound, a ternary compound, or a quaternary compound formed by combining at least one of aluminum (Al), gallium (Ga), and indium (In) As group III elements with one of phosphorus (P), arsenic (As), and antimony (Sb) As group V elements.

The sheet-like pattern may include one of silicon or germanium, each of which is an elemental semiconductor material, a group IV-IV compound semiconductor, or a group III-V compound semiconductor. Each of the sheet patterns may include the same material as the material of the lower pattern, or may include a different material from the material of the lower pattern.

In the semiconductor device according to some embodiments, each lower pattern may be a silicon lower pattern including silicon, and each sheet pattern may be a silicon sheet-like pattern including silicon.

The active contacts CA1 to CA12 and the plurality of gate electrodes PC1 to PC8 may extend in the D2 direction and may be disposed to be spaced apart from each other in the D2 direction. For example, the active contact CA1, the active contact CA2, the active contact CA3, the active contact CA4, and the active contact CA5 may be disposed on the same axis (e.g., first axis) in the D2 direction, and may be disposed to be spaced apart from each other in the D2 direction. The gate electrode PC1, the gate electrode PC2, the gate electrode PC3, and the gate electrode PC4 may be disposed on the same axis (e.g., second axis) in the D2 direction, and may be disposed to be spaced apart from each other in the D2 direction. The active contact CA6 and the active contact CA7 may be disposed on the same axis (e.g., a third axis) in the D2 direction, and may be disposed to be spaced apart from each other in the D2 direction. The gate electrode PC5, the gate electrode PC6, the gate electrode PC7, and the gate electrode PC8 may be disposed on the same axis (e.g., fourth axis) in the D2 direction, and may be disposed to be spaced apart from each other in the D2 direction. The active contacts CA8, CA9, CA10, CA11, and CA12 may be disposed on the same axis (e.g., fifth axis) in the D2 direction, and may be disposed to be spaced apart from each other in the D2 direction. The first to fifth axes in the D2 direction extend in parallel while being spaced apart from each other in the D1 direction and do not intersect each other.

The active vias VA1 to VA10 may be formed on the active contacts CA1 to CA 12. The active contacts CA1 to CA12 and the active vias VA1 to VA10 may be electrically connected. The active contacts CA1 to CA12 and the active vias VA1 to VA10 may transmit voltages provided to define source or drain regions of the transistors to the source/drain regions of the transistors.

Gate vias CBWLA, CBWLB, CB, CB3, CB4, and CB6 or node formation patterns CB2 and CB5 may be formed on the gate electrodes PC1 to PC8. The gate electrodes PC1 to PC8 and the gate vias CBWLA, CBWLB, CB1, CB3, CB4, and CB6 may be electrically connected. The gate vias CBWLA, CBWLB, CB, CB3, CB4, and CB6 may transfer gate voltages provided to the gates of the transistors to the gate electrodes PC1 to PC8. The node formation pattern CB2 may extend in the D1 direction to connect the gate electrode PC3 and the active contact CA6. The node formation pattern CB5 may extend in the D1 direction to connect the gate electrode PC6 and the active contact CA7. The node N2 (see fig. 3) may be formed in the SRAM cell 100 due to the node formation pattern CB2, and the node N1 (see fig. 3) may be formed in the SRAM cell 100 due to the node formation pattern CB 5.

The node forming pattern may include the same material as that of the gate vias CBWLA, CBWLB, CB1, CB3, CB4 and CB 6. For example, referring to fig. 6 showing a cross section of the node formation pattern CB5 taken along the line A-A', an N-type well region (hereinafter, referred to as "well region STI") extending in the D2 direction is formed on the substrate SUB through a shallow trench isolation process, and an active contact CA7 for electrically connecting the well region STI is formed to extend in the D2 direction. A gate electrode PC6 is formed on the substrate to extend in the D2 direction while being spaced apart from the active contact CA7 in the D1 direction, and a node formation pattern CB5 extending in the D1 direction is formed between the active contact CA7 and the gate electrode PC 6. The active contact CA7 is electrically connected to the gate electrode PC6 through the node formation pattern CB5 to form a node N1.

Although not shown, similar to the node formation pattern CB5, a node formation pattern CB2 is formed on the active contact CA6 and the gate electrode PC3 to extend in the D1 direction.

The gate electrodes PC1 to PC8 may include a conductive material. For example, each of the gate electrodes PC1 to PC8 may include, for example, at least one of a metal, a metal alloy, a conductive metal nitride, a conductive metal carbonitride, a metal silicide, a doped semiconductor material, a conductive metal oxide, and a conductive metal oxynitride.

Each of the gate electrodes PC1 and PC5 may intersect the active pattern AP 1. The gate electrode PC2 may intersect the active pattern AP 2. The gate electrode PC6 may intersect each of the active patterns AP2 and AP 3. The gate electrode PC3 may intersect each of the active patterns AP4 and AP 5. The gate electrode PC7 may intersect the active pattern AP 5. Each of the gate electrodes PC4 and PC8 may intersect the active pattern AP 6.

Each of the gate electrodes PC1 to PC8 may intersect a lower pattern included in each active pattern, and may surround a sheet-like pattern of each active pattern.

The pull-up transistor PU1 is defined in a region where the gate electrode PC3 and the active pattern AP4 intersect, and the pull-up transistor PU2 is defined in a region where the gate electrode PC6 and the active pattern AP3 intersect. The pull-down transistor PD1 is defined in a region where the gate electrode PC3 and the active pattern AP5 intersect, and the pull-down transistor PD2 is defined in a region where the gate electrode PC7 and the active pattern AP5 intersect. The pull-down transistor PD3 is defined in a region where the gate electrode PC6 and the active pattern AP2 intersect, and the pull-down transistor PD4 is defined in a region where the gate electrode PC2 and the active pattern AP2 intersect. The pass gate transistor PG1 is defined in a region where the gate electrode PC4 and the active pattern AP6 intersect, and the pass gate transistor PG2 is defined in a region where the gate electrode PC8 and the active pattern AP6 intersect. The pass gate transistor PG4 is defined in a region where the gate electrode PC1 and the active pattern AP1 intersect, and the pass gate transistor PG3 is defined in a region where the gate electrode PC5 and the active pattern AP1 intersect.

The pull-up transistor PU1 and the pull-down transistor PD1 may include a gate electrode PC3. That is, the first inverter INV1 including the pull-up transistor PU1 and the pull-down transistor PD1 may include the gate electrode PC3. The connection wiring M11 is provided to extend in the D1 direction. The gate electrode PC3 of the pull-down transistor PD1 may be electrically connected to the connection wiring M11 through the gate via CB3, and the gate electrode PC7 of the pull-down transistor PD2 may be electrically connected to the connection wiring M11 through the gate via CB 6. The active contact CA6 may be drain regions of the pull-down transistors PD3 and PD4, and may be sources or drains of the pass gate transistors PG4 and PG 3. The active contacts CA2 and CA9, which are source regions of the pull-down transistors PD3 and PD4, may be electrically connected to the metal wirings m1_blb, m1_bla, m1_vss, m1_vdd, m1_btb, and m1_bta through the active vias VA2 and VA7, respectively.

As shown in the circuit of fig. 3, the pull-down transistor PD3 and the pull-down transistor PD4 may be connected in parallel by: the gate electrodes PC2 and PC6 are connected to the same node as the active contact CA7 via the connection wiring M12, the active contacts CA2 and CA9 serving as the source region are electrically connected to the same node, and the active contact CA6 serving as the drain region is electrically connected to the same node. As in the circuit of fig. 3, the pull-down transistor PD1 and the pull-down transistor PD2 may be connected in parallel by: the gate electrodes PC3 and PC7 are connected to the same node as the active contact CA6 via the connection wiring M11, the active contacts CA4 and CA11 serving as the source region are electrically connected to the same node, and the active contact CA7 serving as the drain region is electrically connected to the same node.

The pull-up transistor PU2 and the pull-down transistor PD3 may include a gate electrode PC6. That is, the second inverter INV2 including the pull-up transistor PU2 and the pull-down transistor PD3 may include the gate electrode PC6. The connection wiring M12 is provided to extend in the D1 direction. The gate electrode PC6 of the pull-down transistor PD3 may be electrically connected to the connection wiring M12 through the gate via CB4, and the gate electrode PC2 of the pull-down transistor PD4 may be electrically connected to the connection wiring M12 through the gate via CB 1.

The metal wirings m1_blb, m1_bla, m1_vss, m1_vdd, m1_vss, m1_btb, and m1_bta may be disposed to extend in the D1 direction, and may intersect the gate electrode and the active contact extending in the D2 direction. The metal wirings m1_blb, m1_bla, m1_vss, m1_vdd, m1_vss, m1_btb, and m1_bta may be disposed to extend in the D1 direction while being spaced apart from each other at regular intervals in the D2 direction.

The complementary bit line signal blb_b (see fig. 3) is supplied to the metal wiring m1_blb, the bit line signal bl_a is supplied to the metal wiring m1_bla, the ground voltage VSS is supplied to the metal wiring m1_vss, the power supply voltage VDD is supplied to the metal wiring m1_vdd, the complementary bit line signal blb_b is supplied to the metal wiring m1_btb, and the bit line signal bl_a is supplied to the metal wiring m1_bta.

According to some embodiments, the SRAM cell 100 may also include dummy wirings m1_s1, m1_s2, m1_s3, and m1_s4. The dummy wirings m1_s1, m1_s2, m1_s3, and m1_s4 may be formed through a process different from that of forming the metal wirings m1_blb, m1_bla, m1_vss, m1_vdd, m1_vss, m1_btb, and m1_bta. For example, the metal wirings m1_blb, m1_bla, m1_vss, m1_vdd, m1_vss, m1_btb, and m1_bta may be formed first, and then the dummy wirings m1_s1, m1_s2, m1_s3, and m1_s4 may be formed. The width (width in the D2 direction) of each of the dummy wirings m1_s1, m1_s2, m1_s3, and m1_s4 may be smaller than the width of each of the metal wirings m1_blb, m1_bla, m1_vss, m1_vdd, m1_vss, m1_btb, and m1_bta.

The dummy wirings m1_s1, m1_s2, m1_s3, and m1_s4 may be disposed between metal wirings (e.g., dummy wirings between adjacent metal wirings) to make coupling capacitances generated in the metal wirings uniform. The dummy wirings m1_s1, m1_s2, m1_s3, and m1_s4 may be alternately arranged with the metal wirings in the D2 direction while being spaced apart from the metal wirings at intervals which may be predetermined intervals in some embodiments. That is, as shown in fig. 5, the dummy wirings m1_s1, m1_s2, m1_s3, and m1_s4 may be arranged in the order of the metal wiring m1_blb-dummy wiring m1_s1-metal wiring m1_bla-dummy wiring m1_s2-metal wiring m1_vss in the D2 direction.

Voltages may be applied to the dummy wirings m1_s1, m1_s2, m1_s3, and m1_s4 to reduce capacitance mismatch between adjacent metal wirings. In some embodiments, the voltage may be predetermined.

Metal wirings m1_blb, m1_bla, m1_vss, m1_vdd, m1_vss, m1_btb, and m1_bta; dummy wirings m1_s1, m1_s2, m1_s3, and m1_s4; and the connection wirings M11 and M12 may include, for example, at least one of a metal, a metal alloy, a conductive metal nitride, a conductive metal carbonitride, a metal silicide, a doped semiconductor material, a conductive metal oxide, or a conductive metal oxynitride.

According to some embodiments, the pull-down transistor may include a gate electrode extending in the D2 direction and connection wirings M11 and M12 extending in the D1 direction, and may be connected in a bifurcated shape or an "H" shape. That is, the cascade connection of the pull-down transistors may have a bifurcated shape layout or an "H" shape layout.

Specifically, the gate electrode PC2, the gate vias CB1 and CB4, the connection wiring M12, the gate electrode PC6, the node formation pattern CB5, and the active contact CA7 may be electrically connected in a bifurcate shape, a hook shape, or an "H" shape. The gate electrode PC7, the gate vias CB3 and CB6, the connection wiring M11, the gate electrode PC3, the node formation pattern CB2, and the active contact CA6 may be electrically connected in a bifurcate shape, a hook shape, or an "H" shape. In the following description, a bifurcation shape will be described, but embodiments are not limited to such bifurcation shapes.

The "first bifurcation shape of the common node N1 between the first pull-down transistors PD1 and PD2 and the pass gate transistors PG1 and PG 2" may be set to mesh with or engage (meshed or engaged) with the "second bifurcation shape of the node N2 between the second pull-down transistors PD3 and PD4 and the pass gate transistors PG3 and PG4 while facing each other. In this specification, "provided to engage or engage" means that the protruding portions of the mutually non-contact members are spaced apart in parallel with each other and arranged in point symmetry or center symmetry. For example, the first bifurcation shape and the second bifurcation shape are point-symmetrical about "a point where the axes of the active contacts CA6 and CA7 intersect the metal wiring m1_vdd".

For simplicity of description, it is assumed that the bifurcated shape X1 including the gate electrode PC7, the gate vias CB3 and CB6, the connection wiring M11, the gate electrode PC3, and the node formation pattern CB2 is a first prong, and the active contact CA6 is a first prong. The first prong includes: the first interconnect including the node formation pattern CB2 connected between the gate electrode PC3 and the active contact CA6, and the first branch formed by including the gate electrodes PC7 and PC3 connected via the gate vias CB3 and CB6 and the connection wiring M11.

It is assumed that the second fork shape X2 including the gate electrode PC2, the gate vias CB1 and CB4, the connection wiring M12, the gate electrode PC6, and the node formation pattern CB5 is a second fork, and the active contact CA7 is a second fork. The second prong includes: a second branch formed by including gate electrodes PC2 and PC6 and a connection wiring M12, and a second interconnect including a node formation pattern CB5 connected between the gate electrode PC6 and the active contact CA 7. The prongs and the prongs are arranged symmetrically and the first and second interconnectors are arranged point symmetrically to each other.

When the pull-down transistors PD3 and PD4 and the pull-down transistors PD1 and PD2 are arranged in an "H" shape as shown in fig. 4 and 5, the pull-down transistors and the transfer gate transistors have independent strengths, and thus various experimental Designs (DOEs) can be performed.

The SRAM cell 100 also includes word line wirings m1_wla and m1_wlb that provide word line signals. In fig. 4 to 5, the word line wirings m1_wla and m1_wlb are disposed on the boundary in the D2 direction of the SRAM cell 100. That is, the word line wiring m1_wla and the word line wiring w1_wta may be disposed on the same line as the second axis on which the gate electrodes PC1, PC2, PC3, and PC4 are disposed. The word line wiring m1_wlb and the word line wiring w1_wtb may be disposed on the same line as the fourth axis on which the gate electrodes PC5, PC6, PC7, and PC8 are disposed.

The word line wirings m1_wla and m1_wta supply the word line signal wl_a (see fig. 3), and the word line wirings m1_wlb and m1_wtb supply the word line signal wl_b (see fig. 3).

The word line signals wl_a and wl_b of the SRAM cell 100 of fig. 2 are applied to the gate vias CBWLA, CBWLB, CBWTA and CBWTB (hereinafter, referred to as "word line gate vias"). The word line gate via CBWLA receives the word line signal wl_a through the word line wiring m1_wla, the word line gate via CBWLB receives the word line signal wl_b through the word line wiring m1_wlb, the word line gate via CBWTA receives the word line signal wl_a through the word line wiring m1_wta, and the word line gate via CBWTB receives the word line signal wl_b through the word line wiring m1_wtb.

The word line gate via CBWLA supplies the word line signal wl_a to the gate electrode PC1 of the pass gate transistor PG4, and the word line gate via CBWLB supplies the word line signal wl_b to the gate electrode PC5 of the pass gate transistor PG 3. The word line gate via CBWTA supplies the word line signal wl_a to the gate electrode PC4 of the pass gate transistor PG1, and the word line gate via CBWTB supplies the word line signal wl_b to the gate electrode PC8 of the pass gate transistor PG 2.

FIG. 7 is a layout diagram of an SRAM cell in accordance with some embodiments. For simplicity of description, differences from fig. 5 will be mainly described.

SRAM cell 100 may include active patterns AP1, AP2, AP3, AP4, AP5, and AP6 shown in fig. 4; active contacts CA1, CA2, CA3, CA4, CA5, CA6, CA7, CA8, CA9, CA10, CA11, and CA12; gate electrodes PC1, PC2, PC3, PC4, PC5, PC6, PC7, and PC8; active vias VA1, VA2, VA3, VA4, VA5, VA6, VA7, VA8, VA9, and VA10; gate vias CB1, CB3, CB4, CB6, CBWLA, CBWLB, CBWTA and CBWTB; and nodes form patterns CB2 and CB5.

However, in the embodiment of fig. 7, the gate electrodes PC2 and PC7 may be formed to have a length different from that of the gate electrodes PC2 and PC7 of fig. 5.

Specifically, according to some embodiments, the end portion of the gate electrode PC2 in fig. 5 may be formed to extend through and intersect the boundary of the connection wiring M12 in the D2 direction. An end portion of the gate electrode PC7 may be formed to extend through and intersect a boundary of the connection wiring M11 in the D2 direction. The gate electrode PC7, the connection wiring M11, and the gate electrode PC3 form a first branch, and the gate electrode PC2, the connection wiring M12, and the gate electrode PC6 form a second branch. That is, the first branch included in the first bifurcation shape X1 of fig. 5 and the second branch included in the second bifurcation shape X2 of fig. 5 may be formed in an "H" shape.

According to some embodiments, as shown in fig. 7, the end portion of the gate electrode PC2 may be formed only to the intersection point without passing through the boundary in the D2 direction of the connection wiring M12. The end portion of the gate electrode PC7 may be formed only to the intersection point without passing through the boundary in the D2 direction of the connection wiring M11. The gate electrode PC7, the connection wiring M11, and the gate electrode PC3 form a first branch, and the gate electrode PC2, the connection wiring M12, and the gate electrode PC6 form a second branch. That is, the first branch included in the first bifurcation shape X1 of fig. 7 and the second branch included in the second bifurcation shape X2 of fig. 7 may be formed in a "Y" shape.

In the embodiment of fig. 7, the first bifurcation shape X1 and the second bifurcation shape X2 may be arranged such that the Y-shapes mesh and engage each other. That is, the first bifurcation shape X1 and the second bifurcation shape X2 may be disposed point symmetrically with each other.

FIG. 8 is a layout diagram of an SRAM cell in accordance with some embodiments. For simplicity of description, differences from fig. 5 will be mainly described.

Referring to fig. 8, according to some embodiments, the SRAM cell 100 may include active patterns AP1, AP2, AP3, AP4, AP5, and AP6 as described with reference to fig. 4 and 5; active contacts CA1, CA2, CA3, CA4, CA5, CA6, CA7, CA8, CA9, CA10, CA11, and CA12; gate electrodes PC1, PC2, PC3, PC4, PC5, PC6, PC7, and PC8; active vias VA1, VA2, VA3, VA4, VA5, VA6, VA7, VA8, VA9, and VA10; gate vias CB1, CB3, CB4, CB6, CBWLA, CBWLB, CBWTA and CBWTB; and nodes form patterns CB2 and CB5.

The SRAM cell 100 also includes metal wirings m1_blb, m1_bla, m1_vss, m1_vdd, m1_vss, m1_btb, and m1_bta; dummy wirings m1_s2 and m1_s3; word line wirings m1_wlb, m1_wla, and m1_wta; and connection wirings M11 and M12. Unlike the embodiment of fig. 7, in the unit cell of fig. 8, the word line wirings m1_wlb, m1_wla, m1_wtb, and m1_wta are spaced apart from each other in the D2 direction while extending in the D1 direction. The word line wirings m1_wlb and m1_wla are alternately arranged with the metal wirings m1_blb and m1_bla to which the bit line signals are applied. The word line wiring m1_wta and the word line wiring m1_wtb are alternately arranged with the metal wirings m1_bta and m1_btb to which the bit line signal is applied. The dummy wiring m1_s2 is disposed between the metal wiring m1_bla and the metal wiring m1_vss. The dummy wiring m1_s3 is disposed between the metal wiring m1_btb and the metal wiring m1_vss.

The word line wirings m1_wlb, m1_wla, m1_wtb, and m1_wta intersect the gate electrodes PC1, PC5, PC4, and PC8 extending in the D2 direction, and are electrically connected through the word line gate vias CBWLA, CBWLB, CBWTA and CBWTB. In one embodiment, the lengths of the word line wirings m1_wlb, m1_wla, m1_wtb, and m1_wta in the D1 direction may be shorter than the lengths of the metal wirings m1_blb, m1_bla, m1_vss, m1_vdd, m1_vss, m1_btb, and m1_bta in the D1 direction.

Fig. 9 and 10 are layout diagrams of SRAM cell according to some embodiments.

Referring to fig. 9 and 10, according to some embodiments, SRAM cell units 100 are disposed adjacent to each other in the D1 direction. The plurality of SRAM cell units 100-1 to 100-k are arranged to be electrically connected along metal wirings m1_blb, m1_bla, m1_vss, m1_vdd, m1_vss, m1_btb, and m1_bta extending in the D1 direction, and dummy wirings m1_s1, m1_s2, m1_s3, and m1_s4.

The metal wiring m2_vss or m2_vdd, which is the supply ground voltage VSS or the supply voltage VDD of the power wiring, may be provided to extend in the D2 direction. In one embodiment, the plurality of power gate vias VA21, VA22, VA20, VA40, VA30, VA31, VA32 may be disposed between intersections of the power wiring m2_vss or m2_vdd and a plurality of specific wirings (i.e., the dummy wirings m1_s1, m1_s2, the metal wirings m1_vss, m1_vdd, m1_vss, the dummy wirings m1_s3, m1_s4), respectively.

According to some embodiments, a preset voltage is applied to the dummy wiring. The preset voltage may be, for example, a shield voltage for reducing coupling capacitance between wirings.

For example, as shown in fig. 9, the dummy wirings m1_s1, m1_s2, m1_s3, and m1_s4 may be connected to the power supply wiring m2_vss supplied with the ground voltage VSS (i.e., the ground voltage VSS may be applied to the dummy wirings m1_s1, m1_s2, m1_s3, and m1_s4 through the power supply gate vias VA21, VA22, VA31, VA32, respectively), and thus the ground voltage may be supplied as a shielding voltage. When the ground voltage is supplied to the dummy wiring, the resistance of the ground voltage VSS of the SRAM cell 100 may be reduced, and the coupling capacitance between the metal lines may be increased, thereby improving the read operation margin of the SRAM device 1. The read operation performance of the SRAM device may be improved according to the read operation margin.

For example, as shown in fig. 10, the dummy wirings m1_s1, m1_s2, m1_s3, and m1_s4 may be connected to the power supply wiring m2_vdd to which the power supply voltage VDD is supplied (i.e., the power supply voltage VDD may be applied to the dummy wirings m1_s1, m1_s2, m1_s3, and m1_s4 through the power supply gate vias VA21, VA22, VA31, VA32, respectively), and thus the power supply voltage may be supplied as a shielding voltage. When the power supply voltage is supplied to the dummy wiring, the resistance of the power supply voltage VDD of the SRAM cell 100 may be reduced, and the coupling capacitance between the metal lines may be increased, thereby improving the read operation margin of the SRAM device 1. The read operation performance of the SRAM device may be improved according to the read operation margin.

Those skilled in the art will appreciate that many variations and modifications may be made to the described embodiments without materially departing from the principles of this disclosure. Accordingly, the disclosed embodiments are used in a generic and descriptive sense only and not for purposes of limitation.

Claims (20)

1. An integrated circuit includes a static random access memory SRAM device,

wherein the SRAM device comprises an SRAM unit cell comprising a first output node and a second output node, the first pull-up transistor, the first pull-down transistor, and the second pull-down transistor being commonly connected to the first output node, the second pull-up transistor, the third pull-down transistor, and the fourth pull-down transistor being commonly connected to the second output node,

Wherein the first output node is connected to the first gate electrode, the second gate electrode, the first connection wiring, the first node forming pattern and the first active contact,

wherein the first output node, the first gate electrode, the second gate electrode, the first connection wiring, the first node forming pattern, and the first layout of the first active contact are disposed in a first bifurcated shape.

2. The integrated circuit of claim 1, wherein the second output node is connected to the third gate electrode, the fourth gate electrode, the second connection wiring, the second node formation pattern, and the second active contact, and the second layout of the second output node, the third gate electrode, the fourth gate electrode, the second connection wiring, the second node formation pattern, and the second active contact is provided in a second bifurcated shape.

3. The integrated circuit of claim 2, wherein the first bifurcated shape and the second bifurcated shape are arranged in an H-shape.

4. The integrated circuit according to claim 3, wherein the second gate electrode extends in a first direction and the first connection wiring extends in a second direction, and the second gate electrode is provided to pass through an end portion of the first connection wiring, and

the fourth gate electrode extends in the first direction, and the second connection wiring extends in the second direction, and the fourth gate electrode is disposed to pass through an end portion of the second connection wiring.

5. The integrated circuit of claim 2, wherein the first bifurcated shape and the second bifurcated shape are point-symmetrically disposed with respect to each other.

6. The integrated circuit of claim 3, wherein the second gate electrode extends in a first direction and the first connection wiring extends in a second direction, and the second gate electrode extends up to the first connection wiring, and

the fourth gate electrode extends in the first direction, and the second connection wiring extends in the second direction, and the fourth gate electrode extends up to the second connection wiring.

7. The integrated circuit of any of claims 1-6, wherein the SRAM cell comprises:

a plurality of metal wirings extending in a second direction, spaced apart from each other in a first direction, and to which bit line signals, complementary bit line signals, power supply voltages, and ground voltages are applied, respectively; and

and a plurality of dummy wirings extending in the second direction and spaced apart from each other in the first direction between the plurality of metal wirings.

8. The integrated circuit of claim 7, wherein the SRAM device comprises:

a first power supply wiring extending in a first direction and to which a ground voltage is applied; and

A plurality of first power gate vias respectively provided between intersections of the plurality of dummy wirings and the first power wirings,

wherein a ground voltage is applied to each of the plurality of dummy wirings through the plurality of first power gate vias.

9. The integrated circuit of claim 7, wherein the SRAM device comprises:

a second power supply wiring extending in the first direction and to which a power supply voltage is applied; and

a plurality of second power supply gate vias respectively provided between intersections of the plurality of dummy wirings and the second power supply wirings,

wherein a power supply voltage is applied to each of the plurality of dummy wirings through the plurality of second power supply gate vias.

10. The integrated circuit of any of claims 1-6, wherein the SRAM cell comprises:

a plurality of metal wirings extending in a second direction, spaced apart from each other in a first direction, and to which a first word line signal, a second word line signal, a first bit line signal, a second bit line signal, a power supply voltage, a ground voltage, a first complementary bit line signal, and a second complementary bit line signal are applied, respectively;

A first dummy wiring between a first metal wiring to which a first bit line signal is applied and a second metal wiring to which a ground voltage is applied; and

the second dummy wirings are spaced apart from each other in the first direction between the third metal wiring to which the second complementary bit line signal is applied and the fourth metal wiring to which the ground voltage is applied.

11. The integrated circuit of claim 10, wherein a length of the metal wiring to which the first and second word line signals are respectively applied in the second direction is shorter than a length of the metal wiring to which the first and second bit line signals are respectively applied in the second direction.

12. An integrated circuit comprising a plurality of SRAM cell units, each SRAM cell unit comprising:

a plurality of fully-around gate transistors;

a plurality of active patterns sequentially arranged at intervals in a first direction and extending in a second direction;

a first gate electrode extending on the plurality of active patterns along a first direction of a first axis;

a second gate electrode extending in a first direction of a second axis on the plurality of active patterns;

A first connection wiring extending in the second direction and intersecting the first gate electrode and the second gate electrode on the first gate electrode and the second gate electrode;

the first node forms a pattern extending along the second gate electrode and having a first length in the second direction;

a first active contact extending in a first direction along a third axis and forming a pattern intersecting the first node,

wherein a first input/output node of the SRAM unit cell is connected to the first gate electrode, the second gate electrode, the first connection wiring, the first node forming a pattern and the first active contact, an

Wherein the first input/output node, the first gate electrode, the second gate electrode, the first connection wiring, the first node forming pattern, and the first layout of the first active contact are disposed in a first bifurcated shape.

13. The integrated circuit of claim 12, wherein the first bifurcated shape comprises:

a first branch including a first physical connection between the first gate electrode, the second gate electrode, and the first connection wiring;

a first interconnect including a first node patterned as a second physical connection between a second gate electrode and a first active contact; and

the first fork includes a first active contact.

14. The integrated circuit according to claim 13, wherein in the first branch, the second gate electrode is provided to pass through an end portion of the first connection wiring, and the first bifurcated shape is provided in an H shape.

15. The integrated circuit of claim 13, wherein in the first branch, the second gate electrode extends only up to the first connection wiring, and the first bifurcated shape is provided in a Y-shape.

16. An integrated circuit, comprising:

a first power supply wiring extending in a first direction;

a first gate electrode extending in a second direction of the first axis below the first power supply wiring;

a second gate electrode extending in a second direction of the first axis below the first power supply wiring and spaced apart from the first gate electrode;

a first active contact extending in a second direction of the second shaft under the first power supply wiring;

a second active contact extending in a second direction of the second axis and disposed symmetrically to the first active contact with respect to the first power supply wiring;

a third gate electrode extending in a second direction of a third axis under the first power supply wiring;

a fourth gate electrode under the first power supply wiring and spaced apart from the third gate electrode, the fourth gate electrode extending in a second direction of the third axis;

A first connection wiring extending in a first direction and electrically connected to the first gate electrode and the second gate electrode;

a second connection wiring extending in the first direction and electrically connected to the third gate electrode and the fourth gate electrode;

the first node forms a pattern, extends along a first direction and is configured to electrically connect the second gate electrode and the first active contact; and

a second node is patterned extending along the first direction and configured to electrically connect the third gate electrode and the second active contact,

the first layout shape is point-symmetrical to the second layout shape, the first gate electrode, the first connection wiring, the third gate electrode, the first node forming pattern and the first active contact are connected in the first layout shape, and the fourth gate electrode, the second connection wiring, the second gate electrode, the second node forming pattern and the second active contact are connected in the second layout shape.

17. The integrated circuit of claim 16, wherein the point symmetry is point symmetry about an intersection of the first power supply wiring and the second axis in the second direction.

18. The integrated circuit of claim 16 or 17, further comprising:

two second power supply wirings each spaced apart from a corresponding side of the first power supply wiring in a second direction, the two second power supply wirings extending in the first direction;

A first metal wiring and a second metal wiring to which a first bit line signal and a second bit line signal are applied, respectively, the first metal wiring and the second metal wiring being spaced apart from a first one of the two second power wirings in a second direction and extending in the first direction; and

third and fourth metal wirings to which first and second complementary bit line signals are applied, respectively, the third and fourth metal wirings being spaced apart from a second one of the two second power supply wirings in the second direction and extending in the first direction.

19. The integrated circuit of claim 18, further comprising a plurality of dummy wirings extending in the first direction and disposed between the second metal wiring and the first metal wiring, between the first metal wiring and a first one of the two second power wirings, between the second one of the two second power wirings and the third metal wiring, and between the third metal wiring and the fourth metal wiring.

20. The integrated circuit of claim 19, wherein a supply voltage or a ground voltage is applied to the plurality of dummy wirings.