CN117133722A

CN117133722A - Semiconductor structure and preparation method thereof

Info

Publication number: CN117133722A
Application number: CN202311379664.9A
Authority: CN
Inventors: 张振; 陈世昌; 王焕琛; 杨英英
Original assignee: Nexchip Semiconductor Corp
Current assignee: Nexchip Semiconductor Corp
Priority date: 2023-10-24
Filing date: 2023-10-24
Publication date: 2023-11-28

Abstract

The application relates to a semiconductor structure and a preparation method thereof. The semiconductor structure includes: the semiconductor device comprises a substrate, a first sealing structure, a second sealing structure, a first protection layer and a second protection layer. The substrate has a device region, a dicing region, and a transition region between the device region and the dicing region. The first sealing structure and the second sealing structure are respectively located in the transition region, and the second sealing structure is located on one side, away from the device region, of the first sealing structure. The first protective layer covers the first sealing structure and the second sealing structure. The second protection layer covers the first protection layer. Wherein the first sealing structure and the second sealing structure each include a plurality of metal layers and a plurality of support layers alternately stacked in a direction away from the substrate. The number of stacked metal layers in the second sealing structure is smaller than that in the first sealing structure. The second protective layer on the second sealing structure is provided with a stress relief notch. The semiconductor structure provided by the application can reduce adverse effects of cutting stress and improve performance stability of a semiconductor device.

Description

Semiconductor structure and preparation method thereof

Technical Field

The application relates to the field of semiconductors, in particular to a semiconductor structure and a preparation method thereof.

Background

In conventional semiconductor fabrication processes, it is often necessary to arrange an array of semiconductor devices on a wafer and to provide dicing streets between adjacent semiconductor devices. Thus, after the process of the semiconductor device is completed, the wafer can be cut along the dicing channels to obtain individual semiconductor devices.

However, when dicing a wafer along dicing streets, stress shock is inevitably generated, and defects such as cracks and chips are easily generated at the edges of the streets. Moreover, such defects tend to extend further into the semiconductor device with the use of the semiconductor device, causing serious damage to the semiconductor device.

Therefore, how to improve the semiconductor structure and the preparation method thereof to reduce the adverse effect of the cutting stress is a problem to be solved.

Disclosure of Invention

In view of the foregoing, it is desirable to provide a semiconductor structure and a method for manufacturing the same that can reduce adverse effects of cutting stress, thereby improving performance stability of a semiconductor device.

In one aspect, an embodiment of the present application provides a semiconductor structure, including: the device comprises a substrate, a first sealing structure, a second sealing structure, a first protection layer and a second protection layer. The substrate has a device region, a dicing region, and a transition region between the device region and the dicing region. The first sealing structure and the second sealing structure are respectively located in the transition region, and the second sealing structure is located on one side, away from the device region, of the first sealing structure. The first protective layer covers the first sealing structure and the second sealing structure. The second protection layer covers the first protection layer. Wherein, first seal structure and second seal structure all include: a plurality of metal layers and a plurality of support layers alternately stacked in a direction away from the substrate. The number of stacked metal layers in the second sealing structure is smaller than that in the first sealing structure. The second protective layer on the second sealing structure is provided with a stress relief notch.

In the embodiment of the application, a plurality of metal layers and a plurality of supporting layers are alternately laminated along the direction deviating from the substrate in the transition region between the device region and the cutting region to respectively form a first sealing structure and a second sealing structure, and a laminated first protective layer and a laminated second protective layer are arranged on the two sealing structures. The second sealing structure and the first sealing structure are sequentially arranged in the direction from the cutting region to the device region. The second protective layer is provided with a stress relief notch in a region corresponding to above the second sealing structure. Based on this, when the semiconductor structure receives the dicing stress from the dicing area, the stress will propagate to the second sealing structure and the stress relief notch. Due to the notch effect, most of the impact stress will be concentrated to the open root and released through the stress relief notch or blocked by the second sealing structure located below the notch. While a small portion of the residual stress continues to propagate to the first seal structure, it is effectively blocked by the first seal structure. In this way, the impact stress is greatly reduced until eliminated, and further the semiconductor device in the device region can be effectively prevented from being damaged.

In addition, in the embodiment of the present application, the number of metal layers in the second sealing structure is smaller than the number of metal layers in the first sealing structure, which is favorable for adjusting the material thickness of the first protection layer and/or the second protection layer in the corresponding area of the first sealing structure and the second sealing structure when forming the first protection layer covering the first sealing structure and the second protection layer covering the first protection layer, for example, the thickness of the first protection layer and/or the second protection layer above the second sealing structure is greater than the thickness above the first sealing structure. Therefore, the stress release notch is correspondingly arranged in the second protective layer above the second sealing structure, so that a larger interval can be formed between the bottom of the stress release notch and the topmost metal layer in the second sealing structure. Thus, during the preparation of the stress relief notch and in subsequent other process steps (e.g., etching or cleaning), the bottom of the stress relief notch is prevented from being accidentally opened and exposing the metal layer in the underlying second sealing structure. And further, external water vapor, impurities or free charges and the like can be prevented from entering the device region through the stress release notch, so that the performance stability of the semiconductor device in the device region is ensured and improved.

In some embodiments, the depth of the stress relief notch is less than the thickness of the second protective layer.

In the embodiment of the application, the depth of the stress release notch is smaller than the thickness of the second protective layer, so that the bottom of the stress release notch is isolated from the topmost metal layer in the second sealing structure by a part of the second protective layer and the complete first protective layer, a larger interval between the bottom of the stress release notch and the topmost metal layer in the second sealing structure below the stress release notch is ensured, and the risk of accidental exposure of the metal layer is reduced.

In some embodiments, the support layer comprises: dielectric layer and connection structure. The dielectric layer is positioned between adjacent metal layers and is provided with at least one connecting through hole and/or connecting groove. The connecting structure is arranged in the connecting through hole and/or the connecting groove and is connected with the metal layer adjacent to the dielectric layer. Wherein, the radial dimension of the connecting through holes in each supporting layer is the same.

In the embodiment of the application, the connecting structure is arranged in the medium layer to connect the adjacent metal layers, so that the metal layers are connected through the corresponding connecting structure to form an integral structure, and the mechanical strength of the first sealing structure and the second sealing structure is improved. In some embodiments, the support layers include connection through holes, and the radial dimensions of the connection through holes in each support layer are the same, so that each connection structure formed in the connection through hole has a uniform radial dimension, thereby ensuring that the contact area of each connection structure and the corresponding metal layer is the same. Therefore, the connecting structures with consistent radial dimensions can uniformly bear the stress transmitted by the corresponding metal layers during cutting, so that the stress stability of the first sealing structure and the second sealing structure is improved. Therefore, the problem that the corresponding second sealing structure and the corresponding first sealing structure are broken due to stress concentration at the connecting structure with smaller part of radial dimension caused by inconsistent radial dimension of each connecting structure can be avoided. In some embodiments where the support layer includes a connection groove, the connection structure may be shaped to match the shape of the connection groove, for example, and may be elongated or annular, so as to ensure that the connection structure may have a larger contact area with the corresponding metal layer, thereby providing better protection against cutting stress.

In some embodiments, the substrate of the transition region also has a doped region. The semiconductor structure further includes: an insulating layer and a contact plug. The insulating layer is arranged between the doped region and the first sealing structure and between the doped region and the second sealing structure. The insulating layer has a plurality of contact vias. The contact plug is arranged in the contact through hole and is connected with the doped region adjacent to the insulating layer and the metal layer.

In the embodiment of the application, the doped region is arranged in the substrate, and the contact through holes can be correspondingly arranged between the doped region and the first sealing structure and between the doped region and the second sealing structure so as to respectively connect the metal layer in the first sealing structure and the metal layer in the second sealing structure with the doped region. Based on this, the first sealing structure and the second sealing structure may be kept at an equipotential with the doped region to block the external environment and free charges in the dielectric layer from entering the device region and adversely affecting the performance of the semiconductor device.

In some embodiments, the support layer includes connection vias, the radial dimensions of the contact vias being the same as the radial dimensions of the connection vias in the support layer.

In the embodiment of the application, the radial dimension of the contact through hole is the same as the radial dimension of the connecting through hole in the supporting layer. Thus, the contact through holes and the connection through holes can be prepared and obtained based on the same mask. Is beneficial to simplifying the process steps and reducing the manufacturing cost.

In some embodiments, the semiconductor structure further includes an electrostatic protection layer. The electrostatic protection layer is positioned between the first protection layer and the second protection layer, and penetrates through the first protection layer to be connected with the corresponding metal layer in the first sealing structure.

In the embodiment of the application, the electrostatic protection layer is arranged to be electrically connected with the first sealing structure. Therefore, the first sealing structure and the electrostatic protection layer can be used as an electrostatic protection structure together, and a good electrostatic protection function is provided for the device area.

In another aspect, embodiments of the present application provide a method for manufacturing a semiconductor structure, which is used to manufacture the semiconductor structures described in the foregoing embodiments. The technical advantages of the semiconductor structure described in some of the foregoing embodiments are also provided by the preparation method, which is not described in detail herein. The preparation method comprises the following steps.

A substrate is provided having a device region, a dicing region, and a transition region between the device region and the dicing region.

And forming a first sealing structure and a second sealing structure on the substrate of the transition region respectively, wherein the second sealing structure is positioned on one side of the first sealing structure far away from the device region. The first seal structure and the second seal structure each include: a plurality of metal layers and a plurality of support layers alternately stacked in a direction away from the substrate. The number of stacked metal layers in the second sealing structure is smaller than that in the first sealing structure.

A first protective layer is formed overlying the first seal structure and the second seal structure.

And forming a second protective layer covering the first protective layer, and forming a stress relief notch in the second protective layer on the second sealing structure.

In some embodiments, the first sealing structure and the second sealing structure are respectively formed on the substrate in the transition region, and the method comprises the following steps.

And forming a metal material layer on the substrate of the transition region, and patterning the metal material layer to form a first metal layer in the first sealing structure and a first metal layer in the second sealing structure.

And forming a dielectric layer covering the metal layer, and forming at least one connecting through hole and/or connecting groove in the dielectric layer.

And forming a metal material layer filling the connecting through holes and/or the connecting grooves and covering the dielectric layer, patterning the metal material layer covering the dielectric layer, forming a connecting structure positioned in the connecting through holes and/or the connecting grooves, and forming a second metal layer in the first sealing structure and a second metal layer in the second sealing structure. The dielectric layer and the connection structure formed in the dielectric layer together form a support layer.

And repeating the steps of forming a dielectric layer covering the metal layer and forming at least one connecting through hole and/or connecting groove in the dielectric layer according to the stacking layers of the metal layer and the supporting layer in the first sealing structure and the second sealing structure, forming a metal material layer filling the connecting through hole and/or the connecting groove and covering the dielectric layer and patterning the metal material layer covering the dielectric layer to obtain the first sealing structure and the second sealing structure respectively.

In the embodiment of the application, the connection structure and the corresponding metal layer are synchronously formed by patterning the same metal material layer. The connecting structure and the corresponding metal layer form an integral structure, so that the sealing structure formed by the metal layer, the connecting structure and the supporting layer can be ensured to have larger mechanical strength. Further, a better blocking effect against impact stress can be obtained.

In some embodiments, the substrate also has a doped region. The method of making further comprises the following steps prior to forming the first seal and the second seal.

An insulating layer is formed on the substrate of the doped region, and a plurality of contact through holes are formed in the insulating layer.

And forming a contact plug in the contact through hole.

Wherein the first sealing structure and the second sealing structure are respectively formed on the insulating layer. The first metal layer in the first sealing structure and the second sealing structure is connected with the doped region through the contact plug.

In some embodiments, the method of preparing further comprises the following steps after forming the first protective layer and before forming the second protective layer.

And forming a connecting opening in the first protective layer, wherein the connecting opening exposes a part of the top metal layer in the first sealing structure.

An electrostatic protection layer is formed to fill the connection opening and cover the surface of the first protection layer portion.

The second protection layer covers the static protection layer and the part of the first protection layer which is not covered by the static protection layer.

In the embodiment of the application, a semiconductor structure and a preparation method thereof are provided, and the design improvement of the semiconductor structure is realized. The unexpected effect is: when the semiconductor structure receives the cutting stress from the cutting area, the stress is sequentially transmitted to the second sealing structure and the stress relief notch close to the outer side; and then to the first sealing structure near the inner side. By means of the notch effect and the blocking effect provided by the second sealing structure and the first sealing structure, stresses are greatly reduced until eliminated, so that the semiconductor device in the device region is effectively prevented from being damaged. In addition, the number of the metal layers and the thicknesses of the first protective layer and the second protective layer in different areas are controlled, so that the stress release notch is arranged in the second protective layer on the second sealing structure correspondingly, and a larger interval can be ensured between the bottom of the stress release notch and the topmost metal layer in the second sealing structure, and therefore the situation that the bottom of the stress release notch is opened and the lower metal layer is exposed due to accidents in the preparation process can be effectively avoided; and further, external water vapor, impurities or free charges and the like can be prevented from entering the device region through the stress release notch, so that the performance stability of the semiconductor device in the device region is ensured and improved.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments or the conventional techniques of the present application, the drawings required for the descriptions of the embodiments or the conventional techniques will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to the drawings without inventive effort for those skilled in the art.

FIG. 1 is a schematic diagram of a semiconductor structure provided in some embodiments;

FIG. 2 is a schematic cross-sectional view of the structure of FIG. 1 taken along the A-A direction;

FIG. 3 is a schematic cross-sectional view of the structure of FIG. 2 taken along the direction B-B;

FIG. 4 is a schematic diagram of another semiconductor structure provided in some embodiments;

FIG. 5 is a flow chart of a method of fabricating a semiconductor structure provided in some embodiments;

FIG. 6 is a flow chart of a step S200 provided in some embodiments;

FIG. 7 is a flow chart of another method of fabricating a semiconductor structure provided in some embodiments;

FIG. 8 is a flow chart of a method of fabricating yet another semiconductor structure provided in some embodiments;

FIG. 9 is a schematic diagram of the structure after forming doped regions, as provided in some embodiments;

FIG. 10 is a schematic diagram of the structure after formation of contact vias, as provided in some embodiments;

FIG. 11 is a schematic diagram of a structure after formation of contact plugs, as provided in some embodiments;

FIG. 12 is a schematic diagram of the structure after formation of a metal material layer, as provided in some embodiments;

FIG. 13 is a schematic diagram of a structure obtained after forming a first metal layer according to some embodiments;

FIG. 14 is a schematic illustration of the resulting structure after formation of a via and/or trench, as provided in some embodiments;

FIG. 15 is a schematic cross-sectional view of the structure of FIG. 14 taken along the direction C-C;

FIG. 16 is a schematic illustration of another structure provided in some embodiments after formation of a metal material layer;

FIG. 17 is a schematic diagram of the structure after formation of a second metal layer and a support layer, as provided in some embodiments;

FIG. 18 is a schematic structural view of a resulting structure after formation of a first seal structure and a second seal structure, as provided in some embodiments;

FIG. 19 is a schematic diagram of a structure after forming a first passivation layer and connecting openings according to some embodiments;

FIG. 20 is a schematic diagram of the structure after formation of an electrostatic protection layer, as provided in some embodiments;

FIG. 21 is a schematic diagram of a structure after forming a second passivation layer and a stress relief notch according to some embodiments.

Reference numerals illustrate:

1-substrate, 11-doped region;

2-sealing structure, 21-first sealing structure, 22-second sealing structure, 23' -metal material layer, 23-metal layer, 24-supporting layer, 241-dielectric layer, 242-connecting structure;

3-a first protective layer, 4-a second protective layer, 5-an insulating layer, 6-a contact plug, 7-an electrostatic protection layer and 8-a rewiring layer;

g1-stress relief notch, G2-connection opening, G3-pad opening, H1-connection via, H2-contact via, TR 1-connection trench;

a1-device region, A2-transition region, A3-cut region.

Detailed Description

In order that the application may be readily understood, a more complete description of the application will be rendered by reference to the appended drawings. Embodiments of the application are illustrated in the accompanying drawings. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

It will be understood that when an element is referred to as being "connected" to another element, it can be directly connected to the other element or be connected to the other element through intervening elements. Further, "connection" in the following embodiments should be understood as "electrical connection", "communication connection", and the like if there is transmission of electrical signals or data between objects to be connected.

As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," and/or the like, specify the presence of stated features, integers, steps, operations, elements, components, or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups thereof. Also, the term "and/or" as used in this specification includes any and all combinations of the associated listed items.

However, when dicing a wafer along dicing streets, stress shock is inevitably generated, and defects such as cracks and chips are easily generated at the edges of the streets. And, such defects also tend to extend further into the semiconductor device as it is used. Outside water vapor, impurity particles, free charges and the like can enter the semiconductor device through cracks, and serious damages such as corrosion, disconnection, short circuit and the like are caused to the semiconductor device.

Referring to fig. 1 and 2, in some embodiments, a semiconductor structure is provided. The semiconductor structure includes: a substrate 1, a first sealing structure 21, a second sealing structure 22, a first protective layer 3 and a second protective layer 4. The substrate 1 has a device region A1, a dicing region A3, and a transition region A2 between the device region A1 and the dicing region A3. The first sealing structure 21 and the second sealing structure 22 are respectively located at the transition region A2, and the second sealing structure 22 is located at a side of the first sealing structure 21 away from the device region A1. The first protective layer 3 covers the first sealing structure 21 and the second sealing structure 22. The second protective layer 4 covers the first protective layer 3. Wherein the first sealing structure 21 and the second sealing structure 22 each comprise a plurality of metal layers 23 and a plurality of support layers 24 alternately stacked in a direction away from the substrate 1. The number of stacked layers of the metal layers 23 in the second seal structure 22 is smaller than the number of stacked layers of the metal layers 23 in the first seal structure 21. The second protective layer 4 on the second sealing structure 22 has a stress relief notch G1.

In the embodiment of the present application, a plurality of metal layers 23 and a plurality of support layers 24 are alternately stacked in a transition region A2 between the device region A1 and the dicing region A3 in a direction away from the substrate 1 to respectively constitute a first sealing structure 21 and a second sealing structure 22, and stacked first protective layers 3 and second protective layers 4 are disposed on the two sealing structures. Wherein, the direction from the cutting area A3 to the device area A1 is a second sealing structure 22 and a first sealing structure 21 in sequence. The second protective layer 4 is provided with a stress relief notch G1 in a region corresponding to above the second sealing structure 22. Based on this, when the semiconductor structure receives the dicing stress from the dicing area A3, the stress propagates to the second sealing structure 22 and the stress relief notch G1. Due to the notch effect, most of the impact stress is concentrated to the root of the stress relief notch G1 and released through the stress relief notch G1 or blocked by the second sealing structure 22 located below the stress relief notch G1. While a small portion of the residual stress continues to propagate to the first seal 21, it is effectively blocked by the first seal 21. In this way, the impact stress is greatly reduced until eliminated, and further the semiconductor device in the device region A1 can be effectively prevented from being damaged.

In addition, in the embodiment of the present application, the number of the metal layers 23 in the second sealing structure 22 is smaller than the number of the metal layers 23 in the first sealing structure 21, which is favorable for forming the first protection layer 3 covering the first sealing structure 21 and the second sealing structure 22 and the second protection layer 4 covering the first protection layer 3, by adjusting the material thickness of the first protection layer 3 and/or the second protection layer 4 in the corresponding area of the first sealing structure 21 and the second sealing structure 22, for example, the thickness of the first protection layer 3 and/or the second protection layer 4 above the second sealing structure 22 is larger than the thickness above the first sealing structure 21. In this way, the stress relief notch G1 is correspondingly disposed in the second protection layer 4 above the second sealing structure 22, which is beneficial to enabling a larger interval between the bottom of the stress relief notch G1 and the topmost metal layer 23 in the second sealing structure 22. So that during the preparation of the stress relief notch G1 and in further process steps (e.g. etching or cleaning) it is avoided that the bottom of the stress relief notch G1 is accidentally opened and the metal layer 23 in the underlying second sealing structure 22 is exposed. And further, external water vapor, impurities or free charges and the like can be prevented from entering the device region A1 through the stress release notch G1, so that the performance stability of the semiconductor device in the device region A1 is ensured and improved.

By way of example, the substrate 1 may be formed using a semiconductor material, an insulating material, a conductor material, or any combination of the kinds of materials thereof. The substrate 1 may have a single-layer structure or a multilayer structure. For example, the substrate 1 may be a substrate such as a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate. Alternatively, the substrate 1 may be a layered substrate including, for example, a stack of Si and SiGe, a stack of Si and SiC, a silicon-on-insulator (SOI) or silicon-germanium-on-insulator, or the like.

By way of example, the device regions A1 are used in the preparation of forming semiconductor devices, and the number of device regions A1 may include a plurality and be distributed in an array. The dicing area A3 is located between adjacent device areas A1, and may be disposed around the device areas A1, for example, so as to facilitate subsequent dicing of the substrate 1 along the dicing area A3 to obtain individual semiconductor devices. The transition area A2 is located between the device area A1 and the cutting area A3, and may be used to provide the sealing structures provided by the present application, such as the first sealing structure 21 and the second sealing structure 22.

Illustratively, a first seal structure 21 is disposed around the device region A1, and a corresponding second seal structure 22 is disposed around the first seal structure 21. That is, the orthographic projection of the first seal structure 21 on the substrate 1 is a closed ring shape and surrounds the orthographic projection of the device region A1 on the substrate; the orthographic projection of the second sealing structure 22 on the substrate 1 is a closed ring shape and surrounds the orthographic projection of the corresponding first sealing structure 21 on the substrate 1.

For example, with continued reference to fig. 2, the first seal structure 21 and the second seal structure 22 each include a plurality of metal layers 23 and a plurality of support layers 24 alternately stacked in a direction away from the substrate 1 (e.g., Z-direction).

Illustratively, the number of stacked layers of metal layers 23 in the second seal structure 22 is less than the number of stacked layers of metal layers 23 in the first seal structure 21. Here, the specific number of the metal layers 23 in each sealing structure may be set according to the actual requirement, for example, may be set: the number of stacked layers of the metal layers 23 in the first seal structure 21 is X, and the number of stacked layers of the metal layers 23 in the second seal structure 22 is Y. And the ratio of the difference (X-Y) of the number of the metal layers to X is less than 20%. For example, 5%, 10%, 15% and 18% may be used. In some embodiments below, the first sealing structure 21 comprises 9 metal layers, and the second sealing structure 22 comprises 8 metal layers. But is not limited thereto.

Illustratively, the material of the metal layer 23 may include metallic copper, metallic tungsten, metallic aluminum, or metallic titanium. Preferably, the material of the metal layer 23 is metallic copper. The metallic copper has good conductivity and good interface characteristics, which is beneficial to ensuring the performance of the sealing structure.

Illustratively, the orthographic projection of the stress relief notch G1 onto the substrate 1 falls within the orthographic projection range of the second sealing structure 22 onto the substrate 1.

In some embodiments, the depth of the stress relief notch G1 is less than the thickness of the second protective layer 4.

In the embodiment of the application, the depth of the stress relief notch G1 is smaller than the thickness of the second protection layer 4, so that the bottom of the stress relief notch G1 is isolated from the topmost metal layer 23 in the second sealing structure 22 by a part of the second protection layer 4 and the complete first protection layer 3, thereby ensuring that a larger interval can be provided between the bottom of the stress relief notch G1 and the topmost metal layer 23 in the second sealing structure 22 below the bottom of the stress relief notch G, and reducing the risk of accidental exposure of the metal layer 23.

Referring to fig. 2 and 3, in some embodiments, the support layer 24 includes: dielectric layer 241 and connection structure 242. Dielectric layer 241 is located between adjacent metal layers 23 and has at least one connection via H1 and/or connection trench TR1. The connection structure 242 is disposed in the connection via H1 and/or the connection trench TR1 and is connected to the metal layer 23 adjacent to the dielectric layer 241. Wherein the radial dimensions of the connecting through holes H1 in each supporting layer 24 are the same.

Here, the number and arrangement form of the connection via H1 and the connection trench TR1 in the same dielectric layer 241 are different in accordance with the structure and design requirements of the semiconductor device.

Referring to fig. 3 (a), in some embodiments, the support layer 24 includes: dielectric layer 241 and connection structure 242. Dielectric layer 241 is located between adjacent metal layers 23 and has at least one connection via H1. The connection structure 242 is disposed in the connection via H1 and connected to the metal layer 23 adjacent to the dielectric layer 241. Wherein the radial dimensions of the connecting through holes H1 in each supporting layer 24 are the same.

Here, the radial dimension of the connection through hole H1 matches the shape of the connection through hole H1 in different characterization manners, for example, when the connection through hole H1 is a circular hole, the radial dimension thereof is the diameter of the circular hole; and when the connection through-hole H1 is a polygonal hole, the radial dimension thereof may be the dimension of the polygonal hole in any direction within the radial cross section thereof, for example, the maximum diagonal dimension or the minimum diagonal dimension thereof. Thus, the radial dimension of the connecting through-hole H1 for a non-circular hole can be characterized by its maximum radial dimension or its minimum radial dimension.

In the embodiment of the present application, the connecting structure 242 is disposed in the dielectric layer 241 to connect the adjacent metal layers 23, so that each metal layer 23 is connected through the corresponding connecting structure 242 to form an integral structure, thereby improving the mechanical strength of the first sealing structure 21 and the second sealing structure 22. The radial dimensions of the connection through holes H1 in the support layers 24 are the same, so that the connection structures 242 formed in the connection through holes H1 have uniform radial dimensions, thereby ensuring the same contact area between the connection structures 242 and the corresponding metal layers 23. In this way, the connecting structures 242 with uniform radial dimensions can uniformly bear the stress transmitted by the corresponding metal layer 23 during cutting, so as to improve the stress stability of the first sealing structure 21 and the second sealing structure 22. Therefore, the problem that the corresponding second sealing structure 22 and the corresponding first sealing structure 21 are broken due to stress concentration at the connecting structure 242 with smaller part of radial dimension caused by non-uniform radial dimension of each connecting structure 242 can be avoided.

Illustratively, the range of values of the radial dimension of the connecting through hole H1 includes: 0.34 μm to 0.39 μm. For example, it may be 0.34 μm, 0.36 μm or 0.39 μm.

For example, the number of the connection via holes H1 may be plural, and the plural connection via holes H1 may be uniformly distributed in the dielectric layer 241 between the adjacent metal layers 23. For example, the plurality of connection through holes H1 may be distributed in an array. The application is not limited in this regard.

Referring to fig. 3 (b), in other embodiments, the support layer 24 includes: dielectric layer 241 and connection structure 242. Dielectric layer 241 is located between adjacent metal layers 23 and has at least one connection trench TR1. The connection structure 242 is disposed in the connection trench TR1 and connected to the metal layer 23 adjacent to the dielectric layer 241.

In the embodiment of the present application, the connecting structure 242 is matched with the shape of the connecting groove TR1, for example, the connecting structure may be in a strip shape or a ring shape, so as to ensure that a larger contact area between the connecting structure 242 and the corresponding metal layer 23 is provided, thereby providing a better protection effect against the cutting stress.

For example, the connection groove TR1 may have a rectangular shape, a closed ring shape, or the like in front projection on the substrate 1.

Illustratively, the range of values of the width of the connection trench TR1 includes: 0.34 μm to 0.39 μm. For example, it may be 0.34 μm, 0.36 μm or 0.39 μm.

Referring to fig. 3 (c), in still other embodiments, the support layer 24 includes: dielectric layer 241 and connection structure 242. The dielectric layer 241 is located between the adjacent metal layers 23 and has at least one connection via H1 and at least one connection trench TR1. The connection structure 242 is disposed in the connection via H1 and the connection trench TR1 and is connected to the metal layer 23 adjacent to the dielectric layer 241. Wherein the radial dimensions of the connecting through holes H1 in each supporting layer 24 are the same.

Here, the specific arrangement number and the relative positional relationship of the connection via H1 and the connection trench TR1 in any one of the dielectric layers 241 may be set in accordance with the requirements. For example, the connection through holes H1 and the connection grooves TR1 may be arranged at intervals. The application is not limited in this regard.

Illustratively, the material of the dielectric layer 241 may include oxide, nitride, phosphosilicate glass, or borophosphosilicate glass.

Illustratively, the material of the connection structure 242 may include metallic copper, metallic aluminum, metallic tungsten, or metallic titanium. Preferably, the material of the connection structure 242 may be the same as the metal layer 23, for example, all of metal copper. In this way, the connection structure 242 and the corresponding metal layer 23 can be simultaneously prepared as a unitary structure based on the same material.

In some embodiments, the substrate 1 of the transition region A2 also has a doped region 11. The semiconductor structure further includes: an insulating layer 5 and a contact plug 6. Wherein the insulating layer 5 is arranged between the doped region 11 and the first sealing structure 21 and between the doped region 11 and the second sealing structure 22. The insulating layer 5 has a plurality of contact through holes H2. The contact plug 6 is disposed in the contact via H2 and is connected to the doped region 11 and the metal layer 23 adjacent to the insulating layer 5.

In the embodiment of the present application, the doped region 11 is disposed in the substrate 1, and the contact through hole H2 may be correspondingly disposed between the doped region 11 and the first sealing structure 21 and between the doped region 11 and the second sealing structure 21, so as to connect the metal layer 23 in the first sealing structure 21 and the metal layer 23 in the second sealing structure 22 with the doped region 11 respectively. Based on this, the first sealing structure 21 and the second sealing structure 22 may be kept at an equipotential with the doped region 11 to block the external environment and free charges in the dielectric layer 241 from entering the device region A1 and adversely affecting the performance of the semiconductor device.

The doping type of the doped region 11 is set to match the requirements of the semiconductor device, and may be P-type doping or N-type doping, for example.

The doping type of the doped region 11 is, for example, P-type heavy doping.

For example, the doping concentration range of the doped region 11 may include 10-15/cm.

The material of the insulating layer 5 may include oxide, nitride or oxynitride, for example.

By way of example, the material of the contact plug 6 may include one or more of metallic tungsten, metallic titanium, and titanium nitride. In one example, the contact plug 6 may be a composite structure including titanium nitride and metallic tungsten. The titanium nitride can prevent the diffusion of the tungsten metal into other film layers, which is beneficial to keeping the performance of the contact plug 6 stable.

In some embodiments, the support layer 24 includes connection via H1, and the radial dimension of the contact via H2 is the same as the radial dimension of the connection via H1 in the support layer 24.

Here, the radial dimension of the contact through-hole H2 is consistent with the definition of the radial dimension with respect to the connection through-hole H1 in some of the foregoing embodiments.

In the embodiment of the present application, the radial dimension of the contact through hole H2 is set to be the same as the radial dimension of the connection through hole H1 in the support layer 24. Thus, the contact via H2 and the connection via H1 can be obtained based on the same reticle preparation. Is beneficial to simplifying the process steps and reducing the manufacturing cost.

Illustratively, the range of values of the radial dimension of the contact through hole H2 includes: 0.34 μm to 0.39 μm. For example, it may be 0.34 μm, 0.36 μm or 0.39 μm.

Illustratively, the contact via H2 also exposes a portion of the surface of the doped region 11 to ensure that the contact plug 6 formed in the contact via H1 can connect with the doped region 11 adjacent to the insulating layer 5 and the corresponding metal layer 23.

With continued reference to fig. 2, in some embodiments, the semiconductor structure further includes an electrostatic protection layer 7. The electrostatic protection layer 7 is located between the first protection layer 3 and the second protection layer 4, and penetrates through the first protection layer 3 to be connected with the corresponding metal layer 23 in the first sealing structure 21.

In the embodiment of the present application, the electrostatic protection layer 7 is electrically connected to the first sealing structure 21. In this way, the first sealing structure 21 and the electrostatic protection layer 7 can be used together as an electrostatic protection structure, so as to provide a good electrostatic protection function for the device area A1.

The material of the electrostatic protection layer 7 may be a metal material, for example, metallic aluminum, metallic copper, or metallic titanium, for example. In one example, the material of the electrostatic protection layer 7 is metallic aluminum. The metal aluminum oxide film is compact, and the stable performance of the electrostatic protection layer 7 can be ensured in the subsequent preparation and use processes.

It should be noted that referring to fig. 4, in some embodiments, a plurality of metal layers 23 are generally disposed in the device region A1 _A A plurality of dielectric layers 241 _A The formed stacked structure is stacked for use in preparing a semiconductor device. And a protective layer (such as a first protective layer and a second protective layer) and a packaging layer are arranged above the stacked structure so as to realize the protection and packaging of the semiconductor device. A re-wiring layer 8 is disposed above the stacked structure, and the re-wiring layer 8 can be disposed between the first and second protective layers and with the metal layer 23 _A Correspondingly connected. The rewiring layer 8 may also be led out for connection to external control circuitry of the semiconductor device.

It will be appreciated that the first protective layer 3 and the second protective layer 4 in the transition area A2 may be formed by extending the first protective layer and the second protective layer described in the device area A1, that is, the first protective layer 3 in the transition area A2 is disposed in the same layer as the first protective layer in the device area A1, and the second protective layer 4 in the transition area A2 is disposed in the same layer as the second protective layer in the device area A1. Illustratively, the re-wiring layer 8 in the device region A1 and the electrostatic protection layer 7 in the transition region A2 may be provided in the same layer to be obtained separately based on etching of the same metal material layer.

Further, the metal layer 23 in the device region A1 _A The number of stacked layers is the same as or different from the number of stacked layers of the metal layers 23 in the first seal structure 21.

Illustratively, metal layer 23 in device region A1 _A The number of stacked layers is the same as the number of stacked layers of the metal layers 23 in the first seal structure 21. Metal layer 23 in device region A1 _A One-to-one correspondence with the metal layers 23 in the first sealing structure 21, and the device region A1 is in contact with the corresponding metal layer (metal layer 23 _A And metal layer 23) are provided in the same layer, and can be obtained separately based on etching of the same metal material layer. Accordingly, dielectric layer 241 in device region A1 _A One-to-one correspondence with the dielectric layers 241 in the first sealing structure 21, and the device region A1 is in contact with the corresponding dielectric layer (dielectric layer 241) in the first sealing structure 21 _A And dielectric layer 241) are arranged in the same layer so as to be correspondingly positioned between two adjacent metal material layers.

Referring to fig. 5, some embodiments of the present application further provide a method for manufacturing a semiconductor structure according to the foregoing embodiments. The technical advantages of the semiconductor structure described in some of the foregoing embodiments are also provided by the preparation method, which is not described in detail herein. The preparation method comprises the following steps.

S100, providing a substrate having a device region, a dicing region, and a transition region between the device region and the dicing region.

And S200, forming a first sealing structure and a second sealing structure on the substrate of the transition region respectively, wherein the second sealing structure is positioned at one side of the first sealing structure far away from the device region.

Here, the first sealing structure and the second sealing structure each include: a plurality of metal layers and a plurality of support layers alternately stacked in a direction away from the substrate. The number of stacked metal layers in the second sealing structure is smaller than that in the first sealing structure.

And S300, forming a first protection layer which covers the first sealing structure and the second sealing structure.

S400, forming a second protective layer covering the first protective layer, and forming a stress relief notch in the second protective layer on the second sealing structure.

In step S100, a substrate is provided, the substrate having a device region, a dicing region, and a transition region between the device region and the dicing region.

For example, the substrate may be formed of a semiconductor material, an insulating material, a conductor material, or any combination of material types thereof. The substrate may have a single-layer structure or a multilayer structure. For example, the substrate may be a substrate such as a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate. Alternatively, the substrate 1 may be a layered substrate including, for example, a stack of Si and SiGe, a stack of Si and SiC, a silicon-on-insulator (SOI) or silicon-germanium-on-insulator, or the like.

In step S200, a first sealing structure and a second sealing structure are formed on the substrate of the transition region, respectively, where the second sealing structure is located at a side of the first sealing structure away from the device region.

For example, a plurality of metal layers and a plurality of support layers may be alternately stacked to form the first sealing structure and the second sealing structure, respectively, using a surface of one side of the cover substrate such as a film deposition process, an atomic deposition process, a thermal oxidation process, and an evaporation process. The number of the stacked layers of the metal layers in the second sealing structure is smaller than that of the stacked layers of the metal layers in the first sealing structure.

By way of example, the material of the metal layer may comprise metallic copper, metallic aluminum, metallic tungsten or metallic titanium.

In step S300, a first protective layer is formed covering the first sealing structure and the second sealing structure.

For example, a film deposition process such as a chemical vapor deposition process, a thermal oxidation process, or the like may be used to form a first protective layer over the first sealing structure and the second sealing structure.

Illustratively, the material of the first protective layer may include one or more of silicon nitride, silicon carbon nitrogen (SiCN), tetraethyl silicate (TEOS).

In step S400, a second protective layer is formed to cover the first protective layer, and a stress relief notch is formed in the second protective layer on the second sealing structure.

For example, the second protective layer may be formed by covering the first protective layer with a film deposition process such as a chemical vapor deposition process, a thermal oxidation process, or the like.

Illustratively, the material of the second protective layer may include one or more of silicon nitride, silicon carbon nitrogen (SiCN), tetraethyl silicate (TEOS).

Illustratively, an etching process is used to form a stress relief notch in the second protective layer.

Illustratively, the etched region is controlled such that the orthographic projection of the stress relief notch on the substrate falls within the orthographic projection range of the second seal structure on the substrate.

Illustratively, the etching duration is controlled such that the depth of the stress relief notch does not exceed the thickness of the second protective layer.

Preferably, a dry etching process may be used to prepare the stress relief notch. The dry etching is easy to control on the parameters of the etching area, the etching duration and the like, and the forming position and the forming depth of the obtained stress relief notch can be ensured.

Referring to fig. 6, in some embodiments, the forming a first sealing structure and a second sealing structure on a substrate in a transition region includes the following steps.

And S210, forming a metal material layer on the substrate of the transition region, and patterning the metal material layer to form a first metal layer in the first sealing structure and a first metal layer in the second sealing structure.

S220, forming a dielectric layer covering the metal layer, and forming at least one connecting through hole and/or connecting groove in the dielectric layer.

And S230, forming a metal material layer which fills the connecting through holes and/or the connecting grooves and covers the dielectric layer, patterning the metal material layer which covers the dielectric layer, forming a connecting structure which is positioned in the connecting through holes and/or the connecting grooves, and forming a second metal layer in the first sealing structure and a second metal layer in the second sealing structure.

Here, the dielectric layer and the connection structure formed in the dielectric layer together constitute a support layer.

And S240, repeating the steps of forming a dielectric layer covering the metal layer and forming at least one connecting through hole and/or connecting groove in the dielectric layer according to the number of stacked metal layers and supporting layers in the first sealing structure and the second sealing structure, forming a metal material layer filling the connecting through hole and/or connecting groove and covering the dielectric layer and patterning the metal material layer covering the dielectric layer to obtain the first sealing structure and the second sealing structure respectively.

In step S210, a metal material layer is formed on the substrate in the transition region, and the metal material layer is patterned to form a first metal layer in the first sealing structure and a first metal layer in the second sealing structure.

Illustratively, a metal material layer is formed on the substrate surface in the transition region using a process such as metal film deposition, atomic layer deposition, physical vapor deposition, electroplating, and the like.

By way of example, the material of the metallic material layer may comprise metallic copper, metallic aluminum, metallic tungsten or metallic titanium.

Illustratively, an etching process is performed on the metal material layer to form a first metal layer in the first seal structure and a first metal layer in the second seal structure. Alternatively, the width of the first metal layer in the first sealing structure in the parallel substrate direction may be made larger than the width of the first metal layer in the first sealing structure in the parallel substrate direction.

In step S220, a dielectric layer covering the metal layer is formed, and at least one connection via and/or connection trench is formed in the dielectric layer.

Here, the number of connection vias and connection trenches formed in the same dielectric layer may vary depending on the semiconductor device structure and design requirements.

In some embodiments, at least one connection via is formed in the dielectric layer.

For example, a plurality of connection through holes may be formed, and the plurality of connection through holes are arranged in an array.

In other embodiments, at least one connection trench is formed in the dielectric layer.

Illustratively, the connecting grooves are formed as an orthographic projection of an elongated or closed loop shape on the substrate.

In still other embodiments, at least one connection via and at least one connection trench are formed in the dielectric layer.

For example, a plurality of connection through holes and a plurality of connection trenches may be formed. The connection through holes and the connection grooves may be arranged at intervals. The application is not limited in this regard.

For example, a dielectric layer may be formed on the surface of the metal layer using, for example, a film deposition process, a thermal oxidation process, or a chemical vapor deposition process.

For example, an etching process may be used to form the connection via and/or the connection trench in the dielectric layer, and the etching duration may be controlled such that a portion of the metal layer may be exposed by the connection via and/or the connection trench.

In step S230, a metal material layer filling the connection via and/or the connection trench and covering the dielectric layer is formed, and the metal material layer covering the dielectric layer is patterned, to form a connection structure located in the connection via and/or the connection trench, and a second metal layer in the first sealing structure and a second metal layer in the second sealing structure.

Illustratively, the connecting via and/or the connecting trench are filled and a metal material layer is formed overlying the dielectric layer surface using a process such as metal film deposition, atomic layer deposition, physical vapor deposition, electroplating, and the like.

It is worth to say that the second metal layer and the connecting structure below the second metal layer are made of the same material, based on the same process and prepared synchronously. That is, the second metal layer and the connecting structure below the second metal layer are integrated.

In step S240, the steps of forming a dielectric layer covering the metal layer and forming at least one connection via and/or connection trench in the dielectric layer, forming a metal material layer filling the connection via and/or connection trench and covering the dielectric layer, and patterning the metal material layer covering the dielectric layer are repeated according to the number of stacked metal layers and supporting layers in the first sealing structure and the second sealing structure, so as to obtain the first sealing structure and the second sealing structure, respectively.

For example, the number of repeated execution of each step is determined in accordance with the design requirement of the semiconductor device, and the first sealing structure and the second sealing structure having different stacked number of metal layers are obtained, respectively. The number of the stacked layers of the metal layers in the second sealing structure is smaller than that of the stacked layers of the metal layers in the first sealing structure.

Referring to fig. 8, in some embodiments, the substrate further has a doped region. The manufacturing method further includes steps S110 and S120 before forming the first sealing structure and the second sealing structure.

S110, forming an insulating layer on the substrate of the doped region, and forming a plurality of contact through holes in the insulating layer.

S120, forming a contact plug in the contact through hole.

Here, the first sealing structure and the second sealing structure are formed on the insulating layer, respectively. The first metal layer in the first sealing structure and the second sealing structure can be connected with the doped region through the contact plug.

In step S110, an insulating layer is formed on the substrate of the doped region, and a plurality of contact vias are formed in the insulating layer.

Illustratively, the material of the insulating layer includes an oxide, nitride, or oxynitride.

Optionally, after forming the insulating layer, a planarization operation may also be performed on the insulating layer to facilitate obtaining good surface quality, and forming the first sealing structure and the second sealing structure based on the surface.

With continued reference to fig. 7, in some embodiments, after forming the first protective layer and before forming the second protective layer, the preparation method further includes steps S310 and S320.

S310, forming a connection opening in the first protection layer, wherein the connection opening exposes a part of the top metal layer in the first sealing structure.

Here, the orthographic projection of the connection opening on the substrate falls within the orthographic projection range of the top metal layer on the substrate in the first sealing structure.

S320, forming an electrostatic protection layer which fills the connection opening and covers the surface of the first protection layer part.

Here, the second protection layer covers the electrostatic protection layer and a portion of the first protection layer not covered by the electrostatic protection layer.

Furthermore, in the above embodiments of the present application, the steps of the method are not strictly limited to the order of execution unless explicitly stated herein, and the steps may not necessarily be executed in the order described, but may be executed in other manners. Moreover, at least a portion of the steps of any one of the steps may include a plurality of sub-steps or stages that are not necessarily performed at the same time, but may be performed at different times, nor does the order in which the sub-steps or stages are performed necessarily occur sequentially, but may be performed alternately or alternately with at least a portion of the sub-steps or stages of other steps or other steps.

In order to more clearly illustrate the preparation methods of the semiconductor structures in some of the above embodiments, some of the following embodiments describe the preparation methods of some semiconductor structures in detail with reference to fig. 9 to 21.

In step S100, referring to fig. 9, a substrate 1 is provided, the substrate 1 having a device region A1, a dicing region A3, and a transition region A2 between the device region A1 and the dicing region A3.

To clearly illustrate the fabrication process of the semiconductor structure described in some embodiments of the present application, some of the following figures mainly illustrate the semiconductor structure located in the transition region A2.

In step S110, referring to fig. 10, an insulating layer 5 is formed on the substrate 1 of the doped region 11, and a plurality of contact vias H2 are formed in the insulating layer 5.

Illustratively, the material of the insulating layer 5 comprises an oxide, nitride or oxynitride.

Alternatively, after the insulating layer 5 is formed, a planarization operation is performed on the insulating layer 5.

In step S120, referring to fig. 10 and 11, a contact plug 6 is formed in the contact via H2.

Illustratively, a physical vapor deposition process is employed to fill the contact via H2 with a metallic tungsten material to form the contact plug 6.

Alternatively, after the contact plug 6 is formed, a planarization operation is performed on the insulating layer 5.

In step S200, a first sealing structure 21 and a second sealing structure 22 are formed on the substrate 1 of the transition region 11, respectively, and the second sealing structure 22 is located at a side of the first sealing structure 21 away from the device region A1.

Here, the first sealing structure 21 and the second sealing structure 22 each include: a plurality of metal layers 23 and a plurality of support layers 24 are alternately laminated in a direction away from the substrate 1.

Illustratively, step S200 includes steps S210-S240.

In step S210, referring to fig. 12 and 13, a metal material layer 23 'is formed on the substrate 1 in the transition region 11, and the metal material layer 23' is patterned to form a first metal layer 23 in the first sealing structure 21 and a first metal layer 23 in the second sealing structure 22.

Here, in some embodiments, the first sealing structure 21 and the second sealing structure 23 are also formed on the insulating layer 5, respectively. Accordingly, a metal material layer 23' is formed on the insulating layer 5.

In step S220, referring to fig. 14 and 15, a dielectric layer 241 covering the metal layer 23 is formed, and at least one connection via H1 and/or connection trench TR1 is formed in the dielectric layer 241.

Here, the arrangement form of the connection via H1 and the connection trench TR1 in the same dielectric layer 241 is different in accordance with the structure and design requirements of the semiconductor device.

Referring to fig. 15 (a), in some embodiments, at least one connection via H1 is formed in the dielectric layer 241. For example, the number of the connection via holes H1 may be plural, and the plural connection via holes H1 may be uniformly distributed in the dielectric layer 241 between the adjacent metal layers. For example, the plurality of connection through holes H1 may be distributed in an array.

Referring to fig. 15 (b), in other embodiments, at least one connection trench TR1 is formed in the dielectric layer 241. For example, the connection groove TR1 may have a rectangular shape, a closed ring shape, or the like in front projection on the substrate 1.

Illustratively, the range of values of the width of the connection trench TR1 includes: 0.34 μm to 0.39 μm. For example 0.34 μm, 0.36 μm or 0.39 μm.

Referring to fig. 15 (c), in further embodiments, at least one connection via H1 and at least one connection trench TR1 are formed in the dielectric layer 241. Illustratively, the number of the connection through holes H1 and the connection grooves TR1 is plural, and the connection through holes H1 and the connection grooves TR1 may be arranged at intervals from each other. The application is not limited in this regard.

In step S230, referring to fig. 16 and 17, a metal material layer 23 'filling the connection via H1 and/or the connection trench TR1 and covering the dielectric layer 241 is formed, and the metal material layer 23' covering the dielectric layer 241 is patterned, and a connection structure 242 located in the connection via H1 and/or the connection trench TR1, and the second metal layer 23 in the first sealing structure 21 and the second metal layer 23 in the second sealing structure 22 are formed.

For example, the connection via H1 and/or the connection trench TR1 may be filled with a metal material using an atomic layer deposition, physical vapor deposition, electroplating, or the like to form the metal material layer 23'.

By way of example, the metallic material may include metallic aluminum, metallic copper, or metallic tungsten.

In step S240, referring to fig. 18, the steps of forming a dielectric layer 241 covering the metal layer 23 and forming at least one connection via H1 and/or a connection trench TR1 in the dielectric layer 241, and forming a metal material layer filling the connection via H1 and/or the connection trench TR1 and covering the dielectric layer 241 and patterning the metal material layer 23' covering the dielectric layer 241 are repeated according to the number of stacked layers of the metal layer 23 and the support layer 24 in the first seal structure 21 and the second seal structure 22, so as to obtain the first seal structure 21 and the second seal structure 22, respectively.

Illustratively, repeating the foregoing steps forms a first seal structure 21 comprising 9 metal layers 23 and a second seal structure 22 comprising 8 metal layers 23.

In step S300, referring to fig. 19, a first protective layer 3 is formed to cover the first sealing structure 21 and the second sealing structure 22.

For example, the first protective layer 3 may be formed to cover the first sealing structure 21, the second sealing structure 22, and the exposed portion of the dielectric layer 241 using a film deposition process, a thermal oxidation process, a chemical vapor deposition process, or the like.

By way of example, the first protective layer 3 may include one or more of a silicon nitride layer, a silicon carbon nitrogen layer (SiCN), a tetraethyl silicate layer (TEOS). In order to more clearly express the relative positional relationship between the first protective layer 3 and the electrostatic protection layer and the second protective layer, the first protective layer 3 is illustrated in a single-layer structure in the drawing.

In step S310, referring to fig. 19, a connection opening G2 is formed in the first protection layer 3, and the connection opening G2 exposes a portion of the top metal layer 23 in the first sealing structure 21.

Illustratively, the connection opening G2 is formed in the first protection layer 3 by using an etching process, and the metal layer 23 is used as a stop layer for etching by virtue of the selectivity of the etching process, so that the connection opening G2 can accurately expose a portion of the top metal layer 23 in the first sealing structure 21.

In step S320, referring to fig. 20, an electrostatic protection layer 7 is formed to fill the connection opening G2 and cover a portion of the surface of the first protection layer 3.

For example, an electrostatic protection material layer filling the connection opening G2 and covering the surface of the first protection layer 3 may be formed by using an atomic layer deposition, a metal film deposition, a physical vapor deposition, or the like, and the electrostatic protection material layer may be patterned to obtain the electrostatic protection layer 7 covering a portion of the surface of the first protection layer 3.

The material forming the electrostatic protection layer 7 may be a metal material, for example, metal copper, metal aluminum, metal tungsten, or metal titanium, for example. Preferably, the material forming the electrostatic protection layer 7 is metallic aluminum.

In step S400, referring to fig. 21, a second protection layer 4 is formed to cover the first protection layer 3, and a stress relief notch G1 is formed in the second protection layer 4 on the second sealing structure 22.

For example, the second protective layer 4 may be formed by covering the surface of the first protective layer 3 with a film deposition process, a thermal oxidation process, a chemical vapor deposition process, or the like.

By way of example, the second protective layer 4 may include one or more of a silicon nitride layer, a silicon carbon nitrogen layer (SiCN), a tetraethyl silicate layer (TEOS). In order to more clearly express the relative positional relationship between the second protective layer 4 and the electrostatic protection layer 7 and the stress relief notch G1, the second protective layer 4 is illustrated in a single-layer structure in the drawing.

For example, a dry etching process may be used to form the stress relief notch G1 in the second protection layer 4, and by controlling the etching area and the etching duration, the orthographic projection of the stress relief notch G1 on the substrate 1 falls within the orthographic projection range of the second sealing structure 22 on the substrate 1, and the depth of the stress relief notch G1 does not exceed the thickness of the second protection layer 4.

With continued reference to fig. 4, it should be added that each film layer in the transition region A2 may be disposed in the same layer as the corresponding film layer in the device region A1, and prepared simultaneously.

Illustratively, metal layer 23 is located in device region A1 _A Dielectric layer 241 in device region A1 corresponding to metal layer 23 in first seal structure 21 _A The dielectric layer 241 corresponding to the first sealing structure 21 and the re-wiring layer 8 in the device region A1 and the electrostatic protection layer 7 in the first sealing structure 21 may be formed based on the same material, and may be formed in the same layer and simultaneously.

In the embodiment of the application, a semiconductor structure and a preparation method thereof are provided, and the design improvement of the semiconductor structure is realized. The unexpected effect is: when the semiconductor structure receives the cutting stress from the cutting area A3, the stress is sequentially transferred to the second sealing structure 22 and the stress relief notch G1 near the outer side; and then to the first sealing structure 21 near the inner side. By means of the notch effect and the blocking effect provided by the second sealing structure 22 and the first sealing structure 21, stresses are greatly reduced until eliminated, so that damage to the semiconductor device located in the device region A1 is effectively avoided. In addition, the number of the metal layers 23 and the thicknesses of the first protective layer 3 and the second protective layer 4 in different areas are controlled, so that the stress relief notch G1 is correspondingly arranged in the second protective layer 4 above the second sealing structure 22, and a larger interval between the bottom of the stress relief notch G1 and the top-most metal layer 23 in the second sealing structure 22 is ensured, and therefore, the situation that the bottom of the stress relief notch G1 is opened and the lower metal layer 23 is exposed due to accidents in the preparation process can be effectively avoided; and further, external water vapor, impurities or free charges and the like can be prevented from entering the device region A1 through the stress release notch G1, so that the performance stability of the semiconductor device in the device region A1 is ensured and improved.

In the description of the present specification, reference to the terms "some embodiments," "other embodiments," "desired embodiments," and the like, means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the application. In this specification, schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

The technical features of the above embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.

The above examples merely represent a few embodiments of the present application, which are described in more detail and are not to be construed as limiting the scope of the application. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the application, which are all within the scope of the application. Accordingly, the scope of protection of the present application is to be determined by the appended claims.

Claims

1. A semiconductor structure, comprising:

a substrate having a device region, a dicing region, and a transition region between the device region and the dicing region;

the first sealing structure and the second sealing structure are respectively positioned in the transition region, and the second sealing structure is positioned at one side of the first sealing structure far away from the device region;

a first protective layer covering the first sealing structure and the second sealing structure;

a second protective layer covering the first protective layer;

wherein, the first seal structure and the second seal structure each include: a plurality of metal layers and a plurality of support layers alternately stacked in a direction away from the substrate; the number of the stacked layers of the metal layers in the second sealing structure is smaller than that of the stacked layers of the metal layers in the first sealing structure; the second protective layer on the second sealing structure is provided with a stress relief notch.

2. The semiconductor structure of claim 1, wherein a depth of the stress relief notch is less than a thickness of the second protective layer.

3. The semiconductor structure of claim 1, wherein the support layer comprises:

The dielectric layer is positioned between adjacent metal layers and is provided with at least one connecting through hole and/or connecting groove;

the connecting structure is arranged in the connecting through hole and/or the connecting groove and is connected with the metal layer adjacent to the dielectric layer;

the radial dimensions of the connecting through holes in the supporting layers are the same.

4. The semiconductor structure of claim 3, wherein the substrate of the transition region further has a doped region; the semiconductor structure further includes:

the insulating layer is arranged between the doped region and the first sealing structure and between the doped region and the second sealing structure; the insulating layer is provided with a plurality of contact through holes;

and the contact plug is arranged in the contact through hole and is connected with the doped region adjacent to the insulating layer and the metal layer.

5. The semiconductor structure of claim 4, wherein the support layer comprises a connection via; the radial dimension of the contact through hole is the same as the radial dimension of the connection through hole in the supporting layer.

6. The semiconductor structure of claim 5, further comprising:

the electrostatic protection layer is positioned between the first protection layer and the second protection layer, penetrates through the first protection layer and is connected with the corresponding metal layer in the first sealing structure.

7. A method of fabricating a semiconductor structure, comprising:

providing a substrate, wherein the substrate is provided with a device region, a cutting region and a transition region between the device region and the cutting region;

forming a first sealing structure and a second sealing structure on the substrate of the transition region respectively, wherein the second sealing structure is positioned at one side of the first sealing structure far away from the device region; the first seal structure and the second seal structure each include: a plurality of metal layers and a plurality of support layers alternately stacked in a direction away from the substrate; the number of the stacked layers of the metal layers in the second sealing structure is smaller than that of the stacked layers of the metal layers in the first sealing structure;

forming a first protective layer covering the first sealing structure and the second sealing structure;

8. The method of manufacturing a semiconductor structure according to claim 7, wherein forming a first sealing structure and a second sealing structure on the substrate in the transition region, respectively, comprises:

Forming a metal material layer on the substrate of the transition region, patterning the metal material layer, and forming a first layer of the metal layer in the first sealing structure and a first layer of the metal layer in the second sealing structure;

forming a dielectric layer covering the metal layer, and forming at least one connecting through hole and/or connecting groove in the dielectric layer;

forming a metal material layer which fills the connecting through holes and/or the connecting grooves and covers the dielectric layer, patterning the metal material layer which covers the dielectric layer, forming a connecting structure in the connecting through holes and/or the connecting grooves, and forming a second layer of the metal layer in the first sealing structure and a second layer of the metal layer in the second sealing structure; the medium layer and the connecting structure formed in the medium layer jointly form the supporting layer;

repeating the steps of forming a dielectric layer covering the metal layer and forming at least one connecting through hole and/or connecting groove in the dielectric layer according to the number of stacked layers of the metal layer and the supporting layer in the first sealing structure and the second sealing structure, forming a metal material layer filling the connecting through hole and/or connecting groove and covering the dielectric layer, and patterning the metal material layer covering the dielectric layer to obtain the first sealing structure and the second sealing structure respectively.

9. The method of fabricating a semiconductor structure of claim 7, wherein the substrate further has a doped region; before forming the first sealing structure and the second sealing structure, the preparation method further comprises:

forming an insulating layer on the substrate of the doped region, and forming a plurality of contact through holes in the insulating layer;

forming a contact plug in the contact through hole;

wherein the first sealing structure and the second sealing structure are respectively formed on the insulating layer; the metal layer of the first layer in the first sealing structure and the second sealing structure is connected with the doped region through the contact plug.

10. The method of manufacturing a semiconductor structure according to claim 7, wherein after forming the first protective layer and before forming the second protective layer, the method further comprises:

forming a connection opening in the first protection layer, wherein the connection opening exposes a part of the metal layer on the top layer in the first sealing structure;

forming an electrostatic protection layer filling the connection opening and covering the surface of the first protection layer part;

wherein the second protective layer covers the electrostatic protection layer and the part of the first protective layer not covered by the electrostatic protection layer.