CN117131915A

CN117131915A - Method, equipment and medium for artificial intelligent computation

Info

Publication number: CN117131915A
Application number: CN202311189484.4A
Authority: CN
Inventors: 李承逸
Original assignee: Individual
Current assignee: Individual
Priority date: 2023-09-15
Filing date: 2023-09-15
Publication date: 2023-11-28

Abstract

The application aims to provide a method, equipment and medium for artificial intelligence calculation, wherein the method comprises the following steps: obtaining input information for artificial intelligence computation; and inputting the input information into a first artificial intelligent circuit, so that an artificial intelligent computing unit in the first artificial intelligent circuit performs artificial intelligent computation through an analog circuit technology instead of a digital circuit technology to obtain a decision vector corresponding to the input information. The application performs artificial intelligence calculation in the form of analog signals, which can remarkably reduce the calculation time required for executing artificial intelligence. Furthermore, the present application may also allow a significant reduction in the amount of hardware required to create a chip. The present application also employs a method of expanding the size of an artificial intelligence system by cascading chips in which the artificial intelligence computation performed by the method is a real-time computation without waiting for software intervention, and thus, the present application can accelerate the artificial intelligence computation for very large AI systems.

Description

Method, equipment and medium for artificial intelligent computation

Technical Field

The application relates to the field of communication, in particular to a technology for artificial intelligent computing.

Background

The neural network structure is converted into matrix calculation, and mathematicians well simulate the functions of the human brain. This modeling produces a large number of matrix calculations, and in deep learning systems, nonlinear processing of individual parameters is also introduced, large-sized matrices often result in very slow artificial intelligence calculations.

The solution to this computational problem is a large scale logic chip that performs the computation in parallel and pipelined fashion as quickly as possible, combining multiple GPU chips together to compute a large matrix is one approach currently employed, another approach is to reduce the accuracy of the computation to accommodate more parallel ALUs in a single chip like TPU, the digital system for representing the parameters is sometimes reduced to 8 bits to have more parallel computation logic on a single chip, such a reduction in accuracy is possible in an artificial intelligence system because the artificial intelligence computation does not require accuracy to make the decision. On the other hand, computational methods for scientific computation often require the use of floating point coprocessors to produce very accurate results. However, this type of exact calculation is not necessary in artificial intelligence systems, as each parameter of thousands of neurons need only carry a "preference" or "selection" throughout the decision-making process. For example, an artificial intelligence system that detects the number of circles in a drawing does not care about the size of each circle.

The most time-consuming part of the computation in an artificial intelligence matrix is the process of multiplying, adding, and mapping each parameter using a nonlinear Sigmoid normalization curve, the matrix size can be very large for extreme cases of artificial intelligence problems, and the digital computation of such a system becomes almost impossible to perform, the fastest method of digital multiplication is the wales tree, which is a large hardware, requiring multiple multiplications in parallel methods, and many gate delays. Adding the results of the multiplication also requires a number of stages of adders. This may be a slow process.

Disclosure of Invention

It is an object of the present application to provide a method, apparatus and medium for artificial intelligence computing.

According to one aspect of the present application, there is provided a method for artificial intelligence computing, the method comprising:

obtaining input information for artificial intelligence computation;

and inputting the input information into a first artificial intelligent circuit, so that an artificial intelligent computing unit in the first artificial intelligent circuit performs artificial intelligent computation through an analog circuit technology instead of a digital circuit technology to obtain a decision vector corresponding to the input information.

According to one aspect of the present application, there is provided an apparatus for artificial intelligence computation, the apparatus comprising:

the module is used for obtaining input information for artificial intelligence calculation;

and the two-module is used for inputting the input information into the first artificial intelligent circuit so that an artificial intelligent computing unit in the first artificial intelligent circuit performs artificial intelligent computation through an analog circuit technology instead of a digital circuit technology to obtain a decision vector corresponding to the input information.

According to one aspect of the present application, there is provided a computer device for artificial intelligence computing, the device comprising:

a processor; and

a memory arranged to store computer executable instructions which, when executed, cause the processor to perform the steps of any of the methods described above.

According to one aspect of the present application there is provided a computer readable storage medium having stored thereon a computer program/instruction which, when executed, causes a system to perform the steps of a method as described in any of the above.

According to one aspect of the present application there is provided a computer program product comprising computer programs/instructions which when executed by a processor implement the steps of a method as described in any of the preceding.

Compared with the prior art, the application obtains the input information for artificial intelligence calculation; and inputting the input information into a first artificial intelligence circuit, so that an artificial intelligence calculation unit in the first artificial intelligence circuit performs artificial intelligence calculation through an analog circuit technology instead of a digital circuit technology to obtain a decision vector corresponding to the input information, and thus the calculation time required for executing artificial intelligence can be remarkably reduced through performing artificial intelligence calculation in the form of analog signals. Furthermore, the present application may also allow a significant reduction in the amount of hardware required to create a chip. The present application also employs a method of expanding the size of an artificial intelligence system by cascading chips in which the artificial intelligence computation performed by the method is a real-time computation without waiting for software intervention, and thus, the present application can accelerate the artificial intelligence computation for very large AI systems.

Drawings

Other features, objects and advantages of the present application will become more apparent upon reading of the detailed description of non-limiting embodiments, made with reference to the accompanying drawings in which:

FIG. 1 illustrates a flow chart of a method for artificial intelligence computation according to one embodiment of the application;

FIG. 2 illustrates a block diagram of an apparatus for artificial intelligence computing in accordance with one embodiment of the application;

FIG. 3 shows a schematic diagram of a mathematical formula for a neural network;

FIG. 4 shows a schematic diagram of an artificial intelligence circuit for cascading in accordance with one embodiment of the present application;

FIG. 5 shows a schematic circuit diagram of a D-A converter for obtaining an analog signal according to one embodiment of the application;

FIG. 6 shows a schematic circuit diagram of an analog addition unit according to an embodiment of the application;

FIG. 7 shows a schematic circuit diagram of another analog addition unit of an embodiment of the present application;

FIG. 8 shows a schematic circuit diagram of a comparator unit for obtaining a decision vector according to one embodiment of the application;

FIG. 9 shows a schematic circuit diagram of an analog multiplication unit according to one embodiment of the present application;

FIG. 10 shows a schematic circuit diagram of an analog activation function filter unit according to one embodiment of the application;

FIG. 11 shows a schematic of an analog adder of one embodiment of the present application;

FIG. 12 shows a schematic of an analog multiplier according to one embodiment of the present application;

FIG. 13 shows a schematic of an analog adder of one embodiment of the application;

FIG. 14 is a schematic circuit diagram of a multiple analog input selection unit according to one embodiment of the application;

FIG. 15 illustrates an exemplary system that may be used to implement various embodiments described in the present application.

The same or similar reference numbers in the drawings refer to the same or similar parts.

Description of the embodiments

The application is described in further detail below with reference to the accompanying drawings.

In one exemplary configuration of the application, the terminal, the device of the service network, and the trusted party each include one or more processors (e.g., central processing units (Central Processing Unit, CPU)), input/output interfaces, network interfaces, and memory.

The Memory may include non-volatile Memory in a computer readable medium, random access Memory (Random Access Memory, RAM) and/or non-volatile Memory, etc., such as Read Only Memory (ROM) or Flash Memory (Flash Memory). Memory is an example of computer-readable media.

Computer readable media, including both non-transitory and non-transitory, removable and non-removable media, may implement information storage by any method or technology. The information may be computer readable instructions, data structures, modules of a program, or other data. Examples of storage media for a computer include, but are not limited to, phase-Change Memory (PCM), programmable Random Access Memory (Programmable Random Access Memory, PRAM), static Random Access Memory (SRAM), dynamic Random Access Memory (Dynamic Random Access Memory, DRAM), other types of Random Access Memory (RAM), read-Only Memory (ROM), electrically erasable programmable read-Only Memory (EEPROM), flash Memory or other Memory technology, read-Only Memory (Compact Disc Read-Only Memory, CD-ROM), digital versatile disks (Digital Versatile Disc, DVD) or other optical storage, magnetic cassettes, magnetic tape storage or other magnetic storage devices, or any other non-transmission medium, which can be used to store information that can be accessed by the computing device.

The device includes, but is not limited to, a user device, a network device, or a device formed by integrating a user device and a network device through a network. The user equipment includes, but is not limited to, any mobile electronic product which can perform man-machine interaction with a user (for example, perform man-machine interaction through a touch pad), such as a smart phone, a tablet computer and the like, and the mobile electronic product can adopt any operating system, such as an Android operating system, an iOS operating system and the like. The network device includes an electronic device capable of automatically performing numerical calculation and information processing according to a preset or stored instruction, and the hardware includes, but is not limited to, a microprocessor, an application specific integrated circuit (Application Specific Integrated Circuit, ASIC), a programmable logic device (Programmable Logic Device, PLD), a field programmable gate array (Field Programmable Gate Array, FPGA), a digital signal processor (Digital Signal Processor, DSP), an embedded device, and the like. The network device includes, but is not limited to, a computer, a network host, a single network server, a plurality of network server sets, or a cloud of servers; here, the Cloud is composed of a large number of computers or network servers based on Cloud Computing (Cloud Computing), which is a kind of distributed Computing, a virtual supercomputer composed of a group of loosely coupled computer sets. Including but not limited to the internet, wide area networks, metropolitan area networks, local area networks, VPN networks, wireless Ad Hoc networks (Ad Hoc networks), and the like. Preferably, the device may be a program running on the user device, the network device, or a device formed by integrating the user device and the network device, the touch terminal, or the network device and the touch terminal through a network.

Of course, those skilled in the art will appreciate that the above-described devices are merely examples, and that other devices now known or hereafter may be present as applicable to the present application, and are intended to be within the scope of the present application and are incorporated herein by reference.

In the description of the present application, the meaning of "a plurality" is two or more unless explicitly defined otherwise.

FIG. 1 shows a flow chart of a method for artificial intelligence computation, the method comprising steps S11 and S12, according to an embodiment of the application. In step S11, input information for artificial intelligence calculation is obtained; in step S12, the input information is input to a first artificial intelligence circuit, so that an artificial intelligence calculation unit in the first artificial intelligence circuit performs artificial intelligence calculation through an analog circuit technology instead of a digital circuit technology, and a decision vector corresponding to the input information is obtained.

In step S11, input information for artificial intelligence computation is obtained. In some embodiments, the input information includes, but is not limited to, a weight matrix, a bias vector, and an input vector. In some embodiments, the input information is in digital form, and is required to be stored in a register via a data bus from the CPU, from which it is required to be retrieved. In some embodiments, the artificial intelligence computation is to compute artificial intelligence decision values using a weight matrix, a bias vector, and an input event vector, the weight matrix and bias vector typically being determined by the learning process of the AI and giving the final value prior to the AI computation, the artificial intelligence computation involving many multiplications and additions, typically requiring the AI to perform the artificial intelligence computation as quickly as possible to provide decision points to the digital system, the decision points being represented by decision vectors.

In step S12, the input information is input to a first artificial intelligence circuit, so that an artificial intelligence calculation unit in the first artificial intelligence circuit performs artificial intelligence calculation through an analog circuit technology instead of a digital circuit technology, and a decision vector corresponding to the input information is obtained. In some embodiments, the first artificial intelligence circuit includes an artificial intelligence calculation unit for performing artificial intelligence calculations (AI calculations, matrix calculations) using analog circuit techniques instead of using conventional analog circuit techniques to perform the artificial intelligence calculations, thereby enabling the artificial intelligence calculations to be implemented with a smaller amount of hardware and also enabling the calculation speed of the artificial intelligence calculations to be increased. In some embodiments, the first artificial intelligence circuit further comprises a digital circuit such as a register, a data bus, or the like. In some embodiments, the artificial intelligence computing analog circuitry includes, but is not limited to, modules such as an analog add unit, an analog multiply unit, an analog activate function filter unit, and the like. In some embodiments, the digital input information is required to be converted into a corresponding analog signal, and then the analog signal is input into the first artificial intelligence circuit, so that the artificial intelligence calculation is performed in the artificial intelligence calculation analog circuit in the first artificial intelligence circuit through the form of the analog signal, or the digital input information can be directly input into the first artificial intelligence circuit, the digital input information is firstly converted into the corresponding analog signal in the first artificial intelligence circuit, and then the analog signal is input into the artificial intelligence calculation analog circuit in the first artificial intelligence circuit, and the artificial intelligence calculation is performed in the artificial intelligence calculation analog circuit through the form of the analog signal. In some embodiments, the first artificial intelligence circuit directly outputs the analog-form calculation result obtained by the artificial intelligence calculation analog circuit, and then the calculation result needs to be converted into the corresponding digital-form decision vector, or the first artificial intelligence circuit converts the analog-form calculation result obtained by the artificial intelligence calculation analog circuit into the corresponding digital-form decision vector, and then the first artificial intelligence circuit directly outputs the decision vector. In some embodiments, as an example, fig. 3 shows a matrix formulation description of artificial intelligence computation of a typical machine learning system, where the input vector is Xj, the neural network is a weight matrix Wij, the bias vector of the adjustment decision process is bi, the decision vector is yi, in the artificial intelligence system, the input vector is a plurality of input samples, the first input vector in this scheme refers to one of the input samples, the decision vector is generated by adding the bias vector to the optimized weight matrix, the optimal decision process is to provide the optimal regression result, and the weight matrix and the bias vector are determined by the learning process. In some embodiments, the entire artificial intelligence computation process is performed in the form of analog signals, which are computed without any digital world (e.g., CPU) intervention. In some embodiments, the accuracy of the analog signal depends on two factors: the amplitude exceeding the noise level and the linearity of the analog signal processing. As long as the signal level is higher than 10 MV, the analog signal can maintain good accuracy. The analog circuit can maintain good linearity over a limited voltage range. The application performs artificial intelligence calculation in the form of analog signals, which can remarkably reduce the calculation time required for executing artificial intelligence.

In some embodiments, the artificial intelligence computing unit includes an artificial intelligence computing analog circuit including an analog addition unit, an analog multiplication unit, and an analog activation function filtering unit. In some embodiments, the artificial intelligence computing unit includes analog circuitry for artificial intelligence computing (i.e., artificial intelligence computing analog circuitry). In some embodiments, the artificial intelligence computing analog circuit includes an analog addition unit (analog adder), an analog multiplication unit (analog multiplier), an analog activation function filter unit (e.g., analog Sigmoid converter) for limiting the output of the computing result to within a boundary value of a certain fixed value (e.g., one volt) using an exponential curve.

In some embodiments, the analog multiplication unit is a single logic gate and the analog addition unit is a single logic gate. The largest hardware in artificial intelligence computing (matrix operation) is the logic multiplier in the conventional system made of logic gates, each logic multiplier having about 30 gates to perform multiplication when the X input vector has seven digital bits of one sign bit and the W weight matrix also has seven digital bits of one sign bit, and 3 million gates are required for such parallel multiplication when the matrix size is 1000X 100. In this scheme, the analog multiplication unit is a single logic gate, and since 1 gate corresponds to 1000X 100 matrix elements, 290 ten thousand gates can be immediately saved. When performing the addition after multiplication we need 100000 digital logic adders, which is another large amount of hardware in the traditional digital logic gates, in this solution the analog addition unit is a single logic gate, and at least ten numbers can be added with a single gate, the speed of addition is significantly faster than in the traditional logic adders. In this scheme, since multiplication is performed in one multiplier gate and addition is performed in one adder gate, the calculation speed is very fast.

In some embodiments, the first artificial intelligence circuit includes a D-a converter and an a-D converter; wherein, the step S12 includes: inputting the input information into the D-A converter to obtain an output analog signal; inputting the analog signal into the artificial intelligence computing analog circuit to obtain an output decision analog signal; and inputting the decision analog signal into the A-D converter to obtain an output decision vector. In some embodiments, the D-a converter is configured to convert a digital signal to an analog signal, and the a-D converter is configured to convert the analog signal to a digital signal. In some embodiments, after the input signal in digital form is input into the first artificial intelligence circuit, the a-D converter in the first artificial intelligence circuit will convert the input information in digital form into a corresponding analog signal, then the analog information signal is input into an artificial intelligence computing analog circuit composed of an analog adding unit, an analog multiplying unit and an analog activating function filtering unit, so as to obtain a decision analog signal output by the analog computing analog circuit, then the decision analog signal is input into the D-a converter and is reconverted into a decision vector in digital form, and the signal is distorted by the analog activating function filtering unit, so that it is meaningless to convert the analog signal into an accurate digital signal, and in normal artificial intelligence application, the result is represented by a digital state of 0 or 1. In some embodiments, only 7 logic gates are used per D-a converter, which hardware cost is easily compensated by the hardware savings for digital multipliers and digital adders that cost most of the hardware in digital artificial intelligence systems, in which case analog multipliers and analog adders are single logic gates, which can save a lot of hardware. In some embodiments, another way to eliminate the hardware cost is to eliminate the registers needed to store the weight matrix, which can be achieved by using an analog ROM that stores the resistance value of the corresponding weight resistor (Rax) in the circuit of the D-a converter for each parameter by changing the resistor size according to the weight matrix, which can reduce the amount of hardware used by the D-a converter to about 10%. The application can enable the amount of hardware required to create a chip to be significantly reduced. In some embodiments, the decision vector in digital form output by the first artificial intelligence circuit may be stored in a digital register, the CPU may read the decision vector in the digital register and input the decision vector as input information to an artificial intelligence circuit of a later stage, and the a-D converter in the artificial intelligence circuit of the later stage converts the decision vector in digital form into a corresponding first analog signal and inputs it to an artificial intelligence calculation analog circuit in the artificial intelligence circuit of the later stage.

In some embodiments, the analog signal is located within a preset voltage interval centered around a zero reference voltage, wherein the zero reference voltage is a voltage less than a preset difference in supply voltage. In some embodiments, the analog signal is located within a preset voltage interval centered around a zero reference Voltage (VCC), i.e., the voltage value corresponding to the interval center of the preset voltage interval is zero reference voltage (or may also be referred to as neutral voltage), which is a default voltage lower than the power supply Voltage (VCC) by a preset difference (e.g., 4V). In some embodiments, the amplitude of the analog signal increases from the zero voltage point to the positive or negative end of the preset voltage interval, just like a sequential analog signal, with the idea of converting the digital signal to a normal analog signal for computation using analog circuitry. In some embodiments, the present application can maintain the continuity of the overall analog circuit calculation by limiting the analog signal to a preset voltage interval centered around zero reference voltage.

In some embodiments, the preset difference is 4 volts, and the preset voltage interval is a voltage interval from 1 volt below the zero reference voltage to 1 volt above the zero reference voltage. In some embodiments, the zero reference voltage is a default voltage 4V lower than the supply Voltage (VCC), and the first analog signal is within a preset voltage interval of [ zero reference voltage-1V, zero reference voltage +1v ]. In some embodiments, the preset difference is 3 volts, and the preset voltage interval is a voltage interval from 0.8 volts below the zero reference voltage to 0.8 volts above the zero reference voltage. In some embodiments, the zero reference voltage is a default voltage 3V lower than the supply Voltage (VCC), and the first analog signal is within a preset voltage interval of [ zero reference voltage-0.8V, zero reference voltage +0.8V ]. The above-mentioned preset difference and preset voltage interval are only examples, and are not limiting to the specific embodiment of the present application, and the preset difference and the preset voltage interval may be set to any values.

In some embodiments, the input information includes a first input vector, a weight matrix, a bias vector; wherein the inputting the input information into the D-a converter to obtain an output analog signal includes: respectively inputting a first input vector, a weight matrix and a bias vector into the D-A converter to obtain a first analog signal, a second analog signal and a third analog signal which are output; the step of inputting the analog signal into the artificial intelligence computing analog circuit to obtain an output decision analog signal comprises the following steps: and inputting the first analog signal, the second analog signal and the third analog signal into the artificial intelligence computing analog circuit to obtain an output decision analog signal. In some embodiments, the first input vector is comprised of a set of digits, e.g., the first input vector may use a range of digits between 1 and-1, may be represented by 8 digits or 16 digits, where one digit represents the polarity of the digits, the bias vector may use a range of digits between 4 and-4, where one digit represents the polarity and the remaining digits represent the magnitude, and the decision vector has the same range of digits as the first input vector. As an example, the first input vector (X), the bias vector (B) is represented by an 8-bit number, the first input vector has a polarity of 1 bit and an amplitude of 7 bits, the bias vector has a polarity of 1 bit, an integer of 2, and a fraction of 5 bits, the decision vector (Y) after the sigmoid function (an activation function) conversion is in the same digital format as the first input vector (X), and the decision vector (Y) before the sigmoid function conversion is in the same digital format as the bias vector (B). The above-mentioned digital system is only an example and is not meant to limit the embodiments of the present application; other existing or possible digital systems are, for example, suitable for use with the present application, are also within the scope of the present application and are incorporated herein by reference. In some embodiments, the analog signal includes a first analog signal, a second analog signal, and a third analog signal, the first input vector is input to the D-a converter to obtain a first analog signal output by the first input vector, the weight matrix is input to the D-a converter to obtain a second analog signal output by the second input vector, and the bias vector is input to the D-a converter to obtain a third analog signal output by the third input vector. In some embodiments, the first input vector inputs the same D-a converter as the weight matrix, and because the offset vector has a larger digital range than the first input vector (e.g., the first input vector uses a digital range between 1 and-1, the offset vector uses a digital range between 4 and-4), the D-a converter needs to be adjusted when the offset vector is input to the D-a converter, e.g., the resistance value of at least one resistor in the circuit to which the D-a converter corresponds is adjusted accordingly (e.g., the resistance value of each digital bit in the circuit to which the D-a converter corresponds is adjusted), or the first input vector, the offset vector, the resistance value of at least one resistor in the circuit to which the offset vector corresponds are respectively input to two different D-a converters, the resistance value of at least one resistor in the circuit to which the offset vector corresponds to the D-a converter is distinguished from the resistance value of at least one resistor in the circuit to which the first input vector corresponds (e.g., the resistance value of the resistor in the circuit to which the offset vector corresponds to the D-a converter is compressed, the resistance value in the D-a corresponding to the digital bit in the circuit to which the offset vector corresponds to the D-a converter is compressed, or the ratio of the D-a value in which the offset vector corresponds to the digital bit in the digital bit to which the digital bit in the circuit corresponds to which the D-a value is compressed). In some embodiments, the multiplication is performed in an analog multiplication unit (analog multiplier) using a first analog signal corresponding to a first input vector (X) and a second analog signal corresponding to a weight matrix (W), in which case we choose to have the input vector be a number less than 1 and the weight matrix value also a number less than 1, so the output will always be less than 1 volt. For example, 0.4V X0.8v=0.32V. In some embodiments, for each row of the matrix, the respective analog signals output by the analog multiplication unit and the third analog signal corresponding to the offset vector are input to an analog addition unit (analog adder). In some embodiments, the analog signal output by the analog adding unit is input to an analog activation function filtering unit (e.g., sigmoid converter) to obtain a decision analog signal output by the analog adding unit. Standard digital formats are not used in the artificial intelligence system industry. Some people use 16-bit or even 32-bit digital systems, just for convenience in using existing hardware and software, and when digital systems for AI computation use smaller digital systems (e.g., 8-bit numbers), the number of hardware used to calculate AI parameters can be reduced within a single chip. This allows parallel computing to improve performance within a single chip at the expense of accuracy, with smaller digital systems, such as 8 bits, having less accuracy, but with little impact on the decision making process. For example, for the following decision case "the possibility of raining is 20%" and "the possibility of raining is 21.089%", there is no great difference in decision, and for this reason, the present solution can achieve faster artificial intelligence calculation speed with a smaller digital system. The digital system used in this scheme should not limit the scope of the application claimed in this patent. Instead of using digital in a digital system, the accuracy of the digital system in an analog system is fundamentally different from that in the digital world, and the accuracy of the digital system in an analog system is very flexible in artificial intelligence computation. In some embodiments, the decision analog signal output by the artificial intelligence computing analog circuit in the first artificial intelligence circuit may be directly input as the corresponding first analog signal to the artificial intelligence circuit in the later stage of the first artificial intelligence circuit, without inputting the input vector to the artificial intelligence circuit in the later stage, the artificial intelligence circuit in the later stage may also not need to convert the input vector into the corresponding first analog signal, the artificial intelligence circuit in the later stage may directly use the decision analog signal transmitted from the first artificial intelligence circuit in the previous stage as the corresponding first analog signal, and input it to the artificial intelligence computing analog circuit in the later stage, the significant advantage of using the analog signal for output is that the artificial intelligence computing in the next stage may be performed immediately using the decision analog signal, or the artificial intelligence computing analog signal output by the artificial intelligence computing analog circuit in the first artificial intelligence circuit may also be input into the decision vector in a corresponding digital form and stored in the register, we may spend estimating the time required for storing the first input vector into the register, and may obtain the desired result by obtaining the desired result vector from the time required for storing the first input vector and the desired result from the time register. In some embodiments, the decision vector in digital form output by the first artificial intelligence circuit may be stored in a digital register, the CPU may read the decision vector in the digital register and input the decision vector as a first input vector to an artificial intelligence circuit of a later stage, and the a-D converter in the artificial intelligence circuit of the later stage converts the first input vector in digital form into a corresponding first analog signal and inputs it to an artificial intelligence computing analog circuit in the artificial intelligence circuit of the later stage. In some embodiments, where the a-D converter needs to convert the final result from the decision analog signal output by the Sigmoid converter into a decision vector stored in a digital form, the accuracy requirements for such conversion are not high in artificial intelligence calculations, the a-D converter can be greatly simplified to make a rough estimate of the result, the Sigmoid conversion itself is the result of a warped artificial intelligence matrix calculation, which is why the conversion accuracy of the final result is not required, and if the final result decision vector can be represented by 2 or fewer bits, the a-D converter can have only two comparators per bit.

In some embodiments, the inputting the first analog signal, the second analog signal, and the third analog signal into the artificial intelligence computing analog circuit, to obtain an output decision analog signal, includes: inputting the first analog signal and a second decision analog signal output by a second artificial intelligent circuit positioned at the previous stage of the first artificial intelligent circuit into a multi-channel analog input selection unit to obtain an output target analog signal; and inputting the target analog signal, the second analog signal and the third analog signal into the artificial intelligent computing analog circuit to obtain an output decision analog signal. In some embodiments, the first analog signal and the second analog signal, and the third analog signal after the first input vector is converted by the D-a converter may be input into the artificial intelligence computing analog circuit to obtain an output decision analog signal, or the second decision analog signal (i.e., the second decision analog signal output by the artificial intelligence computing analog circuit in the second artificial intelligence circuit, which is not converted into a corresponding decision vector by the a-D converter, but is directly input into the first artificial intelligence circuit in the later stage of the second artificial intelligence circuit) and the second analog signal, and the third analog signal may be input into the artificial intelligence computing analog circuit to obtain an output decision analog signal, that is, one analog signal is selected as a target analog signal and a second artificial intelligence computing analog signal from among the first analog signal after the first input vector is converted by the D-a converter and the second decision analog signal output from the second artificial intelligence circuit in the earlier stage of the first artificial intelligence circuit, so as to obtain an output decision analog signal. In some embodiments, the first artificial intelligence circuit further includes a multi-path analog input selecting unit, the first analog signal and the second decision analog signal are input to the multi-path analog input selecting unit, the multi-path analog input selecting unit is used for selecting one of the plurality of input analog signals as a final input analog signal, and the multi-path analog input selecting unit inputs the selected analog signal to the artificial intelligence computing analog circuit to obtain an output decision analog signal. In some embodiments, the multiple analog input selection unit may be an analog multiplexer, or may also be an analog adder. As an example, as shown in fig. 14, two input terminals of the multi-channel analog input selecting unit respectively correspond to a first analog signal obtained by converting a first input vector by a D-a converter and a second decision analog signal outputted by a second artificial intelligence circuit located at a previous stage of the first artificial intelligence circuit, an unused input terminal needs to set its corresponding input voltage to a lowest voltage (for example, VCC-4V-1V) of a preset voltage interval centering on a zero reference voltage, and an output of the multi-channel analog input selecting unit is an analog signal inputted by a used input terminal of the two input terminals.

In some embodiments, the input voltage corresponding to the unused input terminal in the multiple analog input selection unit is set to the lowest voltage of the preset voltage interval centered on the zero reference voltage. In some embodiments, the multiple analog input selecting unit is an analog adder, in which a plurality of input ends exist, the first analog signal and the second decision analog signal are respectively corresponding to one of the input ends, if the input end corresponding to the first analog signal is not used, the input voltage corresponding to the input end needs to be set to be the lowest voltage of a preset voltage interval centered on a zero reference voltage, at this time, the analog adder inputs the second decision analog signal input by the other input end as a target analog signal into the first artificial intelligence circuit, that is, at this time, the output of the analog adder is the second decision analog signal, if the input end corresponding to the second decision analog signal is not used, the input voltage corresponding to the input end needs to be set to be the lowest voltage of a preset voltage interval centered on a zero reference voltage, at this time, the analog adder inputs the first analog signal corresponding to the other input end as the target analog signal, that is, the output of the analog adder is the first artificial intelligence circuit, wherein the zero reference voltage is a Voltage (VCC) is lower than a power supply voltage (VCC is, for example, VCC is preset voltage is set to be 1V-4V, and a preset voltage is set to be 1V-V is a preset voltage in the preset voltage interval of-VCC-4V, for example, and a value is set to be 1V is not equal to the zero voltage in the preset voltage interval. As an example, as shown in fig. 11, the analog adder has two input terminals connected to the negative electrode of the analog adder in parallel, the positive electrode of the analog adder is connected to the zero reference voltage, the first analog signal output from the D-a converter is input to one of the input terminals, and the second decision analog signal output from the second artificial intelligence circuit located at the previous stage of the first artificial intelligence circuit is input to the other input terminal.

In some embodiments, before the first input vector, the weight matrix, and the bias vector are input to the D-a converter respectively, the method further includes: splitting a target input vector into a plurality of first input vectors connected in parallel, so that each first input vector is input into one of a plurality of first artificial intelligent circuits connected in parallel in a cascading manner, and a decision vector corresponding to the output first input vector is obtained. In some embodiments, the target input vector may be split into a plurality of parallel first input vectors, for example, x= (X1, X2, … Xn), the size of the weight matrix needs to be adjusted according to the number of parallel first input vectors, and if there are k elements (j= … k) in the first input vector xj, the total column number of the weight matrix is (k×n). In some embodiments, after splitting the target input vector into a plurality of parallel first input vectors, for each first input vector, inputting the first input vector into one of a plurality of first artificial intelligence circuits cascaded in parallel, a D-a converter in the first artificial intelligence circuit converts the first input vector into a corresponding first analog signal, then the first analog signal, a second analog signal corresponding to a weight matrix, and a third analog signal corresponding to a bias vector are input into an artificial intelligence calculation analog circuit in the first artificial intelligence circuit, resulting in an output decision analog signal, which is then converted into a decision vector in digital form by an a-D converter in the first artificial intelligence circuit.

In some embodiments, a target artificial intelligence circuit of the plurality of first artificial intelligence circuits corresponds to one or more artificial intelligence circuits in serial cascade, and the decision analog signal output by the former artificial intelligence circuit is input to the latter artificial intelligence circuit as the first analog signal corresponding to the latter artificial intelligence circuit. In some embodiments, at least one target artificial intelligence circuit exists in the first artificial intelligence circuits, the target artificial intelligence circuit corresponds to one or more artificial intelligence circuits in serial cascade, for example, the next artificial intelligence circuit in serial cascade of the target artificial intelligence circuit C1 is C2, the next artificial intelligence circuit in serial cascade of C2 is C3, the next artificial intelligence circuit in serial cascade of C3 is C4, and so on, the decision analog signal output by the artificial intelligence calculation analog circuit in the previous artificial intelligence circuit in serial cascade is not converted into a corresponding decision vector by the input a-D converter, but is directly input into the next artificial intelligence circuit, and the next artificial intelligence circuit inputs the decision analog signal as a second analog signal corresponding to the weight matrix and a third analog signal corresponding to the bias vector of the first analog signal into the artificial intelligence calculation analog circuit to obtain an output decision analog signal, and so on. In some embodiments, when each artificial intelligence circuit is in a cascade of chips for deep learning, the analog signals may be used for neural network communication between the artificial intelligence circuits to speed up computation, and after the input vector is converted into the analog signal, the computation of the cascade of multiple stages of artificial intelligence computation may be performed without software intervention. As an example, as shown in fig. 4, where n artificial intelligence circuits are cascaded in parallel and m artificial intelligence circuits are cascaded in series, we will have n×m artificial intelligence circuits for artificial intelligence calculations, in which case the interconnections between the individual artificial intelligence circuits are analog communications, meaning that the artificial intelligence calculations are performed instantaneously by analog signals without involving CPU operations. In some embodiments, when artificial intelligence circuits are cascaded for deep learning, the analog signal is passed through the entire deep learning artificial intelligence system to produce results. The artificial intelligence computation may be performed in real time without CPU intervention, and once the artificial intelligence learns of the system, the artificial intelligence computation method described in this solution provides a very fast artificial intelligence system. The present application adopts a method of expanding the size of an artificial intelligence system by cascading chips, in which the artificial intelligence calculation performed by the method is real-time calculation without waiting for software intervention, and thus, the present application can accelerate the artificial intelligence calculation for a very large AI system.

In some embodiments, a pipeline unit is disposed between a chip corresponding to a previous artificial intelligence circuit and a chip corresponding to a next artificial intelligence circuit, and the pipeline unit is configured to convert a decision analog signal output by the previous artificial intelligence circuit into a capacitance charge based on a negative feedback amplifier, and convert the capacitance charge into a corresponding first analog signal to be input to the next artificial intelligence circuit. In some embodiments, each chip corresponds to one artificial intelligence circuit, each artificial intelligence circuit corresponds to one chip, the scheme allows for a "pipeline" structure at the boundary of the chips, i.e. a pipeline unit is provided between two chips in a serial cascade, so that the output signal of each chip can be captured in analog form, as a stage of the pipeline operation, for the decision analog signal output by the previous artificial intelligence circuit, the pipeline captures the decision analog signal in analog form, converts the decision analog signal into a capacitive charge based on a negative feedback amplifier, and then converts the capacitive charge into a corresponding first analog signal for input to the subsequent artificial intelligence circuit in the serial cascade, e.g. by converting the capacitive charge into a corresponding first analog signal for input to the subsequent artificial intelligence circuit in the next clock, by applying this type of pipeline in the cascade architecture, such that the analog signal comes out of one chip and is fed to the subsequent chip of the cascade of the chip.

In some embodiments, the inputting the first analog signal, the second analog signal, and the third analog signal into the artificial intelligence computing analog circuit, to obtain an output decision analog signal, includes: inputting the first analog signal and the second analog signal into an analog multiplication unit in a first artificial intelligent circuit to obtain a plurality of output fourth analog signals; inputting the plurality of fourth analog signals and the third analog signals into an analog adding unit in the first artificial intelligent circuit to obtain an output fifth analog signal; and inputting the fifth analog signal into an analog activation function filtering unit in the first artificial intelligent circuit to obtain an output decision analog signal, wherein the decision analog signal is positioned in a preset voltage interval taking zero reference voltage as a center. In some embodiments, the multiplication is performed in an analog multiplication unit (analog multiplier) using a first analog signal corresponding to the first input vector (Xj) and a second analog signal corresponding to the weight matrix (Wij), as an example, as shown in fig. 12, the first analog signal (Xj) and the second analog signal (Wij) are respectively input to two inputs of the analog multiplier, the analog multiplier outputs a product (xj×wij) of the two, and the analog multiplier performs scaling restriction on the analog signals when multiplying, so that the product of the two is still within a preset voltage interval centered on zero reference voltage. For each row of the weight matrix, a plurality of products of the outputs (i.e., the fourth analog signal) are obtained. In some embodiments, for each row of the weight matrix, the third analog signals corresponding to the Bias vectors are input to an analog adding unit (analog Adder) to obtain an output fifth analog signal, then the fifth analog signal is input to an analog activation function filtering unit (e.g., sigmoid converter) to obtain an output decision analog signal, as an example, as shown in fig. 13, the fourth analog signal Xj and the third analog signal bj (Bias vector) are respectively input to two input terminals of the analog Adder (Adder), and then the output fifth analog signal of the analog Adder is input to the Sigmoid converter to obtain an output decision analog signal, where the analog multiplier scales the analog signals when adding, so that the added result is still within a preset voltage interval centered on the zero reference voltage. The analog activation function filtering unit is configured to limit the output of the calculation result within a boundary value of one volt using an exponential curve, the decision analog signal is located within a preset voltage interval centered on a zero reference Voltage (VCC), which is a default voltage lower than a power supply Voltage (VCC) by a preset difference value (e.g., 4V), and then the preset voltage interval is a voltage interval centered on the zero reference voltage, for example, the decision analog signal is located within a preset voltage interval [ VCC-4V-1V, VCC-4v+1v ]. In some embodiments, the artificial intelligence computation is performed significantly faster in the present scheme by using adders, multipliers and sigmoid converters for analog signals, the definition of analog signals in the present scheme being signals between VCC and ground, we use the example of signal ranges above and below neutral voltage 1 volt, which is 4 volts below VCC level. In some embodiments, the number of multipliers increases as the number of weight matrix sizes increases. This will result in a larger total power consumption, which we can reduce when the size of each transistor is very small, the design parameters are largely dependent on the current density rather than the current, however, smaller currents require higher transistor values to produce the desired voltage range, and the design parameters have to be adjusted according to existing chip technology. Since the number of transistor elements will be much smaller than artificial intelligence systems designed by digital methods, the limiting factor for the size of the matrix will be the total power consumption.

In some embodiments, the inputting the plurality of fourth analog signals and the third analog signals into the analog adding unit in the first artificial intelligence circuit, to obtain an output fifth analog signal, includes: dividing the plurality of fourth analog signals into a plurality of packets, each packet including at least two fourth analog signals; for each group, inputting at least two fourth analog signals in the group into an analog adding unit in the first artificial intelligent circuit to obtain an output sixth analog signal corresponding to the group; and inputting the sixth analog signals corresponding to the groups and the third analog signals into another analog adding unit in the first artificial intelligent circuit to obtain output fifth analog signals. In some embodiments, the plurality of fourth analog signals are divided into a plurality of groups, each group includes the same number of fourth analog signals, then for each group, at least two fourth analog signals in the group are respectively input into an analog adding unit (analog adder), so as to obtain output sixth analog signals corresponding to the group, as an example, fig. 6 shows a circuit diagram of the analog adding unit, at least two fourth analog signals (P1 … Pn) in one group are respectively input into respective input terminals of the analog adding unit, each input terminal is respectively connected with a resistor (Rin), a plurality of input terminals are connected in parallel, on one hand, with an output terminal through a resistor (Rf), and on the other hand, with a branch composed of a plurality of triodes, the branch composed of a plurality of triodes is connected with collectors of a plurality of base biased triodes, each base biased triode is connected with a resistor, and the output terminal outputs the sixth analog signals corresponding to the group (PSn). In some embodiments, the sixth analog signal (PS 1 … km) and the third analog signal (B) corresponding to each packet are respectively input to the respective input terminals of the analog adding unit, the respective input terminals of each sixth analog signal are connected to a resistor (Rin), the respective input terminals of the third analog signal are connected to the other resistor (Rb), the plurality of input terminals are connected in parallel to the output terminal through a resistor (Rf), and the branch composed of a plurality of transistors is connected to the output terminal through a collector of a plurality of base-biased transistors, the emitter of each base-biased transistor is connected to a resistor, and the output terminal outputs the respective fifth analog signal.

In some embodiments, the fifth analog signal is compressed in the analog adding unit by the number of the plurality of fourth analog signals. In some embodiments, when N fourth analog signals are added in the analog adding unit, the output fifth analog signal is scaled down by a factor of N, e.g., when 4 fourth analog signals are added in the analog adding unit, the final output fifth analog signal is divided by 4 (i.e., compressed by a factor of 4). In some embodiments, the fourth analog signal is compressed in the analog multiplication unit at a predetermined ratio (e.g., 4) such that the compressed fourth analog signal is still within a preset voltage interval (e.g., [ VCC-4V-1V, VCC-4v+1v ]) centered around the zero reference voltage. In some embodiments, the fifth analog signal is compressed in the analog adding unit by the number of the plurality of fourth analog signals.

In some embodiments, each of the fourth analog signals is connected to a resistor at a corresponding input in the analog summing unit, the fourth analog signal scaled in the other analog summing unit by the resistor, the third analog signal is connected to another resistor at a corresponding input in the analog summing unit, and the third analog signal scaled in the other analog summing unit by the other resistor. As an example, as shown in fig. 7, fig. 7 shows a circuit diagram of another analog adding unit, in which a sixth analog signal (PS 1 … pm) and a third analog signal (B) corresponding to each group are input to respective input terminals of the analog adding unit, an input terminal corresponding to each sixth analog signal is connected to one resistor (Rin), an input terminal corresponding to the third analog signal is connected to the other resistor (Rb), and the fourth analog signal and the third analog signal are scaled by adjusting the resistance value of Rin and the resistance value of Rb, and the scaled fourth analog signal and the scaled third analog signal are added.

In some embodiments, the analog multiplication unit includes two output terminals with opposite polarities, the positive polarity output terminal in the analog multiplication unit outputs the fourth model signal if the polarity of the fourth analog signal is positive, and the negative polarity output terminal in the analog multiplication unit outputs the fourth model signal if the polarity of the fourth analog signal is negative. In some embodiments, the fourth analog signal is located within a preset voltage interval centered around a zero reference voltage, which is a voltage less than a preset difference of the supply voltage, e.g., the zero reference voltage is a default voltage VCC-4V lower than the supply Voltage (VCC) by a preset difference (e.g., 4V), e.g., the fourth analog signal is located within an interval of [ VCC-4V-1V, VCC-4v+1v ], the voltage polarity of the fourth analog signal may be positive or negative, e.g., the voltage of the fourth analog signal is located within a voltage range of-1V to +1v. In some embodiments, the analog multiplication unit includes two output terminals with opposite polarities, if the polarity of the fourth analog signal obtained after multiplication is positive, the positive polarity output terminal in the analog multiplication unit outputs the fourth model signal, at this time, the negative polarity output terminal does not output the analog signal, and if the polarity of the fourth analog signal obtained after multiplication is negative, the negative polarity output terminal in the analog multiplication unit outputs the fourth model signal, at this time, the positive polarity output terminal does not output the analog signal, i.e. the difference between the positive result and the negative result with opposite voltage polarities is represented by the two output terminals with opposite polarities.

In some embodiments, the analog multiplication unit includes a fifth composite triode unit and a sixth composite triode unit, the fifth composite triode unit includes a sixth target triode and a seventh target triode, the emitter of the sixth target triode and the emitter of the seventh target triode are connected through a first target resistor, the base input of the sixth target triode is the second analog signal, the base input of the seventh target triode is the first reference voltage, the sixth composite triode unit includes an eighth target triode and a ninth target triode, the emitter of the eighth target triode and the emitter of the ninth target triode are also connected through a first target resistor, the base input of the eighth target triode is the first analog signal, the base input of the ninth target triode is the first reference voltage, the base input of the sixth target triode is connected to a voltage through two second target resistors in parallel, the positive polarity output end and the negative polarity output end are respectively connected to the analog signal in one of the fourth target resistors through the second target resistors in the second power supply unit, and the analog signal is scaled according to the analog signal in the second resistor. As an example, fig. 9 shows an analog multiplication unit including a fifth composite triode unit including a sixth target triode whose base input is a second analog signal Wij-Vbe (base and emitter inter-stage voltage), a seventh target triode whose base input is a first reference voltage-4V-Vbe (base and emitter inter-stage voltage), an emitter of the sixth target triode is connected to an emitter of the seventh target triode through a first target resistor (Ri), an emitter of the sixth target triode is connected to a base-biased triode, a collector of the sixth target triode is connected to a supply voltage through a base of the seventh target triode, a base of the eighth target triode is connected to a base of the eighth target triode, a base of the eighth target triode is connected to an emitter of the eighth target triode, an input of the eighth target triode is a first analog signal Xi-Vbe (base and emitter inter-stage voltage), an emitter of the sixth target triode is connected to a base-bias voltage of the eighth target triode through a base of the eighth target triode, an emitter of the eighth target triode is connected to a base of the eighth target triode, a base of the eighth target triode is connected to an emitter of the eighth target triode is connected to a base of the eighth target triode is connected to the base of the seventh target triode is connected to the base of the seventh target triode, the collector of the eighth target triode and the collector of the ninth target triode are connected to the power supply voltage through a plurality of triodes and then through two second target resistors (Rc) connected in parallel, the analog multiplication unit comprises two output ends with opposite polarities, namely a positive polarity output end Pout+ and a negative polarity output end Pout-, and the fourth analog signal output by the analog multiplication unit can be scaled according to a preset proportion in the analog multiplication unit by adjusting the resistance value of Ri and the resistance value of Rc, so that the scaled fourth analog signal still exists in a preset voltage interval (for example, [ VCC-4V-1V, VCC-4V+1V ] taking zero reference voltage as a center, wherein the preset proportion is calculated according to the resistance value of Ri and the resistance value of Rc.

In some embodiments, the analog activation function filtering unit includes a seventh composite triode unit, a first target triode, a second target triode, and a third target triode, where the seventh composite triode unit includes a fourth target triode and a fifth target triode, an emitter of the fourth target triode is connected with an emitter of the fifth target triode, a base input of the fourth target triode is the fifth analog signal, a base input of the fifth target triode is the second reference voltage, an emitter of the fourth target triode and an emitter of the fifth target triode are all connected with the first target triode, a collector of the fifth target triode is connected with a base of the second target triode, an emitter of the second target triode is connected with a collector of the third target triode, bases of the first target triode and the third target triode are biased, and an emitter of the second target triode is the output end of the analog activation function filtering unit. As an example, fig. 10 shows an analog activation function filter unit (sigmoid converter) comprising a seventh composite triode unit, a first target triode, a second target triode, and a third target triode, the seventh composite triode unit comprising a fourth target triode and a fifth target triode, the emitter of the fourth target triode being connected to the emitter of the fifth target triode, the emitter of the fourth target triode and the emitter of the fifth target triode being connected to the same base-biased first target triode, the base input of the fourth target triode being a fifth analog signal Wi, the base input of the fifth target triode is a second reference voltage-4V-Vbe (base-to-emitter voltage), the collector of the fifth target triode is connected with a resistor, the collector of the fifth target triode is also connected with the base of the second target triode, the emitter of the second target triode is connected with a third target triode with a biased base, the emitter of the second target triode is the output end of the sigmoid converter, the voltage swing of the decision analog signal output by the sigmoid converter is 2V, namely, the voltage value of the decision analog signal is in the interval of VCC-4V-1V, VCC-4V+1V, wherein VCC refers to the power supply voltage.

In some embodiments, the input information comprises a plurality of digital bits; wherein the inputting the input information into the D-a converter to obtain an output analog signal includes: and inputting an input signal corresponding to each digital bit in the input information into an input end corresponding to the digital bit in the D-A converter to obtain an output analog signal. In some embodiments, the input information includes a plurality of digital bits (e.g., 8 digital bits), and for each digital bit in the input information, a predetermined input signal (input voltage or input current, e.g., 0 corresponds to-1V or 0V,1 corresponds to 1V) corresponding to the value is input to an input terminal corresponding to the digital bit in the D-a converter, so as to obtain an analog signal output by an output terminal of the D-a converter.

In some embodiments, the input information further includes a polarity bit; wherein for each numerical value on each digital bit in the input information, inputting an input signal corresponding to the numerical value into an input end corresponding to the digital bit in the D-a converter to obtain an output analog signal, and the method comprises the following steps: and for the numerical value of each digital bit in the input information, inputting an input signal corresponding to the numerical value into an input end corresponding to the digital bit in the D-A converter, and inputting an input signal corresponding to the numerical value in the polarity bit in the input information into an input end corresponding to the polarity bit in the D-A converter to obtain an output analog signal. In some embodiments, the input information includes a plurality of digital bits (e.g., 7 digital bits) and a polarity bit indicating the polarity of the input information, and a predetermined input signal (input voltage or input current, e.g., 0 corresponds to-1V or 0V,1 corresponds to 1V) corresponding to a value (e.g., 0 or 1) on the polarity bit in the input information is input to the input terminal corresponding to the polarity bit in the D-a converter.

In some embodiments, the D-a converter includes a first branch and a second branch corresponding to each digital bit, the first branch corresponding to each digital bit includes a first composite triode unit and a first triode corresponding to the digital bit, a base input of the first triode is a reference voltage, the first composite triode unit is connected with an output end of the D-a converter and a collector of the first triode, the second branch corresponding to each digital bit includes a second composite triode unit and a second triode corresponding to the digital bit, an emitter of the second triode is connected with a weight resistor corresponding to the digital bit, and the second composite triode unit is connected with an output end of the D-a converter and a collector of the second triode; wherein for each numerical value on each digital bit in the input information, inputting an input signal corresponding to the numerical value into an input end corresponding to the digital bit in the D-a converter to obtain an output analog signal, and the method comprises the following steps: and inputting an input signal corresponding to the numerical value into a first composite triode unit in a first branch corresponding to the numerical value and a second composite triode unit in a second branch corresponding to the numerical value to obtain an output analog signal for the numerical value on each numerical digit in the input information. In some embodiments, the circuit of the D-a converter includes a first branch corresponding to each digital bit and a second branch, the first branch corresponding to each digital bit includes a first composite triode unit corresponding to the digital bit and a first triode, a base input of the first triode is a reference voltage (Vref), an emitter of the first triode is connected to a resistor, a collector of the first triode is connected to an output terminal of the D-a converter through the first composite triode unit, the second branch corresponding to each digital bit includes a second composite triode unit corresponding to the digital bit and a second triode, an emitter of the second triode is connected to a weighting resistor through a base-biased triode, another end of the weighting resistor is grounded, and a collector of the second triode is connected to an output terminal of the D-a converter through the second composite triode unit, where the composite triode unit refers to a composite triode composed of a plurality of connected (e.g., respective connected) triode units. In some embodiments, for each digital bit in the input information, an input signal (input voltage or input current, for example, 0 corresponds to-1V or 0V,1 corresponds to 1V) corresponding to the digital bit is input to the base of at least one transistor in the first composite transistor unit in the first branch corresponding to the digital bit and the base of at least one transistor in the second composite transistor unit in the second branch corresponding to the digital bit, so as to obtain the analog signal output by the D-a converter.

In some embodiments, the first composite triode unit includes a third triode and a fourth triode, the emitter of the third triode is connected with the emitter of the fourth triode, the emitter of the third triode and the emitter of the fourth triode are both connected with the collector of the first triode, the collector of the third triode is connected with the output end of the D-a converter, the second composite triode unit includes a fifth triode and a sixth triode, the emitter of the fifth triode is connected with the emitter of the sixth triode, the emitter of the fifth triode and the emitter of the sixth triode are both connected with the collector of the second triode, and the collector of the fifth triode is connected with the output end of the D-a converter; the method for obtaining the output analog signal includes the steps of: and inputting an input signal corresponding to the numerical value into the base electrode of a third triode in a first branch corresponding to the numerical value and the base electrode of a sixth triode in a second branch corresponding to the numerical value, and inputting an inverted input signal corresponding to the numerical value into the base electrode of a fourth triode in the first branch corresponding to the numerical value and the base electrode of a fifth triode in the second branch corresponding to the numerical value to obtain an output analog signal. In some embodiments, the first composite triode unit includes two triodes, which are a third triode and a fourth triode respectively, an emitter of the third triode is connected with an emitter of the fourth triode, an emitter of the third triode and an emitter of the fourth triode are both connected with a collector of the first triode, a collector of the third triode is connected with an output end of the D-a converter, the second composite triode unit also includes two triodes, which are a fifth triode and a sixth triode respectively, an emitter of the fifth triode is connected with an emitter of the sixth triode, an emitter of the fifth triode and an emitter of the sixth triode are both connected with a collector of the second triode, and a collector of the fifth triode is connected with an output end of the D-a converter.

In some embodiments, the input information further includes a polarity bit, the first branch corresponding to each digital bit further includes a third composite triode unit corresponding to the polarity bit, the third composite triode unit includes a seventh triode and an eighth triode, the emitter of the third triode and the emitter of the fourth triode are both connected with the collector of the seventh triode, the emitter of the seventh triode and the emitter of the eighth triode are both connected with the collector of the first triode, the second branch corresponding to each digital bit further includes a fourth composite triode unit corresponding to the polarity bit, the fourth composite triode unit includes a ninth triode and a thirteenth triode, the emitter of the fifth triode and the emitter of the sixth triode are both connected with the collector of the ninth triode, and the emitter of the ninth triode and the emitter of the tenth triode are both connected with the collector of the second triode; the method includes inputting, for each numerical value in the input information, an input signal corresponding to the numerical value to a base of a third triode in a first branch corresponding to the numerical value and a base of a sixth triode in a second branch corresponding to the numerical value, inputting an inverted input signal corresponding to the numerical value to a base of a fourth triode in the first branch corresponding to the numerical value and a base of a fifth triode in the second branch corresponding to the numerical value, and obtaining an output analog signal, and further includes: for each digital bit in the input information, inputting an input signal corresponding to a numerical value on a polarity bit in the input information into a base electrode of a seventh triode in a first branch corresponding to the digital bit and a base electrode of a thirteenth triode in a second branch corresponding to the digital bit, and inputting an inverted input signal corresponding to the numerical value into a base electrode of an eighth triode in the first branch corresponding to the digital bit and a base electrode of a ninth triode in the second branch corresponding to the digital bit. In some embodiments, the first branch corresponding to each digital bit further includes a third composite triode unit corresponding to the polarity bit, the third composite triode unit includes two triodes, a seventh triode and an eighth triode, an emitter of the seventh triode is connected with an emitter of the eighth triode, an emitter of the third triode and an emitter of the fourth triode are all connected with a collector of the seventh triode, an emitter of the seventh triode and an emitter of the eighth triode are all connected with a collector of the first triode, the second branch corresponding to each digital bit further includes a fourth composite triode unit corresponding to the polarity bit, the fourth composite triode unit also includes two triodes, a ninth triode and a thirteenth triode, an emitter of the ninth triode is connected with an emitter of the thirteenth triode, an emitter of the fifth triode and an emitter of the sixth triode are all connected with a collector of the ninth triode, and an emitter of the thirteenth triode are all connected with a collector of the second triode. As an example, fig. 5 shows a D-a converter for obtaining an analog signal, the input signal inputted by the D-a converter is represented by 8 bits, and includes 7 digital bits (a 6-a 0) and 1 polarity bit(s), each digital bit is in the D-a converter corresponding to a first branch and a second branch, the first branch includes a first composite transistor unit corresponding to the digital bit, a third composite transistor unit corresponding to the polarity bit, and a first transistor, one end of the first composite transistor unit is connected to an output terminal of the D-a converter, the other end of the first composite transistor unit is connected to the third composite transistor unit, the other end of the third composite transistor unit is connected to a collector of the first transistor, an emitter of the first transistor is connected to a resistor, a base input of the first transistor is a reference voltage (Vref), the second branch includes a second composite transistor unit corresponding to the digital bit, a third composite transistor unit corresponding to the polarity bit, and a first transistor, one end of the first composite transistor unit is connected to an output terminal of the second composite transistor unit is connected to a base of the second composite transistor unit, the other end of the second composite transistor unit is connected to a base of the third composite transistor unit is connected to the other end of the resistor (Ra, the base of the third composite transistor is connected to the base of the third composite transistor unit) and the resistor is connected to the base of the resistor, the analog signal output by the D-a converter is present between the 1 volt positive terminal and the 1 volt negative terminal of the zero reference voltage (VCC-4V).

In some embodiments, the a-D converter includes a comparator unit that performs level comparison on the decision analog signal based on one or more reference input voltages, and a coding unit that encodes a comparison result of the comparator unit to output a decision vector. In some embodiments, the decision analog signal output by the first artificial intelligence circuit may be input to the latter artificial intelligence circuit as a first analog signal corresponding to the latter artificial intelligence circuit in the cascade, or the decision analog signal may be input to an a-D converter, resulting in an output digitized decision vector, and the digitized decision vector is stored in a register, the decision vector having to be digitized for the microprocessor to read out and use the result, for the process, using an a-D converter comprising a comparator unit and an encoding unit, the comparator unit level comparing the decision analog signal based on one or more reference input voltages, the encoding unit encoding the comparison result of the comparator unit and outputting the digitized decision vector. In some embodiments, the decision analog signal must be digitized to store the result in a register, for which an a-D converter is used, but the final result's digitized resolution is not required for most artificial intelligence processes, the magnitude of the values between the decision vector components is important, the result tends to be positive or negative after undergoing Sigmoid conversion, and the difference in the values of the results is often not significant, so that the present scheme can use a simple a-D converter, such as a comparator.

In some embodiments, the comparator unit includes a first target triode, one or more second target triodes, the base input of the first target triode is the decision analog signal, the base input of each second target triode corresponds to different reference input voltages, the emitter of the first target triode and the emitter of each second target triode are connected, and the collector of each second target triode corresponds to one output terminal. As an example, fig. 8 shows a comparator unit for obtaining a decision vector, the comparator unit comprising a first target transistor, the base input of which is a decision analog signal, one or more second target transistors, the base inputs of which are respectively different reference input voltages (e.g. VCC-1.5V, VCC-2V, VCC-2.5V), the emitter of which are connected, the collector of which are connected with a resistor, the collector of which are respectively corresponding to an output (e.g. V1, V2, V3), the emitter of which are connected with a base biased transistor, the emitter of which is connected with a resistor. For example, V1, V2, V3 are voltage levels output from the three output terminals, respectively, (V1, V1) = (H, H) corresponding to the decision vector yi= (0, 0), (V1, V2, V3) = (H, L) corresponding to the decision vector yi= (0, 1), (V1, V2, V3) = (H, L) corresponding to the decision vector yi= (1, 0), (V1, V2, V3) = (L, L, L) corresponding to the decision vector Yi is equal to (1, 1).

FIG. 2 shows a block diagram of an apparatus for artificial intelligence computing, including a one-to-one module 11 and a two-to-two module 12, in accordance with one embodiment of the present application. A one-to-one module 11 for obtaining input information for artificial intelligence computation; and a second module 12, configured to input the input information to the first artificial intelligence circuit, so that the artificial intelligence calculation unit in the first artificial intelligence circuit performs artificial intelligence calculation through an analog circuit technology instead of a digital circuit technology, and obtains a decision vector corresponding to the input information.

One module 11 for obtaining input information for artificial intelligence calculations. In some embodiments, the input information includes, but is not limited to, a weight matrix, a bias vector, and an input vector. In some embodiments, the input information is in digital form, and is required to be stored in a register via a data bus from the CPU, from which it is required to be retrieved. In some embodiments, the artificial intelligence computation is to compute artificial intelligence decision values using a weight matrix, a bias vector, and an input event vector, the weight matrix and bias vector typically being determined by the learning process of the AI and giving the final value prior to the AI computation, the artificial intelligence computation involving many multiplications and additions, typically requiring the AI to perform the artificial intelligence computation as quickly as possible to provide decision points to the digital system, the decision points being represented by decision vectors.

And a second module 12, configured to input the input information to the first artificial intelligence circuit, so that the artificial intelligence calculation unit in the first artificial intelligence circuit performs artificial intelligence calculation through an analog circuit technology instead of a digital circuit technology, and obtains a decision vector corresponding to the input information. In some embodiments, the first artificial intelligence circuit includes an artificial intelligence calculation unit for performing artificial intelligence calculations (AI calculations, matrix calculations) using analog circuit techniques instead of using conventional analog circuit techniques to perform the artificial intelligence calculations, thereby enabling the artificial intelligence calculations to be implemented with a smaller amount of hardware and also enabling the calculation speed of the artificial intelligence calculations to be increased. In some embodiments, the first artificial intelligence circuit further comprises a digital circuit such as a register, a data bus, or the like. In some embodiments, the artificial intelligence computing analog circuitry includes, but is not limited to, modules such as an analog add unit, an analog multiply unit, an analog activate function filter unit, and the like. In some embodiments, the digital input information is required to be converted into a corresponding analog signal, and then the analog signal is input into the first artificial intelligence circuit, so that the artificial intelligence calculation is performed in the artificial intelligence calculation analog circuit in the first artificial intelligence circuit through the form of the analog signal, or the digital input information can be directly input into the first artificial intelligence circuit, the digital input information is firstly converted into the corresponding analog signal in the first artificial intelligence circuit, and then the analog signal is input into the artificial intelligence calculation analog circuit in the first artificial intelligence circuit, and the artificial intelligence calculation is performed in the artificial intelligence calculation analog circuit through the form of the analog signal. In some embodiments, the first artificial intelligence circuit directly outputs the analog-form calculation result obtained by the artificial intelligence calculation analog circuit, and then the calculation result needs to be converted into the corresponding digital-form decision vector, or the first artificial intelligence circuit converts the analog-form calculation result obtained by the artificial intelligence calculation analog circuit into the corresponding digital-form decision vector, and then the first artificial intelligence circuit directly outputs the decision vector. In some embodiments, as an example, fig. 3 shows a matrix formulation description of artificial intelligence computation of a typical machine learning system, where the input vector is Xj, the neural network is a weight matrix Wij, the bias vector of the adjustment decision process is bi, the decision vector is yi, in the artificial intelligence system, the input vector is a plurality of input samples, the first input vector in this scheme refers to one of the input samples, the decision vector is generated by adding the bias vector to the optimized weight matrix, the optimal decision process is to provide the optimal regression result, and the weight matrix and the bias vector are determined by the learning process. In some embodiments, the entire artificial intelligence computation process is performed in the form of analog signals, which are computed without any digital world (e.g., CPU) intervention. In some embodiments, the accuracy of the analog signal depends on two factors: the amplitude exceeding the noise level and the linearity of the analog signal processing. As long as the signal level is higher than 10 MV, the analog signal can maintain good accuracy. The analog circuit can maintain good linearity over a limited voltage range. The application performs artificial intelligence calculation in the form of analog signals, which can remarkably reduce the calculation time required for executing artificial intelligence.

In some embodiments, the artificial intelligence computing simulation circuit includes a simulation addition unit, a simulation multiplication unit, a simulation activation function filtering unit. The related operations are the same as or similar to those of the embodiment shown in fig. 1, and thus are not described in detail herein, and are incorporated by reference.

In some embodiments, the analog multiplication unit is a single logic gate and the analog addition unit is a single logic gate. The related operations are the same as or similar to those of the embodiment shown in fig. 1, and thus are not described in detail herein, and are incorporated by reference.

In some embodiments, the first artificial intelligence circuit includes a D-a converter and an a-D converter; wherein, two module 12 is used for: inputting the input information into the D-A converter to obtain an output analog signal; inputting the analog signal into the artificial intelligence computing analog circuit to obtain an output decision analog signal; and inputting the decision analog signal into the A-D converter to obtain an output decision vector. The related operations are the same as or similar to those of the embodiment shown in fig. 1, and thus are not described in detail herein, and are incorporated by reference.

In some embodiments, the analog signal is located within a preset voltage interval centered around a zero reference voltage, wherein the zero reference voltage is a voltage less than a preset difference in supply voltage. The related operations are the same as or similar to those of the embodiment shown in fig. 1, and thus are not described in detail herein, and are incorporated by reference.

In some embodiments, the input information includes a first input vector, a weight matrix, a bias vector; wherein the inputting the input information into the D-a converter to obtain an output analog signal includes: respectively inputting a first input vector, a weight matrix and a bias vector into the D-A converter to obtain a first analog signal, a second analog signal and a third analog signal which are output; the step of inputting the analog signal into the artificial intelligence computing analog circuit to obtain an output decision analog signal comprises the following steps: and inputting the first analog signal, the second analog signal and the third analog signal into the artificial intelligence computing analog circuit to obtain an output decision analog signal. The related operations are the same as or similar to those of the embodiment shown in fig. 1, and thus are not described in detail herein, and are incorporated by reference.

In some embodiments, the inputting the first analog signal, the second analog signal, and the third analog signal into the artificial intelligence computing analog circuit, to obtain an output decision analog signal, includes: inputting the first analog signal and a second decision analog signal output by a second artificial intelligent circuit positioned at the previous stage of the first artificial intelligent circuit into a multi-channel analog input selection unit to obtain an output target analog signal; and inputting the target analog signal, the second analog signal and the third analog signal into the artificial intelligent computing analog circuit to obtain an output decision analog signal. The related operations are the same as or similar to those of the embodiment shown in fig. 1, and thus are not described in detail herein, and are incorporated by reference.

In some embodiments, the input voltage corresponding to the unused input terminal in the multiple analog input selection unit is set to the lowest voltage of the preset voltage interval centered on the zero reference voltage. The related operations are the same as or similar to those of the embodiment shown in fig. 1, and thus are not described in detail herein, and are incorporated by reference.

In some embodiments, before the first input vector, the weight matrix, and the bias vector are input to the D-a converter respectively, the method further includes: splitting a target input vector into a plurality of first input vectors connected in parallel, so that each first input vector is input into one of a plurality of first artificial intelligent circuits connected in parallel in a cascading manner, and a decision vector corresponding to the output first input vector is obtained. The related operations are the same as or similar to those of the embodiment shown in fig. 1, and thus are not described in detail herein, and are incorporated by reference.

In some embodiments, a target artificial intelligence circuit of the plurality of first artificial intelligence circuits corresponds to one or more artificial intelligence circuits in serial cascade, and the decision analog signal output by the former artificial intelligence circuit is input to the latter artificial intelligence circuit as the first analog signal corresponding to the latter artificial intelligence circuit. The related operations are the same as or similar to those of the embodiment shown in fig. 1, and thus are not described in detail herein, and are incorporated by reference.

In some embodiments, a pipeline unit is disposed between a chip corresponding to a previous artificial intelligence circuit and a chip corresponding to a next artificial intelligence circuit, and the pipeline unit is configured to convert a decision analog signal output by the previous artificial intelligence circuit into a capacitance charge based on a negative feedback amplifier, and convert the capacitance charge into a corresponding first analog signal to be input to the next artificial intelligence circuit. The related operations are the same as or similar to those of the embodiment shown in fig. 1, and thus are not described in detail herein, and are incorporated by reference.

In some embodiments, the inputting the first analog signal, the second analog signal, and the third analog signal into the artificial intelligence computing analog circuit, to obtain an output decision analog signal, includes: inputting the first analog signal and the second analog signal into an analog multiplication unit in a first artificial intelligent circuit to obtain a plurality of output fourth analog signals; inputting the plurality of fourth analog signals and the third analog signals into an analog adding unit in the first artificial intelligent circuit to obtain an output fifth analog signal; and inputting the fifth analog signal into an analog activation function filtering unit in the first artificial intelligent circuit to obtain an output decision analog signal, wherein the decision analog signal is positioned in a preset voltage interval taking zero reference voltage as a center. The related operations are the same as or similar to those of the embodiment shown in fig. 1, and thus are not described in detail herein, and are incorporated by reference.

In some embodiments, the inputting the plurality of fourth analog signals and the third analog signals into the analog adding unit in the first artificial intelligence circuit, to obtain an output fifth analog signal, includes: dividing the plurality of fourth analog signals into a plurality of packets, each packet including at least two fourth analog signals; for each group, inputting at least two fourth analog signals in the group into an analog adding unit in the first artificial intelligent circuit to obtain an output sixth analog signal corresponding to the group; and inputting the sixth analog signals corresponding to the groups and the third analog signals into another analog adding unit in the first artificial intelligent circuit to obtain output fifth analog signals. The related operations are the same as or similar to those of the embodiment shown in fig. 1, and thus are not described in detail herein, and are incorporated by reference.

In some embodiments, the fifth analog signal is compressed in the analog adding unit by the number of the plurality of fourth analog signals. The related operations are the same as or similar to those of the embodiment shown in fig. 1, and thus are not described in detail herein, and are incorporated by reference.

In some embodiments, each of the fourth analog signals is connected to a resistor at a corresponding input in the analog summing unit, the fourth analog signal scaled in the other analog summing unit by the resistor, the third analog signal is connected to another resistor at a corresponding input in the analog summing unit, and the third analog signal scaled in the other analog summing unit by the other resistor. The related operations are the same as or similar to those of the embodiment shown in fig. 1, and thus are not described in detail herein, and are incorporated by reference.

In some embodiments, the analog multiplication unit includes two output terminals with opposite polarities, the positive polarity output terminal in the analog multiplication unit outputs the fourth model signal if the polarity of the fourth analog signal is positive, and the negative polarity output terminal in the analog multiplication unit outputs the fourth model signal if the polarity of the fourth analog signal is negative. The related operations are the same as or similar to those of the embodiment shown in fig. 1, and thus are not described in detail herein, and are incorporated by reference.

In some embodiments, the analog multiplication unit includes a fifth composite triode unit and a sixth composite triode unit, the fifth composite triode unit includes a sixth target triode and a seventh target triode, the emitter of the sixth target triode and the emitter of the seventh target triode are connected through a first target resistor, the base input of the sixth target triode is the second analog signal, the base input of the seventh target triode is the first reference voltage, the sixth composite triode unit includes an eighth target triode and a ninth target triode, the emitter of the eighth target triode and the emitter of the ninth target triode are also connected through a first target resistor, the base input of the eighth target triode is the first analog signal, the base input of the ninth target triode is the first reference voltage, the base input of the sixth target triode is connected to a voltage through two second target resistors in parallel, the positive polarity output end and the negative polarity output end are respectively connected to the analog signal in one of the fourth target resistors through the second target resistors in the second power supply unit, and the analog signal is scaled according to the analog signal in the second resistor. The related operations are the same as or similar to those of the embodiment shown in fig. 1, and thus are not described in detail herein, and are incorporated by reference.

In some embodiments, the analog activation function filtering unit includes a seventh composite triode unit, a first target triode, a second target triode, and a third target triode, where the seventh composite triode unit includes a fourth target triode and a fifth target triode, an emitter of the fourth target triode is connected with an emitter of the fifth target triode, a base input of the fourth target triode is the fifth analog signal, a base input of the fifth target triode is the second reference voltage, an emitter of the fourth target triode and an emitter of the fifth target triode are all connected with the first target triode, a collector of the fifth target triode is connected with a base of the second target triode, an emitter of the second target triode is connected with a collector of the third target triode, bases of the first target triode and the third target triode are biased, and an emitter of the second target triode is the output end of the analog activation function filtering unit. The related operations are the same as or similar to those of the embodiment shown in fig. 1, and thus are not described in detail herein, and are incorporated by reference.

In some embodiments, the input information comprises a plurality of digital bits; wherein the inputting the input information into the D-a converter to obtain an output analog signal includes: and inputting an input signal corresponding to each digital bit in the input information into an input end corresponding to the digital bit in the D-A converter to obtain an output analog signal. The related operations are the same as or similar to those of the embodiment shown in fig. 1, and thus are not described in detail herein, and are incorporated by reference.

In some embodiments, the input information further includes a polarity bit; wherein for each numerical value on each digital bit in the input information, inputting an input signal corresponding to the numerical value into an input end corresponding to the digital bit in the D-a converter to obtain an output analog signal, and the method comprises the following steps: and for the numerical value of each digital bit in the input information, inputting an input signal corresponding to the numerical value into an input end corresponding to the digital bit in the D-A converter, and inputting an input signal corresponding to the numerical value in the polarity bit in the input information into an input end corresponding to the polarity bit in the D-A converter to obtain an output analog signal. The related operations are the same as or similar to those of the embodiment shown in fig. 1, and thus are not described in detail herein, and are incorporated by reference.

In some embodiments, the D-a converter includes a first branch and a second branch corresponding to each digital bit, the first branch corresponding to each digital bit includes a first composite triode unit and a first triode corresponding to the digital bit, a base input of the first triode is a reference voltage, the first composite triode unit is connected with an output end of the D-a converter and a collector of the first triode, the second branch corresponding to each digital bit includes a second composite triode unit and a second triode corresponding to the digital bit, an emitter of the second triode is connected with a weight resistor corresponding to the digital bit, and the second composite triode unit is connected with an output end of the D-a converter and a collector of the second triode; wherein for each numerical value on each digital bit in the input information, inputting an input signal corresponding to the numerical value into an input end corresponding to the digital bit in the D-a converter to obtain an output analog signal, and the method comprises the following steps: and inputting an input signal corresponding to the numerical value into a first composite triode unit in a first branch corresponding to the numerical value and a second composite triode unit in a second branch corresponding to the numerical value to obtain an output analog signal for the numerical value on each numerical digit in the input information. The related operations are the same as or similar to those of the embodiment shown in fig. 1, and thus are not described in detail herein, and are incorporated by reference.

In some embodiments, the first composite triode unit includes a third triode and a fourth triode, the emitter of the third triode is connected with the emitter of the fourth triode, the emitter of the third triode and the emitter of the fourth triode are both connected with the collector of the first triode, the collector of the third triode is connected with the output end of the D-a converter, the second composite triode unit includes a fifth triode and a sixth triode, the emitter of the fifth triode is connected with the emitter of the sixth triode, the emitter of the fifth triode and the emitter of the sixth triode are both connected with the collector of the second triode, and the collector of the fifth triode is connected with the output end of the D-a converter; the method for obtaining the output analog signal includes the steps of: and inputting an input signal corresponding to the numerical value into the base electrode of a third triode in a first branch corresponding to the numerical value and the base electrode of a sixth triode in a second branch corresponding to the numerical value, and inputting an inverted input signal corresponding to the numerical value into the base electrode of a fourth triode in the first branch corresponding to the numerical value and the base electrode of a fifth triode in the second branch corresponding to the numerical value to obtain an output analog signal. The related operations are the same as or similar to those of the embodiment shown in fig. 1, and thus are not described in detail herein, and are incorporated by reference.

In some embodiments, the input information further includes a polarity bit, the first branch corresponding to each digital bit further includes a third composite triode unit corresponding to the polarity bit, the third composite triode unit includes a seventh triode and an eighth triode, the emitter of the third triode and the emitter of the fourth triode are both connected with the collector of the seventh triode, the emitter of the seventh triode and the emitter of the eighth triode are both connected with the collector of the first triode, the second branch corresponding to each digital bit further includes a fourth composite triode unit corresponding to the polarity bit, the fourth composite triode unit includes a ninth triode and a thirteenth triode, the emitter of the fifth triode and the emitter of the sixth triode are both connected with the collector of the ninth triode, and the emitter of the ninth triode and the emitter of the tenth triode are both connected with the collector of the second triode; the method includes inputting, for each numerical value in the input information, an input signal corresponding to the numerical value to a base of a third triode in a first branch corresponding to the numerical value and a base of a sixth triode in a second branch corresponding to the numerical value, inputting an inverted input signal corresponding to the numerical value to a base of a fourth triode in the first branch corresponding to the numerical value and a base of a fifth triode in the second branch corresponding to the numerical value, and obtaining an output analog signal, and further includes: for each digital bit in the input information, inputting an input signal corresponding to a numerical value on a polarity bit in the input information into a base electrode of a seventh triode in a first branch corresponding to the digital bit and a base electrode of a thirteenth triode in a second branch corresponding to the digital bit, and inputting an inverted input signal corresponding to the numerical value into a base electrode of an eighth triode in the first branch corresponding to the digital bit and a base electrode of a ninth triode in the second branch corresponding to the digital bit. The related operations are the same as or similar to those of the embodiment shown in fig. 1, and thus are not described in detail herein, and are incorporated by reference.

In some embodiments, the a-D converter includes a comparator unit that performs level comparison on the decision analog signal based on one or more reference input voltages, and a coding unit that encodes a comparison result of the comparator unit to output a decision vector. The related operations are the same as or similar to those of the embodiment shown in fig. 1, and thus are not described in detail herein, and are incorporated by reference.

In some embodiments, the comparator unit includes a first target triode, one or more second target triodes, the base input of the first target triode is the decision analog signal, the base input of each second target triode corresponds to different reference input voltages, the emitter of the first target triode and the emitter of each second target triode are connected, and the collector of each second target triode corresponds to one output terminal. The related operations are the same as or similar to those of the embodiment shown in fig. 1, and thus are not described in detail herein, and are incorporated by reference.

In addition to the methods and apparatus described in the above embodiments, the present application also provides a computer-readable storage medium storing computer code which, when executed, performs a method as described in any one of the preceding claims.

The application also provides a computer program product which, when executed by a computer device, performs a method as claimed in any preceding claim.

The present application also provides a computer device comprising:

one or more processors;

a memory for storing one or more computer programs;

the one or more computer programs, when executed by the one or more processors, cause the one or more processors to implement the method of any preceding claim.

FIG. 15 illustrates an exemplary system that may be used to implement various embodiments described in the present disclosure;

in some embodiments, as shown in fig. 15, the system 300 can function as any of the devices of the various described embodiments. In some embodiments, system 300 may include one or more computer-readable media (e.g., system memory or NVM/storage 320) having instructions and one or more processors (e.g., processor(s) 305) coupled with the one or more computer-readable media and configured to execute the instructions to implement the modules to perform the actions described in the present application.

For one embodiment, the system control module 310 may include any suitable interface controller to provide any suitable interface to at least one of the processor(s) 305 and/or any suitable device or component in communication with the system control module 310.

The system control module 310 may include a memory controller module 330 to provide an interface to the system memory 315. Memory controller module 330 may be a hardware module, a software module, and/or a firmware module.

The system memory 315 may be used, for example, to load and store data and/or instructions for the system 300. For one embodiment, system memory 315 may include any suitable volatile memory, such as, for example, a suitable DRAM. In some embodiments, the system memory 315 may comprise a double data rate type four synchronous dynamic random access memory (DDR 4 SDRAM).

For one embodiment, system control module 310 may include one or more input/output (I/O) controllers to provide an interface to NVM/storage 320 and communication interface(s) 325.

For example, NVM/storage 320 may be used to store data and/or instructions. NVM/storage 320 may include any suitable nonvolatile memory (e.g., flash memory) and/or may include any suitable nonvolatile storage device(s) (e.g., one or more Hard Disk Drives (HDDs), one or more Compact Disc (CD) drives, and/or one or more Digital Versatile Disc (DVD) drives).

NVM/storage 320 may include storage resources that are physically part of the device on which system 300 is installed or which may be accessed by the device without being part of the device. For example, NVM/storage 320 may be accessed over a network via communication interface(s) 325.

Communication interface(s) 325 may provide an interface for system 300 to communicate over one or more networks and/or with any other suitable device. The system 300 may wirelessly communicate with one or more components of a wireless network in accordance with any of one or more wireless network standards and/or protocols.

For one embodiment, at least one of the processor(s) 305 may be packaged together with logic of one or more controllers (e.g., memory controller module 330) of the system control module 310. For one embodiment, at least one of the processor(s) 305 may be packaged together with logic of one or more controllers of the system control module 310 to form a System In Package (SiP). For one embodiment, at least one of the processor(s) 305 may be integrated on the same die as logic of one or more controllers of the system control module 310. For one embodiment, at least one of the processor(s) 305 may be integrated on the same die with logic of one or more controllers of the system control module 310 to form a system on chip (SoC).

In various embodiments, the system 300 may be, but is not limited to being: a server, workstation, desktop computing device, or mobile computing device (e.g., laptop computing device, handheld computing device, tablet, netbook, etc.). In various embodiments, system 300 may have more or fewer components and/or different architectures. For example, in some embodiments, system 300 includes one or more cameras, keyboards, liquid Crystal Display (LCD) screens (including touch screen displays), non-volatile memory ports, multiple antennas, graphics chips, application Specific Integrated Circuits (ASICs), and speakers.

The present application also provides a computer device comprising:

one or more processors;

A memory for storing one or more computer programs;

It should be noted that the present application may be implemented in software and/or a combination of software and hardware, e.g., using Application Specific Integrated Circuits (ASIC), a general purpose computer or any other similar hardware device. In one embodiment, the software program of the present application may be executed by a processor to perform the steps or functions described above. Likewise, the software programs of the present application (including associated data structures) may be stored on a computer readable recording medium, such as RAM memory, magnetic or optical drive or diskette and the like. In addition, some steps or functions of the present application may be implemented in hardware, for example, as circuitry that cooperates with the processor to perform various steps or functions.

Furthermore, portions of the present application may be implemented as a computer program product, such as computer program instructions, which when executed by a computer, may invoke or provide methods and/or techniques in accordance with the present application by way of operation of the computer. Those skilled in the art will appreciate that the form of computer program instructions present in a computer readable medium includes, but is not limited to, source files, executable files, installation package files, etc., and accordingly, the manner in which the computer program instructions are executed by a computer includes, but is not limited to: the computer directly executes the instruction, or the computer compiles the instruction and then executes the corresponding compiled program, or the computer reads and executes the instruction, or the computer reads and installs the instruction and then executes the corresponding installed program. Herein, a computer-readable medium may be any available computer-readable storage medium or communication medium that can be accessed by a computer.

Communication media includes media whereby a communication signal containing, for example, computer readable instructions, data structures, program modules, or other data, is transferred from one system to another. Communication media may include conductive transmission media such as electrical cables and wires (e.g., optical fibers, coaxial, etc.) and wireless (non-conductive transmission) media capable of transmitting energy waves, such as acoustic, electromagnetic, RF, microwave, and infrared. Computer readable instructions, data structures, program modules, or other data may be embodied as a modulated data signal, for example, in a wireless medium, such as a carrier wave or similar mechanism, such as that embodied as part of spread spectrum technology. The term "modulated data signal" means a signal that has one or more of its characteristics set or changed in such a manner as to encode information in the signal. The modulation may be analog, digital or hybrid modulation techniques.

By way of example, and not limitation, computer-readable storage media may include volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer-readable instructions, data structures, program modules or other data. For example, computer-readable storage media include, but are not limited to, volatile memory, such as random access memory (RAM, DRAM, SRAM); and nonvolatile memory such as flash memory, various read only memory (ROM, PROM, EPROM, EEPROM), magnetic and ferromagnetic/ferroelectric memory (MRAM, feRAM); and magnetic and optical storage devices (hard disk, tape, CD, DVD); or other now known media or later developed computer-readable information/data that can be stored for use by a computer system.

An embodiment according to the application comprises an apparatus comprising a memory for storing computer program instructions and a processor for executing the program instructions, wherein the computer program instructions, when executed by the processor, trigger the apparatus to operate a method and/or a solution according to the embodiments of the application as described above.

It will be evident to those skilled in the art that the application is not limited to the details of the foregoing illustrative embodiments, and that the present application may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The present embodiments are, therefore, to be considered in all respects as illustrative and not restrictive, the scope of the application being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned. Furthermore, it is evident that the word "comprising" does not exclude other elements or steps, and that the singular does not exclude a plurality. A plurality of units or means recited in the apparatus claims can also be implemented by means of one unit or means in software or hardware. The terms first, second, etc. are used to denote a name, but not any particular order.

Claims

1. A method for artificial intelligence computation, wherein the method comprises:

obtaining input information for artificial intelligence computation;

2. The method of claim 1, wherein the artificial intelligence computing unit comprises an artificial intelligence computing analog circuit comprising an analog summing unit, an analog multiplying unit, an analog activation function filtering unit.

3. The method of claim 2, wherein the analog multiplication unit is a single logic gate and the analog addition unit is a single logic gate.

4. The method of claim 2, wherein the first artificial intelligence circuit comprises a D-a converter and an a-D converter;

the step of inputting the input information into a first artificial intelligence circuit to perform artificial intelligence calculation through the first artificial intelligence circuit to obtain a decision vector corresponding to the input information includes:

Inputting the input information into the D-A converter to obtain an output analog signal;

inputting the analog signal into the artificial intelligence computing analog circuit to obtain an output decision analog signal;

and inputting the decision analog signal into the A-D converter to obtain an output decision vector.

5. The method of claim 4, wherein the analog signal is located within a preset voltage interval centered around a zero reference voltage, wherein the zero reference voltage is a voltage less than a preset difference in supply voltage.

6. The method of claim 4, wherein the input information comprises a first input vector, a weight matrix, a bias vector;

wherein the inputting the input information into the D-a converter to obtain an output analog signal includes:

respectively inputting a first input vector, a weight matrix and a bias vector into the D-A converter to obtain a first analog signal, a second analog signal and a third analog signal which are output;

the step of inputting the analog signal into the artificial intelligence computing analog circuit to obtain an output decision analog signal comprises the following steps:

and inputting the first analog signal, the second analog signal and the third analog signal into the artificial intelligence computing analog circuit to obtain an output decision analog signal.

7. The method of claim 6, the inputting the first analog signal, the second analog signal, and the third analog signal into the artificial intelligence computing analog circuit to obtain an output decision analog signal, comprising:

inputting the first analog signal and a second decision analog signal output by a second artificial intelligent circuit positioned at the previous stage of the first artificial intelligent circuit into a multi-channel analog input selection unit to obtain an output target analog signal;

and inputting the target analog signal, the second analog signal and the third analog signal into the artificial intelligent computing analog circuit to obtain an output decision analog signal.

8. The method of claim 7, wherein the input voltage corresponding to the unused input terminal in the multi-path analog input selection unit is set to a lowest voltage of a preset voltage interval centered around a zero reference voltage.

9. The method of claim 6, wherein before the inputting of the first input vector, the weight matrix, and the bias vector to the D-a converter, respectively, results in the output first analog signal, the second analog signal, and the third analog signal, the method further comprises:

Splitting a target input vector into a plurality of first input vectors connected in parallel, so that each first input vector is input into one of a plurality of first artificial intelligent circuits connected in parallel in a cascading manner, and a decision vector corresponding to the output first input vector is obtained.

10. The method of claim 9, wherein a target artificial intelligence circuit of the plurality of first artificial intelligence circuits corresponds to one or more serially cascaded artificial intelligence circuits, the decision analog signal output by a previous artificial intelligence circuit being input to a subsequent artificial intelligence circuit as a first analog signal corresponding to the subsequent artificial intelligence circuit.

11. The method of claim 10, wherein a pipeline unit is disposed between a chip corresponding to a previous artificial intelligence circuit and a chip corresponding to a next artificial intelligence circuit, and the pipeline unit is configured to convert a decision analog signal output by the previous artificial intelligence circuit into a capacitance charge based on a negative feedback amplifier, and convert the capacitance charge into a corresponding first analog signal, and input the corresponding first analog signal to the next artificial intelligence circuit.

12. The method of claim 6, wherein said inputting the first analog signal, the second analog signal, and the third analog signal into the artificial intelligence computing analog circuit results in an output decision analog signal, comprising:

Inputting the first analog signal and the second analog signal into an analog multiplication unit in a first artificial intelligent circuit to obtain a plurality of output fourth analog signals;

inputting the plurality of fourth analog signals and the third analog signals into an analog adding unit in the first artificial intelligent circuit to obtain an output fifth analog signal;

and inputting the fifth analog signal into an analog activation function filtering unit in the first artificial intelligent circuit to obtain an output decision analog signal, wherein the decision analog signal is positioned in a preset voltage interval taking zero reference voltage as a center.

13. The method of claim 12, wherein said inputting the plurality of fourth analog signals, the third analog signals, into an analog adding unit in the first artificial intelligence circuit, results in an output fifth analog signal, comprising:

dividing the plurality of fourth analog signals into a plurality of packets, each packet including at least two fourth analog signals;

for each group, inputting at least two fourth analog signals in the group into an analog adding unit in the first artificial intelligent circuit to obtain an output sixth analog signal corresponding to the group;

And inputting the sixth analog signals corresponding to the groups and the third analog signals into another analog adding unit in the first artificial intelligent circuit to obtain output fifth analog signals.

14. The method of claim 12, wherein the fifth analog signal is compressed in the analog adding unit by the number of the plurality of fourth analog signals.

15. The method of claim 12, wherein each fourth analog signal is connected at a corresponding input in the analog summing unit to a resistor through which the fourth analog signal is scaled in the other analog summing unit, the third analog signal is connected at a corresponding input in the analog summing unit to another resistor through which the third analog signal is scaled in the other analog summing unit.

16. The method of claim 12, wherein the analog multiplication unit includes two output terminals with opposite polarities, the positive polarity output terminal in the analog multiplication unit outputs the fourth model signal if the polarity of the fourth analog signal is positive, and the negative polarity output terminal in the analog multiplication unit outputs the fourth model signal if the polarity of the fourth analog signal is negative.

17. The method of claim 16, wherein the analog multiplication unit comprises a fifth composite triode unit and a sixth composite triode unit, the fifth composite triode unit comprises a sixth target triode and a seventh target triode, the emitter of the sixth target triode and the emitter of the seventh target triode are connected through a first target resistor, the base input of the sixth target triode is the second analog signal, the base input of the seventh target triode is the first reference voltage, the sixth composite triode unit comprises an eighth target triode and a ninth target triode, the emitter of the eighth target triode and the emitter of the ninth target triode are also connected through a first target resistor, the base input of the eighth target triode is the first analog signal, the base input of the ninth target triode is the first reference voltage, the base input of the sixth composite triode is connected to the second analog signal through two second target resistors in parallel, the base input of the seventh target triode is the first reference voltage, the positive polarity output end, the negative polarity output end is connected to the analog signal in parallel through the second target resistor and the fourth target resistor in the analog resistor, and the analog signal is scaled according to the values of the second target resistor in the multiplication unit.

18. The method of claim 12, wherein the analog activation function filter unit comprises a seventh composite triode unit, a first target triode, a second target triode and a third target triode, wherein the seventh composite triode unit comprises a fourth target triode and a fifth target triode, an emitter of the fourth target triode is connected with an emitter of the fifth target triode, a base input of the fourth target triode is the fifth analog signal, a base input of the fifth target triode is a second reference voltage, an emitter of the fourth target triode and an emitter of the fifth target triode are both connected with the first target triode, a collector of the fifth target triode is connected with a base of the second target triode, an emitter of the second target triode is connected with a collector of the third target triode, the bases of the first target triode and the third target triode are biased, and an emitter of the second target triode is the output of the analog activation function filter unit.

19. The method of claim 4, wherein the input information comprises a plurality of digital bits;

and inputting an input signal corresponding to each digital bit in the input information into an input end corresponding to the digital bit in the D-A converter to obtain an output analog signal.

20. The method of claim 19, wherein the input information further comprises a polarity bit;

wherein for each numerical value on each digital bit in the input information, inputting an input signal corresponding to the numerical value into an input end corresponding to the digital bit in the D-a converter to obtain an output analog signal, and the method comprises the following steps:

and for the numerical value of each digital bit in the input information, inputting an input signal corresponding to the numerical value into an input end corresponding to the digital bit in the D-A converter, and inputting an input signal corresponding to the numerical value in the polarity bit in the input information into an input end corresponding to the polarity bit in the D-A converter to obtain an output analog signal.

21. The method of claim 19, wherein the D-a converter includes a first branch and a second branch corresponding to each digital bit, the first branch corresponding to each digital bit includes a first composite triode unit and a first triode corresponding to the digital bit, a base input of the first triode is a reference voltage, the first composite triode unit is connected with an output end of the D-a converter and a collector of the first triode, the second branch corresponding to each digital bit includes a second composite triode unit and a second triode corresponding to the digital bit, an emitter of the second triode is connected with a weighted resistor corresponding to the digital bit, and the second composite triode unit is connected with an output end of the D-a converter and a collector of the second triode;

and inputting an input signal corresponding to the numerical value into a first composite triode unit in a first branch corresponding to the numerical value and a second composite triode unit in a second branch corresponding to the numerical value to obtain an output analog signal for the numerical value on each numerical digit in the input information.

22. The method of claim 21, the first composite triode unit comprising a third triode and a fourth triode, the third triode having an emitter connected to the emitter of the fourth triode, the third triode having an emitter connected to the collector of the first triode, the third triode having a collector connected to the output of the D-a converter, the second composite triode unit comprising a fifth triode and a sixth triode, the fifth triode having an emitter connected to the emitter of the sixth triode, the fifth triode having an emitter connected to the collector of the second triode, the fifth triode having a collector connected to the output of the D-a converter;

The method for obtaining the output analog signal includes the steps of:

and inputting an input signal corresponding to the numerical value into the base electrode of a third triode in a first branch corresponding to the numerical value and the base electrode of a sixth triode in a second branch corresponding to the numerical value, and inputting an inverted input signal corresponding to the numerical value into the base electrode of a fourth triode in the first branch corresponding to the numerical value and the base electrode of a fifth triode in the second branch corresponding to the numerical value to obtain an output analog signal.

23. The method of claim 22, wherein the input information further comprises a polarity bit, the first branch corresponding to each digital bit further comprises a third composite triode unit corresponding to the polarity bit, the third composite triode unit comprises a seventh triode and an eighth triode, the emitter of the third triode and the emitter of the fourth triode are all connected with the collector of the seventh triode, the emitter of the seventh triode and the emitter of the eighth triode are all connected with the collector of the first triode, the second branch corresponding to each digital bit further comprises a fourth composite triode unit corresponding to the polarity bit, the fourth composite triode unit comprises a ninth triode and a thirteenth triode, the emitter of the fifth triode and the emitter of the sixth triode are all connected with the collector of the ninth triode, and the emitter of the ninth triode and the emitter of the tenth triode are all connected with the collector of the second triode;

The method includes inputting, for each numerical value in the input information, an input signal corresponding to the numerical value to a base of a third triode in a first branch corresponding to the numerical value and a base of a sixth triode in a second branch corresponding to the numerical value, inputting an inverted input signal corresponding to the numerical value to a base of a fourth triode in the first branch corresponding to the numerical value and a base of a fifth triode in the second branch corresponding to the numerical value, and obtaining an output analog signal, and further includes:

for each digital bit in the input information, inputting an input signal corresponding to a numerical value on a polarity bit in the input information into a base electrode of a seventh triode in a first branch corresponding to the digital bit and a base electrode of a thirteenth triode in a second branch corresponding to the digital bit, and inputting an inverted input signal corresponding to the numerical value into a base electrode of an eighth triode in the first branch corresponding to the digital bit and a base electrode of a ninth triode in the second branch corresponding to the digital bit.

24. The method of claim 4, wherein the a-D converter comprises a comparator unit that performs level comparison on the decision analog signal based on one or more reference input voltages, and a coding unit that encodes a comparison result of the comparator unit to output a decision vector.

25. The method of claim 24, wherein the comparator unit comprises a first target triode, one or more second target triodes, the base input of the first target triode is the decision analog signal, the base input of each second target triode corresponds to a different reference input voltage, the emitter of the first target triode and the emitter of each second target triode are connected, and the collector of each second target triode corresponds to an output terminal.

26. An apparatus for artificial intelligence computing, the apparatus comprising:

and the two-module is used for inputting the input information into the first artificial intelligent circuit so as to perform artificial intelligent calculation through an artificial intelligent calculation analog circuit in the first artificial intelligent circuit and obtain a decision vector corresponding to the input information.

27. A computer device for artificial intelligence computation, comprising a memory, a processor and a computer program stored on the memory, characterized in that the processor executes the computer program to carry out the steps of the method according to any one of claims 1 to 25.

28. A computer readable storage medium having stored thereon a computer program/instruction which when executed by a processor performs the steps of the method according to any of claims 1 to 25.

29. A computer program product comprising a computer program which, when executed by a processor, implements the steps of the method according to any one of claims 1 to 25.