WO2023130725A1

WO2023130725A1 - Hardware implementation method and apparatus for reservoir computing model based on random resistor array, and electronic device

Info

Publication number: WO2023130725A1
Application number: PCT/CN2022/112493
Authority: WO
Inventors: 尚大山; 李熠; 张握瑜; 王少聪; 王中锐
Original assignee: 中国科学院微电子研究所
Priority date: 2022-01-04
Filing date: 2022-08-15
Publication date: 2023-07-13
Also published as: CN114330697A

Abstract

A hardware implementation method and apparatus for a reservoir computing model based on a random resistor array, and an electronic device, which relate to the fields of machine learning and artificial intelligence. The method comprises: acquiring a random weight of a reservoir layer, which is generated on the basis of a resistance-variable device crossbar array; applying a breakdown voltage to the resistance-variable device crossbar array, so as to form a randomly distributed random resistance matrix; converting an input signal into a read voltage signal by means of a circuit of a printed circuit board, and performing, on the basis of the read voltage signal and the random resistance matrix, vector matrix multiplication to determine an output voltage signal; and repeating the step of converting an input signal into a read voltage signal by means of the circuit of the printed circuit board and performing, on the basis of the read voltage signal and the random resistance matrix, vector matrix multiplication to determine an output voltage signal, and then simulating a loop iteration process of the reservoir layer. Therefore, the efficient hardware realization of a large-scale random weight and a reservoir computing model is achieved, and in an edge computing application scenario in which the computing power is limited, the possibility is provided for the efficient hardware realization of the reservoir computing model.

Description

A hardware implementation method, device and electronic equipment of a reserve pool calculation model based on a random resistance array

This application claims the priority of a Chinese patent submitted to the China Patent Office on January 04, 2022, with the application number 202210002137.5, and the application name "A hardware implementation method, device and electronic equipment for a storage pool calculation model based on a random resistor array" , the entire contents of which are incorporated in this application by reference.

technical field

The present application relates to the field of machine learning and artificial intelligence, and in particular to a hardware implementation method, device and electronic equipment of a reserve pool calculation model based on a random resistance array.

Background technique

With the development of machine learning and artificial intelligence, deep learning technology based on artificial neural network has also developed rapidly, especially in many fields such as image recognition and natural language processing. However, with the advent of the Internet of Things era, many new application scenarios such as autonomous driving and smart home require us not only to be able to handle static tasks, but also to have the ability to process dynamic tasks in real time. The traditional recurrent neural network and its variants can effectively deal with dynamic systems containing timing information, but there are some limitations, including large number of parameters, large amount of calculation, complex training, high cost, and difficult hardware implementation. The above problems lead to the widespread limitation of recurrent neural networks in application scenarios with limited computing power resources.

In order to solve the above problems, the reserve pool calculation model is proposed as an efficient neural network algorithm. As a special recurrent neural network, the reserve pool calculation model consists of an input layer, a reserve pool layer containing nonlinear nodes, and a readout layer. The nodes in the reserve layer are initialized randomly, and the current state of each node is not only related to the input, but also depends on the previous state. During the training process of the model, neither the input weight nor the weight of the reserve pool node needs to be changed, only the final readout layer needs to be trained. This not only preserves the ability of the model to deal with timing problems, but also greatly shortens the model training time and reduces the difficulty of training. It is very suitable for edge computing application scenarios with limited computing power in the Internet of Things era.

However, as Moore's Law has approached the physical limit, it is difficult to further reduce the size of the transistor, and the computing power and energy efficiency of the chip tend to be the bottleneck. At the same time, the traditional Von Neumann architecture that separates storage and computing also faces the problem of storage walls and power consumption walls, which makes it difficult for traditional hardware platforms to efficiently run the reserve pool computing model. The storage-computing integrated hardware based on new neuromorphic devices can effectively reduce the migration of data between computing and storage units, and greatly reduce the vector matrix multiplication in the reserve pool calculation model through Kirchhoff's law and Ohm's law. Operation, thereby greatly improving processing speed and reducing system power consumption.

However, because the reserve pool calculation model requires large-scale random weights, and the existing method of generating random weights through traditional digital circuits and then mapping them to neuromorphic device arrays is very inefficient and has high implementation costs, making the new neuromorphic device-based The storage-computing integrated hardware is still facing great challenges in implementing the reserve pool computing model.

Contents of the invention

In view of this, the present application discloses a hardware implementation method, device and electronic equipment for a storage pool calculation model based on a random resistance array, which are used to provide a hardware implementation method and device for a storage pool calculation model based on a random resistance array.

In the first aspect, the present application provides a hardware implementation method of a reserve pool calculation model based on a random resistance array, which is applied to electronic equipment running the reserve pool calculation model, and the electronic equipment has a resistive switch device composed of multiple resistive switch devices such as The cross array and the printed circuit board circuit, the cross array of the resistive variable devices are electrically connected to the printed circuit board circuit; the number of the resistive variable devices is the same as the corresponding number of trained weights in the electronic equipment, so The storage pool calculation model based on the random resistance array includes a storage pool layer, and the method includes:

Obtaining the random weight of the reserve pool layer generated based on the intersecting array of resistive switching devices;

forming a randomly distributed random resistance matrix by applying a breakdown voltage to the intersecting array of resistive switching devices;

converting the input signal into a read voltage signal through the printed circuit board circuit, and performing vector matrix multiplication based on the read voltage signal and the random resistance matrix to determine the output voltage signal;

Repeating the step of converting the input signal into a read voltage signal by the printed circuit board circuit, and performing vector matrix multiplication to determine the output voltage signal based on the read voltage signal and the random resistance matrix, simulating the cyclic iteration of the reserve pool layer process until the output voltage signal is determined to be the final target output voltage signal when it is determined that the input signal satisfies the output preset condition.

In the case of adopting the above technical solution, the hardware implementation method of the reserve pool calculation model based on the random resistance array provided in the embodiment of the present application can obtain the random weight of the reserve pool layer generated based on the cross array of the resistive variable device, through Apply a breakdown voltage to the cross array of resistive switching devices to form a randomly distributed random resistance matrix, convert the input signal into a read voltage signal through the printed circuit board circuit, based on the read voltage signal and the random resistance matrix performing vector matrix multiplication to determine the output voltage signal, repeating the step of converting the input signal into a read voltage signal by the printed circuit board circuit, and performing vector matrix multiplication based on the read voltage signal and the random resistance matrix to determine the output voltage signal, Simulating the iterative process of the reserve pool layer until the output voltage signal is determined to be the final target output voltage signal when the input signal satisfies the output preset condition. The hardware implementation method of the calculation model of the reserve pool is to perform a breakdown operation by applying a breakdown voltage to the cross array of resistive switching devices composed of resistive switching devices, and to use the breakdown randomness of the resistive switching devices themselves to generate large-scale The random resistor array and the random weights formed by the random resistor array can efficiently implement the reserve pool calculation model in hardware, and provide the possibility for the hardware to efficiently implement the reserve pool calculation model in the edge computing application scenario with limited computing power.

In a possible implementation manner, the random resistance matrix represents the breakdown voltage, each of the resistive switching devices in the interleaved array of resistive switching devices is in a breakdown state or is not broken down at random state, and the random conductance state of each device after being subjected to breakdown, including a double random state.

In a possible implementation manner, the converting the input signal into a read voltage signal through the printed circuit board circuit, and performing vector matrix multiplication based on the read voltage signal and the random resistance matrix to determine the output voltage signal includes :

The input signal is converted into a read voltage signal through the printed circuit board circuit, the read voltage signal is applied to the random resistance matrix, and the read voltage signal and the The random resistance matrix is processed by vector matrix multiplication to determine the output voltage signal.

In a possible implementation manner, the repeated conversion of the printed circuit board circuit from an input signal into a read voltage signal, and performing vector matrix multiplication on the basis of the read voltage signal and the random resistance matrix to determine the output voltage signal Step, simulating the cyclic iterative process of the reserve pool layer until the output voltage signal is determined to be the final target output voltage signal under the condition that the input signal satisfies the output preset condition, including:

repeating the process of converting the input signal into a read voltage signal through the printed circuit board circuit, applying the read voltage signal to the random resistance matrix, and converting the read voltage signal to Perform vector matrix multiplication processing with the random resistance matrix, determine the step of output voltage signal, simulate the cycle iteration process of the reserve pool layer, until the input signal is determined to meet the output preset condition, determine the The output voltage signal is the final target output voltage signal.

In a possible implementation manner, the reserve pool calculation model further includes a classification layer connected to the reserve pool layer, and the target output voltage signal includes a data set characterizing node characteristics in the determination of the output voltage After the signal is the final target output voltage signal, the method also includes:

The target output voltage signal is input to the classification layer, and after the classification process is performed on the data set in the target output voltage signal, the prediction result is finally determined and output.

In a possible implementation manner, the electronic device further includes an on-board digital processor electrically connected to the cross array of resistive switching devices and the printed circuit board circuit, and the on-board digital processor is used to perform the classification of the classification layer. number crunching.

In the second aspect, the present application also provides a hardware realization device of a reserve pool calculation model based on a random resistance array, which is applied to electronic equipment running the reserve pool calculation model, and the electronic equipment has a resistive switch composed of multiple resistive switch devices such as A cross array of devices and a printed circuit board circuit, the cross array of resistive variable devices is electrically connected to the printed circuit board circuit; the number of the resistive variable devices is the same as the number of corresponding trained weights in the electronic device, The storage pool calculation model based on the random resistance array includes a storage pool layer, and the device includes:

a random weight acquisition module, configured to acquire the random weight of the reserve pool layer generated based on the intersecting array of resistive switching devices;

A breakdown voltage applying module, configured to form a randomly distributed random resistance matrix by applying a breakdown voltage to the intersecting array of resistive switching devices;

An output voltage determination module, configured to convert the input signal into a read voltage signal through the printed circuit board circuit, and determine the output voltage signal by vector matrix multiplication based on the read voltage signal and the random resistance matrix;

The target output voltage signal determination module is used to repeat the step of converting the input signal into a read voltage signal by the printed circuit board circuit, and performing vector matrix multiplication based on the read voltage signal and the random resistance matrix to determine the output voltage signal, Simulating the cyclic iterative process of the reserve pool layer until the output voltage signal is determined to be the final target output voltage signal when the input signal is determined to meet the output preset condition.

In a possible implementation manner, the output voltage signal determination module includes:

The output voltage signal determination sub-module is used to convert the input signal into a read voltage signal through the printed circuit board circuit, apply the read voltage signal to the random resistance matrix, and use Kirchhoff's law and Ohm's law performing vector matrix multiplication processing on the read voltage signal and the random resistance matrix to determine an output voltage signal;

The random resistance matrix represents that under the breakdown voltage, each of the resistive switching devices in the cross array is in a breakdown state or a random state without breakdown, and the random state of each device after being broken down. Conductance states, including double random states.

In a possible implementation manner, the target output voltage signal determination module includes:

The target output voltage signal determination sub-module is used to repeat the conversion of the input signal into a read voltage signal through the printed circuit board circuit, apply the read voltage signal to the random resistance matrix, and use Kirchhoff law and Ohm's law, the read voltage signal and the random resistance matrix are subjected to vector matrix multiplication processing, and the step of determining the output voltage signal simulates the iterative process of the reserve pool layer until the input signal is determined to meet the output In the case of preset conditions, the output voltage signal is determined to be the final target output voltage signal.

The reserve pool calculation model also includes a classification layer connected to the reserve pool layer, and the device also includes:

The prediction result output module is configured to input the target output voltage signal into the classification layer, and finally determine and output the prediction result after the classification process is performed on the data sets in the target output voltage signal.

The electronic equipment also includes an on-board digital processor electrically connected to the cross array of resistive variable devices and the printed circuit board circuit, and the on-board digital processor is used to perform digital operations on the classification layer.

The beneficial effect of the hardware implementation device of the storage pool calculation model based on the random resistance array provided by the second aspect is the same as the hardware implementation method of the storage pool calculation model based on the random resistance array described in the first aspect or any possible implementation of the first aspect. The beneficial effects are the same, and will not be repeated here.

In a third aspect, the present application also provides an electronic device, including: one or more processors; and one or more machine-readable media having instructions stored thereon, when executed by the one or more processors , so that the device executes the hardware implementation device of the random resistance array-based reserve pool calculation model described in any possible implementation manner of the second aspect.

The beneficial effect of the electronic device provided by the third aspect is the same as that of the hardware implementation device of the storage pool calculation model based on the random resistance array described in the second aspect or any possible implementation of the second aspect, and details are not repeated here.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will describe the drawings that need to be used in the description of the embodiments or the prior art:

Fig. 1 shows a schematic structural diagram of a hardware implementation method of a reserve pool calculation model based on a random resistance array provided in an embodiment of the present application;

FIG. 2 shows a schematic structural diagram of another hardware implementation method of a reserve pool calculation model based on a random resistance array provided by an embodiment of the present application;

Fig. 3 shows a schematic diagram of using a cross array of resistive devices to form random weights provided by the embodiment of the present application;

Fig. 4 shows a breakdown voltage distribution diagram of a resistive switch device cross array composed of a resistive switch device provided by an embodiment of the present application;

Fig. 5 shows a schematic structural diagram of a cross array of resistive switching devices and a printed circuit board circuit provided by an embodiment of the present application;

FIG. 6 shows a schematic diagram of a network structure for implementing a reserve pool calculation model provided by an embodiment of the present application;

FIG. 7 shows a schematic diagram of a network CORA dataset provided by an embodiment of the present application;

Fig. 8 shows a schematic diagram of the accuracy rate of a reserve pool calculation model based on a random resistance array measured by hardware according to an embodiment of the present application;

Fig. 9 shows a schematic diagram of the comparison of the number of operands and power consumption between an electronic device running a reserve pool calculation model provided by an embodiment of the present application and a traditional CMOS digital circuit system hardware implementing the reserve pool calculation model;

FIG. 10 shows a schematic structural diagram of a hardware implementation device for a reserve pool calculation model based on a random resistance array provided by an embodiment of the present application;

FIG. 11 is a schematic diagram of a hardware structure of an electronic device provided by an embodiment of the present application;

FIG. 12 is a schematic structural diagram of a chip provided by an embodiment of the present application.

Detailed ways

The core of the present application is to provide a hardware implementation method of a reserve pool calculation model based on a random resistance array. Fig. 1 shows a schematic flowchart of a hardware implementation method of a reserve pool calculation model based on a random resistance array provided by an embodiment of the present application, the hardware implementation method of the reserve pool calculation model is applied to an electronic device running the reserve pool calculation model, The electronic equipment has a resistive switching device cross array and a printed circuit board circuit composed of a plurality of resistive switching devices, and the resistive switching device cross array is electrically connected to the printed circuit board circuit; the number of the resistive switching devices The number of weights corresponding to the training in the electronic device is the same, and the reserve pool calculation model based on the random resistor array includes a reserve pool layer. As shown in Figure 1, the hardware implementation method of the reserve pool computing model includes:

Step 101: Obtain the random weight of the reserve pool layer generated based on the intersecting array of resistive switching devices.

In this application, the same number of resistive devices as the weights trained in the electronic device can be used to form a cross array of resistive devices to generate random weights of the reserve pool layer in the reserve pool calculation model.

Step 102: Form a randomly distributed random resistance matrix by applying a breakdown voltage to the intersecting array of resistive switching devices.

Wherein, the random resistance matrix represents that under the breakdown voltage, each of the resistive switching devices in the cross array of resistive switching devices is in a breakdown state or a non-breakdown state.

In this application, by applying a breakdown voltage to the resistive switching device, the randomness of device breakdown can be used to form a randomly distributed breakdown-non-breakdown random state, and the random conductance state of each device after being broken down, Contains a double random resistor matrix, where the random distribution can be tuned by applying different breakdown voltages.

Step 103: Convert the input signal into a read voltage signal through the printed circuit board circuit, and perform vector matrix multiplication based on the read voltage signal and the random resistance matrix to determine an output voltage signal.

In this application, the input signal can be converted into a read voltage signal through the printed circuit board circuit, the read voltage signal is applied to the random resistance matrix, and the The read voltage signal and the random resistance matrix are subjected to vector matrix multiplication processing to determine the output voltage signal.

Step 104: repeating the step of converting the input signal into a read voltage signal by the printed circuit board circuit, performing vector matrix multiplication based on the read voltage signal and the random resistance matrix to determine the output voltage signal, and simulating the reserve pool layer The loop iterative process until the output voltage signal is determined to be the final target output voltage signal in the case of determining that the input signal satisfies the output preset condition.

In the present application, the conversion of the input signal into a read voltage signal through the printed circuit board circuit can be repeated, and the read voltage signal is applied to the random resistance matrix, using Kirchhoff's law and Ohm's law Performing vector matrix multiplication processing on the read voltage signal and the random resistance matrix to determine the output voltage signal, simulating the cyclic iteration process of the reserve pool layer, so as to realize the hardware implementation of the reserve pool layer until the When the input signal satisfies the output preset condition, it is determined that the output voltage signal is the final target output voltage signal, and the target output voltage signal can be input to the classification layer, and the target output voltage signal can be output at the classification layer After the data set in the voltage signal is classified, the prediction result is finally determined and output.

In this application, the hardware implementation method of the above-mentioned reserve pool calculation model based on the random resistance array is to perform a breakdown operation by applying a breakdown voltage to the cross array of resistive switching devices composed of resistive switching devices, and to use the breakdown randomness of the resistive switching device itself A large-scale random resistor array is generated quickly and at low cost. The random weights formed by the random resistor array can efficiently implement the reserve pool calculation model in hardware, which provides a high-efficiency hardware implementation of the reserve pool calculation model in edge computing application scenarios with limited computing power. possible.

The hardware implementation method of the storage pool calculation model based on the random resistance array provided in the embodiment of the present application can obtain the random weight of the storage pool layer generated based on the cross array of the resistive switching devices, and pass the cross array of the resistive switching devices Apply a breakdown voltage to form a randomly distributed random resistance matrix, convert the input signal into a read voltage signal through the printed circuit board circuit, and perform vector matrix multiplication based on the read voltage signal and the random resistance matrix to determine the output voltage signal , repeating the step of converting the input signal into a read voltage signal by the printed circuit board circuit, and performing vector matrix multiplication based on the read voltage signal and the random resistance matrix to determine the output voltage signal, simulating the cycle of the reserve pool layer An iterative process until the output voltage signal is determined to be the final target output voltage signal when it is determined that the input signal satisfies the output preset condition, wherein, due to the above-mentioned hardware implementation method of the reserve pool calculation model based on a random resistor array , the breakdown operation is performed by applying a breakdown voltage to the cross array of resistive switching devices composed of resistive switching devices, using the breakdown randomness of the resistive switching device itself to generate a large-scale random resistance array quickly and at low cost, the random resistance array consists of The random weights can efficiently implement the reserve pool calculation model in hardware, and provide the possibility for hardware to efficiently implement the reserve pool calculation model in edge computing application scenarios with limited computing power.

Optionally, FIG. 2 shows a schematic flowchart of another hardware implementation method for a reserve pool calculation model based on a random resistor array provided in an embodiment of the present application, which is applied to an electronic device running a reserve pool calculation model, and the electronic device A cross array of resistance switching devices and a printed circuit board circuit composed of a plurality of resistance switching devices, the cross array of resistance switching devices and the printed circuit board circuit are electrically connected; the number of the resistance switching devices and the electronic equipment The number of weights corresponding to the training is the same, the reserve pool calculation model based on the random resistance array includes a reserve pool layer, and the reserve pool calculation model also includes a classification layer connected to the reserve pool layer, as shown in Figure 2 , methods include:

Step 201: Obtain the random weight of the reserve pool layer generated based on the intersecting array of resistive switching devices.

Optionally, the resistive switching device may include any one of a memristor, a phase change memory, a ferroelectric tunneling device, or a magnetic random access memory, and may also include other resistive switching devices, which are not specifically limited in this embodiment of the present application , and can be adjusted according to actual application scenarios.

Fig. 3 shows a schematic diagram of a random weight using a cross array of resistive switching devices provided by an embodiment of the present application. As shown in Fig. 3, A represents a cross array of resistive switching devices composed of multiple resistive switching devices, and B represents a resistive switching device The measured conductance distribution diagram of the cross array of resistive switching devices composed of devices can use the resistive switching devices with the same number of trained weights in the electronic equipment to form the cross array A of resistive switching devices, and generate the reserve pool in the calculation model of the reserve pool The random weight of the layer, from the conductance distribution diagram B, it can be seen that under a given breakdown voltage, the cross-array of resistive switching devices forms a random breakdown-unbreakdown random resistance array, and the device conductance value has Random distribution properties. A large number of random weights composed of random resistor arrays have good random characteristics and meet the requirements of the reserve pool calculation model.

Step 202: Form a randomly distributed random resistance matrix by applying a breakdown voltage to the intersecting array of resistive switching devices.

Wherein, the random resistance matrix represents that under the breakdown voltage, each of the resistive switching devices in the intersecting array of resistive switching devices is in a breakdown state or a random state without breakdown, and after being broken down Random conductance states for each device, including double random states.

Optionally, the value of the breakdown voltage is between 3.0 volts and 3.7 volts, and the breakdown operation is performed on the resistive switching device. The embodiment of the present application does not limit the specific value of the breakdown voltage, and it can be marked and adjusted according to the actual application scenario . Due to the randomness of the resistive switching device itself, whether the resistive switching device breaks down at a given breakdown voltage and the conductance after the breakdown operation are random, so a random distribution composed of breakdown and non-breakdown devices can be obtained The resistance array can adjust the random distribution by adjusting the size of the applied breakdown voltage, so that the large-scale random weight required by the reserve pool layer can be obtained quickly and at low cost, and the generated random resistance array can be used as the reserve pool layer The random weight matrix of .

Fig. 4 shows the distribution diagram of the breakdown voltage of a resistive switching device cross array composed of resistive switching devices provided by the embodiment of the present application. As shown in Fig. 4, the breakdown voltage of the device is random, so when a given When the breakdown voltage is reached, whether the device breaks down and the conductance after the breakdown operation will obey the random distribution, so this randomness can be used to generate a large number of random weights required by the reserve pool layer in the reserve pool model quickly and at low cost. At the same time, the random distribution can be further tuned by changing the breakdown voltage.

Step 203: Convert the input signal into a read voltage signal through the printed circuit board circuit, apply the read voltage signal to the random resistance matrix, and use Kirchhoff's law and Ohm's law to convert the read voltage signal Perform vector matrix multiplication processing with the random resistance matrix to determine the output voltage signal.

In this application, Fig. 5 shows a schematic structural diagram of a cross array of resistive switching devices and a printed circuit board circuit provided by an embodiment of the present application. As shown in Fig. 5, a random resistor array and a resistive switching device array (resistive switching device A cross array) C and a printed circuit board (PCB) circuit D, and the resistive variable device cross array C is electrically connected to the printed circuit board circuit D. Wherein, the size of the interleaved array of resistive switching devices composed of resistive switching devices may be 256Kb, and consists of 512 columns and 512 rows.

In this application, the hardware system consists of a Field Programmable Gate Array (Field Programmable Gate Array, FPGA) with an ARM core, a resistive switching device cross array composed of resistive switching devices, and a high-speed PCB circuit. The PCB circuit contains common electronic devices such as digital-to-analog converters, multiplexers, analog-to-digital converters, and transconductance amplifiers. The read voltage is converted by the digital-to-analog converter and input to the array from the bit line through the decoding circuit. The result of the vector matrix multiplication is obtained by reading the current gathered at the source line. The result is converted by the analog-to-digital converter and amplified by the transconductance amplifier. Input to the onboard digital processor for subsequent calculations.

Step 204: Repeat the conversion of the input signal into a read voltage signal through the printed circuit board circuit, apply the read voltage signal to the random resistance matrix, and convert the The step of performing vector matrix multiplication processing on the read voltage signal and the random resistance matrix, determining the output voltage signal, simulating the cyclic iteration process of the reserve pool layer, until it is determined that the input signal satisfies the output preset condition, The output voltage signal is determined as the final target output voltage signal.

Step 205: Input the target output voltage signal into the classification layer, and after the classification process is performed on the data set in the target output voltage signal, the prediction result is finally determined and output.

In the present application, the electronic device further includes an onboard digital processor electrically connected to the cross array of resistive variable devices and the printed circuit board circuit, and the onboard digital processor is used to perform digital operations on the classification layer.

As an example, FIG. 6 shows a schematic diagram of a network structure for implementing a reserve pool calculation model based on a random resistance array provided by an embodiment of the present application. As shown in FIG. 6 , the network structure includes an input layer 01 and a reserve pool layer 02 , classification layer 03 and output layer 04, wherein the reserve pool layer is also a random weight layer, the classification layer is also a fully connected neural network layer or a linear regression layer, the input signal is input from the input layer, and after passing through the reserve pool layer, the Iteration completion judgment, when the iteration is not completed, return to the reserve pool layer for processing, until when the iteration is completed, output the signal to the classification layer, and finally output the prediction result from the output layer.

Optionally, the typical values of the number of nodes and the number of weights used in the reserve pool layer are 50 and 2500 respectively, and the classification layer is realized by two methods of multi-layer fully connected neural network or linear regression, wherein the multi-layer fully connected neural network can specifically be A double-layer fully connected layer with a structure of 2500-50-3 is used. The double-layer fully connected layer means that the number of nodes in each hidden layer in the neural network is 64, 256 and 10. The linear regression adopts the ridge regression method.

Optionally, the hardware platform of this application may include a ZYNQ XC7Z020 FPGA with an ARM core and a 256Kb resistive variable device array chip; the software platform is CPU: i7-6700K, GPU: GTX1060 6G, Pytorch: 1.6.0.

This application specifically refers to the network CORA data set in the experiment. Figure 7 shows a schematic diagram of a network CORA data set provided by the embodiment of the present application. As shown in Figure 7, the CORA data set is typical data for node classification in neural networks set. Each node in the graph represents an academic article, and the connecting edge between points indicates that there is a citation relationship between two articles. The number of nodes is 2708, there are 7 categories in total, and the feature dimension of nodes is 1433. This application is tested on the CORA data set of the citation network, and its average recognition rate reaches 87.12%, and the number of operations and system energy consumption are reduced by about 300 times.

As an example, FIG. 8 shows a schematic diagram of the accuracy of a hardware measured reserve pool calculation model provided by the embodiment of the present application. It can be seen from FIG. 8 that the reserve pool calculation model implemented on a hardware system based on a random resistor array It has a good performance on the CORA data set, with an average accuracy rate of 87.12%, which is comparable to the existing results based on traditional CMOS digital circuit systems.

Exemplarily, Fig. 9 shows a kind of random resistance array hardware system (the electronic device that runs the reserve pool calculation model) and the traditional CMOS digital circuit system hardware implementation reserve pool calculation model provided by the embodiment of the present application in terms of operands and power consumption comparison diagram. It can be seen that by using the hardware implementation scheme of the storage-computing integrated architecture based on random resistor arrays, the complexity of hardware implementation is greatly reduced, thereby greatly optimizing the number of operations and system power consumption, which is reduced by about 300 times.

The hardware implementation method of the storage pool calculation model based on the random resistance array provided in the embodiment of the present application can obtain the random weight of the storage pool layer generated based on the cross array of the resistive switching devices, and by crossing the resistive switching devices The array applies a breakdown voltage to form a randomly distributed random resistance matrix, the input signal is converted into a read voltage signal through the printed circuit board circuit, and the output voltage is determined by vector matrix multiplication based on the read voltage signal and the random resistance matrix signal, repeating the step of converting the input signal into a read voltage signal by the printed circuit board circuit, determining the output voltage signal based on the read voltage signal and the random resistance matrix, and simulating the step of the output voltage signal of the reserve pool layer The iterative process is repeated until the output voltage signal is determined to be the final target output voltage signal when it is determined that the input signal satisfies the output preset condition, wherein, due to the hardware implementation of the above-mentioned reserve pool calculation model based on a random resistance array The method is to perform a breakdown operation by applying a breakdown voltage to a cross-array composed of resistive switching devices, and use the randomness of the breakdown of the resistive switching device itself to generate a large-scale random resistance array quickly and at low cost. The weight can efficiently realize the calculation model of the reserve pool in hardware, which provides the possibility for the hardware to efficiently realize the calculation model of the reserve pool in the edge computing application scenario with limited computing power.

Fig. 10 shows a schematic structural diagram of a hardware implementation device for a reserve pool calculation model based on a random resistance array provided by an embodiment of the present application, which is applied to an electronic device running a reserve pool calculation model, and the electronic device has multiple resistive devices such as A cross array of resistive switching devices and a printed circuit board circuit are formed, and the cross array of resistive switching devices is electrically connected to the printed circuit board circuit; the number of the resistive switching devices and the corresponding trained The number of weights is the same, and the reserve pool calculation model based on the random resistance array includes a reserve pool layer. As shown in FIG. 10 , the hardware implementation device 300 of the reserve pool calculation model includes:

A random weight acquisition module 301, configured to acquire the random weight of the reserve pool layer generated based on the intersecting array of resistive switching devices;

A breakdown voltage applying module 302, configured to form a randomly distributed random resistance matrix by applying a breakdown voltage to the intersecting array of resistive switching devices;

An output voltage determination module 303, configured to convert the input signal into a read voltage signal through the printed circuit board circuit, and perform matrix-vector multiplication based on the read voltage signal and the random resistance matrix to determine the output voltage signal;

The target output voltage signal determination module 304 is used to repeat the step of converting the input signal into a read voltage signal by the printed circuit board circuit, and performing matrix-vector multiplication based on the read voltage signal and the random resistance matrix to determine the output voltage signal. , simulating a cyclic iterative process of the reserve pool layer, until the output voltage signal is determined to be the final target output voltage signal under the condition that the input signal satisfies the output preset condition.

Optionally, the output voltage signal determination module includes:

Optionally, the target output voltage signal determination module includes:

The hardware implementation device for the calculation model of the reserve pool provided in the embodiment of the present application can obtain the random weight of the reserve pool layer generated based on the intersecting array of resistive switching devices, and apply a breakdown voltage to the intersecting array of resistive switching devices, forming a randomly distributed random resistance matrix, converting the input signal into a read voltage signal through the printed circuit board circuit, performing matrix-vector multiplication based on the read voltage signal and the random resistance matrix to determine the output voltage signal, and repeating the printing The circuit board circuit converts the input signal into a read voltage signal, and performs vector matrix multiplication based on the read voltage signal and the random resistance matrix to determine the output voltage signal, simulating the cyclic iteration process of the reserve pool layer until the When it is determined that the input signal satisfies the output preset condition, the output voltage signal is determined to be the final target output voltage signal, wherein, due to the above-mentioned hardware implementation method of the reserve pool calculation model based on the random resistance array, the resistance A cross-array of resistive variable devices composed of variable devices applies a breakdown voltage for breakdown operation, and a large-scale random resistance array is generated quickly and at low cost by using the breakdown randomness of the resistive variable device itself. The random weights formed by the random resistance array can be efficiently The computing model of the reserve pool is realized by the hardware, which provides the possibility for the hardware to efficiently realize the computing model of the reserve pool in the edge computing application scenario with limited computing power.

A hardware implementation device for a reserve pool calculation model provided by the present application is applied to the hardware implementation of the reserve pool calculation model shown in any one of Figures 1 to 9 including a controller and at least one detection circuit electrically connected to the controller method, in order to avoid repetition, it is not repeated here.

The electronic device in the embodiment of the present application may be a device, or may be a component, an integrated circuit, or a chip in a terminal. The device may be a mobile electronic device or a non-mobile electronic device. Exemplarily, the mobile electronic device may be a mobile phone, a tablet computer, a notebook computer, a handheld computer, a vehicle electronic device, a wearable device, an ultra-mobile personal computer (ultra-mobile personal computer, UMPC), a netbook or a personal digital assistant (personal digital assistant). assistant, PDA), etc., non-mobile electronic devices can be servers, network attached storage (Network Attached Storage, NAS), personal computer (personal computer, PC), television (television, TV), teller machine or self-service machine, etc., this application Examples are not specifically limited.

The electronic device in this embodiment of the present application may be a device with an operating system. The operating system may be an Android (Android) operating system, an ios operating system, or other possible operating systems, which are not specifically limited in this embodiment of the present application.

FIG. 11 shows a schematic diagram of a hardware structure of an electronic device provided by an embodiment of the present application. As shown in FIG. 11 , the electronic device 400 includes a processor 410 .

As shown in Figure 11, the above-mentioned processor 410 can be a general central processing unit (central processing unit, CPU), a microprocessor, an application-specific integrated circuit (application-specific integrated circuit, ASIC), or one or more for controlling This application programs the implementation of integrated circuits.

As shown in FIG. 11 , the electronic device 400 may further include a communication line 440 . Communication line 440 may comprise a pathway for communicating information between the above-described components.

Optionally, as shown in FIG. 11 , the electronic device may further include a communication interface 420 . There may be one or more communication interfaces 420 . Communication interface 420 may use any transceiver-like device for communicating with other devices or a communication network.

Optionally, as shown in FIG. 11 , the electronic device may further include a memory 430 . The memory 430 is used to store computer-executed instructions for implementing the solutions of the present application, and the execution is controlled by the processor. The processor is configured to execute the computer-executed instructions stored in the memory, so as to realize the method provided by the embodiment of the present application.

As shown in Figure 11, the memory 430 can be a read-only memory (read-only memory, ROM) or other types of static storage devices that can store static information and instructions, a random access memory (random access memory, RAM) or can store Other types of dynamic storage devices for information and instructions can also be electrically erasable programmable read-only memory (EEPROM), compact disc read-only memory (CD-ROM) or Other optical disc storage, optical disc storage (including compact disc, laser disc, optical disc, digital versatile disc, blu-ray disc, etc.), magnetic disc storage medium or other magnetic storage device, or can be used to carry or store desired information in the form of instructions or data structures program code and any other medium that can be accessed by a computer, but is not limited to this. The memory 430 may exist independently, and is connected to the processor 410 through the communication line 440 . The memory 430 can also be integrated with the processor 410 .

Optionally, the computer-executed instructions in the embodiments of the present application may also be referred to as application program codes, which is not specifically limited in the embodiments of the present application.

In a specific implementation, as an example, as shown in FIG. 11 , the processor 410 may include one or more CPUs, such as CPU0 and CPU1 in FIG. 11 .

In a specific implementation, as an example, as shown in FIG. 11 , a terminal device may include multiple processors, such as a first processor 4101 and a second processor 4102 in FIG. 11 . Each of these processors can be a single-core processor or a multi-core processor.

FIG. 12 is a schematic structural diagram of a chip provided by an embodiment of the present application. As shown in FIG. 12 , the chip 500 includes one or more than two (including two) processors 410 .

Optionally, as shown in FIG. 12, the chip further includes a communication interface 420 and a memory 430. The memory 430 may include a read-only memory and a random access memory, and provides operation instructions and data to the processor. A portion of the memory may also include non-volatile random access memory (NVRAM).

In some implementations, as shown in FIG. 12 , the memory 430 stores the following elements, execution modules or data structures, or their subsets, or their extended sets.

In the embodiment of the present application, as shown in FIG. 12 , corresponding operations are executed by calling an operation instruction stored in a memory (the operation instruction may be stored in an operating system).

As shown in FIG. 12, the processor 410 controls the processing operation of any one of the terminal devices, and the processor 410 may also be called a central processing unit (central processing unit, CPU).

As shown in FIG. 12, the memory 430 may include read-only memory and random-access memory, and provides instructions and data to the processor. A portion of memory 430 may also include NVRAM. For example, in the application, the memory, the communication interface, and the memory are coupled together through a bus system, where the bus system may include not only a data bus, but also a power bus, a control bus, and a status signal bus. However, the various buses are labeled as bus system 540 in FIG. 12 for clarity of illustration.

As shown in FIG. 12 , the methods disclosed in the foregoing embodiments of the present application may be applied to or implemented by a processor. A processor may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method can be completed by an integrated logic circuit of hardware in a processor or an instruction in the form of software. The above-mentioned processor can be a general-purpose processor, a digital signal processor (digital signal processing, DSP), an ASIC, an off-the-shelf programmable gate array (field-programmable gate array, FPGA) or other programmable logic device, discrete gate or transistor logic devices, discrete hardware components. Various methods, steps, and logic block diagrams disclosed in the embodiments of the present application may be implemented or executed. A general-purpose processor may be a microprocessor, or the processor may be any conventional processor, or the like. The steps of the method disclosed in connection with the embodiments of the present application may be directly implemented by a hardware decoding processor, or implemented by a combination of hardware and software modules in the decoding processor. The software module can be located in a mature storage medium in the field such as random access memory, flash memory, read-only memory, programmable read-only memory or electrically erasable programmable memory, register. The storage medium is located in the memory, and the processor reads the information in the memory, and completes the steps of the above method in combination with its hardware.

In one aspect, a computer-readable storage medium is provided. Instructions are stored in the computer-readable storage medium. When the instructions are executed, the functions performed by the terminal device in the foregoing embodiments are realized.

On the one hand, a chip is provided, the chip is applied in a terminal device, the chip includes at least one processor and a communication interface, the communication interface is coupled to at least one processor, and the processor is used to run instructions to implement the storage pool in the above embodiment. The functions performed by the hardware implementation method of the computing model.

In the above embodiments, all or part of them may be implemented by software, hardware, firmware or any combination thereof. When implemented using software, it may be implemented in whole or in part in the form of a computer program product. The computer program product comprises one or more computer programs or instructions. When the computer program or instructions are loaded and executed on the computer, the processes or functions described in the embodiments of the present application are executed in whole or in part. The computer may be a general purpose computer, a special purpose computer, a computer network, a terminal, user equipment or other programmable devices. The computer program or instructions may be stored in or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer program or instructions may be downloaded from a website, computer, A server or data center transmits to another website site, computer, server or data center by wired or wireless means. The computer-readable storage medium may be any available medium that can be accessed by a computer, or a data storage device such as a server or a data center integrating one or more available media. Described usable medium can be magnetic medium, for example, floppy disk, hard disk, magnetic tape; It can also be optical medium, for example, digital video disc (digital video disc, DVD); It can also be a semiconductor medium, for example, solid state drive (solid state drive) , SSD).

Although the present application has been described in conjunction with various embodiments herein, those skilled in the art can understand and realize the disclosure by viewing the drawings, the disclosure, and the appended claims during the implementation of the claimed application. Other Variations of Embodiments. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality. A single processor or other unit may fulfill the functions of several items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that these measures cannot be combined to advantage.

Although the application has been described in conjunction with specific features and embodiments thereof, it will be apparent that various modifications and combinations can be made thereto without departing from the spirit and scope of the application. Accordingly, the specification and drawings are merely illustrative of the application as defined by the appended claims and are deemed to cover any and all modifications, variations, combinations or equivalents within the scope of this application. Obviously, those skilled in the art can make various changes and modifications to the application without departing from the spirit and scope of the application. In this way, if these modifications and variations of the application fall within the scope of the claims of the application and their equivalent technologies, the application also intends to include these modifications and variations.

Claims

A hardware implementation method of a reserve pool calculation model based on a random resistance array, characterized in that it is applied to electronic equipment running the reserve pool calculation model, and the electronic equipment has a resistive variable device cross array composed of a plurality of resistive variable devices and printed circuit boards. printed circuit board circuit, the resistive variable device cross array is electrically connected to the printed circuit board circuit; the number of the resistive variable device is the same as the corresponding number of trained weights in the electronic device, and the random resistance based The reservoir computing model of the array includes a reservoir layer, the method comprising:

Obtaining the random weight of the reserve pool layer generated based on the intersecting array of resistive switching devices;

forming a randomly distributed random resistance matrix for mapping random weights of the reserve pool layer by applying a breakdown voltage to the intersecting array of resistive switching devices;

converting the input signal into a read voltage signal through the printed circuit board circuit, and performing vector matrix multiplication based on the read voltage signal and the random resistance matrix to determine the output voltage signal;

Repeating the step of converting the input signal into a read voltage signal by the printed circuit board circuit, and performing vector matrix multiplication to determine the output voltage signal based on the read voltage signal and the random resistance matrix, simulating the cyclic iteration of the reserve pool layer process until the output voltage signal is determined to be the final target output voltage signal when it is determined that the input signal satisfies the output preset condition.
The method according to claim 1, characterized in that, the random resistance matrix represents that under the breakdown voltage, each of the resistive switching devices in the intersecting array of resistive switching devices is in a breakdown state or not The random state of the breakdown, and the random conductance state of each device after being subjected to the breakdown, contains a double random state.
The method according to claim 1, wherein the input signal is converted into a read voltage signal through the printed circuit board circuit, and the output is determined by vector matrix multiplication based on the read voltage signal and the random resistance matrix. Voltage signals, including:

The input signal is converted into a read voltage signal through the printed circuit board circuit, the read voltage signal is applied to the random resistance matrix, and the read voltage signal and the The random resistance matrix is processed by vector matrix multiplication to determine the output voltage signal.
The method according to claim 3, wherein the repeating the printed circuit board circuit converts the input signal into a read voltage signal, and performs vector matrix multiplication based on the read voltage signal and the random resistance matrix to determine the output The step of voltage signal simulates the cyclic iteration process of the reserve pool layer until the output voltage signal is determined to be the final target output voltage signal under the condition that the input signal satisfies the output preset condition, including:

repeating the process of converting the input signal into a read voltage signal through the printed circuit board circuit, applying the read voltage signal to the random resistance matrix, and converting the read voltage signal to Perform vector matrix multiplication processing with the random resistance matrix, determine the step of output voltage signal, simulate the cycle iteration process of the reserve pool layer, until the input signal is determined to meet the output preset condition, determine the The output voltage signal is the final target output voltage signal.
The method according to claim 1, wherein the reserve pool calculation model further comprises a classification layer connected to the reserve pool layer, and the target output voltage signal includes a data set representing node characteristics in the determined After the output voltage signal is the final target output voltage signal, the method further includes:

The target output voltage signal is input to the classification layer, and after the classification process is performed on the data set in the target output voltage signal, the prediction result is finally determined and output.
The method according to claim 5, wherein the electronic equipment further comprises an onboard digital processor electrically connected to the cross array of resistive switching devices and the printed circuit board circuit, and the onboard digital processor is used to perform the Number crunching at the classification layer.
A hardware realization device of a reserve pool calculation model based on a random resistance array, characterized in that it is applied to electronic equipment running the reserve pool calculation model, and the electronic equipment has a resistive variable device cross array composed of a plurality of resistive variable devices and printed circuit boards. printed circuit board circuit, the resistive variable device cross array is electrically connected to the printed circuit board circuit; the number of the resistive variable device is the same as the corresponding number of trained weights in the electronic device, and the random resistance based The reserve pool calculation model of the array includes a reserve pool layer, and the device includes:

a random weight acquisition module, configured to acquire the random weight of the reserve pool layer generated based on the intersecting array of resistive switching devices;

A breakdown voltage applying module, configured to form a randomly distributed random resistance matrix by applying a breakdown voltage to the intersecting array of resistive switching devices;

The output voltage determination module is used to convert the input signal into a read voltage signal through the printed circuit board circuit, and perform vector matrix multiplication based on the read voltage signal and the random resistance matrix to determine the output voltage signal;

The target output voltage signal determination module is used to repeat the step of converting the input signal into a read voltage signal by the printed circuit board circuit, and performing vector matrix multiplication based on the read voltage signal and the random resistance matrix to determine the output voltage signal, Simulating the cyclic iterative process of the reserve pool layer until the output voltage signal is determined to be the final target output voltage signal when the input signal is determined to meet the output preset condition.
The device according to claim 7, wherein the output voltage signal determination module comprises:

The output voltage signal determination sub-module is used to convert the input signal into a read voltage signal through the printed circuit board circuit, apply the read voltage signal to the random resistance matrix, and use Kirchhoff's law and Ohm's law performing vector matrix multiplication processing on the read voltage signal and the random resistance matrix to determine an output voltage signal;

The random resistance matrix represents that under the breakdown voltage, each of the resistive switching devices in the intersecting array of resistive switching devices is in a breakdown state or a random state without breakdown, and each Random conductance states of the device, including double random states.
The device according to claim 8, wherein the target output voltage signal determination module comprises:

The target output voltage signal determination sub-module is used to repeat the conversion of the input signal into a read voltage signal through the printed circuit board circuit, apply the read voltage signal to the random resistance matrix, and use Kirchhoff law and Ohm's law, the read voltage signal and the random resistance matrix are subjected to vector matrix multiplication processing, and the step of determining the output voltage signal simulates the iterative process of the reserve pool layer until the input signal is determined to meet the output In the case of preset conditions, the output voltage signal is determined to be the final target output voltage signal.

The reserve pool calculation model also includes a classification layer connected to the reserve pool layer, and the device also includes:

The prediction result output module is configured to input the target output voltage signal into the classification layer, and finally determine and output the prediction result after the classification process is performed on the data sets in the target output voltage signal.

The electronic equipment also includes an on-board digital processor electrically connected to the cross array of resistive variable devices and the printed circuit board circuit, and the on-board digital processor is used to perform digital operations on the classification layer.
An electronic device comprising: one or more processors; and one or more machine-readable media having instructions stored thereon which, when executed by the one or more processors, cause the The device executes the hardware realization device of the reserve pool calculation model described in any one of claims 7-9.