CN117130722A - Optimization method and device for WebAsssembly instruction set - Google Patents
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Abstract
The specification provides an optimization method and device for a WebAssembley instruction set. The method comprises the following steps: replacing the instruction based on the 64-bit wide integer in the WebAssembly instruction set with the instruction based on the 16-bit wide integer; the instruction which is converted between the 64-bit wide integer and other bit wide integers in the WebAsssembly instruction set is replaced by the instruction which is converted between the 16-bit wide integer and other bit wide integers; and replacing the instruction of the non-bit-width integer which is not needed by the resource-constrained device in the WebAssembly instruction set with the instruction of the needed non-bit-width integer.
Description
Technical Field
Embodiments of the present disclosure relate to the field of computers, and in particular, to a method and apparatus for optimizing a WebAssembly instruction set.
Background
WebAssembly (also simply called wasm) is a new code technology that can run in a browser, and can provide an efficient compiling target for low-level source languages such as C, C ++ and Rust; the system has the characteristics of rapidness, high efficiency and portability, and can run on different platforms at a near-local speed.
Since the standard WebAssembly instruction set is directed to devices that are not resource-constrained, the resource-constrained devices are less efficient to execute when executing bytecodes using the standard WebAssembly instruction set.
Disclosure of Invention
The embodiment of the specification provides an optimization method and device for a WebAssemble instruction set. The method is used for solving the problem that the resource-constrained device has lower execution efficiency when the standard WebAssemble instruction set is used for executing the byte code.
According to a first aspect of embodiments of the present specification, there is provided a method for optimizing a WebAssembly instruction set, the method comprising:
replacing the instruction based on the 64-bit wide integer in the WebAssembly instruction set with the instruction based on the 16-bit wide integer;
the instruction which is converted between the 64-bit wide integer and other bit wide integers in the WebAsssembly instruction set is replaced by the instruction which is converted between the 16-bit wide integer and other bit wide integers;
and replacing the instruction of the non-bit-width integer which is not needed by the resource-constrained device in the WebAssembly instruction set with the instruction of the needed non-bit-width integer.
Optionally, the replacing the instruction based on the 64-bit wide integer in the WebAssembly instruction set with the instruction based on the 16-bit wide integer includes:
deleting a constant instruction, a comparison instruction, an arithmetic operation instruction, a bit operation instruction and a memory instruction which are based on the 64-bit wide integer in the WebAssemble instruction set;
and adding a constant instruction, a comparison instruction, an arithmetic operation instruction, a bit operation instruction and a memory instruction which are based on the 16-bit wide integer in the WebAssemble instruction set.
Optionally, the added constant instruction based on a 16-bit wide integer comprises a high frequency instruction in an opcode.
Optionally, the high frequency instruction in the operation code includes a constant instruction in the operation code;
accordingly, the added constant instruction based on the integer with the width of 16 bits comprises a constant instruction in an operation code, and the method comprises the following steps:
the constant instructions in the opcode add instructions i16.const_0, i16.const_1, i16.const_2, i16.const_3, i16.const_4, i16.const_5, i32.const_0, i32.const_1, i32.const_2, i32.const_3, i32.const_4, i32.const_5.
Optionally, the high-frequency instruction in the operation code comprises a variable instruction in the operation code;
accordingly, the added constant instruction based on the integer with the width of 16 bits comprises a constant instruction in an operation code, and the method comprises the following steps:
the constant instructions in the opcode add the instructions of local.get0, local.get1, local.get2, local.get3, local.get0, local.set1, local.set2, local.set3, local.te0, local.te1, local.te2, local.te3.
Optionally, the replacing the instruction for the interconversion between the 64-bit wide integer and the other bit wide integers in the WebAssembly instruction set with the instruction for the interconversion between the 16-bit wide integer and the other bit wide integers includes:
deleting the instruction of the interconversion between the 64-bit wide integer and other bit wide integers in the WebAsssembly instruction set;
and adding instructions for interconversion between the 16-bit wide integer and the 32-bit wide integer in the WebAssemble instruction set, and cutting the 16-bit wide integer into the 8-bit wide integer.
Optionally, the replacing the instruction of the non-bit-width integer not needed by the resource-constrained device in the WebAssembly instruction set with the instruction of the needed non-bit-width integer includes:
deleting a reference instruction and a table instruction in the WebAsssembly instruction set;
deleting the floating point type instruction in the WebAsssembly instruction set; and instructions for interconversion between the floating point type instructions and integer instructions;
adding a control instruction taking jump offset as an operand in the WebAsssembly instruction set;
adding a control instruction with a return value type in the WebAsssembly instruction set;
a compound instruction combining common operations into a single instruction is added in the WebAssemble instruction set.
Optionally, adding a control instruction using a jump offset as an operand in the WebAssembly instruction set includes:
adding control instructions of br_leb, br_if_leb and br_table_ leb in the WebAssembly instruction set;
optionally, the adding a control instruction with a return value type in the WebAssembly instruction set includes:
adding control instructions of return_i32 and return_void in the WebAssemble instruction set;
optionally, adding a compound instruction for merging common operations into a single instruction in the WebAssembly instruction set includes:
and adding composite instructions of call_drop, i32.const_eq, i32.const_ne, i32.const_add, i32.const_sub, i32.const_and_0xFF, i32.const_and_0xFFFF, i32.const_and_any, i32.const_or, i32.const_load and i32.const_load8_u in the WebAssembly instruction set.
Optionally, the method further comprises:
the resource constrained device executes bytecode using the optimized WebAssembly instruction set.
According to a second aspect of embodiments of the present specification, there is provided an optimizing apparatus of WebAssembly instruction set, the apparatus comprising:
a first replacement unit that replaces an instruction based on a 64-bit wide integer in the WebAssembly instruction set with an instruction based on a 16-bit wide integer;
a second replacing unit, replacing the instruction of the interconversion between the 64-bit wide integer and other bit wide integers in the WebAssembly instruction set with the instruction of the interconversion between the 16-bit wide integer and other bit wide integers;
and a third replacing unit, configured to replace an instruction of a non-bit-width integer not required by the resource-constrained device in the WebAssembly instruction set with an instruction of a required non-bit-width integer.
According to a third aspect of embodiments of the present specification, there is provided an electronic device comprising:
a processor;
a memory for storing processor-executable instructions;
wherein the processor is configured to optimize the method of any of the above WebAssembly instruction sets.
According to the embodiment of the specification, an optimization scheme of a WebAssemble instruction set is provided, and an instruction which does not accord with resource-restricted equipment in the standard WebAssemble instruction set is replaced by an instruction which accords with the requirement of the resource-restricted equipment, so that when the resource-restricted equipment uses the optimized WebAssemble instruction set to execute the byte codes, the size of the byte codes can be reduced, and the execution efficiency of the byte codes is improved.
Drawings
FIG. 1 is a flow chart of a method of optimizing a WebAssemblem instruction set in a resource constrained device according to one embodiment of the present disclosure;
FIG. 2 is a hardware architecture diagram of an optimizing apparatus for a WebAssemblem instruction set in a resource-constrained device according to an embodiment of the present disclosure;
FIG. 3 is a block diagram of an optimization apparatus for a WebAssemblem instruction set in a resource constrained device according to one embodiment of the present disclosure.
Detailed Description
Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The implementations described in the following exemplary examples do not represent all implementations consistent with the present specification. Rather, they are merely examples of apparatus and methods consistent with some aspects of the present description as detailed in the accompanying claims.
The terminology used in the description presented herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the description. As used in this specification and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any or all possible combinations of one or more of the associated listed items.
It should be understood that although the terms first, second, third, etc. may be used in this specification to describe various information, these information should not be limited to these terms. These terms are only used to distinguish one type of information from another. For example, the first information may also be referred to as second information, and similarly, the second information may also be referred to as first information, without departing from the scope of the present description. The word "if" as used herein may be interpreted as "at … …" or "at … …" or "responsive to a determination", depending on the context.
In this specification, webAssembly bytecode is an intermediate code format that can be interpreted and executed in all runtime supporting WebAssembly. It is a low-level language similar to assembly language, consisting of a series of instructions called opcodes (opcodes).
The instruction set of WebAssembly bytecode (hereinafter simply referred to as WebAssembly instruction set) is very compact and can be easily translated into a variety of different machine languages. This makes WebAssembly an efficient, portable and secure virtual machine technology that can be used for a variety of applications and platforms other than Web browsers.
WebAssembly bytecode also has readability and can be described using a text format (.wat file). Such a text format may help developers better understand and analyze WebAssembly code, as well as manually debug or disassemble.
Since the standard WebAssembly instruction set is oriented to 32-bit and 64-bit operating systems, the minimum bit width of the bytecode in the instruction set is also 32-bit, whereas resource-constrained devices are typically 16-bit processor-based, it is often inefficient to execute bytecode in resource-constrained devices using the standard WebAssembly instruction set.
In order to solve the above problems, the present specification aims to provide a WebAssembly instruction set suitable for use by a resource-constrained device, where the WebAssembly instruction set may be optimized based on a standard WebAssembly instruction set. The method specifically can replace the instruction which does not accord with the resource-restricted equipment in the standard WebAssemblem instruction set with the instruction which accords with the requirement of the resource-restricted equipment, so that the size of the byte code can be reduced and the execution efficiency of the byte code can be improved when the resource-restricted equipment uses the optimized WebAssemblem instruction set to execute the byte code.
Referring to the flowchart of the method for optimizing the WebAssembly instruction set in the resource-constrained device shown in fig. 1, the method may be applied to the resource-constrained device, and the method may include the following steps:
step 110, replacing the instruction based on the 64-bit wide integer in the WebAssembly instruction set with an instruction based on the 16-bit wide integer.
Because the resource-constrained device is 16-bit processor-based, and the standard WebAssembly instruction set does not have 16-bit wide operating instructions, the resource-constrained device can be better adapted by replacing instructions based on 64-bit wide integers in the standard WebAssembly instruction set with instructions based on 16-bit wide integers.
In an exemplary embodiment, the step 110 may further include:
deleting a constant instruction, a comparison instruction, an arithmetic operation instruction, a bit operation instruction and a memory instruction which are based on the 64-bit wide integer in the WebAssemble instruction set;
and adding a constant instruction, a comparison instruction, an arithmetic operation instruction, a bit operation instruction and a memory instruction which are based on the 16-bit wide integer in the WebAssemble instruction set.
When the WebAssemble instruction set in the resource-constrained device is optimized, constant instructions, comparison instructions, arithmetic operation instructions, bit operation instructions and memory instructions which are not needed in the resource-constrained device can be deleted; and adding a constant instruction, a comparison instruction, an arithmetic operation instruction, a bit operation instruction and a memory instruction which are based on the 16-bit wide integer; thereby improving the execution efficiency of the byte code.
Referring now to the instructions of the increased 16-bit wide integers shown in Table 1, the instructions shown in Table 1 include a constant instruction, a compare instruction, an arithmetic operation instruction, a bit operation instruction, and a type conversion instruction. The mnemonics and opcodes for each instruction are shown in Table 1 below and will not be described in detail.
TABLE 1
In the WebAssembly instruction set, the instruction set can be classified into: numerical instructions, parameter instructions, variable instructions, memory instructions, control instructions, compound instructions. The numerical instructions may include the constant instructions, the comparison instructions, the arithmetic operation instructions, the bit operation instructions, and the type conversion instructions described above.
In an exemplary embodiment, the added constant instruction based on a 16-bit wide integer comprises a high frequency instruction in the opcode.
Since the constant instructions in the standard WebAssembly are typically located in the high frequency instructions in the opcode, the added constant instructions based on 16-bit wide integers can be included in the high frequency instructions in the opcode; thereby optimizing the WebAssembly instruction set in the resource-constrained device.
In an exemplary embodiment, the high frequency instructions in the opcode include constant instructions in the opcode;
accordingly, the added constant instruction based on the integer with the width of 16 bits comprises a constant instruction in an operation code, as shown as "constant instruction" in table 2, and may include instructions of i16.const_0, i16.const_1, i 16.const_2, i 16.const_3, i16.const_4, i 16.const_5, i32.const_0, i32.const_1, i32.const_2, i32.const_3, i32.const_4 and i32.const_5. The operation code corresponding to each instruction is shown in table 2 below, and will not be described here again.
TABLE 2
Since the operands of the constant instruction i32.const in standard WebAssembly are constants in the LEB128 encoding format, and the constants which often appear as operands in the instruction are usually 0-5 in the resource-constrained device, by increasing the byte code space occupied by the operands, i16.const_0, i16.const_1, i 16.const_2, i 16.const_3, i16.const_4, i 16.const_5, i32.const_0, i32.const_1, i32.const_2, i32.const_3, i32.const_4, i32.const_5 instructions, byte code size can be compressed, and byte code execution efficiency can be improved.
In an exemplary embodiment, the high frequency instructions in the opcode include variable instructions in the opcode;
accordingly, the added constant instruction based on the 16-bit wide integer includes a constant instruction in the opcode, as indicated by the variable instruction in table 2, which may include local_get0, local_get1, local_get2, local_get3, local_get0, local_set1, local_set2, local_set3, local_te0, local_te1, local_te2, and local_te3; and global.get_0, global.set_0 instructions. The operation code corresponding to each instruction is shown in the above table 2, and will not be described here again.
Since the variable instructions in the standard WebAssembly have local. Get, local. Set, local. Tee, etc., the operands of these instructions are indexes of local variables, but the local variable indexes commonly used in resource-constrained devices are not so much in practice; however, the frequency of occurrence of these instructions is very high, so by adding the local.get0, local.get1, local.get2, local.get3, local.get0, local.set1, local.set2, local.set3, local.te0, local.te1, local.te2, local.te3 instructions, the operands of these instructions are the offsets of the local variables to be operated, the local variables can be found directly, thereby improving the execution efficiency of the byte code.
Step 120, replacing the instruction of the WebAssembly instruction set, which is converted between the 64-bit wide integer and other bit wide integers, with the instruction of the conversion between the 16-bit wide integer and other bit wide integers.
Because the instruction based on the 64-bit wide integer in the standard WebAssembly instruction set is not needed by the resource limited device, the instruction based on the 64-bit wide integer can be replaced by the instruction based on the 16-bit wide integer, and meanwhile, the instruction which is mutually converted between the 64-bit wide integer and other bit wide integers in the WebAssembly instruction set can be replaced by the instruction which is mutually converted between the 16-bit wide integer and other bit wide integers; thereby better adapting the resource-constrained device.
In an exemplary embodiment, the step 120 may further include:
deleting the instruction of the interconversion between the 64-bit wide integer and other bit wide integers in the WebAsssembly instruction set;
and adding instructions for interconversion between the 16-bit wide integer and the 32-bit wide integer in the WebAssemble instruction set, and cutting the 16-bit wide integer into the 8-bit wide integer.
Because the standard WebAssemble has no 16-bit-wide operation instruction, the instruction which is converted between the 16-bit-wide instruction and the 32-bit-wide instruction can be correspondingly increased by increasing the 16-bit-wide instruction; and instructions truncated from a 16-bit wide integer to an 8-bit wide integer are also added.
And 130, replacing the instruction of the non-bit-width integer which is not needed by the resource-constrained device in the WebAssemble instruction set with the instruction of the needed non-bit-width integer.
In an exemplary embodiment, the replacing the instruction of the non-bit-wide integer not needed by the resource constrained device in the WebAssembly instruction set with the instruction of the needed non-bit-wide integer includes:
deleting a reference instruction and a table instruction in the WebAsssembly instruction set;
deleting the floating point type instruction in the WebAsssembly instruction set; and instructions for interconversion between the floating point type instructions and integer instructions;
adding a control instruction taking jump offset as an operand in the WebAsssembly instruction set;
adding a control instruction with a return value type in the WebAsssembly instruction set;
a compound instruction combining common operations into a single instruction is added in the WebAssemble instruction set.
Because the reference instruction, the table instruction and the floating point type instruction in the WebAssemble instruction set are not needed in the resource limited device; meanwhile, instructions for mutual conversion between floating point type instructions and integer instructions are not used; these instructions can be deleted.
In an exemplary embodiment, adding a control instruction using a jump offset as an operand in the WebAssembly instruction set includes:
and adding control instructions of br_leb, br_if_leb and br_table_ leb in the WebAssembly instruction set.
The operation code corresponding to each instruction is shown in table 3, and will not be described here again. The execution efficiency of byte codes in a resource-constrained device can be improved by adding control instructions with jump offsets as operands.
TABLE 3 Table 3
In an exemplary embodiment, adding a control instruction with a return value type in the WebAssembly instruction set includes:
and adding control instructions of return_i32 and return_void in the WebAssemblem instruction set.
The operation code corresponding to each instruction is shown in table 4, and will not be described here again. The execution efficiency of byte codes in the resource-constrained device can be improved by adding control instructions with return value types.
TABLE 4 Table 4
In an exemplary embodiment, adding a compound instruction that merges common operations into a single instruction in the WebAssembly instruction set includes:
and adding composite instructions of call_drop, i32.const_eq, i32.const_ne, i32.const_add, i32.const_sub, i32.const_and_0xFF, i32.const_and_0xFFFF, i32.const_and_any, i32.const_or, i32.const_load and i32.const_load8_u in the WebAssembly instruction set.
The operation code corresponding to each instruction is shown in table 5, and will not be described here again. The size of the byte code can be compressed by adding the compound instruction which combines the common operations into a single instruction, so that the execution efficiency of the byte code in the resource-constrained device is improved.
TABLE 5
The call_drop is an instruction for merging the function call and the operation of discarding one data on the stack;
i 16.const_eq、i 16.const_ne、i 16.const_add、i 16.const_sub、i 16.const_and_0xFF、
i 16.const_and_0xFFFF、i 16.const_and_any、i 16.const_or、i32.const_eq、
i32.const_ne、i32.const_add、i32.const_sub、i32.const_and_0xFF、
the i32.const_and_0xFFFF, i32.const_and_any, i32.const_or instruction is a number to be constant based
A value operation and operation result push operation combined instruction;
the i16.const_load, i16.const_load8_u, i32.const_load, i32.const_load8_u instructions are instructions that combine data read from memory and data push operations.
In the present specification, after optimizing the WebAssembly instruction set in the resource-constrained device, the resource-constrained device may execute the bytecode using the optimized WebAssembly instruction set.
Please refer to the following schematic diagram of the optimized WebAssembly instruction set in the resource-constrained device shown in table 6, and the mnemonics and the operation codes of each instruction are shown in table 6, which will not be described in detail herein.
TABLE 6
Because the standard WebAssemble instruction set is deleted, the instruction which is not needed by the resource-constrained device and is converted between the 64-bit wide instruction and other unnecessary reference instructions and table instructions, floating point type instructions and integer instructions, and the instruction which is converted between the integer 64-bit wide instruction and other bit wide instructions are deleted; and instructions based on 16-bit width are added, instructions which are converted between the instructions with 16-bit width and 32-bit width are added, high-frequency instructions which directly contain constant operands in operation codes are added, control instructions which take jump offsets as operands are added, control instructions with return value types are added, and compound instructions which combine common operations into a single instruction are added for improving the execution efficiency, so that the size of byte codes in resource-limited equipment can be reduced, and the execution efficiency of byte codes can be improved.
Corresponding to the foregoing embodiment of the method for optimizing the WebAssembly instruction set in the resource-constrained device, the present disclosure further provides an embodiment of an apparatus for optimizing the WebAssembly instruction set in the resource-constrained device. The embodiment of the device can be implemented by software, or can be implemented by hardware or a combination of hardware and software. Taking a software implementation as an example, the device in a logic sense is formed by reading a corresponding computer program in a nonvolatile memory into a memory by a processor of a device where the device is located. From the hardware level, as shown in fig. 2, a hardware structure diagram of a device where a WebAssembly instruction set optimizing device is located in the resource-constrained device in this specification is shown, and in addition to the processor, the network interface, the memory and the nonvolatile memory shown in fig. 2, the device where the device is located in the embodiment may generally include other hardware according to actual communication functions, which is not described herein again.
Referring to fig. 3, a block diagram of an apparatus for optimizing a WebAssembly instruction set in a resource-constrained device according to an embodiment of the present disclosure, where the apparatus corresponds to the embodiment shown in fig. 1, and the apparatus includes:
a first replacing unit 710 that replaces the instruction based on the 64-bit wide integer in the WebAssembly instruction set with an instruction based on the 16-bit wide integer;
a second replacing unit 720, configured to replace the instruction of the WebAssembly instruction set, which is converted between the 64-bit wide integer and other bit wide integers, with the instruction of the conversion between the 16-bit wide integer and other bit wide integers;
and a third replacing unit 730, configured to replace an instruction of a non-bit-width integer not required by the resource-constrained device in the WebAssembly instruction set with an instruction of a required non-bit-width integer.
In an exemplary embodiment, the first replacing unit 710 includes:
a first deleting subunit, configured to delete a constant instruction, a comparison instruction, an arithmetic operation instruction, a bit operation instruction, and a memory instruction based on a 64-bit wide integer in the WebAssembly instruction set;
and a second adding subunit for adding a constant instruction, a comparison instruction, an arithmetic operation instruction, a bit operation instruction and a memory instruction which are based on the integer with the width of 16 bits in the WebAssemble instruction set.
In an exemplary embodiment, the added constant instruction based on a 16-bit wide integer comprises a high frequency instruction in the opcode.
In an exemplary embodiment, the high frequency instructions in the opcode include constant instructions in the opcode;
accordingly, the added constant instruction based on the integer with the width of 16 bits comprises a constant instruction in an operation code, and the method comprises the following steps:
the constant instructions in the opcode add instructions i16.const_0, i16.const_1, i16.const_2, i16.const_3, i16.const_4, i16.const_5, i32.const_0, i32.const_1, i32.const_2, i32.const_3, i32.const_4, i32.const_5.
In an exemplary embodiment, the high frequency instructions in the opcode include variable instructions in the opcode;
accordingly, the added constant instruction based on the integer with the width of 16 bits comprises a constant instruction in an operation code, and the method comprises the following steps:
the constant instructions in the opcode add the instructions of local.get0, local.get1, local.get2, local.get3, local.get0, local.set1, local.set2, local.set3, local.te0, local.te1, local.te2, local.te3.
In an exemplary embodiment, the second replacing unit 720 includes:
a second deletion subunit, configured to delete instructions for interconversion between the 64-bit wide integer and other bit wide integers in the WebAssembly instruction set;
a second increment subunit for incrementing an instruction that is converted between a 16-bit wide integer and a 32-bit wide integer in the WebAssembly instruction set, and an instruction that truncates the 16-bit wide integer to an 8-bit wide integer.
In an exemplary embodiment, the third replacing unit 730 includes:
a third deletion subunit, configured to delete a reference instruction and a table instruction in the WebAssembly instruction set;
a fourth deletion subunit, configured to delete a floating point type instruction in the WebAssembly instruction set; and instructions for interconversion between the floating point type instructions and integer instructions;
a third adding subunit for adding a control instruction using jump offset as an operand in the WebAssembly instruction set;
a fourth adding subunit for adding a control instruction with a return value type in the WebAssembly instruction set;
and a fifth adding subunit for adding a compound instruction combining the common operations into a single instruction in the WebAssembly instruction set.
In an exemplary embodiment, the third adding subunit is further configured to add a control instruction of br_leb, br_if_leb, br_table_ leb to the WebAssembly instruction set.
In an exemplary embodiment, the fourth adding subunit is further configured to add a control instruction of return_i32 and return_void in the WebAssembly instruction set.
In an exemplary embodiment, the fifth adding subunit is further configured to add a composite instruction of call_drop, i16.const_eq, i16.const_ne, i16.const_add, i16.const_sub, i16.const_and_0xFF, i16.const_and_0xFFFF, i16.const_and_any, i16.const_or, i16.const_load 8_u, i32.const_eq, i32.const_ne, i32.const_add, i32.const_sub, i32.const_and_0xFF, i32.const_and_0xFFFF, i32.const_and_any, i32.const_or, i32.con_load, i32.conad_8_load. In an exemplary embodiment, further comprising:
and the execution unit is used for executing byte codes by the resource-constrained device by using the optimized WebAsssembly instruction set.
The system, apparatus, module or unit set forth in the above embodiments may be implemented in particular by a computer chip or entity, or by a product having a certain function. A typical implementation device is a computer, which may be in the form of a personal computer, laptop computer, cellular telephone, camera phone, smart phone, personal digital assistant, media player, navigation device, email device, game console, tablet computer, wearable device, or a combination of any of these devices.
The implementation process of the functions and roles of each unit in the above device is specifically shown in the implementation process of the corresponding steps in the above method, and will not be described herein again.
For the device embodiments, reference is made to the description of the method embodiments for the relevant points, since they essentially correspond to the method embodiments. The apparatus embodiments described above are merely illustrative, wherein the elements illustrated as separate elements may or may not be physically separate, and the elements shown as elements may or may not be physical elements, may be located in one place, or may be distributed over a plurality of network elements. Some or all of the modules may be selected according to actual needs to achieve the purposes of the present description. Those of ordinary skill in the art will understand and implement the present invention without undue burden.
Fig. 3 above describes internal functional modules and a schematic of an optimizing apparatus of WebAssembly instruction set in a resource-constrained device, and the substantial execution subject thereof may be an electronic device, including:
a processor;
a memory for storing processor-executable instructions;
wherein the processor is configured to perform an embodiment of the method of optimizing a WebAssembly instruction set in any of the resource-constrained devices described above.
In the above embodiment of the electronic device, it should be understood that the processor may be a central processing unit (english: central Processing Unit, abbreviated as CPU), or may be other general purpose processors, digital signal processors (english: digital Signal Processor, abbreviated as DSP), application specific integrated circuits (english: application Specific Integrated Circuit, abbreviated as ASIC), or the like. A general-purpose processor may be a microprocessor or the processor may be any conventional processor, etc., and the aforementioned memory may be a read-only memory (ROM), a random access memory (random access memory, RAM), a flash memory, a hard disk, or a solid state disk. The steps of a method disclosed in connection with the embodiments of the present invention may be embodied directly in a hardware processor for execution, or in a combination of hardware and software modules in the processor for execution.
In this specification, each embodiment is described in a progressive manner, and identical and similar parts of each embodiment are all referred to each other, and each embodiment mainly describes differences from other embodiments. In particular, for the electronic device embodiments, since they are substantially similar to the method embodiments, the description is relatively simple, and reference is made to the description of the method embodiments in part.
Other embodiments of the present disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. This specification is intended to cover any variations, uses, or adaptations of the specification following, in general, the principles of the specification and including such departures from the present disclosure as come within known or customary practice within the art to which the specification pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the specification being indicated by the following claims.
It is to be understood that the present description is not limited to the precise arrangements and instrumentalities shown in the drawings, which have been described above, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present description is limited only by the appended claims.
Claims (13)
1. A method for optimizing a WebAssembly instruction set, the method comprising:
replacing the instruction based on the 64-bit wide integer in the WebAssembly instruction set with the instruction based on the 16-bit wide integer;
the instruction which is converted between the 64-bit wide integer and other bit wide integers in the WebAsssembly instruction set is replaced by the instruction which is converted between the 16-bit wide integer and other bit wide integers;
and replacing the instruction of the non-bit-width integer which is not needed by the resource-constrained device in the WebAsssembly instruction set with the instruction of the needed non-bit-width integer.
2. The method of claim 1, wherein replacing the 64-bit wide integer based instruction in the WebAssembly instruction set with a 16-bit wide integer based instruction comprises:
deleting a constant instruction, a comparison instruction, an arithmetic operation instruction, a bit operation instruction and a memory instruction which are based on the 64-bit wide integer in the WebAssemble instruction set;
and adding a constant instruction, a comparison instruction, an arithmetic operation instruction, a bit operation instruction and a memory instruction which are based on the 16-bit wide integer in the WebAssemble instruction set.
3. The method of claim 2, wherein the added 16-bit wide integer based constant instruction comprises a high frequency instruction in an opcode.
4. A method according to claim 3, wherein the high frequency instructions in the opcode comprise constant instructions in the opcode;
accordingly, the added constant instruction based on the integer with the width of 16 bits comprises a constant instruction in an operation code, and the method comprises the following steps:
the constant instructions in the opcode add instructions i16.const_0, i16.const_1, i16.const_2, i16.const_3, i16.const_4, i16.const_5, i32.const_0, i32.const_1, i32.const_2, i32.const_3, i32.const_4, i32.const_5.
5. A method according to claim 3, wherein the high frequency instructions in the opcode comprise variable instructions in the opcode;
accordingly, the added constant instruction based on the integer with the width of 16 bits comprises a constant instruction in an operation code, and the method comprises the following steps:
the constant instructions in the opcode add the instructions of local.get0, local.get1, local.get2, local.get3, local.get0, local.set1, local.set2, local.set3, local.te0, local.te1, local.te2, local.te3.
6. The method of claim 2, wherein the replacing the instruction in the WebAssembly instruction set that interconverts between the 64-bit wide integer and the other bit wide integers with the instruction that interconverts between the 16-bit wide integer and the other bit wide integers comprises:
deleting the instruction of the interconversion between the 64-bit wide integer and other bit wide integers in the WebAsssembly instruction set;
and adding instructions for interconversion between the 16-bit wide integer and the 32-bit wide integer in the WebAssemble instruction set, and cutting the 16-bit wide integer into the 8-bit wide integer.
7. The method of claim 1, wherein the replacing the non-bit wide integer instructions not required by the resource constrained device in the WebAssembly instruction set with the required non-bit wide integer instructions comprises:
deleting a reference instruction and a table instruction in the WebAsssembly instruction set;
deleting the floating point type instruction in the WebAsssembly instruction set; and instructions for interconversion between the floating point type instructions and integer instructions;
adding a control instruction taking jump offset as an operand in the WebAsssembly instruction set;
adding a control instruction with a return value type in the WebAsssembly instruction set;
a compound instruction combining common operations into a single instruction is added in the WebAssemble instruction set.
8. The method of claim 7, wherein adding a control instruction having a jump offset as an operand in the WebAssembly instruction set comprises:
and adding control instructions of br_leb, br_if_leb and br_table_ leb in the WebAssembly instruction set.
9. The method of claim 7, wherein adding control instructions with return value types in the WebAssembly instruction set comprises:
and adding control instructions of return_i32 and return_void in the WebAssemblem instruction set.
10. The method of claim 7, wherein adding a compound instruction that merges common operations into a single instruction in the WebAssembly instruction set, comprises:
and adding composite instructions of call_drop, i32.const_eq, i32.const_ne, i32.const_add, i32.const_sub, i32.const_and_0xFF, i32.const_and_0xFFFF, i32.const_and_any, i32.const_or, i32.const_load and i32.const_load8_u in the WebAssembly instruction set.
11. The method as recited in claim 1, further comprising:
the resource constrained device executes bytecode using the optimized WebAssembly instruction set.
12. An optimization apparatus for WebAssembly instruction set, the apparatus comprising:
a first replacement unit that replaces an instruction based on a 64-bit wide integer in the WebAssembly instruction set with an instruction based on a 16-bit wide integer;
a second replacing unit, replacing the instruction of the interconversion between the 64-bit wide integer and other bit wide integers in the WebAssembly instruction set with the instruction of the interconversion between the 16-bit wide integer and other bit wide integers;
and a third replacing unit for replacing the non-bit-width integer instruction which is not needed by the resource-limited device in the WebAssembly instruction set with the needed non-bit-width integer instruction.
13. An electronic device, comprising:
a processor;
a memory for storing processor-executable instructions;
wherein the processor is configured to perform the method of any of the preceding claims 1-11.
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