CN117119793A - Manufacturing method of memory device and memory device - Google Patents
Manufacturing method of memory device and memory device Download PDFInfo
- Publication number
- CN117119793A CN117119793A CN202310944935.4A CN202310944935A CN117119793A CN 117119793 A CN117119793 A CN 117119793A CN 202310944935 A CN202310944935 A CN 202310944935A CN 117119793 A CN117119793 A CN 117119793A
- Authority
- CN
- China
- Prior art keywords
- gate
- dielectric layer
- substrate
- layer
- grid electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 150
- 239000004065 semiconductor Substances 0.000 claims abstract description 46
- 238000003860 storage Methods 0.000 claims abstract description 35
- 238000007667 floating Methods 0.000 claims abstract description 31
- 239000011159 matrix material Substances 0.000 claims abstract description 13
- 238000002955 isolation Methods 0.000 claims description 71
- 238000000034 method Methods 0.000 claims description 24
- 238000005530 etching Methods 0.000 claims description 21
- 239000000463 material Substances 0.000 claims description 14
- 230000004888 barrier function Effects 0.000 claims description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 10
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 10
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 8
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 8
- 238000005468 ion implantation Methods 0.000 claims description 7
- 239000000126 substance Substances 0.000 claims description 4
- 239000000523 sample Substances 0.000 claims 3
- 230000010354 integration Effects 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 23
- 239000003990 capacitor Substances 0.000 description 6
- 239000012212 insulator Substances 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 229920005591 polysilicon Polymers 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 230000005641 tunneling Effects 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- AXQKVSDUCKWEKE-UHFFFAOYSA-N [C].[Ge].[Si] Chemical compound [C].[Ge].[Si] AXQKVSDUCKWEKE-UHFFFAOYSA-N 0.000 description 1
- HMDDXIMCDZRSNE-UHFFFAOYSA-N [C].[Si] Chemical compound [C].[Si] HMDDXIMCDZRSNE-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 229910001928 zirconium oxide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/20—DRAM devices comprising floating-body transistors, e.g. floating-body cells
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
Abstract
The application discloses a manufacturing method of a memory device and the memory device, wherein the manufacturing method comprises the following steps: providing a semiconductor matrix, wherein the semiconductor matrix comprises a substrate and a dielectric layer formed on the substrate; forming a first groove from the dielectric layer towards the substrate, and sequentially forming a gate insulating layer and a first gate in the first groove; forming a second grid electrode on one side of the first grid electrode, wherein the second grid electrode contacts the substrate and the first grid electrode, and the first grid electrode and the second grid electrode form a semi-floating gate of a storage unit in the storage device; namely, the application can effectively improve the integration density of the memory device, correspondingly improve the memory density and reduce the cost.
Description
Technical Field
The present application relates to the field of semiconductor technologies, and in particular, to a method for manufacturing a memory device and a memory device.
Background
In the application of integrated circuits, the performance of various devices is affected by the dimensions between the layers of material, especially memory devices, because the width dimensions between the layers of material affect the cell size of the device.
In the practical operation process, the research and development personnel of the present application find that in the current memory device manufacturing scheme, particularly in the memory device manufacturing scheme, the memory device is generally manufactured by adopting a dynamic random access memory (Dynamic Random Access Memory, DRAM) scheme, and the basic unit is formed by 1T1C, namely a structure of a transistor and a capacitor, and the occupied area of the memory device is generally reduced by manufacturing the capacitor with a corresponding structure through deep trench and other means, but with the increase of the memory density, the technical difficulty and cost of capacitor processing are greatly increased, and the memory density of the memory device is affected.
Disclosure of Invention
The application mainly solves the technical problems that: the manufacturing method of the memory device and the memory device are provided, so that the memory density of the memory device can be effectively improved, and the cost is reduced.
In order to solve the technical problems, the application adopts a technical scheme that: provided is a method of manufacturing a memory device, including: providing a semiconductor matrix, wherein the semiconductor matrix comprises a substrate and a dielectric layer formed on the substrate; forming a first groove from the dielectric layer towards the substrate, and forming a gate insulating layer and a first gate in the first groove in sequence; and forming a second grid electrode on one side of the first grid electrode, wherein the second grid electrode contacts the substrate and the first grid electrode, and the first grid electrode and the second grid electrode form a semi-floating gate of a storage unit in the storage device.
In one embodiment of the present application, the providing a semiconductor substrate includes: providing the substrate, wherein the doped region is formed in one side of the substrate, and has a first doping type; forming the dielectric layer on the doped region; a plurality of second grooves are formed from the dielectric layer towards the substrate, wherein the second grooves are distributed in sequence along a first direction; and forming a shallow trench isolation structure in the second groove, thereby forming the semiconductor matrix.
In an embodiment of the present application, the substrate is a substrate with a well region of a second doping type, and after the shallow trench isolation structure is formed in the second recess, the providing a semiconductor body further includes: and performing ion implantation on the substrate to form a well region with a second doping type on the substrate, wherein the second doping type is opposite to the first doping type.
In an embodiment of the present application, the forming a first groove from the dielectric layer toward the substrate, and forming a gate insulating layer and a first gate in the first groove sequentially includes: forming a plurality of first grooves along a second direction from the dielectric layer towards the semiconductor substrate; forming a gate insulating layer in the first groove, wherein the gate insulating layer covers the part of the substrate exposed through the first groove; and filling a first gate substance in the first groove formed with the gate insulating layer to form the first gate, wherein the first gate is isolated from the substrate through the gate insulating layer.
In an embodiment of the present application, forming a second gate on one side of the first gate includes: etching the dielectric layer to remove part of the dielectric layer, and reserving the dielectric layer on the common source electrode end to expose the first drain electrode end and the second drain electrode end, wherein the substrate is divided into the common source electrode end, the first drain electrode end and the second drain electrode end by the first groove; forming a second gate layer on the first drain terminal and the second drain terminal, the second gate layer contacting sidewalls of the first drain terminal and the second drain terminal of the first gate; forming an inter-gate dielectric layer on the second gate layer, the first gate and the residual dielectric layer, and forming a third gate layer on the inter-gate dielectric layer; and then etching to form a first island-shaped structure, wherein a part of the second gate layer is remained at the side wall ends of the first drain end and the second drain end of the first gate in the first island-shaped structure, and the remained second gate layer is used as the second gate.
In an embodiment of the present application, further comprising: etching the first island-shaped structure to remove part of the third gate electrode layer, the inter-gate dielectric layer and the dielectric layer, and form a second island-shaped structure, wherein the residual third gate electrode layer is used as a control gate of a storage unit in the storage device, and the control gate is isolated from the first gate electrode and the second gate electrode serving as a semi-floating gate by the inter-gate dielectric layer; and forming side walls on two sides of the second island-shaped structure respectively.
In an embodiment of the present application, the dielectric layer includes a first dielectric layer and a second dielectric layer, where the first dielectric layer covers the substrate, the second dielectric layer covers the first dielectric layer, and materials of the first dielectric layer and the second dielectric layer are different.
In an embodiment of the present application, the etching the dielectric layer to remove a portion of the dielectric layer, and leaving the dielectric layer on the common source terminal to expose the first drain terminal and the second drain terminal, includes: etching the dielectric layer, and removing part of the dielectric layers on the first drain electrode end and the second drain electrode end to form a third island-shaped structure, wherein a part of the second dielectric layer is remained on one side, far away from the shared source electrode end, of the first grid electrode in the third island-shaped structure, and the dielectric layer is remained on the shared source electrode end; removing the second dielectric layer remained on one side of the first grid electrode far away from the common source electrode end; and removing the residual first dielectric layer on the first drain electrode end and the second drain electrode end, and reserving the dielectric layer on the common source electrode end to expose the first drain electrode end and the second drain electrode end.
In an embodiment of the present application, before forming an inter-gate dielectric layer on the second gate layer, the first gate, and the remaining dielectric layer, the method further includes: and removing part of the shallow trench isolation structure so that the first gate is higher than the shallow trench isolation structure to form a tooth-shaped structure.
In order to solve the technical problems, the application adopts another technical scheme that: a memory device is provided, comprising a substrate, a groove, a first gate and a second gate, wherein the groove extends from the first surface of the substrate to the substrate, and a gate insulating layer is formed on the inner wall of the groove; a first gate filled in the recess with the gate insulation layer and extending onto the substrate, the first gate being isolated from the substrate by the gate insulation layer; the second grid electrode is arranged on one side of the first grid electrode and is in contact with the substrate and the first grid electrode, and the second grid electrode and the first grid electrode form a semi-floating gate of a storage unit in the storage device.
In an embodiment of the application, the device further includes a dielectric isolation retaining wall disposed on the other side of the first gate.
In an embodiment of the present application, a width of the second gate in the second direction is 10nm-20nm.
In an embodiment of the present application, further comprising: the inter-gate dielectric layer is arranged on the second grid electrode and the first grid electrode; the third grid electrode is arranged on the inter-grid dielectric layer and forms a control grid electrode of a storage unit in the storage device.
In an embodiment of the present application, further comprising: and the side walls are arranged at two sides of the storage unit in the storage device.
In an embodiment of the present application, further comprising: and the first grid is higher than the shallow trench isolation structure so as to form a tooth-shaped structure.
Unlike the prior art, the manufacturing method of the memory device provided by the application comprises the following steps: providing a semiconductor matrix, wherein the semiconductor matrix comprises a substrate, a dielectric layer formed on the substrate and a shallow trench isolation structure for isolating a memory cell in a memory device; forming a first groove from the dielectric layer towards the substrate, and sequentially forming a gate insulating layer and a first gate in the first groove; and forming a second grid electrode on one side of the first grid electrode, wherein the second grid electrode contacts the substrate and the first grid electrode, and the first grid electrode and the second grid electrode form a semi-floating gate of a storage unit in the storage device. The first grid electrode is formed in the first groove, so that the size of the first grid electrode is reduced, the size of the semi-floating gate is reduced in the extending direction of the bit line, the storage density is correspondingly improved under the same size, and the cost is reduced when the storage devices with the same density are manufactured.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art. Wherein:
FIG. 1 is a flow chart of a method of fabricating a memory device according to an embodiment of the present application;
FIG. 2a is a schematic view of a first direction structure of an embodiment of a semiconductor substrate according to the present application; FIG. 2b is a schematic diagram illustrating a second direction of an embodiment of a semiconductor substrate according to the present application;
FIG. 3a is a schematic view illustrating a first direction of an embodiment of the semiconductor substrate with a second recess according to the present application; FIG. 3b is a schematic view of a second direction of an embodiment of the semiconductor substrate with a second recess according to the present application;
FIG. 4a is a schematic diagram illustrating a first direction of forming a shallow trench isolation structure on a semiconductor substrate according to an embodiment of the present application; FIG. 4b is a schematic diagram illustrating a second direction of forming a shallow trench isolation structure on a semiconductor substrate according to an embodiment of the present application;
FIG. 5a is a schematic view illustrating a first direction of an embodiment of forming a first recess in a semiconductor substrate according to the present application; FIG. 5b is a schematic diagram illustrating a second direction of an embodiment of the present application for forming a first recess in a semiconductor substrate;
fig. 6a is a schematic view of a first direction of an embodiment of forming a gate insulating layer in a first recess in the present application; fig. 6b is a schematic structural diagram of an embodiment of forming a gate insulating layer in a first recess in a second direction in the present application;
fig. 7a is a schematic view illustrating a first direction of an embodiment of forming a first gate in a first recess according to the present application; fig. 7b is a schematic view illustrating a second direction of an embodiment of forming a first gate in a first recess according to the present application;
FIG. 8a is a schematic view of a first direction of an embodiment of forming a mask pattern on a first insulating layer according to the present application; FIG. 8b is a schematic diagram illustrating a second direction of an embodiment of forming a mask pattern on a first insulating layer according to the present application;
FIG. 9a is a schematic view of a first direction of an embodiment of forming a third island structure according to the present application; FIG. 9b is a schematic diagram illustrating a second direction of an embodiment of forming a third island structure according to the present application;
FIG. 10a is a schematic view illustrating a first direction of an embodiment of the present application for removing a residual second dielectric layer on a side of the first gate away from the common source doped region; FIG. 10b is a schematic diagram illustrating a second direction of an embodiment of the present application for removing the residual second dielectric layer on the side of the first gate away from the common source doped region;
FIG. 11a is a schematic view illustrating a first direction of an embodiment of removing a first dielectric layer according to the present application; FIG. 11b is a schematic diagram illustrating a second direction of an embodiment of the present application for removing the first dielectric layer;
FIG. 12a is a schematic view of a first direction of an embodiment of forming a second gate layer according to the present application; FIG. 12b is a schematic diagram illustrating a second direction of an embodiment of forming a second gate layer according to the present application;
FIG. 13a is a schematic view illustrating a first direction of a shallow trench isolation structure according to an embodiment of the present application; FIG. 13b is a schematic diagram illustrating a second direction of the removal of a portion of a STI structure according to an embodiment of the present application;
FIG. 14a is a schematic view illustrating a first direction of an embodiment of forming a third gate layer according to the present application; FIG. 14b is a schematic diagram illustrating a second direction of an embodiment of forming a third gate layer according to the present application;
FIG. 15a is a schematic view of a first direction of an embodiment of forming a first island structure according to the present application; FIG. 15b is a schematic view of a second direction of an embodiment of the present application for forming a first island;
FIG. 16a is a schematic view of a first direction of an embodiment of forming a second island structure according to the present application; fig. 16b is a schematic view of a second direction of an embodiment of forming a second island structure according to the present application.
In the drawings, a semiconductor body 100, a second recess 101, a first recess 102, a substrate 110, a doped region 120, a common source terminal 122, a first drain terminal 121, a second drain terminal 123, a dielectric layer 130, a first dielectric layer 131, a second dielectric layer 132, a shallow trench isolation structure 140, a second doping type well region 150, a gate insulating layer 160, a first gate 200, a second gate layer 300, a second gate 310, a first insulating layer 400, an inter-gate dielectric layer 500, a third gate layer 600, and a sidewall 700.
Detailed Description
The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
The terms "first," "second," "third," and the like in this disclosure are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first", "a second", and "a third" may explicitly or implicitly include at least one such feature. In the description of the present application, the meaning of "plurality" means at least two, for example, two, three, etc., unless specifically defined otherwise. All directional indications (such as up, down, left, right, front, back … …) in embodiments of the present application are merely used to explain the relative positional relationship, movement, etc. between the components in a particular gesture (as shown in the drawings), and if the particular gesture changes, the directional indication changes accordingly. Furthermore, the terms "comprise" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those listed steps or elements but may include other steps or elements not listed or inherent to such process, method, article, or apparatus.
Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the application. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those of skill in the art will explicitly and implicitly appreciate that the embodiments described herein may be combined with other embodiments.
The present application will be described in detail with reference to the accompanying drawings and examples.
In the current manufacturing process of the memory device, a scheme of a dynamic random access memory (Dynamic Random Access Memory, DRAM) is generally adopted for manufacturing, for example, a common MOSFET transistor is adopted, a basic unit of the memory device is formed by 1T1C, namely, a structure of a transistor and a capacitor is adopted, and the occupied area of the memory device is usually reduced by manufacturing the capacitor with a corresponding structure through deep groove digging and other means, but with the increase of the memory density, the technical difficulty and cost of capacitor processing are greatly increased, and the memory density of the memory device is affected.
Semi-floating gate memory is an alternative concept to DRAM devices, which include one floating gate transistor and an embedded tunneling transistor, and write and erase operations are performed on the floating gate of the floating gate transistor through the channel of the embedded tunneling transistor, unlike the usual 1T1C structure.
Therefore, the manufacturing method of the memory device can effectively reduce the size of the semi-floating gate in the extending direction of the bit line, correspondingly improve the memory density under the same size, and further reduce the cost when the memory device with the same density is manufactured.
Referring to fig. 1, fig. 1 is a flow chart illustrating an embodiment of a method for manufacturing a memory device according to the present application.
As shown in fig. 1, the method for manufacturing a memory device of the present application includes:
s11, providing a semiconductor matrix, wherein the semiconductor matrix comprises a substrate and a dielectric layer formed on the substrate. The semiconductor substrate is provided as shown in fig. 4a and 4 b.
The operation flow of one embodiment of step S11 is as follows:
a substrate is provided, and a doped region is formed in one side of the substrate, the doped region having a first doping type.
Wherein the substrate may be any suitable substrate known in the art, for example, at least one of the following mentioned materials: silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbon (SiC), silicon germanium carbon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), or other III/V compound semiconductors, and also include multilayer structures made of these semiconductors, or the like, or are silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator (S ≡sigeoi), silicon-on-insulator (SiGeOI), and germanium-on-insulator (GeOI).
In some embodiments, a doped region is formed by ion implantation in a substrate, the doped region being formed on one side of the substrate, the doped region having a first doping type.
A dielectric layer is formed over the doped region.
Referring to fig. 2a and 2b, fig. 2a is a schematic view illustrating a first direction structure of an embodiment of a semiconductor substrate according to the present application, and fig. 2b is a schematic view illustrating a second direction structure of an embodiment of a semiconductor substrate according to the present application.
The first direction is a word line extending direction (WL), the first direction is an X direction, the second direction is a bit line extending direction (BL), and the second direction is a Y direction, that is, the first direction and the second direction are perpendicular to each other in the same horizontal plane.
Specifically, the semiconductor body 100 may include a substrate 110, a doped region 120 in the substrate 110, a dielectric layer 130; as shown in fig. 2a, in the first direction, the doped region 120 is formed on one side of the substrate 110, and the dielectric layer 130 forms a surface of the doped region 120 away from the substrate 110; as shown in fig. 2b, in the second direction, the doped region 120 is formed on the substrate 110 side, and the dielectric layer 130 is formed on the doped region 120.
In some embodiments, the dielectric layer 130 may be a nitride layer, an oxide layer, a oxynitride layer, etc., such as at least one of silicon nitride, silicon oxide, silicon oxynitride. In the following embodiment, the dielectric layer 130 includes a first dielectric layer 131 and a second dielectric layer 132, where the first dielectric layer 131 is silicon oxide and the second dielectric layer 132 is silicon nitride.
A plurality of second grooves are formed from the dielectric layer towards the substrate, wherein the second grooves are distributed in sequence along the first direction. An active region is defined by the shallow trench isolation structure, and a plurality of second grooves are formed in the active region.
Referring to fig. 3a and 3b, fig. 3a is a schematic view illustrating a first direction structure of an embodiment of forming a second recess on a semiconductor substrate according to the present application; FIG. 3b is a schematic diagram illustrating a second direction of an embodiment of the semiconductor substrate with a second recess according to the present application.
As shown in fig. 3a, in the first direction, a plurality of second grooves 101 are opened from the first surface of the dielectric layer 130 away from the substrate 110 toward the dielectric layer 130, the doped region 120, and the substrate 110. As shown in fig. 3b, in the second direction, the doped region 120 is formed on the substrate 110 side, and the dielectric layer 130 is formed on the doped region 120.
In some embodiments, the plurality of second grooves 101 are sequentially spaced apart along the first direction (X-direction), and the bottoms of the second grooves are lower than the bottoms of the doped regions 120, i.e., the second grooves 101 extend to a portion of the substrate 110.
And forming a shallow trench isolation structure in the second groove, thereby forming a semiconductor substrate.
Referring to fig. 4a and 4b, fig. 4a is a schematic structural diagram illustrating a first direction of an embodiment of forming a shallow trench isolation structure on a semiconductor substrate according to the present application; FIG. 4b is a schematic diagram illustrating a second direction of forming a shallow trench isolation structure on a semiconductor substrate according to an embodiment of the present application.
Specifically, in the first direction, as shown in fig. 4a, the doped region 120 is formed on one side of the substrate 110, the dielectric layer 130 is formed on the doped region 120, a shallow trench, that is, a second groove is formed from the surface of the dielectric layer 130 away from the doped region 120 toward the semiconductor substrate 100, and a shallow trench isolation material is filled in the second groove to form a shallow trench isolation structure 140; in the second direction, as shown in fig. 4b, the doped region 120 is formed on the substrate 110 side, and the dielectric layer 130 is formed on the doped region 120.
In some embodiments, substrate 110 is a substrate having a well region 150 of a second doping type.
Wherein the second doping type is opposite to the doping type of the first doping type, i.e. the doping type of the doped region 120 and the second doping type well region 150 is opposite; for example, the first doping type is N-type doping, and the second doping type is P-type doping; otherwise, the first doping type is P-type doping, and the second doping type is N-type doping.
Specifically, the substrate 110 includes a well region 150 having a second doping type, and after the shallow trench isolation structure 140 is formed in the second recess 101, ion implantation is performed on the substrate 110 to form the well region 150 having the second doping type on the substrate, so that the substrate 110 is formed into the substrate 110 with the well region 150 having the second doping type after processing; that is, ion implantation is performed on the side of the doped region 120 away from the dielectric layer 130, so that a second doping type well region 150 is formed in the substrate; i.e. the semiconductor body 100 comprises, from bottom to top, the substrate 110, the well region 150 of the second doping type in the substrate 110, the doped region 120 in the substrate 110, and the dielectric layer 130.
S12, forming a first groove from the dielectric layer towards the substrate, and sequentially forming a gate insulating layer and a first gate in the first groove.
The operation flow of one embodiment of step S12 is as follows:
a plurality of first grooves are formed in the second direction from the dielectric layer toward the substrate.
Referring to fig. 5a and 5b, fig. 5a is a schematic view illustrating a first direction of an embodiment of forming a first recess in a semiconductor substrate according to the present application; fig. 5b is a schematic view illustrating a second direction of an embodiment of forming a first recess in a semiconductor substrate according to the present application.
Specifically, a plurality of first grooves 102 are formed in the second direction from the first surface of the dielectric layer 130 away from the substrate 110 toward the semiconductor body 100; that is, in the second direction, a plurality of first recesses 102 are formed, each first recess 102 penetrates through the dielectric layer 130 and the doped region 120, such that the bottom of the first recess 102 exposes the second doping type well region 150, and the doped region 120 is divided into a common source terminal 122, a first drain terminal 121 and a second drain terminal 123 by the first recess 102; in the first direction, the correspondingly formed first grooves 102 are located at two sides of the shallow trench isolation structure 140. Wherein the first drain terminal 121, the second drain terminal 123, and the common source terminal 122 represent that a source region or a drain region will be formed at the terminal later, and do not represent a specific location for forming the source and drain regions.
In some embodiments, in the first direction, a portion of the doped region 120 may remain in the first groove 102, where the cross section of the first groove may be U-shaped, trapezoidal, square, etc., and one or more first grooves may be determined according to the actual device structure; for example, the first groove 102 is a U-shaped groove, that is, a groove with a large opening and a small bottom at the doped region 120.
And forming a gate insulating layer in the first groove, wherein the gate insulating layer covers the exposed part of the substrate through the first groove.
The gate insulating layer 160 may perform an insulating function, and the material may include at least one of silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and the like. In one embodiment, the gate insulating layer 160 is silicon oxide, and is formed on the sidewall and the bottom wall of the first recess by thermal oxidation, and the gate insulating layer is formed only on the exposed surface of the substrate.
In another embodiment, the gate insulating layer 160 may be formed on the sidewalls and the bottom wall of the first recess 102 by deposition, where the gate insulating layer 160 is not only located on the exposed substrate surface but also on the exposed dielectric layer 130. The formation of the first gate electrode continues in the first recess 102, and the gate insulating layer of the first gate electrode on the sidewalls of the first drain terminal 121 and the second drain terminal 123 needs to be removed before the subsequent formation of the second gate electrode layer, so that the second gate electrode layer can be in contact with the first gate electrode.
Referring to fig. 6a and 6b, fig. 6a is a schematic structural diagram illustrating a first direction of an embodiment of forming a gate insulating layer in a first recess according to the present application; fig. 6b is a schematic structural diagram of a second direction of an embodiment of forming a gate insulating layer in a first recess in the present application.
Specifically, the gate insulating layer 160 is formed inside the first groove 102, so that the substrate 110 exposed through the first groove 102 is covered by the gate insulating layer 160, i.e., the doped regions 120 in the substrate 110 on both sides of the first groove 102 are partitioned by the gate insulating layer; in the first direction, the corresponding first groove 102 is located between the two shallow trench isolation structures 140, a gate insulating layer 160 is formed in the first groove 102, and the gate insulating layer 160 covers the exposed portion of the doped region 120 through the first groove 102; in the second direction, the doped region 120 in the substrate 110 is partitioned by the corresponding first recess 102, that is, the doped region 120 in the substrate 110 is partitioned into the common source terminal 122, the first drain terminal 121 and the second drain terminal 123 by the first recess, and the gate insulating layer 160 is formed in the first recess 102, so that the exposed doped region 120 in the first recess 102 is covered.
And filling a first gate substance in the first groove with the gate insulating layer to form a first gate, wherein the first gate is isolated from the substrate by the gate insulating layer.
Referring to fig. 7a and 7b, fig. 7a is a schematic view illustrating a first direction of an embodiment of forming a first gate in a first recess according to the present application; fig. 7b is a schematic diagram illustrating a second direction of an embodiment of forming a first gate in a first recess according to the present application.
Specifically, the first groove 102 formed with the gate insulating layer 160 is filled with a first gate material, so that the first gate 200 is formed in the corresponding first groove 102, and the doped region 120 in the substrate 110 and the first gate 200 are isolated by the gate insulating layer due to the presence of the gate insulating layer 160, so that in the second direction, one side of the first gate 200 in the first groove 102 is the common source terminal 122, and the other side is the first drain terminal 121 or the second drain terminal 123; as shown in fig. 7b, the doped region 120 in the middle of the two first grooves 102 is partially a common source terminal 122, and two sides are respectively a first drain terminal 121 or a second drain terminal 123.
In some embodiments, the first gate material may be a polysilicon material, such as polysilicon.
In some embodiments, polysilicon may be deposited in the first recess 102 by deposition to form the first gate 200, and the surface of the dielectric layer 130 may be subjected to chemical mechanical polishing after deposition, so that the surface of the dielectric layer 130 in which the first recess 102 is formed is flat.
S13, forming a second grid electrode on one side of the first grid electrode, wherein the second grid electrode contacts the substrate and the first grid electrode, and the first grid electrode and the second grid electrode form a semi-floating gate of a storage unit in the storage device.
The semi-floating gate needs to have a portion of the gate electrode contacting the doped region 120 in the substrate 110, and the first gate electrode 200 is in the first recess 102, so that a dielectric layer on one side of the first gate electrode 200 needs to be processed, so that the doped region 120 in the substrate 110 is exposed to form a corresponding contact window, and further, a second gate electrode is formed at the exposed doped region 120, i.e. a second gate electrode is formed at the contact window, so that the second gate electrode and the first gate electrode 200 contact and form the semi-floating gate of the memory cell in the memory device.
The operation flow of one embodiment of step S13 is as follows:
and etching the dielectric layer to remove part of the dielectric layer, and reserving the dielectric layer on the common source electrode end to expose the first drain electrode end and the second drain electrode end, wherein the substrate is divided into the common source electrode end, the first drain electrode end and the second drain electrode end by the first groove.
In order to expose the first drain terminal 121 and the second drain terminal 123, an etching process is required for the dielectric layer 130.
In some embodiments, the dielectric layer 130 includes a first dielectric layer 131 and a second dielectric layer 132, where the first dielectric layer 131 covers the doped region 120, the second dielectric layer 132 covers the first dielectric layer 131, the first dielectric layer 131 and the second dielectric layer 132 are made of different materials, and the first dielectric layer 131 and the first insulating layer 400 are made of the same material; for example: the first dielectric layer 131 is silicon oxide and the second dielectric layer 132 is silicon nitride. The first insulating layer 400 is silicon oxide.
In some embodiments, a first insulating layer 400 may be formed on the dielectric layer 130 before the etching process, wherein the first insulating layer 400 covers the dielectric layer 130 and the first gate 200. The first insulating layer 400 is a hard mask layer formed of an insulating material, such as an oxide layer. In another embodiment, photoresist may also be directly used as a mask layer.
Specifically, after forming the first gate electrode 200, a first insulating layer 400 is formed on the dielectric layer 130; in the first direction, a first insulating layer 400 is formed on the first gate 200 and the shallow trench isolation structure 140; forming a first insulating layer 400 on the dielectric layer 130 in the second direction; further, when the dielectric layer 130 is etched, the first insulating layer 400 is also etched to remove a portion of the first insulating layer 400, so as to expose the first drain terminal 121 and the second drain terminal 123.
The operation flow of an embodiment of etching the dielectric layer is as follows:
and etching the dielectric layer, and removing part of the dielectric layers at the first drain electrode end and the second drain electrode end to form a third island-shaped structure, wherein a part of the second dielectric layer remains at one side of the first grid electrode in the third island-shaped structure, which is far away from the common source electrode end, and the dielectric layer remains on the common source electrode end.
In some embodiments, a mask pattern is formed on the first insulating layer on the basis of the first insulating layer, wherein the mask pattern covers the first insulating layer on the common source terminal and the first gate electrode, and a portion of the first insulating layer on a side of the first gate electrode remote from the common source terminal.
Referring to fig. 8a and 8b, fig. 8a is a schematic view illustrating a first direction of an embodiment of forming a mask pattern on a first insulating layer according to the present application; fig. 8b is a schematic diagram illustrating a second direction of an embodiment of forming a mask pattern on a first insulating layer according to the present application.
Specifically, after forming the first insulating layer 400 on the first gate electrode 200 and the shallow trench isolation structure 140 in the first direction, a mask pattern is formed on the first insulating layer 400 to cover the first insulating layer 400; in the second direction, the first insulating layer 400 on the common source terminal 122 and the first gate electrode 200, and the first insulating layer 400 on a side of the first gate electrode 200 remote from the common source terminal 122 are covered with a mask pattern.
Further, referring to fig. 9a and 9b, fig. 9a is a schematic structural view of a first direction of an embodiment of forming a third island structure according to the present application; fig. 9b is a schematic diagram illustrating a second direction of an embodiment of forming a third island structure according to the present application.
Specifically, after forming the mask pattern, etching is performed using the mask pattern such that the first insulating layer 400 and the dielectric layer 130 of the etched region are etched away; as shown in fig. 9a, since the mask pattern covers the first insulating layer 400 on the first gate electrode 200 and the shallow trench isolation structure 140, the first insulating layer 400 is not etched in the first direction; as shown in fig. 9b, in the second direction, a portion of the second dielectric layer 132 remains on a side of the first gate 200 away from the common source terminal 122, the dielectric layer 130 remains on the common source terminal 122, and the first insulating layer 400 remains on the remaining second dielectric layer 132 and the remaining dielectric layer 130, thereby forming a third island-like structure.
And removing the second dielectric layer remained on one side of the first grid electrode far away from the common source electrode terminal.
The first dielectric layer 131 on the first drain terminal 121 and the second drain terminal 123 serves as an etching stop layer for protecting the substrate from damage.
In some embodiments, the first insulating layer 400 and the second dielectric layer 132 on the first drain terminal 121 and the second drain terminal 123 may be directly etched away when the first insulating layer 400 and the dielectric layer 130 are etched.
Referring to fig. 10a and 10b, fig. 10a is a schematic structural diagram of a first direction of an embodiment of the present application for removing a residual second dielectric layer on a side of a first gate electrode away from a common source terminal; fig. 10b is a schematic diagram illustrating a second direction of an embodiment of the present application for removing the residual second dielectric layer on the side of the first gate away from the common source terminal.
Specifically, in the second direction, the second dielectric layer 132 remaining on the side of the first gate 200 away from the common source terminal 122 is removed, as shown in fig. 10b, two sides of the common source terminal 122 are respectively provided with the corresponding first gate 200, and therefore, the second dielectric layer 132 remaining on the side of the two first gates 200 away from the common source terminal 122 needs to be removed.
And then, removing the first dielectric layer on the residual first drain electrode terminal and the second drain electrode terminal, and reserving the dielectric layer on the common source electrode terminal to expose the first drain electrode terminal and the second drain electrode terminal.
Referring to fig. 11a and 11b, fig. 11a is a schematic view illustrating a first direction of an embodiment of removing a first dielectric layer according to the present application; fig. 11b is a schematic view illustrating a second direction of an embodiment of removing the first dielectric layer in the present application.
In some embodiments, when the first dielectric layer 131 on the remaining first drain terminal 121 and second drain terminal 123 is removed in the presence of the first insulating layer 400, the corresponding first insulating layer 400 is also removed.
Specifically, in the first direction, the first gate 200 and the first insulating layer 400 on the shallow trench isolation structure 140 are removed; in the second direction, the first insulating layer 400 remaining on the third island structure and the first dielectric layer 131 on the first drain terminal 121 and the second drain terminal 123 are removed, and the dielectric layer 130 on the common source terminal 122 is left, so that the first drain terminal 121 and the second drain terminal 123 are exposed.
Thereafter, a second gate layer is formed on the first drain terminal and the second drain terminal, the second gate layer contacting sidewalls of the first drain terminal and the second drain terminal of the first gate.
The second gate layer 300 contacts a side of the first gate electrode 200 remote from the common source terminal 122, and a contact window is formed at a position where the second gate layer 300 contacts the substrate 110, such that the second gate layer 300 contacts the first drain terminal 121 and the second drain terminal 123 in the substrate 110 through the contact window, respectively.
Referring to fig. 12a and 12b, fig. 12a is a schematic view illustrating a first direction of an embodiment of forming a second gate layer according to the present application; fig. 12b is a schematic view of a structure in a second direction of an embodiment of forming a second gate layer in the present application.
Specifically, as shown in fig. 12b, on the basis of exposing the first drain terminal 121 and the second drain terminal 123 in the second direction, corresponding second gate layers are formed on the first drain terminal 121 and the second drain terminal 123, respectively, that is, the second gate layer 300 corresponding to the first drain terminal 121 contacts a side of the corresponding first gate 200 away from the common source terminal 122, and the second gate layer 300 corresponding to the second drain terminal 123 contacts a side of the corresponding first gate 200 away from the common source terminal 122.
In some embodiments, the second gate layer 300 may be formed by an epitaxial manner.
In some embodiments, the second gate layer 300 includes single crystal silicon and polysilicon, with single crystal silicon at the contact window.
In some embodiments, after forming the second gate layer 300 and before forming the third gate layer, that is, before forming the inter-gate dielectric layer on the second gate layer 300, the first gate 200, and the residual dielectric layer 130, the portions of the shallow trench isolation structures 140 are removed such that the first gate 200 is higher than the shallow trench isolation structures 140, forming a tooth structure.
Referring to fig. 13a and 13b, fig. 13a is a schematic view illustrating a first direction of an embodiment of removing a portion of a shallow trench isolation structure according to the present application; FIG. 13b is a schematic diagram illustrating a second direction of the removal of a portion of a STI structure according to one embodiment of the present application.
Specifically, as shown in fig. 13a, in the first direction, a portion of the shallow trench isolation structure 140 is removed, so that all the first gates 200 are higher than the shallow trench isolation structure 140, forming a tooth structure. The tooth-shaped structure can increase the coupling area between the semi-floating gate and the control gate in the semi-floating gate transistor and improve the coupling rate.
In some embodiments, the portion of the shallow trench isolation structure 140 is removed based on the doped region 120, i.e., the portion of the shallow trench isolation structure 140 above the doped region 120 is removed.
An inter-gate dielectric layer is formed over the second gate layer, the first gate, and the remaining dielectric layer, and a third gate layer is formed over the inter-gate dielectric layer.
Referring to fig. 14a and 14b, fig. 14a is a schematic view illustrating a first direction of an embodiment of forming a third gate layer according to the present application; fig. 14b is a schematic view illustrating a structure of a second direction of an embodiment of forming a third gate layer in the present application.
Specifically, as shown in fig. 14a, in the first direction, an inter-gate dielectric layer 500 is formed on the tooth-like structure from which a portion of the shallow trench isolation structure 140 is removed, and a third gate layer 600 is formed on the inter-gate dielectric layer 500; as shown in fig. 14b, in the second direction, an inter-gate dielectric layer 500 is formed on the second gate layer 300, the first gate 200, and the dielectric layer 130 remaining on the common source terminal 122, and a third gate layer 600 is formed on the inter-gate dielectric layer 500.
In some embodiments, the inter-gate dielectric layer 500 may have an ON (Oxide-Nitride) structure, i.e., the inter-gate dielectric layer 500 may include an Oxide layer and a Nitride layer, such as a silicon Oxide layer and a silicon Nitride layer, to form an ON structure.
In some embodiments, the material of the third gate layer 600 may be a polycrystalline material, such as polysilicon.
And then etching to form a first island-shaped structure, wherein a part of the second gate layer is remained at the side wall ends of the first drain end and the second drain end of the first gate in the first island-shaped structure, and the remained second gate layer is used as the second gate.
Referring to fig. 15a and 15b, fig. 15a is a schematic view illustrating a first direction of an embodiment of forming a first island structure according to the present application; fig. 15b is a schematic view of a second direction of an embodiment of forming a first island structure according to the present application.
Specifically, as shown in fig. 15b, the third gate layer 600, the inter-gate dielectric layer 500 and the second gate layer 300 on the first drain terminal 121 and the second drain terminal 123 are subjected to etching treatment in the second direction to form a first island-like structure; and in the first island structure, a portion of the second gate layer 300 remains on a side of the first gate 200 away from the common source terminal 122, that is, on a side wall of the first drain terminal and the second drain terminal of the first gate in the first island structure, the remaining portion of the second gate layer 300 is used as the second gate 310, and the second gate 310 contacts with a side of the first gate 200 away from the common source terminal 122 and contacts with the first drain terminal 121 and/or the second drain terminal 123; for example, two sides of the common source terminal 122 are respectively provided with a corresponding second gate 310, wherein the second gate 310 on one side is contacted with the first drain terminal 121, the second gate 310 on the other side is contacted with the second drain terminal 123, and the semi-floating gate formed by the first gate 200 and the second gate 310 is contacted with the first drain terminal 121 and/or the second drain terminal 123 to form a PN junction contact.
In some embodiments, the width of the second gate 310 in the second direction may be a preset line width, which may be 10nm-20nm.
In some embodiments, the first island structure is further etched to remove a portion of the third gate layer 600, the inter-gate dielectric layer 500, and the dielectric layer 130 on the common source terminal, and form a second island structure, where the remaining third gate layer 600 is used as a control gate of a memory cell in the memory device, and the control gate is isolated from the first gate 200 and the second gate 310, which are half floating gates, by the remaining inter-gate dielectric layer 500. Wherein, a portion of the dielectric layer 130 remains on the other side of the first gate 200 near the common source terminal 122, and the first gate 200 is isolated from the doped region 120 by the gate insulating layer 160 and the remaining dielectric layer 130.
And side walls 700 are formed at both sides of the first island structure, respectively.
Referring to fig. 16a and 16b, fig. 16a is a schematic view illustrating a first direction of an embodiment of forming a second island structure according to the present application; fig. 16b is a schematic view of a second direction of an embodiment of forming a second island structure according to the present application.
Specifically, as shown in fig. 16b, in the second direction, etching is performed on a portion of the first island-shaped structure that shares the source terminal 122 to remove the third gate layer 600, the inter-gate dielectric layer 500 and the dielectric layer 130 that share a portion on the source terminal 122, and form a second island-shaped structure, because the first drain terminal 121 and the second drain terminal 123 are corresponding to both sides of the shared source terminal 122, so that two corresponding second island-shaped structures are formed; wherein, a portion of the dielectric layer 130 remains on a side of the first gate 200 near the common source terminal 122, such that the first gate 200 is isolated from the doped region 120 by the gate insulating layer 160 and the remaining dielectric layer 130, that is, the first gate 200 and the common source terminal 122 are isolated by the gate insulating layer 160 and the remaining dielectric layer 130; the third gate layer 600 remained in the second island structure is used as the control gate 610 of the memory cell in the memory device, the control gate 610 is isolated from the first gate 200 and the second gate 310 which are half floating gates by the remained inter-gate dielectric layer 500, and the remained dielectric layer 130 is used as a dielectric isolation retaining wall; the medium isolation retaining wall comprises a first medium isolation retaining wall and a second medium isolation retaining wall, wherein the first medium isolation retaining wall is arranged on the substrate, the second medium isolation retaining wall is arranged on the first medium isolation retaining wall, the first medium isolation retaining wall is made of silicon oxide, and the second medium isolation retaining wall is made of silicon nitride.
In some embodiments, the dielectric layer 130 may be removed entirely when the portion of the first island structure that shares the source terminal 122 is subjected to an etching process, so that the dielectric layer 130 does not remain in the second island structure.
And after the second island structure is formed, forming side walls 700 on two sides of the second island structure respectively, wherein the side walls 700 are insulating side walls.
In some embodiments, after forming the sidewall 700, under the outer side of the sidewall 700, a source-drain ion implantation is performed on the substrate 110 to form a corresponding common source doped region in the common source terminal 122, a first drain doped region in the first drain terminal 121, and a second drain doped region in the second drain terminal 123, that is, a source-drain ion implantation is performed on the substrate to form a corresponding source and drain.
In some embodiments, a width of the dielectric layer 130 where a portion of the side of the first gate 200 near the common source terminal 122 remains may be the same as a line width of the second gate 310, that is, a line width of the dielectric layer 130 in the second island structure may be 10nm-20nm in the second direction.
Through the above steps, the independently separated semi-floating gate transistors J1 and J2 may be formed on the semiconductor substrate 100, respectively, to thereby form a memory cell in the memory device.
In some embodiments, the uniformity of the line width of the second gate 310 in the semi-floating gate transistors J1 and J2 is beneficial to ensure uniformity of the storage time of the semi-floating gate transistors.
The application also relates to a memory device comprising the semi-floating gate transistor.
The memory device comprises a substrate, a groove, a first grid electrode and a second grid electrode; wherein the groove extends from the first surface of the substrate to the substrate, and a gate insulating layer is formed on the inner wall of the groove; the first grid is filled in the groove with the grid insulating layer and extends to the substrate, and the first grid is isolated from the substrate by the grid insulating layer; the second grid electrode is arranged on one side of the first grid electrode and is in contact with the substrate and the first grid electrode, and the first grid electrode and the second grid electrode form a semi-floating gate of a storage unit in the storage device.
In some embodiments, a second doping type well region and a doping region are formed in the substrate, wherein the doping region is located on one side of the substrate, the second doping type well region is located below the doping region and is in contact with the doping region, and the doping region has a first doping type, and the doping type of the first doping type is opposite to that of the second doping type.
In some embodiments, the substrate further includes shallow trench isolation structures for isolating memory cells in the memory device, the first gate being higher than the shallow trench isolation structures to form a tooth structure.
In some embodiments, the number of the semi-floating gate transistors in the memory device may be multiple, for example, 2, 3, 4, etc., and the line width of the second gate 310 in the different semi-floating gate transistors is 10nm-20nm, where the corresponding contact window in the current technology is greater than the value, resulting in the corresponding gate line width being greater than the value.
In some embodiments, the memory device further includes a dielectric isolation barrier disposed on a side of the first gate near the common source terminal, the dielectric isolation barrier includes a first dielectric isolation barrier and a second dielectric isolation barrier, the first dielectric isolation barrier is disposed on the substrate, the second dielectric isolation barrier is disposed on the first dielectric isolation barrier, the first dielectric isolation barrier is made of silicon oxide, and the second dielectric isolation barrier is made of silicon nitride.
In some embodiments, a media-insulated retaining wall comprises: the first medium isolation retaining wall and the second medium isolation retaining wall are arranged on the doping area, and the second medium isolation retaining wall is arranged on the first medium isolation retaining wall.
In some embodiments, the memory device further includes an inter-gate dielectric layer and a third gate; the inter-gate dielectric layer is arranged on the second grid electrode, the first grid electrode and the dielectric isolation barrier wall; the third grid electrode is arranged on the inter-grid dielectric layer, wherein the third grid electrode forms a control grid electrode of a storage unit in the storage device.
In some embodiments, the memory device further includes sidewalls disposed on both sides of the memory cells in the memory device.
The manufacturing method of the memory device includes: providing a semiconductor substrate, wherein the semiconductor substrate comprises a substrate, a dielectric layer formed on the substrate and a shallow trench isolation structure for isolating a memory cell in a memory device; forming a first groove from the dielectric layer towards the substrate, and sequentially forming a gate insulating layer and a first gate in the first groove; and forming a second grid electrode on one side of the first grid electrode, wherein the second grid electrode contacts the substrate and the first grid electrode, and the second grid electrode and the first grid electrode form a semi-floating gate of a storage unit in the storage device. By the method, the first grid electrode is formed in the first groove, so that the size of the first grid electrode can be effectively reduced, the size of the semi-floating gate is reduced in the extending direction of the bit line, the integration density of the memory device is improved under the same size, the memory density is correspondingly improved, and when the memory device with the same density is manufactured, the cost is reduced.
The foregoing description is only of embodiments of the present invention, and is not intended to limit the scope of the invention, and all equivalent structures or equivalent processes using the descriptions and the drawings of the present invention or directly or indirectly applied to other related technical fields are included in the scope of the present invention.
Claims (16)
1. A method of manufacturing a memory device, comprising:
providing a semiconductor matrix, wherein the semiconductor matrix comprises a substrate and a dielectric layer formed on the substrate;
forming a first groove from the dielectric layer towards the substrate, and forming a gate insulating layer and a first gate in the first groove in sequence;
and forming a second grid electrode on one side of the first grid electrode, wherein the second grid electrode contacts the substrate and the first grid electrode, and the first grid electrode and the second grid electrode form a semi-floating gate of a storage unit in the storage device.
2. The method of claim 1, wherein providing a semiconductor substrate comprises:
providing the substrate, and forming a doped region in one side of the substrate, wherein the doped region has a first doping type;
forming the dielectric layer on the doped region;
A plurality of second grooves are formed from the dielectric layer towards the substrate, wherein the second grooves are distributed in sequence along a first direction;
and forming a shallow trench isolation structure in the second groove, thereby forming the semiconductor matrix.
3. The method of claim 2, wherein the step of determining the position of the substrate comprises,
the substrate is a substrate with a second doping type well region, and after the shallow trench isolation structure is formed in the second groove, the method for providing the semiconductor matrix further comprises the following steps:
and performing ion implantation on the substrate to form a well region with a second doping type on the substrate, wherein the second doping type is opposite to the first doping type.
4. The method of claim 1, wherein the step of determining the position of the substrate comprises,
the first groove is formed from the dielectric layer towards the substrate, and a gate insulating layer and a first gate are sequentially formed in the first groove, comprising:
a plurality of first grooves are formed in the second direction from the dielectric layer towards the substrate;
forming a gate insulating layer in the first groove, wherein the gate insulating layer covers the part of the substrate exposed through the first groove;
And filling a first gate substance in the first groove formed with the gate insulating layer to form the first gate, wherein the first gate is isolated from the substrate through the gate insulating layer.
5. The method of claim 1, wherein the step of determining the position of the substrate comprises,
forming a second gate on one side of the first gate, comprising:
etching the dielectric layer to remove part of the dielectric layer, and reserving the dielectric layer on the common source electrode end to expose a first drain electrode end and a second drain electrode end, wherein the substrate is divided into the common source electrode end, the first drain electrode end and the second drain electrode end by the first groove;
forming a second gate layer on the first drain terminal and the second drain terminal, the second gate layer contacting sidewalls of the first drain terminal and the second drain terminal of the first gate;
forming an inter-gate dielectric layer on the second gate layer, the first gate and the residual dielectric layer, and forming a third gate layer on the inter-gate dielectric layer;
and then etching to form a first island-shaped structure, wherein a part of the second gate layer is remained at the side wall ends of the first drain end and the second drain end of the first gate in the first island-shaped structure, and the remained second gate layer is used as the second gate.
6. The method as recited in claim 5, further comprising:
etching the first island-shaped structure to remove part of the third gate electrode layer, the inter-gate dielectric layer and the dielectric layer and form a second island-shaped structure, wherein the residual third gate electrode layer is used as a control gate of a storage unit in the storage device, and the control gate is isolated from the first gate electrode and the second gate electrode serving as a semi-floating gate by the inter-gate dielectric layer;
and forming side walls on two sides of the second island-shaped structure respectively.
7. The method of claim 5, wherein the step of determining the position of the probe is performed,
the dielectric layer comprises a first dielectric layer and a second dielectric layer, wherein the first dielectric layer is covered on the substrate, the second dielectric layer is covered on the first dielectric layer, and the materials of the first dielectric layer and the second dielectric layer are different.
8. The method of claim 7, wherein the step of determining the position of the probe is performed,
etching the dielectric layer to remove a portion of the dielectric layer, and reserving the dielectric layer on the common source terminal to expose the first drain terminal and the second drain terminal, including:
Etching the dielectric layer, and removing part of the dielectric layers on the first drain electrode end and the second drain electrode end to form a third island-shaped structure, wherein a part of the second dielectric layer is remained on one side, far away from the shared source electrode end, of the first grid electrode in the third island-shaped structure, and the dielectric layer is remained on the shared source electrode end;
removing the second dielectric layer remained on one side of the first grid electrode far away from the common source electrode end;
and removing the residual first dielectric layer on the first drain terminal and the second drain terminal, and reserving the dielectric layer on the common source terminal to expose the first drain terminal and the second drain terminal.
9. The method of claim 5, wherein the step of determining the position of the probe is performed,
before forming the inter-gate dielectric layer on the second gate layer, the first gate and the residual dielectric layer, the method further comprises:
and removing part of the shallow trench isolation structure so that the first gate is higher than the shallow trench isolation structure to form a tooth-shaped structure.
10. A memory device, comprising:
a substrate;
a groove extending from the first surface of the substrate toward the substrate, and a gate insulating layer formed on an inner wall of the groove;
A first gate filled in the recess having the gate insulating layer and extending onto the substrate, the first gate being isolated from the substrate by the gate insulating layer;
and the second grid electrode is arranged on one side of the first grid electrode and is in contact with the substrate and the first grid electrode, and the second grid electrode and the first grid electrode form a semi-floating gate of a storage unit in the storage device.
11. The memory device of claim 10, further comprising:
and the medium isolation retaining wall is arranged on the other side of the first grid electrode.
12. The memory device of claim 10, wherein:
the width of the second grid electrode in the second direction is 10nm-20nm.
13. The memory device of claim 10, further comprising:
the inter-gate dielectric layer is arranged on the second grid electrode and the first grid electrode;
and the third grid electrode is arranged on the inter-grid dielectric layer, wherein the third grid electrode forms a control grid electrode of a storage unit in the storage device.
14. The memory device of claim 10, further comprising:
and the side walls are arranged at two sides of the storage unit in the storage device.
15. The memory device of claim 11, wherein the dielectric isolation barrier comprises: the first medium isolation retaining wall and the second medium isolation retaining wall are arranged on the substrate, the second medium isolation retaining wall is arranged on the first medium isolation retaining wall, the first medium isolation retaining wall is made of silicon oxide, and the second medium isolation retaining wall is made of silicon nitride.
16. The memory device of any of claims 10-15, further comprising: and the first grid is higher than the shallow trench isolation structure so as to form a tooth-shaped structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310944935.4A CN117119793A (en) | 2023-07-28 | 2023-07-28 | Manufacturing method of memory device and memory device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310944935.4A CN117119793A (en) | 2023-07-28 | 2023-07-28 | Manufacturing method of memory device and memory device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN117119793A true CN117119793A (en) | 2023-11-24 |
Family
ID=88793332
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310944935.4A Pending CN117119793A (en) | 2023-07-28 | 2023-07-28 | Manufacturing method of memory device and memory device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN117119793A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN118475123A (en) * | 2024-07-09 | 2024-08-09 | 武汉新芯集成电路股份有限公司 | Method for manufacturing memory device and memory device |
-
2023
- 2023-07-28 CN CN202310944935.4A patent/CN117119793A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN118475123A (en) * | 2024-07-09 | 2024-08-09 | 武汉新芯集成电路股份有限公司 | Method for manufacturing memory device and memory device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8680588B2 (en) | Field effect transistor with buried gate pattern | |
| US8624350B2 (en) | Semiconductor device and method of fabricating the same | |
| US7160780B2 (en) | Method of manufacturing a fin field effect transistor | |
| US8263460B2 (en) | Method for manufacturing semiconductor device with buried gates | |
| KR100945511B1 (en) | Semiconductor device and method for manufacturing the same | |
| US8274111B2 (en) | Method for fabricating a semiconductor memory device having a buried word line structure | |
| US8299517B2 (en) | Semiconductor device employing transistor having recessed channel region and method of fabricating the same | |
| US20100258858A1 (en) | Method of fabricating semiconductor device | |
| US8415733B2 (en) | Semiconductor memory device and method for fabricating the same | |
| KR20180056031A (en) | Semiconductor device and method for fabricating the same | |
| US20120012925A1 (en) | Semiconductor device and method for manufacturing the same | |
| CN111564442B (en) | Semiconductor structure and preparation method | |
| CN104103640A (en) | Semiconductor device with U-shaped channel and manufacturing method thereof | |
| CN114284270A (en) | Memory cell, memory and manufacturing method thereof | |
| CN117119793A (en) | Manufacturing method of memory device and memory device | |
| KR20110080802A (en) | Semiconductor apparatus and fabrication method thereof | |
| US6917064B2 (en) | Trench capacitor and a method for manufacturing the same | |
| CN114267641B (en) | Manufacturing method of embedded word line transistor, transistor and memory | |
| KR101061264B1 (en) | Semiconductor device and manufacturing method thereof | |
| CN114267640B (en) | Semiconductor device and method for manufacturing the same | |
| KR101074232B1 (en) | Semiconductor device and manufacturing method thereof | |
| CN110957325B (en) | Semiconductor memory and method of manufacturing the same | |
| CN113394272A (en) | Semiconductor structure and forming method thereof | |
| CN114267640A (en) | Semiconductor device and method for manufacturing the same | |
| KR101004527B1 (en) | Method of fabricating semiconductor apparatus and semiconductor apparatus fabricated thereby |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| CB02 | Change of applicant information |
Country or region after: China Address after: 430205 No.18, Gaoxin 4th Road, Donghu Development Zone, Wuhan City, Hubei Province Applicant after: Wuhan Xinxin Integrated Circuit Co.,Ltd. Address before: 430205 No.18, Gaoxin 4th Road, Donghu Development Zone, Wuhan City, Hubei Province Applicant before: Wuhan Xinxin Semiconductor Manufacturing Co.,Ltd. Country or region before: China |
|
| CB02 | Change of applicant information |