CN117119792A

CN117119792A - Method for embedding a conductor line in a semiconductor structure and semiconductor structure

Info

Publication number: CN117119792A
Application number: CN202310841597.1A
Authority: CN
Inventors: 潘立阳; 刘子易; 张志刚
Original assignee: Tsinghua University; Beijing Superstring Academy of Memory Technology
Current assignee: Tsinghua University; Beijing Superstring Academy of Memory Technology
Priority date: 2023-07-10
Filing date: 2023-07-10
Publication date: 2023-11-24

Abstract

The present disclosure provides a method of burying a conductor line in a semiconductor structure and a semiconductor structure. The method according to the present disclosure comprises: providing a substrate; sequentially arranging a first sacrificial layer, a semiconductor layer, a second sacrificial layer, an active layer and a hard mask layer on a substrate; patterning and etching the hard mask layer to form a hard mask barrier part and forming side walls on two sides of the hard mask barrier part; self-aligned etching the active layer, the second sacrificial layer, the semiconductor layer and the first sacrificial layer using the hard mask barrier and the sidewall to form a first trench extending to the substrate and filling the first trench with a first isolation medium; removing the hard mask barrier portion, and self-aligning etching the active layer by using the side wall to form a second groove exposing the second sacrificial layer; removing the second sacrificial layer through the second trench to embed the conductor line under the active layer; etching the semiconductor layer through the second trench to expose the first sacrificial layer; removing the first sacrificial layer through the second trench; and filling the second trench and removing the space left by the first sacrificial layer with a second isolation medium.

Description

Method for embedding a conductor line in a semiconductor structure and semiconductor structure

Technical Field

The present disclosure relates to the field of semiconductor technology, and in particular, to a method for embedding a conductor line in a semiconductor structure and a semiconductor structure having an embedded conductor line fabricated using the method.

Background

Since the invention of dynamic random access memory (Dynamic Random Access Memory, DRAM) by intel corporation of seventies in the twentieth century (Intel Corporation), DRAM has been widely used in various computing or control electronic circuitry.

DRAM cell circuits are typically constructed of one transistor for gating and one capacitor for storing charge (1T 1C structure). In a DRAM cell structure implementing a gate transistor using a conventional planar structure-based horizontal transistor, such as a metal oxide semiconductor field effect transistor (Metal Oxide Semiconductor Field Effect Transistor, MOSFET), the source, gate and drain of the transistor are arranged in a horizontal direction parallel to the substrate surface. Since the source, gate and drain of the transistor each occupy an independent area in the horizontal direction, the miniaturization of the DRAM cell circuit structure is limited by the gate length and the contact size, and the continuous miniaturization requirement of the DRAM device cannot be satisfied, thereby limiting the further increase of the integration level and the bandwidth of the DRAM device.

Accordingly, in recent years, a vertical DRAM cell structure has been proposed in which the source, gate and drain of the transistor are arranged in a vertical direction perpendicular to the substrate surface, without requiring an additional occupied area, which is advantageous in downsizing of the DRAM array structure.

However, with a DRAM array structure constituted by a vertical type DRAM cell structure, it is necessary to arrange bit lines and word lines in the vertical direction to interconnect the DRAM cell structures into a DRAM array structure in the column direction and the row direction, and thus how to arrange bit lines in the DRAM array structure while ensuring performance and increasing density is still a problem to be improved.

The above information disclosed in this background section is only for the understanding of the background of the inventive concept and thus may contain information that does not form the prior art.

Disclosure of Invention

In order to solve the above problems in the prior art, the present disclosure proposes a novel method for embedding conductor lines in a semiconductor structure.

According to one aspect of the present disclosure, there is provided a method for burying a conductor line in a semiconductor structure, including: providing a substrate; sequentially arranging a first sacrificial layer, a semiconductor layer, a second sacrificial layer, an active layer and a hard mask layer on a substrate; patterning and etching the hard mask layer to form a hard mask barrier part, and forming side walls on two sides of the hard mask barrier part; self-aligned etching the active layer, the second sacrificial layer, the semiconductor layer and the first sacrificial layer using the hard mask barrier and the sidewall to form a first trench extending to the substrate, and filling the first trench with a first isolation medium; removing the hard mask barrier portion, and self-aligning etching the active layer by using the side wall to form a second groove exposing the second sacrificial layer; removing the second sacrificial layer through the second trench to embed the conductor line under the active layer through the second trench; etching the semiconductor layer through the second trench to expose the first sacrificial layer; removing the first sacrificial layer through the second trench; and filling the second trench and removing the space left by the first sacrificial layer with a second isolation medium.

According to another aspect of the present disclosure, there is provided a method for burying a conductor line in a semiconductor structure, including: providing a substrate; sequentially arranging a first sacrificial layer, a semiconductor layer, a second sacrificial layer, an active layer and a hard mask layer on a substrate, wherein the second sacrificial layer has etching selectivity relative to the first sacrificial layer; patterning and etching the hard mask layer to form a hard mask barrier part, and forming side walls on two sides of the hard mask barrier part; self-aligned etching the active layer, the second sacrificial layer, the semiconductor layer, the first sacrificial layer and/or the substrate using the hard mask barrier and the sidewall to form a first trench extending to the substrate; removing a portion of the second sacrificial layer through the first trench to embed the conductor line under the active layer through the first trench; filling the first trench with a first isolation medium; removing the hard mask barrier portion, and performing self-aligned etching on the active layer, the second sacrificial layer and the semiconductor layer by using the side wall to form a second groove exposing the first sacrificial layer; removing the remaining portion of the second sacrificial layer and the first sacrificial layer through the second trench; and filling the second trench with a second isolation medium and removing the remaining portion of the second sacrificial layer and the space left by the first sacrificial layer.

According to another aspect of the present disclosure, there is provided a method for burying a conductor line in a semiconductor structure, including: providing a substrate; sequentially arranging a first sacrificial layer, a semiconductor layer, a second sacrificial layer, an active layer and a hard mask layer on a substrate; patterning and etching the hard mask layer to form a hard mask barrier part, and forming side walls on two sides of the hard mask barrier part; self-aligned etching the active layer using the hard mask barrier and the sidewall to form a first trench exposing the second sacrificial layer; removing a portion of the second sacrificial layer through the first trench to embed the conductor line under the active layer through the first trench; etching the semiconductor layer, the first sacrificial layer and/or the substrate through the first trench such that the first trench extends to the substrate; filling the first trench with a first isolation medium; removing the hard mask barrier portion, and performing self-aligned etching on the active layer, the second sacrificial layer and the semiconductor layer by using the side wall to form a second groove exposing the first sacrificial layer; removing the remaining portion of the second sacrificial layer and the first sacrificial layer through the second trench; and filling the second trench with a second isolation medium and removing the remaining portion of the second sacrificial layer and the space left by the first sacrificial layer.

According to another aspect of the present disclosure, there is provided a method for burying a conductor line in a semiconductor structure, including: providing a substrate; a first sacrificial layer, a semiconductor layer, a second sacrificial layer and an active layer are sequentially arranged on a substrate; forming a first groove and a second groove exposing the first sacrificial layer and the second sacrificial layer respectively through two times of self-alignment etching; removing the first sacrificial layer through the second trench to provide an isolation structure under the semiconductor layer; removing all or a portion of the second sacrificial layer through at least one of the first and second trenches to embed the conductor line under the active layer; and filling the first and second trenches with an isolation medium.

According to another aspect of the present disclosure, there is provided a semiconductor structure with buried conductor lines manufactured using the method according to the above aspect of the present disclosure.

According to the method for embedding a conductor line in a semiconductor structure of the present disclosure, a plurality of embedded conductor lines isolated from each other can be formed by forming a first trench and a second trench isolated from each other by two self-aligned etches, and disposing an isolation medium under the semiconductor layer through the second trench using two sacrificial layers.

However, the effects of the present disclosure are not limited to the above-described effects, and various extensions may be made without departing from the spirit and scope of the present disclosure. It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the disclosure as claimed.

Drawings

The accompanying drawings, which are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the disclosure and together with the description serve to explain the principles of the invention.

Fig. 1 is a circuit diagram illustrating a DRAM cell structure according to an embodiment of the present disclosure.

Fig. 2 is a circuit diagram illustrating a DRAM array structure comprised of the DRAM cell structure of fig. 1, according to an embodiment of the present disclosure.

Fig. 3 is a schematic cross-sectional view along a bit line direction showing a DRAM array structure according to an embodiment of the present disclosure.

Fig. 4A to 4O are schematic cross-sectional views respectively showing process steps of a method for burying a conductor line in a semiconductor structure according to an embodiment of the present disclosure.

Fig. 5 is a schematic cross-sectional view illustrating a semiconductor structure with buried conductor lines according to another embodiment of the present disclosure.

Fig. 6A to 6E are schematic cross-sectional views each showing a process step of a method for burying a conductor line in a semiconductor structure according to another embodiment of the present disclosure.

Fig. 7A to 7C are schematic cross-sectional views each showing a process step of a method for burying a conductor line in a semiconductor structure according to another embodiment of the present disclosure.

Fig. 8 is a schematic cross-sectional view illustrating a semiconductor structure with buried conductor lines according to another embodiment of the present disclosure.

Fig. 9 is a schematic cross-sectional view showing the semiconductor structure taken along line BB' in fig. 4O, 5, 6E, and 7.

Detailed Description

In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the various exemplary embodiments of the present disclosure. As used herein, an "embodiment" is a non-limiting example of an apparatus or method employing one or more of the inventive concepts disclosed herein. It may be evident, however, that the exemplary embodiments may be practiced without these specific details or with one or more equivalent arrangements. Furthermore, the various exemplary embodiments may be different, but are not necessarily exclusive. For example, certain features of other exemplary embodiments may be used or implemented in some exemplary embodiments without departing from the inventive concept.

Unless otherwise indicated, the described exemplary embodiments should be understood to provide exemplary features of varying detail in some ways that the inventive concept may be practiced. Thus, unless otherwise indicated, features, components, modules, regions, and/or aspects of the embodiments (hereinafter referred to individually or collectively as "elements") may be otherwise combined, separated, interchanged, and/or rearranged without departing from the inventive concepts.

For the purposes of this disclosure, "at least one of X, Y and Z" and "at least one selected from the group consisting of X, Y and Z" may be construed as any combination of two or more of X only, Y only, Z only, or X, Y and Z, such as XYZ, XYY, YZ and ZZ. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

Although the terms "first," "second," etc. may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another element. Thus, a first element discussed below could be termed a second element without departing from the teachings of the present disclosure.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Furthermore, the terms "comprises" and/or "comprising," when used in this specification, mean that there are stated features, steps, operations, elements, components, and/or groups thereof, but that the presence or addition of one or more other features, steps, operations, elements, components, and/or groups thereof is not precluded. It should also be noted that as used herein, the terms "substantially," "about," and other similar terms are used as approximation terms and not degree terms and, thus, are used to account for inherent deviations in measured, calculated, and/or provided values that would be recognized by one of ordinary skill in the art.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. Terms such as defined in commonly used dictionaries should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

Embodiments of the present disclosure will now be described more fully hereinafter with reference to the accompanying drawings. The present disclosure may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. Like numbers refer to like elements throughout. Also, in the drawings, the components are not necessarily drawn to scale and the ratio and size of the components may be exaggerated for clarity of illustration.

Fig. 1 shows a circuit diagram of a Dynamic Random Access Memory (DRAM) cell structure 100 according to an embodiment of the present disclosure.

As shown in fig. 1, a DRAM cell structure 100 according to an embodiment of the present disclosure may include a gate transistor T and a storage capacitor C. As shown in fig. 1, the gate of the gate transistor T is connected to the word line WL, the first source/drain thereof is connected to the bit line BL, and the second source/drain thereof is connected to one plate of the storage capacitor C. Further, as shown in fig. 1, the other plate of the storage capacitor C is connected to the source line SL. The source line SL is typically connected to a fixed voltage lower than the power supply voltage. The fixed voltage is used as a reference voltage, typically half the supply voltage.

Fig. 2 illustrates a circuit diagram of a DRAM array structure 200 comprised of the DRAM cell structure 100 of fig. 1, in accordance with an embodiment of the present disclosure.

As shown in fig. 2, a DRAM array structure 200 according to an embodiment of the present disclosure may include a plurality of DRAM cell structures 100 as shown in fig. 1. Specifically, as shown in FIG. 2, DRAM array structure 200 may include M rows and N columns of identical DRAM cell circuits 100 as shown in FIG. 1, where M and N are natural numbers greater than zero. Reference numerals in each DRAM cell circuit 100 are omitted from fig. 2 for convenience of description. In addition, peripheral circuits of the DRAM array structure 200, such as reference cells, sense amplifiers, etc., are omitted from fig. 2 for convenience of description.

As shown in fig. 2, adjacent rows of DRAM cell structures may share a source line SL in a DRAM array structure 200 in order to increase density according to embodiments of the present disclosure. According to an embodiment of the present disclosure, the source lines SL may be commonly connected to a fixed voltage as described above. Further, as shown in FIG. 2, a DRAM array structure 200 may have M word lines WL [1] to WL [ M ] respectively connected to M rows of DRAM cell structures and N bit lines BL [1] to BL [ N ] respectively connected to N columns of DRAM cell structures, according to embodiments of the present disclosure.

Fig. 3 is a schematic cross-sectional view along a bit line direction showing a DRAM array structure according to an embodiment of the present disclosure. Referring to fig. 3 in combination with fig. 1 and 2, in forming a DRAM array structure 200 using the vertical type DRAM cell structures 100 according to an embodiment of the present disclosure, since a word line extending in a row direction is connected to a gate of a gate transistor T in each DRAM cell structure 100, the word line may be disposed between the DRAM cell structures 100 of adjacent rows in the DRAM array structure 200. Further, according to the embodiment of the present disclosure, since the gate transistor T in each DRAM cell structure 100 is connected between the storage capacitor C and the bit line BL in the vertical direction, the bit line BL extending in the column direction may be buried under the gate transistor T for the convenience of process implementation, so that the storage capacitor is conveniently formed above the gate transistor T.

Fig. 4A to 4O are schematic cross-sectional views respectively showing respective process steps of a method for burying a conductor line in a semiconductor structure according to an embodiment of the present disclosure. Those skilled in the art will recognize that while described herein with reference to buried conductor lines as bit lines for a DRAM array structure comprised of vertical DRAM cell structures, the methods of buried conductor lines in a DRAM array structure according to the concepts of the present disclosure may also be applied to buried conductor lines in other semiconductor structures, and are not limited to the applications described herein.

It should be noted that fig. 4A to 4O are cross-sectional views taken along the row direction, i.e., the word line direction, of the DRAM array structure, which show the cross-section of the bit lines.

In the following description, materials of the respective layers are exemplified. The main purpose of selecting the different materials is to provide the desired etch selectivity. The following description "(with respect to a) selective etching B" means that the etching recipe used may act primarily on B with little or no effect on a or other material layers exposed to the etching recipe when etching B (in the case where a is not explicitly mentioned or only some of such material layers are mentioned). Those skilled in the art will know how to select the materials of the layers based on this description and are not limited to the materials illustrated herein.

As shown in fig. 4A, a substrate 411 may be provided according to an embodiment of the present disclosure. According to embodiments of the present disclosure, the substrate 411 may be various forms of substrates including, but not limited to, bulk semiconductor material substrates such as bulk silicon (Si) substrates, semiconductor-on-insulator (SOI) substrates such as silicon-on-insulator substrates, compound semiconductor substrates such as silicon germanium (SiGe) substrates, and the like. In the following description, the substrate 411 is described as a bulk silicon substrate for convenience.

Subsequently, as shown in fig. 4B, according to an embodiment of the present disclosure, a first sacrificial layer 401, a semiconductor layer 402, a second sacrificial layer 403, and an active layer 404 may be sequentially grown on a substrate 411 by, for example, an epitaxial process. According to embodiments of the present disclosure, the first sacrificial layer 401 and the second sacrificial layer 403 may include a material having etching selectivity, such as silicon germanium (SiGe). According to embodiments of the present disclosure, the first sacrificial layer 401 and the second sacrificial layer 403 may or may not have etch selectivity with respect to each other. For example, when the first sacrificial layer 401 and the second sacrificial layer 403 each include a germanium-silicon material, the first sacrificial layer 401 and the second sacrificial layer 403 may have the same or different germanium concentrations according to embodiments of the present disclosure.

According to embodiments of the present disclosure, the first sacrificial layer 401 may be used to form an isolation structure for isolating a conductor line in a subsequent process step. Further, according to embodiments of the present disclosure, the second sacrificial layer 403 may be used to form conductor lines used as, for example, bit lines in subsequent process steps.

According to embodiments of the present disclosure, the semiconductor layer may include a semiconductor material, such as silicon (Si). Further, according to embodiments of the present disclosure, the active layer 404 may include a semiconductor material, such as silicon.

In accordance with embodiments of the present disclosure, active layer 404 may be doped in-situ as it is grown, for example, by an epitaxial process. It should be noted that the active layer 404 may be used to form an active region, i.e., a first source/drain, a channel region, and a second source/drain sequentially disposed from bottom to top in a vertical direction, of the gate transistor T, e.g., the DRAM cell structure 100, in subsequent process steps, according to embodiments of the present disclosure.

According to embodiments of the present disclosure, the gate transistor T may be a junction-free device, in which case the active layer 404 may be doped with the same type, e.g., N-type doping.

Furthermore, the gating transistor T may also be a junction device, in which case the active layer 404 may be doped differently, according to embodiments of the present disclosure. For example, a lower end portion and an upper end portion of the active layer 404 may be N-doped to form a first source/drain and a second source/drain of the gate transistor T, respectively, and an intermediate portion of the active layer 404 may be P-doped to form a channel region.

Subsequently, as shown in fig. 4C, a hard mask layer may be formed on the active layer 404 by, for example, a deposition process according to an embodiment of the present disclosure. According to embodiments of the present disclosure, the hard mask layer may include, for example, silicon oxide, silicon nitride, a silicate glass material, polysilicon, amorphous silicon, or a combination of the above materials.

Subsequently, as shown in fig. 4D, a hard mask barrier 407, which may expose a portion of the upper surface of the active layer 404, may be formed by patterning and etching the hard mask layer according to an embodiment of the present disclosure. Note that the hard mask blocking portion 407 shown in fig. 4D extends in the column direction (i.e., the direction perpendicular to the paper surface), i.e., the bit line direction.

Subsequently, as shown in fig. 4E, a sidewall material layer may be conformally formed on the exposed upper surface of the active layer 404 and the upper and side surfaces of the hard mask barrier 407 by, for example, a deposition process, according to an embodiment of the present disclosure. According to embodiments of the present disclosure, the sidewall material layer may include a material having etch selectivity with respect to the hard mask barrier 407 and the active layer 404, such as silicon nitride, silicon oxide, a silicon glass material, polysilicon, amorphous silicon, or a combination thereof.

Subsequently, as shown in fig. 4F, according to an embodiment of the present disclosure, the sidewall material layer may be etched by, for example, an anisotropic etching process to form sidewalls 405 at both sides of the hard mask barrier 407 and expose a portion of the upper surface of the active layer 404. Note that, similarly to the hard mask blocking portion 407, the side wall 405 formed in fig. 4F also extends in the column direction (i.e., the direction perpendicular to the paper surface), i.e., the bit line direction. The sidewall 405, which serves as a mask for self-aligned etching in subsequent process steps, may be used to define the dimension of the active region of the gate transistor of the DRAM cell structure in the row direction, in accordance with embodiments of the present disclosure.

Subsequently, as shown in fig. 4G, the active layer 404, the second sacrificial layer 403, the semiconductor layer 402, the first sacrificial layer 401, and/or the substrate 411 may be sequentially self-aligned by, for example, an etching process using the hard mask barrier 407 and the sidewall 405 as masks to form a first trench G1 extending to the substrate 411, according to an embodiment of the present disclosure. According to an embodiment of the present disclosure, the first groove G1 may extend to the substrate 411 in a vertical direction.

It should be noted that the first grooves G1 shown in fig. 4G also extend in the column direction (i.e., the direction perpendicular to the paper surface), i.e., the bit line direction, according to the embodiment of the present disclosure.

Subsequently, as shown in fig. 4H, according to an embodiment of the present disclosure, the first isolation medium 406 may be filled in the first trench G1 by, for example, a deposition process, and upper surfaces of the hard mask barrier 407, the first isolation medium 406, and the sidewall 405 may be planarized by, for example, a grinding process or an etching process. According to embodiments of the present disclosure, first isolation medium 406 may include an oxide (e.g., silicon oxide), a nitride (e.g., silicon nitride), an oxynitride (e.g., silicon oxynitride), or a combination of the above materials.

Subsequently, as shown in fig. 4I, the hard mask blocking portion 407 may be removed by, for example, an etching process, and the active layer 404 is self-aligned etched using the sidewall 405 as a mask to form a second groove G2 exposing the second sacrificial layer 403, according to an embodiment of the present disclosure.

It should be noted that, according to the embodiment of the present disclosure, the second groove G2 shown in fig. 4I also extends in the column direction (i.e., the direction perpendicular to the paper surface), i.e., the bit line direction, similarly to the first groove G1 shown in fig. 4G.

According to an embodiment of the present disclosure, after the second groove G2 is formed, a protective layer may be formed along an inner surface of the second groove G2 for protecting an active region of a gate transistor of a DRAM cell structure in a subsequent process step. According to embodiments of the present disclosure, the protective layer may include an oxide, such as silicon oxide.

According to an embodiment of the present disclosure, the first and second trenches G1 and G2 may be formed by performing self-aligned etching twice using the sidewall 405 as a mask.

Subsequently, as shown in fig. 4J, according to an embodiment of the present disclosure, the second sacrificial layer 403 may be removed through the second groove G2 by, for example, an etching process.

Subsequently, as shown in fig. 4K, according to an embodiment of the present disclosure, a conductor layer may be conformally formed along the inner surface of the second trench G2 and the upper surface of the entire semiconductor structure (i.e., DRAM array structure) by, for example, a deposition process (e.g., atomic Layer Deposition (ALD)). According to embodiments of the present disclosure, the conductor layer may include a metal or an alloy, for example, cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), tungsten (W), molybdenum (Mo), cobalt (Go), manganese (Mn), platinum (Pt), or palladium (Pd), or an alloy of the above metals. In particular, according to embodiments of the present disclosure, the conductor layer may include, for example, titanium nitride (TiN).

Subsequently, as shown in fig. 4L, according to an embodiment of the present disclosure, a portion of the conductor layer may be removed by, for example, an etching process to embed the conductor line 409 in a space left by removing the second sacrificial layer 403 under the active layer 404. As shown in fig. 4L, the conductor line 409 may be formed to have a mirrored "[ -shaped cross-sectional structure according to an embodiment of the present disclosure. According to the embodiment of the present disclosure, as shown in fig. 4L, the opening of the "[ -shaped section of the conductor line 409 formed using the second groove G2 faces the second groove G2, i.e., the openings of the" [ -shaped section of the conductor line 409 formed using the same second groove G2 face each other. However, the present disclosure is not limited thereto. The conductor line 409 may also be formed in a structure having a solid rectangular cross section according to an embodiment of the present disclosure.

According to an alternative embodiment of the present disclosure, when the conductor layer includes a metal, the silicidation process may be performed by, for example, an annealing process, so that metal silicide is formed under the active layer 404 in a space left by the removal of the second sacrificial layer 403 through the second trench G2, so that these metal silicide may form a conductor line used as, for example, a bit line.

The sidewall 405, which serves as a mask for the self-aligned etch, may also define the dimension of the conductor line 409, which serves as a bit line, in the row direction, in accordance with embodiments of the present disclosure.

Subsequently, as shown in fig. 4M, the semiconductor layer 402 may be etched downward through the second trench G2 by, for example, a self-aligned etching process with the sidewall 405 as a mask to expose the first sacrificial layer 401 according to an embodiment of the present disclosure. In other words, according to embodiments of the present disclosure, the second trench G2 may be extended downward through the semiconductor layer 402 by an etching process.

Subsequently, as shown in fig. 4N, according to an embodiment of the present disclosure, the first sacrificial layer 401 may be removed through the second groove G2 by, for example, an etching process.

Subsequently, as shown in fig. 4O, the second trench G2 may be filled with a second isolation medium 410 by, for example, a deposition process and the space left by the removal of the first sacrificial layer 401 as shown in fig. 4N, according to an embodiment of the present disclosure. According to embodiments of the present disclosure, the second isolation medium 410 may include an oxide (e.g., silicon oxide), a nitride (e.g., silicon nitride), an oxynitride (e.g., silicon oxynitride), or a combination of the above materials. According to embodiments of the present disclosure, second isolation medium 410 may be formed of the same material as first isolation medium 406, or may be formed of a different material than first isolation medium 406. According to an embodiment of the present disclosure, the second isolation medium 410 may fill the concave portion of the conductor line 409 having a "[ -shaped cross section formed through the second trench G2.

According to an embodiment of the present disclosure, the first groove G1 may extend into the substrate 411, and the second groove G2 extends only to the surface of the substrate 411.

According to the embodiment of the present disclosure, the conductor lines 409 may be isolated from each other from the bottom by the first and second trenches G1 and G2 extending to the substrate 411 and respectively filled with the first and second isolation media 406 and 410 that are nonconductive, and by the second isolation media 410 disposed under the semiconductor layer 402, and the influence of parasitic capacitance between the conductor lines 409 may be reduced.

Through the process steps shown in fig. 4A to 4O, the first trench G1 and the second trench G2 may be formed by two self-aligned etches using the sidewall 405 (and the hard mask barrier 407) as a mask, such that buried conductor lines 409 extending in a column direction (i.e., a direction perpendicular to the paper surface of fig. 4A to 4O) are formed in the DRAM array structure composed of the vertical DRAM cell structures, and the size of the active region of the gate transistor of each DRAM cell structure of the DRAM array structure in the row direction is also defined.

Fig. 5 is a schematic cross-sectional view illustrating a semiconductor structure with buried conductor lines according to another embodiment of the present disclosure. The semiconductor structure shown in fig. 5 corresponds to the semiconductor structure shown in fig. 4O, and therefore the same components of the semiconductor structure shown in fig. 5 as those shown in fig. 4O are denoted by the same reference numerals.

The semiconductor structure shown in fig. 5 differs from the semiconductor structure shown in fig. 4O in that the second isolation medium 410 may not fill the concave portion of the conductor line 409 having a "[" shaped cross section (as shown in fig. 5) or partially fill the concave portion of the conductor line 409 having a "[" shaped cross section (not shown) according to an embodiment of the present disclosure, so that a cavity may be formed between the conductor line 409 and the second isolation medium 410. According to embodiments of the present disclosure, the cavity may be filled with air.

According to the embodiment of the present disclosure, by forming a cavity between the conductor line 409 and the second isolation medium 410, the influence of parasitic capacitance between adjacent conductor lines 409 can be further reduced.

According to an embodiment of the present disclosure, the conductor line may also be buried under the active layer 404 through the first trench G1. Process steps of a method for burying a conductor line in a semiconductor structure according to another embodiment of the present disclosure are described below with reference to fig. 6A to 6E. Fig. 6A to 6E are schematic cross-sectional views each showing a process step of a method for burying a conductor line in a semiconductor structure according to another embodiment of the present disclosure. The same components in fig. 6A to 6E as those in fig. 4A to 4O are denoted by the same reference numerals, and detailed description thereof will be omitted.

According to embodiments of the present disclosure, the process steps shown in fig. 6A-6D may be incorporated between the process steps shown in fig. 4G and 4H.

Specifically, as shown in fig. 6A, a portion of the second sacrificial layer 403 may be removed through the first trench G1 by an etching process after the process step shown in fig. 4G according to an embodiment of the present disclosure. According to an embodiment of the present disclosure, the width d2 of the remaining portion of the second sacrificial layer 403 in the row direction may be greater than the width d1 of the hard mask barrier 407 in the row direction to ensure that a conductor line having an "i" shaped cross section may be formed in a subsequent process step.

As shown in fig. 6A, according to an embodiment of the present disclosure, since the first sacrificial layer 401 needs to be maintained while the second sacrificial layer 403 is removed, the first sacrificial layer 401 and the second sacrificial layer 403 may have etching selectivity with respect to each other. For example, when the first sacrificial layer 401 and the second sacrificial layer 403 each include a germanium-silicon material, the germanium concentration of the first sacrificial layer 401 may be higher than the germanium concentration of the second sacrificial layer 403 according to embodiments of the present disclosure.

According to an embodiment of the present disclosure, after the first groove G1 is formed, a protective layer may be formed along an inner surface of the first groove G1 for protecting an active region of a gate transistor of a DRAM cell structure in a subsequent process step. According to embodiments of the present disclosure, the protective layer may include an oxide, such as silicon oxide.

According to an embodiment of the present disclosure, the protective layer formed at the inner surface of the first groove G1 may include the same or different material from that of the protective layer formed at the inner surface of the second groove G2.

Subsequently, as shown in fig. 6B, similar to fig. 4K, a conductor layer may be conformally formed along the inner surface of the first trench G1 and the upper surface of the entire semiconductor structure (i.e., DRAM array structure) by, for example, a deposition process (e.g., atomic Layer Deposition (ALD)), according to an embodiment of the present disclosure. According to embodiments of the present disclosure, the conductor layer may include a metal or an alloy, for example, cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), tungsten (W), molybdenum (Mo), cobalt (Go), manganese (Mn), platinum (Pt), or palladium (Pd), or an alloy of the above metals. In particular, according to embodiments of the present disclosure, the conductor layer may include, for example, titanium nitride (TiN).

According to an embodiment of the present disclosure, the conductor layer formed along the inner surface of the first groove G1 may include the same or different material from that of the conductor layer formed along the inner surface of the second groove G2.

Subsequently, as shown in fig. 6C, similar to fig. 4L, a portion of the conductor layer may be removed by, for example, an etching process to embed the conductor line 409 in a space left by removing a portion of the second sacrificial layer 403 under the active layer 404 according to an embodiment of the present disclosure. As shown in fig. 6C, according to an embodiment of the present disclosure, the conductor line 409 may be formed to have a structure of a "]" shaped section. According to the embodiment of the present disclosure, as shown in fig. 6C, the opening of the "]" shaped section of the conductor line 409 formed using the first groove G1 faces the first groove G1, i.e., the openings of the "]" shaped section of the conductor line 409 formed using the same first groove G1 face each other. However, the present disclosure is not limited thereto. According to an embodiment of the present disclosure, the conductor line 409 formed using the first groove G1 may also be formed to have a structure of a solid rectangular cross section.

According to an alternative embodiment of the present disclosure, when the conductor layer includes a metal, the silicidation process may be performed by, for example, an annealing process, so that metal silicide is formed in a space left by removing a portion of the second sacrificial layer 403 through the first trench G1 under the active layer 404, so that these metal silicide may form the conductor line 409 serving as, for example, a bit line.

Subsequently, as shown in fig. 6D, the first trench G1 may be filled with a first isolation medium 406 by, for example, a deposition process, according to an embodiment of the present disclosure. According to embodiments of the present disclosure, the first isolation medium 406 may fill the concave portion of the conductor line 409 having a "]" shaped cross section formed through the first trench G1.

Subsequently, the process steps described above with reference to fig. 4H to 4O, that is, the process steps of filling the second isolation medium 410 and the buried conductor line 409 through the second trench G2, may be performed, so that the semiconductor structure as shown in fig. 6E may be obtained. As shown in fig. 6E, according to an embodiment of the present disclosure, the conductor line 409 may include a portion having a "]" shaped section formed in the first groove G1 and a portion having a "[" shaped section formed in the second groove G2, openings of the two portions facing away from each other, and thus the conductor line 409 may be formed to have a structure having an "i" shaped section.

Returning to fig. 6A, according to an alternative embodiment of the present disclosure, the width d2 of the remaining portion of the second sacrificial layer 403 in the row direction may also be smaller than the width d1 of the hard mask barrier 407 in the row direction but should be greater than zero to ensure that structures above the second sacrificial layer 403 do not collapse. In this case, when the second trench G2 is formed in a subsequent process step, the conductor line formed through the first trench G1 may be left without being further buried through the second trench G2 by selective etching, while the conductor line still has a "]" shaped cross section without having an "i" shaped cross section.

Those skilled in the art will recognize that the method of burying the conductor line 409 through the first trench G1 is not limited to the method described above with reference to fig. 6A to 6E. Fig. 7A to 7C are schematic cross-sectional views each showing a process step of a method for burying a conductor line in a semiconductor structure according to another embodiment of the present disclosure. The same components in fig. 7A to 7C as those in fig. 4A to 4O and 6A to 6E are denoted by the same reference numerals, and detailed description thereof will be omitted.

Specifically, as shown in fig. 7A, after the process step shown in fig. 4F, the active layer 404 may be self-aligned etched by, for example, an etching process using the hard mask barrier 407 and the sidewall 405 as a mask to form a first trench G1 exposing the second sacrificial layer 403, according to an embodiment of the present disclosure.

Subsequently, as shown in fig. 7B, a portion of the second sacrificial layer 403 may be removed through the first groove G1 by an etching process, similar to fig. 6A, according to an embodiment of the present disclosure.

Subsequently, as shown in fig. 7C, according to an embodiment of the present disclosure, similar to fig. 6B and 6C, the conductor line 409 may be buried in a space left by removing a portion of the second sacrificial layer 403 under the active layer 404 through the first trench G1 by, for example, a deposition process and an etching process.

Subsequently, according to an embodiment of the present disclosure, the semiconductor layer 402, the first sacrificial layer 401 and/or the substrate 411 may be continuously etched downward through the first trench G1 by, for example, an etching process such that the first trench G1 extends downward to the substrate 411, thereby obtaining the same semiconductor structure as shown in fig. 6C. Subsequently, according to embodiments of the present disclosure, the process steps described above with reference to fig. 6D may be continued to finally obtain a semiconductor structure with buried conductor lines as shown in fig. 6E.

Fig. 7 is a schematic cross-sectional view illustrating a semiconductor structure with buried conductor lines according to another embodiment of the present disclosure. The semiconductor structure shown in fig. 7 corresponds to the semiconductor structure shown in fig. 6E, and therefore the same components of the semiconductor structure shown in fig. 7 as those shown in fig. 6E are denoted by the same reference numerals.

The semiconductor structure shown in fig. 7 differs from the semiconductor structure shown in fig. 6E in that, according to an embodiment of the present disclosure, the first isolation medium 406 and the second isolation medium 410 may not fill the concave portion of the conductor line 409 having the "i" shape cross section (as shown in fig. 7) or partially fill the concave portion of the conductor line 409 having the "i" shape cross section (not shown), so that cavities may be formed between the conductor line 409 and the first isolation medium 406 and/or between the conductor line 409 and the second isolation medium 410, respectively. According to embodiments of the present disclosure, the cavity may be filled with air.

According to embodiments of the present disclosure, the cavity may also be formed only between the conductor line 409 and the first isolation medium 406, or only between the conductor line 409 and the second isolation medium 410.

Those skilled in the art will recognize that conductor line 409 may also be formed under active layer 404 by only first trench G1 and conductor line 409 may not be formed under active layer 404 by second trench G2 in accordance with alternative embodiments of the present disclosure, all of which are equally well within the scope of the present disclosure.

Fig. 8 is a schematic cross-sectional view showing the semiconductor structure taken along line BB' in fig. 4O, 5, 6E, and 7.

According to the method for burying a conductor line in a semiconductor structure of the present disclosure, by providing two sacrificial layers on a substrate, wherein a lower sacrificial layer is used to form a bottom structure of an isolated conductor line, an upper sacrificial layer is used to bury the conductor line, forming a first trench and a second trench extending to the substrate isolated from each other by two self-aligned etches using the same mask, and forming the conductor line in at least one of the first trench and the second trench, a plurality of buried conductor lines isolated from each other can be formed. Further, according to the semiconductor structure having buried conductor lines and the method of manufacturing the same of the present disclosure, by forming the cavity filled with air in the buried conductor lines, the influence of parasitic capacitance between the buried conductor lines can be reduced.

The foregoing has been presented for purposes of illustration a limited number of possible embodiments of the present disclosure. Although the present disclosure has been described with reference to embodiments thereof, those skilled in the art will appreciate that various modifications and changes can be made to the embodiments of the disclosure without departing from the spirit and scope of the disclosure as disclosed in the appended claims.

Although numerous details are contained herein, these details should not be construed as limitations on the scope of the disclosure or of what may be claimed, but rather as descriptions of features that may be specific to particular embodiments. Certain features that are described herein in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment can also be implemented in multiple embodiments separately or in any suitable subcombination. Furthermore, although features may be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination can in some cases be excised from the combination, and the claimed combination may be directed to a subcombination or variation of a subcombination.

Claims

1. A method for embedding a conductor line in a semiconductor structure, comprising:

providing a substrate;

a first sacrificial layer, a semiconductor layer, a second sacrificial layer, an active layer and a hard mask layer are sequentially arranged on the substrate;

patterning and etching the hard mask layer to form a hard mask barrier part, and forming side walls on two sides of the hard mask barrier part;

self-aligned etching the active layer, the second sacrificial layer, the semiconductor layer and the first sacrificial layer using the hard mask barrier and the sidewall to form a first trench extending to the substrate, and filling the first trench with a first isolation medium;

removing the hard mask blocking part, and using the side wall to self-align and etch the active layer to form a second groove exposing the second sacrificial layer;

removing the second sacrificial layer through the second trench to embed the conductor line under the active layer through the second trench;

etching the semiconductor layer through the second trench to expose the first sacrificial layer;

removing the first sacrificial layer through the second trench; and

filling the second trench and removing the space left by the first sacrificial layer with a second isolation medium.

2. The method of claim 1, wherein the conductor line comprises a metal and/or a metal silicide.

3. The method of claim 1, wherein the conductor line has a mirrored "[" shaped cross section.

4. The method of claim 1, wherein the conductor line has a cross-section of a solid rectangle.

5. A method according to claim 3, wherein an air filled cavity is formed in the recessed portion of the conductor line having a mirrored "[" shaped cross section.

6. The method of claim 1, wherein the first isolation medium is the same or different than the second isolation medium.

7. The method of claim 1, further comprising:

a protective layer is formed at an inner surface of the second groove.

8. The method of claim 1, wherein adjacent conductor lines are isolated from the bottom by the second isolation medium under the semiconductor layer.

9. The method of claim 1, wherein the first and second sacrificial layers comprise silicon germanium, the first sacrificial layer having a germanium concentration that is the same as or different from a germanium concentration of the second sacrificial layer.

10. The method of claim 1, further comprising:

A portion of the second sacrificial layer is removed through the first trench to embed the conductor line under the active layer.

11. The method of claim 10, wherein the conductor line has an "i" shaped cross section.

12. The method of claim 10, further comprising:

a protective layer is formed at an inner surface of the first groove.

13. The method of claim 11, wherein an air-filled cavity is formed in the recessed portion of the conductor line having an "i" shaped cross section.

14. The method of claim 10, wherein the first and second sacrificial layers comprise silicon germanium, the first sacrificial layer having a different germanium concentration than the second sacrificial layer.

15. A method for embedding a conductor line in a semiconductor structure, comprising:

providing a substrate;

sequentially arranging a first sacrificial layer, a semiconductor layer, a second sacrificial layer, an active layer and a hard mask layer on the substrate, wherein the second sacrificial layer has etching selectivity relative to the first sacrificial layer;

Self-aligned etching the active layer, the second sacrificial layer, the semiconductor layer, the first sacrificial layer and/or the substrate using the hard mask barrier and the sidewall to form a first trench extending to the substrate;

removing a portion of the second sacrificial layer through the first trench to embed the conductor line under the active layer through the first trench;

filling the first trench with a first isolation medium;

removing the hard mask blocking part, and using the side wall to self-align and etch the active layer, the second sacrificial layer and the semiconductor layer to form a second groove exposing the first sacrificial layer;

removing the remaining portion of the second sacrificial layer and the first sacrificial layer through the second trench; and

filling the second trench with a second isolation medium and removing the remaining portion of the second sacrificial layer and the space left by the first sacrificial layer.

16. A method for embedding a conductor line in a semiconductor structure, comprising:

providing a substrate;

Self-aligned etching the active layer using the hard mask barrier and the sidewall to form a first trench exposing the second sacrificial layer;

etching the semiconductor layer, the first sacrificial layer and/or the substrate through the first trench such that the first trench extends to the substrate;

filling the first trench with a first isolation medium;

17. A method for embedding a conductor line in a semiconductor structure, comprising:

providing a substrate;

a first sacrificial layer, a semiconductor layer, a second sacrificial layer and an active layer are sequentially arranged on the substrate;

Forming a first groove and a second groove exposing the first sacrificial layer and the second sacrificial layer respectively through two times of self-alignment etching;

removing the first sacrificial layer through the second trench to provide an isolation structure under the semiconductor layer;

removing all or a portion of the second sacrificial layer through at least one of the first and second trenches to embed the conductor line under the active layer; and

the first and second trenches are filled with an isolation medium.

18. A semiconductor structure with buried conductor lines manufactured using the method of any one of claims 1 to 17.